阅读说明：本技术 以静态模拟校准电路实现的钟控数据采样器的动态积分时间调节 (Dynamic integration time adjustment of clocked data samplers with static analog calibration circuits ) 是由 凯拉什·加里杜 阿明·塔亚丽 帕万·库马尔·詹帕尼 阿里·霍马提 于 2020-04-03 设计创作，主要内容包括：在所描述的方法和系统中：由参考分支电路根据经带隙发生器和共模电压输入获得的参考电流,生成工艺/电压/温度(PVT)相关参考电压；由静态模拟校准电路的输出端响应于所述共模电压输入和可调节电流,生成PVT相关输出电压；由所述静态模拟校准电路根据响应于所述PVT相关输出电压与所述PVT相关参考电压之间的比较结果所生成的控制信号,调节所述可调节电流；以及通过将所述控制信号提供给钟控数据采样器而实现以PVT校准后电流对所述钟控数据采样器的设置。(In the described method and system: generating, by a reference branch circuit, a process/voltage/temperature (PVT) dependent reference voltage from a reference current obtained via a bandgap generator and a common mode voltage input; generating, by an output of a static analog calibration circuit, a PVT-related output voltage in response to the common-mode voltage input and an adjustable current; adjusting, by the static analog calibration circuit, the adjustable current according to a control signal generated in response to a comparison between the PVT-related output voltage and the PVT-related reference voltage; and enabling setting of the clocked data sampler with the PVT-calibrated current by providing the control signal to the clocked data sampler.)

1. An apparatus, comprising:

a reference branch circuit for generating a process/voltage/temperature (PVT) dependent reference voltage from a reference current obtained via the bandgap generator and a common mode voltage input;

a static analog calibration circuit for generating a PVT dependent output voltage in response to the common mode voltage input and an adjustable current;

a control signal generator for comparing the PVT related output voltage with the PVT related reference voltage and responsively generating a control signal for adjusting the adjustable current by the static analog calibration circuit, wherein the control signal sets the clock-controlled data sampler with the PVT calibrated current.

2. The apparatus of claim 1, wherein the control signal generator is to adjust the adjustable current until the PVT-related output voltage is within a threshold of the PVT-related reference voltage.

3. The apparatus of claim 1, wherein the reference branch circuit is a replica circuit of a branch circuit within the static analog calibration circuit.

4. The apparatus of any of claims 1-3, wherein each of the static analog calibration circuit and the reference branch circuit comprises an enable transistor, wherein the enable transistor calibrates the PVT calibrated current by selective activation.

5. The apparatus of claim 4, the enable transistor selectively activated in response to a change in temperature.

6. The apparatus of claim 4, the enable transistor selectively activated in response to a change in a common mode input voltage.

7. The apparatus of claim 1, wherein the control signal generator comprises an accumulator to accumulate a comparison result between the PVT-related output voltage and the PVT-related reference voltage.

8. The apparatus of claim 7, wherein the control signal generator comprises a chopper amplifier to generate a comparison between the PVT-related output voltage and the PVT-related reference voltage.

9. A method, comprising:

generating, by a reference branch circuit, a process/voltage/temperature (PVT) dependent reference voltage from a reference current obtained via a bandgap generator and a common mode voltage input;

generating, by an output of a static analog calibration circuit, a PVT-related output voltage in response to the common-mode voltage input and an adjustable current;

adjusting, by the static analog calibration circuit, the adjustable current according to a control signal generated in response to a comparison between the PVT-related output voltage and the PVT-related reference voltage; and

setting the clocked data sampler with the PVT calibrated current is accomplished by providing the control signal to the clocked data sampler.

10. The method of claim 9, wherein the adjustable current is adjusted until the PVT-related output voltage is within a threshold of the PVT-related reference voltage.

11. The method of claim 9, wherein the reference branch circuit is a replica of a branch circuit within the static analog calibration circuit.

12. The method of any of claims 9 to 11, further comprising: enabled transistors enable the static analog calibration circuit and the reference branch circuit to enable calibration of the PVT calibrated current.

13. The method of claim 12, wherein the static analog calibration circuit and the reference subcircuit are enabled in response to a change in temperature.

14. The method of claim 12, wherein the static analog calibration circuit and the reference branch circuit are enabled in response to a change in a common mode input voltage.

15. The method of claim 9, wherein the magnitude of the adjustable current flowing through the static analog calibration circuit is twice the reference current.

Technical Field

The present invention relates generally to communication system circuits, and more particularly to the regulation and control of circuits that obtain measurements of the amplitude of an input signal relative to a given reference signal level and clock instant.

Background

In today's digital systems, digital information must be efficiently and reliably processed. In this context, digital information must be understood as information contained within discrete values (i.e. non-continuous values). Digital information may be represented not only by bits and bit sets, but also by numbers within a limited set.

To increase the overall bandwidth, most inter-chip or inter-device communication systems employ multiple lines for communication. Each or each pair of these lines may be referred to as a channel or link, and the multiple channels make up a communication bus between the electronic devices. At the physical circuit level, buses within an inter-chip communication system are typically made up of encapsulated electrical conductors between the chip and the motherboard, on a Printed Circuit Board (PCB), or within inter-PCB cables and connectors. Furthermore, in high frequency applications, microstrip or strip PCB traces may also be employed.

Common bus line signaling methods include single-ended signaling and differential signaling. In applications requiring high-speed communication, these methods may be further optimized in terms of power consumption and pin utilization, particularly in high-speed communication. Recently proposed vector signaling approaches can achieve more optimal trade-offs in power consumption, pin utilization, and noise robustness of inter-chip communication systems. Such vector signaling systems convert the digital information of the transmitter into a different representation space of vector codewords, and select different vector codewords according to the characteristics of the transmission channel and the design constraints of the communication system to make a better trade-off between power consumption, pin utilization, and speed. This process is referred to as "encoding" in this application. The encoded codeword is transmitted from the transmitter to one or more receivers in the form of a set of signals. The receiver inverts the received signal corresponding to the codeword into the original digital information representation space. This process is referred to as "decoding" in this application.

Regardless of the encoding method employed, the signals received by the receiving device must be sampled at intervals (or otherwise have their signal values recorded), and the sampling intervals must be such that the sampled values represent the original transmitted values in an optimal manner, regardless of the delay, interference and noise conditions of the transmission channel. This sampling operation can be performed independently in the time domain (e.g., with sample and hold circuits in the analog domain, or with clocked latches in the digital domain) and amplitude domain (e.g., with comparators or slicers) by clocked comparators or samplers, or as a combined time domain/amplitude domain sampling operation. The timing of this sampling or slicing operation is controlled by an associated Clock and Data Alignment (CDA) timing system that determines the correct sampling time.

Disclosure of Invention

In the methods and systems described herein: generating, by a reference branch circuit, a process/voltage/temperature (PVT) dependent reference voltage from a reference current obtained via a bandgap generator and a common mode voltage input; generating, by an output of a static analog calibration circuit, a PVT-related output voltage in response to the common-mode voltage input and an adjustable current; adjusting, by the static analog calibration circuit, the adjustable current according to a control signal that should be generated in response to a comparison between the PVT related output voltage and the PVT related reference voltage; and enabling setting of the clocked data sampler with the PVT-calibrated current by providing the control signal to the clocked data sampler.

It is known in the art that there are circuits, commonly referred to as "samplers", for making timing signal amplitude measurements. Such samplers are a common element of data communication receivers that combine the time sampling function of an analog sample and hold circuit or digital latch with the amplitude comparison function of a digital comparator or slicer, typically as an interface between front-end analog signal processing and back-end digital data processing.

Sampler circuits currently exist that derive from analog signal comparators, clocked digital latches, and other hybrid analog/digital circuit architectures, the benefits and limitations of each variant of such architecture are known. One of these architectures, particularly the clocked dynamic integrator/sampler architecture, has been identified as having the ability to consume less supply current while achieving high speed operation. The sampler is derived from a classical analog differential comparator as described in [ Tajalli I ], and operates in a dynamic manner to first charge an internal circuit node under control of a clock signal, and then discharge the node through a comparison circuit, thereby enabling timed comparisons between the active input signal and the reference input signal at the time of the clock signal transition. An implementation of a clock-controlled dynamic sampler is described in the text Tajalli II.

Despite the high speed and low power consumption advantages described above, the dynamic nature of such circuits can lead to drift and stability problems in a manufacturing environment. Although the individual MOS transistors within a given integrated circuit may be fabricated to closely match one another, the absolute operating parameters, particularly gate threshold voltage, gain, and channel resistance, may vary widely from wafer to wafer, and such parameters within the same wafer may vary widely with fluctuations in temperature and supply voltage. Such fluctuations may cause differences in data detection accuracy between devices, and may cause the data detection function of the same device to degrade with operating conditions.

The embodiments described herein are used to measure the operating characteristics of a sampler as part of a closed loop control system to mitigate the effects of the aforementioned fluctuating variations. Wherein a separate static analog calibration circuit is used as a measurement replacement circuit for post-fabrication dynamic circuit operating characteristics in order to minimize the impact on the post-fabrication data detection path.

Drawings

Fig. 1 shows one embodiment of a clocked dynamic integrator/sampler circuit.

FIG. 2 illustrates one embodiment of a static analog calibration circuit that may be used as a measurement replacement circuit for the dynamic circuit shown in FIG. 1.

FIG. 3 illustrates one embodiment of a reference branch circuit that provides a known reference signal to be compared to a measured value as a decision input to a control signal generator.

FIG. 4 is a flow diagram of a method according to one embodiment.

Detailed Description

In order to reliably detect data values transmitted over a communication system, a communication receiver must accurately measure the amplitude of received signal values at carefully selected points in time, typically selected at or near the center of the settling time period between received signal transitions (i.e., once per receive Unit Interval (UI)). The source of the received signal may be derived from a single in-line signal, or a weighted linear combination of multiple in-line signals, for example as provided by a multiple input comparator or Mixer (MIC) for detecting vector signalling codes.

In some embodiments, the values of the received signal are first collected at selected points in time with a sample-and-hold or track-and-hold circuit, and then the resulting values are measured with respect to one or more reference values with a known voltage comparator circuit. Alternatively, the analog level of the received signal may be measured with a comparator or "slicer" relative to a reference voltage before the digital result is collected by a clocked digital latch.

The best measurement point for the received signal is generally referred to as the "eye center" (see the well-known "eye diagram" which represents the signal amplitude versus clock spacing). In the time dimension, the sampling point is typically determined by a local "receive clock" set to occur at the desired sampling time point. Such a manner of generating and continuously controlling the receive clock time is well known in the art-a clock data alignment (CDA, also known as Clock Data Recovery (CDR)) system measures and incrementally adjusts the sample time relative to the receive signal settling time to achieve optimization of the sample time.

Similarly, the optimal reference level for received signal amplitude comparison may be generated in a dynamic manner. Decision Feedback Equalization (DFE) is one of the techniques used to improve signal detection capability in serial communication systems. It is assumed in the art that the communication line characteristics of the communication channel between the transmitter and the receiver are imperfect, and therefore the energy associated with the previously transmitted bit may remain within the channel (e.g., in the form of reflected waves caused by impedance perturbations), thereby negatively affecting the reception of subsequent bits. The DFE system of the receiver processes each bit detected in a previous Unit Interval (UI) through simulation of the communication channel to obtain an estimate of the effect of the bit on a subsequent unit interval. This estimate, referred to herein as the "DFE correction amount," can be compensated for the predicted amount of intersymbol interference by subtracting the DFE correction amount from the received signal. In an alternative embodiment, a functionally equivalent operation to the subtraction operation may be achieved by measuring the received signal at a reference voltage level derived from the DFE correction signal (e.g., with a differential comparator). In actual use, the DFE system applies DFE corrections (referred to herein as "DEE factors," respectively) derived from a plurality of previous unit intervals to the received signal prior to data bit detection.

It is also known in the art that there are circuits for making combined amplitude/time measurements, which are commonly referred to as "samplers". Such samplers are a common element of data communication receivers that combine the time sampling function of an analog sample and hold circuit or digital latch with the amplitude comparison function of a digital comparator or slicer, typically as an interface between front-end analog signal processing and back-end digital data processing. Sampler circuits currently exist that derive from analog signal comparators, clocked digital latches, and other hybrid analog/digital circuit architectures, the benefits and limitations of each variant of such architecture are known.

One of the sampler architectures, particularly the clocked dynamic integrator/sampler architecture, has been identified as having the ability to consume less supply current while achieving high speed operation. The sampler is derived from a classical analog differential comparator as described in [ Tajalli I ], and operates in a dynamic manner to first charge an internal circuit node under control of a clock signal, and then discharge the node through a comparison circuit, thereby enabling timed comparisons between the active input signal and the reference input signal at the time of the clock signal transition. An implementation of a clock-controlled dynamic sampler is described in the text Tajalli II.

Despite the high speed and low power consumption advantages described above, the dynamic nature of such circuits can lead to drift and stability problems in a manufacturing environment. Although the individual MOS transistors within a given integrated circuit may be fabricated to closely match one another, the absolute operating parameters, particularly gate threshold voltage, gain, and channel resistance, may vary widely from wafer to wafer, and such parameters within the same wafer may vary widely with fluctuations in temperature and supply voltage. Such fluctuations may cause differences in data detection accuracy between devices, and may cause the data detection function of the same device to degrade with operating conditions.

The embodiments described herein are used to measure the operating characteristics of a sampler as part of a closed loop control system to mitigate the effects of the aforementioned fluctuating variations. Wherein a separate static analog calibration circuit is used as a measurement replacement circuit for post-fabrication dynamic circuit operating characteristics in order to minimize the impact on the post-fabrication data detection path.

Fig. 1 shows one embodiment of a clocked dynamic integrator/sampler circuit, which in one embodiment is a component of a DFE computation subsystem. Dynamic circuits typically operate in multiple active phases controlled by an input clock signal. For the circuit of fig. 1, transistors 111, 112,.. 119 provide a charging path when the input clock Clk is low, to enable current from Vdd to charge the distributed capacitance of internal circuit node 125. Wherein the control signal [ b ] can be used to control the operation of the motor₁，b₂，...b_n]More than one charge transistor is enabled for setting the charge speed. More control bits may also be supported by incorporating more 220 in parallel with the charge path transistors 111, 112 … …, as shown by the dashed lines. For a given clock signal low potential charge interval duration and node capacitance, a greater control signal [ b ] may be obtained by increasing the terminal voltage of node 225₁，b₂，...b_n]Value (i.e., more transistors enabled). After the charge path is enabled, current flows through differential input transistors 130 and 131, the magnitude of which is proportional to the difference between the input signals Vin + and Vin-. Thus, the output voltages of Vout-and Vout + are first low (discharged) and increase from the falling edge of Clk toward Vdd at a rate determined by the input signals Vin + and Vin-of transistors 130 and 131, respectively. Thus, the charging process (also referred to as the integration time of the integrator/sampler) starts from the falling clock edge and continues until the output voltage at one of the output nodes rises to such an extent that the gate-drain voltage of the transistor 140 or 141 no longer remains conductive.

When the input clock Clk rises to a high level, the charging path is disconnected and the discharging path is enabled through two branch circuits to reset the pair of output nodes before the next sampling interval. As shown in fig. 1, the discharge path may include transistors 130, 140, 150 and transistors 131, 141, 151, respectively. Further, a control signal en is used for enabling and disabling these discharge paths, and for the purposes of the description of this specification, it may be assumed that en is set such that the discharge path is enabled by the clock signal Clk due to the conduction of the transistors 140 and 141.

In some embodiments, the clocked data sampler may take an inverse configuration, where the pair of output nodes are pre-charged according to the sampling clock and then discharged at various rates according to the input signals Vin + and Vin-. Latches connected to the differential output nodes Vout + and Vout-can be used to convert the integrated signal to a latched digital output for use in either of the above two implementations.

The resulting differential result Vout depends not only on the input signal, but also to some extent on the gain of input transistor 130/131 and the channel characteristics of transistors 140, 141, 150, 151, with such gains and characteristics known to vary with integrated circuit process, current, time lapse, and temperature. Thus, the associated control signal generator is typically adapted to modify the control signal [ b ]₁，b₂，...b_n]To adjust the current amplitude charging the pair of output nodes Vout + and Vout-to obtain a constant uniform differential result.

In some cases, the sampler may be calibrated by: the current is adjusted according to the common mode value and then the sampler performance is measured to ensure that the current provides the correct sampling interval. Such a scenario can enable a replication of the dynamic sampler shown in fig. 1, but it needs to be clocked at the same frequency as the main sampler, and such circuit replication cannot eliminate the need for fast output measurements.

Alternatively, as described in this application, a static analog calibration circuit is used as a measurement surrogate for a dynamic circuit such as that shown in FIG. 1. It is noted that the inherent characteristics of the transistor that cause the characteristics of fig. 1 to fluctuate with process and environment are transistor gain, transistor threshold voltage, and transistor channel characteristics such as "on" resistance, all of which are beneficial for static or steady state measurements.

FIG. 2 illustrates one embodiment of a static analog calibration circuit that replicates the structure of the dynamic circuit of FIG. 1 but omits clocking operations. In keeping with the equivalent arrangement of fig. 1, each of the transistors in the circuit of fig. 2 has identical size and design characteristics. Thus, for example, in the control signal [ b ]₁，b₂，...b_n]With the same value, the quiescent current i of FIG. 2₁，i₂，...i_nInitial (i.e., peak) charging current i from fig. 1₁，i₂，...i_nAre substantially identical. For convenience of description, in this application, the total current is referred to asIn the static embodiment of fig. 2, both signal inputs are connected to a common mode voltage input Vcm corresponding to the active inputs Vin + and Vin-. For systems that capacitively couple the input signal, the voltage is equivalent to the bias voltage downstream of the capacitor. The static analog calibration circuit generates a process/voltage/temperature (PVT) dependent output voltage Vfb based on the common mode voltage input and an adjustable current provided via transistors 211, 212.

FIG. 3 illustrates one embodiment of a reference branch circuit that provides a known reference signal to be compared to a measured value as a decision input to a control signal generator. The reference branch circuit includes a current source 320 and transistors 330, 340, 350 having the same topology as transistors (e.g., 130, 140, 150) of the circuit branches having similar dimensions and design characteristics. However, the current provided by the reference current source 320 originates from a standard bandgap reference circuit and does not fluctuate with the process and the device voltage and temperature variations. Thus, Vref represents the PVT-related reference voltage generated by applying a known normalized reference current obtained from a bandgap generator to the transistors 330, 340, 350 in dependence on the common mode voltage input Vcm.

Comparator 310 compares the PVT-related output voltage Vfb from FIG. 2 with the PVT-related reference voltage Vref to generate an error indication for control signal generator 380 that contains the control signal [ b [ ]₁，b₂，...b_n]For the adjustable current I_totAnd (6) carrying out adjustment. For simplicity of description, 380 is shown to include an up-down accumulator 381 that increments or decrements according to the result of 310 to control [ b [₁，b₂，...b_n]And the supplied current i_totChanges occur such that the fig. 2 static analog calibration circuit and the fig. 3 reference branch circuit produce substantially equal results. Subsequently, the same control signal value [ b ] may be set₁，b₂，...b_n]Application to a clocked dynamic integrator/sampler circuit as shown in fig. 1 can be accomplished by a substitute measurement function of the static circuit, thereby enabling the provision of updated control values to the active dynamic circuit.

Fig. 4 is a flow diagram of a method 400 according to some embodiments. As shown, the method 400 includes: generating, by a reference branch circuit, a process/voltage/temperature (PVT) dependent reference voltage (410) from a reference current obtained via a bandgap generator and a common mode voltage input; generating, by an output of a static analog calibration circuit, a PVT-dependent output voltage (420) in response to the common-mode voltage input and an adjustable current; adjusting, by a static analog calibration circuit, the adjustable current (430) according to a control signal generated in response to a comparison between the PVT-related output voltage and a PVT-related reference voltage; and configuring (440) the clock-controlled data sampler with the PVT-calibrated current by providing the control signal to the clock-controlled data sampler.

In some embodiments, the adjustable current is adjusted until the PVT-related output voltage is equal to the PVT-related reference voltage or within some preset threshold. In some implementations, the reference branch circuit corresponds to a replica circuit of a branch circuit within the static analog calibration circuit. In some such implementations, the adjustable current is split between two branch circuits of the static analog calibration circuit and is twice the size of the reference current.

In some implementations, the method further includes enabling the static analog calibration circuit and the reference branch circuit by enabling transistors. In some such embodiments, calibration of the PVT calibrated current is achieved by enabling the static analog calibration circuit and a reference subcircuit. In some implementations, the static analog calibration circuit and the reference branch circuit are enabled in response to temperature changes. In some embodiments, the static analog calibration circuit and the reference branch circuit are enabled at system start-up. In some implementations, the static analog calibration circuit and the reference branch circuit are enabled in response to a change in a common mode input voltage.

In some embodiments, the control signal comprises a plurality of bits. In some implementations, respective current sources of different sizes in the clocked data sampler and in parallel with each other can be enabled with a binary code control signal. In an alternative embodiment, thermometer code control signals may be utilized to enable respective current sources of the clocked data samplers that are of the same size and are in parallel with each other.

In some embodiments, the comparison between the PVT-related output voltage and the PVT-related reference voltage is accumulated by an accumulator circuit. Such an accumulator circuit may be a digital accumulator for accumulating the comparison results obtained from the Least Significant Bit (LSB) portion of the comparator 310, while the most significant bit portion provides the multi-bit control signal. Other accumulation means may be used besides this. In some embodiments, as shown in fig. 3, the comparison between the PVT-related output voltage and the PVT-related reference voltage is generated by a chopper amplifier 310. Such amplifiers may be clocked by a system clock having a suitable frequency, such as 50 MHz.

In some embodiments, the method further comprises: the common mode voltage input is obtained via a resistor-capacitor (RC) network connected to an output of a Variable Gain Amplifier (VGA) that operates on information signals processed by the clocked data sampler. Such an RC network may correspond to a low pass filter.

Other embodiments of the control signal generator 380 may include a finite state machine, software or firmware executing within an embedded processor, or dedicated hardware, for implementing the generating, measuring, adjusting and configuring operations. In some embodiments, the operation of the control signal is performed periodically. In some embodiments, to reduce overall power consumption, some or all of the static analog calibration circuit and the reference subcircuit may be powered down or disabled during the gap in measurement operation. Some embodiments operate at initial system start-up to measure and compensate for process related circuit variations. Other embodiments operate during some portion of the normal operation of the system to measure and compensate for PVT-related fluctuations. The control signals and/or their corresponding adjustments may represent equal-sized amounts of change encoded in the thermometer code, binary-weighted amounts of adjustment represented in the binary or gray code, and/or other functional encodings.