阅读说明：本技术 包含低洼结构的微电子装置以及相关方法、存储器装置和电子系统 (Microelectronic device including recessed structures, and related methods, memory devices, and electronic systems ) 是由 D·A·克朗皮特 R·W·林赛 J·D·鲁尼亚 M·霍兰 C·N·查蒙达 于 2021-04-29 设计创作，主要内容包括：本申请案涉及包含低洼结构的微电子装置以及相关方法、存储器装置和电子系统。微电子装置包括堆叠结构、所述堆叠结构内的低洼结构以及导电触点结构。所述堆叠结构包括布置于层中的导电结构和绝缘结构的竖直交替序列。所述层中的每一个包括所述导电结构中的一个和所述绝缘结构中的一个。所述低洼结构包括：正向阶梯结构,其具有包括所述层的边缘的台阶；以及反向阶梯结构,其与所述正向阶梯结构相对且具有包括所述层的额外边缘的额外台阶。所述导电触点结构在所述正向阶梯结构的所述台阶和所述反向阶梯结构的所述额外台阶处竖直延伸到所述堆叠结构的所述导电结构中的至少一些的上部竖直边界,且各自与所述导电结构中的一个成一体式且连续。还描述存储器装置、电子系统和形成微电子装置的方法。(The present application relates to microelectronic devices including recessed structures, and related methods, memory devices, and electronic systems. A microelectronic device includes a stack structure, a depression within the stack structure, and a conductive contact structure. The stacked structure includes a vertically alternating sequence of conductive structures and insulating structures arranged in layers. Each of the layers includes one of the conductive structures and one of the insulating structures. The low-lying structure includes: a forward stair step structure having a step comprising an edge of the layer; and a reverse stair step structure opposite the forward stair step structure and having an additional step comprising an additional edge of the layer. The conductive contact structures extend vertically to an upper vertical boundary of at least some of the conductive structures of the stacked structure at the step of the forward stair-step structure and the additional step of the reverse stair-step structure, and are each integral and continuous with one of the conductive structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.)

1. A microelectronic device, comprising:

a stacked structure comprising a vertically alternating sequence of conductive structures and insulating structures arranged in layers, each of the layers comprising one of the conductive structures and one of the insulating structures;

a recessed structure within the stacked structure and comprising:

a forward stair step structure having a step comprising an edge of the layer; and

a reverse stair step structure opposite the forward stair step structure and having an additional step comprising an additional edge of the layer; and

conductive contact structures extending vertically to an upper vertical boundary of at least some of the conductive structures of the stacked structure at the step of the forward stair-step structure and the additional step of the reverse stair-step structure, the conductive contact structures each being integral and continuous with one of the conductive structures.

2. The microelectronic device of claim 1, wherein the conductive contact structure comprises:

first conductive contact structures integral and continuous with some of the conductive structures of the stacked structure at the steps of the forward stair-step structure, each of the first conductive contact structures individually having a horizontal boundary substantially coplanar with a horizontal boundary of one of the steps; and

second conductive contact structures integral and continuous with some other of the conductive structures of the stacked structure at the additional steps of the inverted stair-step structure, each of the first conductive contact structures individually having a horizontal boundary substantially coplanar with a horizontal boundary of one of the additional steps.

3. The microelectronic device of claim 1, wherein a horizontal width of one or more of the conductive contact structures is substantially equal to a vertical height of one or more of the conductive structures integral and continuous with the one or more of the conductive contact structures.

4. The microelectronic device of claim 1, further comprising dielectric spacer structures on the steps of the forward stair-step structure and the additional steps of the reverse stair-step structure, the dielectric spacer structures horizontally alternating with the conductive contact structures.

5. The microelectronic device of claim 4, wherein the dielectric spacer structure comprises:

first dielectric spacer structures on the steps of the forward stair step structure and individually horizontally interposed between horizontally adjacent pairs of the conductive contact structures; and

second dielectric spacer structures on the additional steps of the inverted stair-step structure and individually horizontally interposed between additional horizontally adjacent pairs of the conductive contact structures.

6. The microelectronic device as claimed in any one of claims 1 to 5, wherein an upper vertical boundary of each of the steps of the forward stair-step structure is vertically offset from an upper vertical boundary of each of the additional steps of the reverse stair-step structure.

7. The microelectronic device as claimed in any one of claims 1 to 5, wherein an upper surface of the step of the forward stair-step structure is vertically offset from an upper surface of the additional step of the reverse stair-step structure vertically closest thereto by a distance substantially equal to a vertical height of one of the layers of the stacked structure.

8. The microelectronic device of any of claims 1 to 5, wherein the depression further comprises a central region horizontally interposed between the forward and reverse step structures, the central region having a partially non-planar lower vertical boundary extending horizontally from and between a bottom of the forward and reverse step structures.

9. The microelectronic device of any of claims 1 to 5, wherein:

each of the steps of the forward stair-step structure individually comprises a horizontal end of a pair of the layers of the stacked structure; and is

Each of the additional steps of the inverted stair-step structure individually comprises a horizontal end of an additional pair of the layers of the stacked structure.

10. The microelectronic device of any of claims 1 to 5, wherein:

each of the steps of the forward stair-step structure individually comprises a horizontal end of a group of at least four of the layers of the stacked structure; and is

Each of the additional steps of the inverted stair-step structure individually comprises a horizontal end of an additional group of at least four of the layers of the stacked structure.

11. The microelectronic device as claimed in any one of claims 1 to 5, wherein upper vertical boundaries of at least some of the steps of the forward stair-step structure are substantially coplanar with upper vertical boundaries of at least some of the additional steps of the reverse stair-step structure.

12. The microelectronic device of any of claims 1 to 5, wherein the depression further comprises a central region horizontally interposed between the forward and reverse stair-step structures, the central region having a substantially flat lower vertical boundary extending horizontally from a bottom of the forward stair-step structure to a bottom of the reverse stair-step structure.

13. The microelectronic device of any of claims 1 to 5, wherein:

one of the steps of the forward stair step structure comprises a horizontal end of one of the layers of the stacked structure; and is

One of the additional steps of the inverted stair-step structure comprises an additional horizontal end of the one of the layers of the stacked structure.

14. A method of forming a microelectronic device, comprising:

forming a preliminary stacked structure comprising a vertically alternating sequence of insulating structures and additional insulating structures arranged in layers, each of the layers comprising one of the insulating structures and one of the additional insulating structures;

forming a trench extending vertically into the preliminary stacked structure;

forming a horizontally alternating sequence of dielectric spacer structures and dielectric liner structures within horizontal boundaries of the trench, at least some of the dielectric liner structures physically contacting mutually different insulating structures of the preliminary stack structure; and

at least partially replacing dielectric material of the dielectric liner structure and the insulating structure of the preliminary stack structure with a conductive material.

15. The method of claim 14, wherein forming a horizontally alternating sequence of dielectric spacer structures and dielectric liner structures within horizontal boundaries of the trench comprises:

forming a first dielectric spacer structure within the trench;

forming a first dielectric liner structure within the trench and horizontally inward of the first dielectric spacer structure, the first dielectric liner structure physically contacting at least one of the insulating structures of the preliminary stack structure;

forming a second dielectric spacer structure within the trench and horizontally inward of the first dielectric liner structure; and

forming a second dielectric liner structure within the trench and horizontally inward of the second dielectric spacer structure, the second dielectric liner structure physically contacting at least one other of the insulating structures at a relatively lower vertical position within the preliminary stacked structure than the at least one of the insulating structures.

16. The method of claim 15, wherein:

forming a first dielectric liner structure within the trench comprises:

forming a first portion of the first dielectric liner structure to physically contact a first one of the insulating structures; and

forming a second portion of the first dielectric liner structure to physically contact a second one of the insulating structures vertically adjacent to the first one of the insulating structures; and is

Forming a second dielectric liner structure within the trench comprises:

forming a first portion of the second dielectric liner structure to physically contact a third one of the insulating structures vertically underlying the second one of the insulating structures; and

forming a second portion of the second dielectric liner structure to physically contact a fourth one of the insulating structures vertically adjacent to the third one of the insulating structures.

17. The method according to any one of claims 15 and 16, wherein:

forming a first dielectric spacer structure within the trench comprises:

forming a first portion of the first dielectric spacer structure to physically contact a first one of the additional insulating structures; and

forming a second portion of the first dielectric spacer structure to physically contact a second one of the additional insulating structures vertically adjacent to the first one of the additional insulating structures; and is

Forming a second dielectric spacer structure within the trench comprises:

forming a first portion of the second dielectric spacer structure to physically contact a third one of the additional insulating structures that vertically underlies the second one of the additional insulating structures; and

forming a second portion of the second dielectric spacer structure to physically contact a fourth one of the additional insulating structures vertically adjacent to the third one of the additional insulating structures.

18. The method of claim 14, wherein forming a horizontally alternating sequence of dielectric spacer structures and dielectric liner structures within horizontal boundaries of the trench comprises forming a recess within the preliminary stack structure and within horizontal boundaries of the trench, the recess comprising:

a forward stair-step structure having steps including horizontal ends of the layers, some portions of the dielectric liner structure being in physical contact with some of the insulating structures of the preliminary stack structure at the steps of the forward stair-step structure; and

an inverted stair-step structure opposite the forward stair-step structure and having an additional step comprising an additional horizontal end of the layer, some other portion of the dielectric liner structure being in physical contact with some other of the insulating structures of the preliminary stack structure at the additional step of the inverted stair-step structure.

19. The method of claim 18, wherein forming a low-lying structure comprises forming an upper surface of each of the steps of the forward stair-step structure to be vertically offset from an upper surface of each of the additional steps of the reverse stair-step structure.

20. The method of claim 18, wherein forming a depression comprises forming upper surfaces of some of the steps of the forward stair-step structure to be substantially coplanar with upper surfaces of some of the additional steps of the reverse stair-step structure.

21. The method of any one of claims 18 to 20, wherein forming recessed structures comprises:

forming each of the steps of the forward stair step structure to individually include horizontal ends of groups of at least two of the layers of the preliminary stacked structure; and

forming each of the additional steps of the inverted stair-step structure to include horizontal ends of an additional group of at least two of the layers of the preliminary stacked structure, the additional group sharing at least one of the layers of the preliminary stacked structure with the group.

22. A memory device, comprising:

a stacked structure having layers each including a conductive structure and an insulating structure vertically adjacent to the conductive structure;

-lowered structures positioned at vertical depths different from each other within the stacked structure, each of the lowered structures comprising:

a forward stair step structure having steps comprising horizontal ends of the groups of layers; and

a reverse stair step structure opposite the forward stair step structure and having additional steps comprising additional horizontal ends of the group of the layers;

conductive contact structures extending vertically from at least some of the conductive structures of the stacked structure at the step and the additional step of the depression, the conductive contact structures each being integral and continuous with one of the conductive structures; and

a memory cell string extending vertically through the stacked structure.

23. The memory device of claim 22, wherein:

the stacked structure is divided into an array of blocks, adjacent blocks of the array of blocks being separated from each other by dielectric-filled slots in a first horizontal direction and each extending in a second horizontal direction orthogonal to the first horizontal direction; and is

The depressions are individually divided between two or more of the adjacent blocks of the array of blocks, the dielectric-filled slots being horizontally interposed between different sections of the depressions.

24. The memory device of claim 23, wherein at least some blocks of the array of blocks individually comprise wordline bridge regions extending horizontally from and between segments of some of the recessed structures that are horizontally adjacent to each other in the first horizontal direction.

25. The memory device of any one of claims 22-24, further comprising:

a data line overlying the stacked structure and electrically coupled to the string of memory cells;

a source structure underlying the stack structure and electrically coupled to the string of memory cells;

access lines electrically coupled to the conductive contact structures; and

a control device electrically coupled to the source structure, the data line, and the access line.

26. An electronic system, comprising:

an input device;

an output device;

a processor device operably coupled to the input device and the output device; and

a memory device operably coupled to the processor device and comprising at least one microelectronic device structure, the microelectronic device structure comprising:

a stacked structure comprising a vertically alternating sequence of conductive structures and insulating structures arranged in layers;

a recessed structure within the stacked structure and comprising opposing stepped structures each having a step comprising an edge of at least some of the layers; and

conductive contact structures integral with and continuous with at least some of the conductive structures of the stacked structure at the steps of the opposing stair step structures of the recessed structure, each of the conductive contact structures individually having an inner horizontal boundary substantially coplanar with an inner horizontal boundary of one of the steps of the opposing stair step structures.

Technical Field

In various embodiments, the present disclosure relates generally to the field of microelectronic device design and fabrication. More particularly, the present disclosure relates to microelectronic devices including recessed structures, and related methods, memory devices, and electronic systems.

Background

A continuing goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize a vertical memory array (also referred to as a "three-dimensional (3D) memory array") architecture. Conventional vertical memory arrays include vertical memory strings that extend through openings in one or more stacked structures that include conductive structures and layers of dielectric material. Each vertical memory string may include at least one select device coupled in series with a series combination of vertically stacked memory cells. This configuration permits a greater number of switching devices (e.g., transistors) to be located in a unit of die area (i.e., length and width of active surface consumed) by building an array up (e.g., vertically) on the die, as compared to structures with conventional planar (e.g., two-dimensional) transistor arrangements.

Vertical memory array architectures generally include electrical connections between conductive structures and access lines (e.g., word lines) of layers of a stacked structure of a memory device such that memory cells of the vertical memory array can be selected exclusively for write, read, or erase operations. One method of forming such electrical connections includes forming so-called "stair-step" (or "stair-step") structures at the edges (e.g., horizontal ends) of the layers of the stacked structure of the memory device. The stair-step structure includes individual "steps" defining contact regions of conductive structures on which conductive contact structures may be positioned to provide electrical access to the conductive structures.

As vertical memory array technology evolves, additional memory density has been provided by forming vertical memory arrays to include additional layers of conductive structures and, thus, additional steps in the staircase structure associated therewith. However, increasing the number of steps of the stair-step structure without undesirably increasing the overall width (e.g., horizontal footprint) of the stair-step structure reduces the acceptable error margin associated with different actions in forming the increased number of steps. A conventional process of forming a stair-step structure may include the following acts: the method includes the steps of trimming a uniform width of a mask (e.g., photoresist) overlying alternating conductive and insulating structures, etching portions of the insulating structures not covered by remaining portions of the mask, and then etching portions of the conductive structures not covered by remaining portions of the insulating structures. Each of these repetitive actions has an associated error tolerance permitting the steps of the stair-step structure to be appropriately sized and positioned to form a contact structure thereon. As the number of repetitive actions increases, deviations from the desired step width and/or the desired step position may be accommodated, as errors in the size and/or position of one structure are transferred later in the process to subsequently formed structures. For a large number of steps in a stepped structure, the error tolerance for achieving a suitably sized and positioned step may be small, e.g., less than one percent (1%). Achieving such small error margins using conventional methods can be extremely difficult, can result in improperly positioned contact structures and can undesirably reduce yield (e.g., the number of properly programmable and erasable memory cells as a percentage of the total number of memory cells in a given lot). In addition, as feature packing density has increased and the margin for formation errors has decreased, conventional configurations have resulted in undesirable defects (e.g., contact punch-through) as well as current leakage and shorting, which can impair desired memory device performance, reliability, and endurance.

Accordingly, there is a continuing need for new microelectronic device (e.g., memory devices, such as 3D NAND flash memory devices) configurations to facilitate increased memory density while alleviating the problems of conventional microelectronic device configurations, and for new methods of forming microelectronic devices and new electronic systems including the new microelectronic device configurations.

Disclosure of Invention

According to an embodiment of the present disclosure, a microelectronic device includes a stack structure, a depression within the stack structure, and a conductive contact structure. The stacked structure includes a vertically alternating sequence of conductive structures and insulating structures arranged in layers. Each of the layers includes one of the conductive structures and one of the insulating structures. The low-lying structure includes: a forward stair step structure having a step comprising an edge of the layer; and a reverse stair step structure opposite the forward stair step structure and having an additional step comprising an additional edge of the layer. The conductive contact structure extends vertically at the step of the forward stair-step structure and the additional step of the reverse stair-step structure to an upper vertical boundary of at least some of the conductive structures of the stacked structure. The conductive contact structures are each integral and continuous with one of the conductive structures.

According to additional embodiments of the present disclosure, a method of forming a microelectronic device includes forming a preliminary stacked structure including a vertically alternating sequence of insulating structures and additional insulating structures arranged in layers. Each of the layers includes one of the insulating structures and one of the additional insulating structures. The trenches are formed to extend vertically into the preliminary stacked structure. A horizontally alternating sequence of dielectric spacer structures and dielectric liner structures is formed within the horizontal boundaries of the trench. At least some of the dielectric liner structures physically contact insulating structures of the preliminary stack structures that are different from one another. The dielectric material of the dielectric liner structure and the insulating structure of the preliminary stack structure are at least partially replaced by a conductive material.

According to other embodiments of the present disclosure, a memory device includes a stack structure, a depression structure, a conductive contact structure, and a memory cell string. The stacked structure has several layers each including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The lowered structures are positioned at different vertical depths from each other within the stacked structure. Each of the low-lying structures includes: a forward stair step structure having steps comprising horizontal ends of a group of layers; and an inverted stair step structure opposite the forward stair step structure and having additional steps comprising additional horizontal ends of the group of layers. Conductive contact structures extend vertically from at least some of the conductive structures of the stacked structure at the steps of the depression structure and the additional steps. The conductive contact structures are each integral and continuous with one of the conductive structures. The memory cell string extends vertically through the stacked structure.

According to still other embodiments of the present disclosure, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device. The memory device includes a microelectronic device structure including a stack structure, a depression structure, and a conductive contact structure. The stacked structure includes a vertically alternating sequence of conductive structures and insulating structures arranged in layers. The depression is within the stacked structure and includes opposing stepped structures each having a step including an edge of at least some of the layers. The conductive contact structure is integral and continuous with at least some of the conductive structures of the stacked structure at the step of the opposing step structure of the depression structure. Each of the conductive contact structures individually has an inner horizontal boundary that is substantially coplanar with an inner horizontal boundary of one of the steps of the opposing stair step structure.

Drawings

Fig. 1A through 1L are simplified partial cross-sectional views illustrating a method of forming a microelectronic device, according to an embodiment of the present disclosure.

Fig. 2 is a simplified top view of a microelectronic device according to an embodiment of the present disclosure.

Fig. 3 is a simplified top view of a microelectronic device, according to additional embodiments of the present disclosure.

Fig. 4A-4C are simplified partial cross-sectional views illustrating methods of forming microelectronic devices, according to additional embodiments of the present disclosure.

Fig. 5A-5G are simplified partial cross-sectional views illustrating methods of forming microelectronic devices, according to additional embodiments of the present disclosure.

Fig. 6 is a schematic block diagram illustrating an electronic system according to an embodiment of the present disclosure.

Detailed Description

The following description provides specific details such as material compositions, shapes and sizes in order to provide a thorough description of embodiments of the present disclosure. However, it will be understood by those of ordinary skill in the art that the embodiments of the present disclosure may be practiced without these specific details. Indeed, embodiments of the present disclosure may be practiced in conjunction with conventional microelectronic device fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for fabricating microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices). The structures described below do not form complete microelectronic devices. Only those process actions and structures necessary for an understanding of the embodiments of the present disclosure are described in detail below. Additional acts to form a complete microelectronic device from the structure may be performed by conventional fabrication techniques.

The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes or regions as illustrated, but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box-shaped may have rough and/or non-linear features, and a region illustrated or described as circular may include some rough and/or linear features. Further, the illustrated acute angles may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims. The drawings are not necessarily to scale. In addition, common elements between the drawings may retain the same numerical designation.

As used herein, the term "memory device" means and includes a microelectronic device that exhibits memory functionality, but is not necessarily limited to memory functionality. In other words and by way of non-limiting example only, the term "memory device" includes not only conventional memory (e.g., conventional volatile memory such as conventional Dynamic Random Access Memory (DRAM); conventional non-volatile memory such as conventional NAND memory), but also Application Specific Integrated Circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic device combinational logic and memory, and Graphics Processing Units (GPUs) that incorporate memory.

As used herein, the terms "vertical", "longitudinal", "horizontal" and "lateral" refer to the major plane of a structure and are not necessarily defined by the earth's gravitational field. A "horizontal" or "lateral" direction is a direction substantially parallel to the major plane of the structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to the major plane of the structure. The main plane of the structure is defined by the surface of the structure having a relatively large area compared to the other surfaces of the structure.

As used herein, features (e.g., regions, structures, devices) that are described as "adjacent" to one another refer to and encompass the features of the disclosed identity (or identities) that are located in closest proximity (e.g., closest proximity) to one another. Additional features (e.g., additional regions, additional structures, additional devices) that do not match the disclosed identity (or identities) of "neighboring" features may be disposed between the "neighboring" features. In other words, "adjacent" features may be positioned directly adjacent to each other such that no other feature is interposed between the "adjacent" features; or "neighboring" features may be positioned in indirect proximity to each other such that at least one feature having an identity other than the identity associated with the at least one "neighboring" feature is positioned between the "neighboring" features. Thus, features described as being "vertically adjacent" to each other refer to and encompass features of the disclosed identity (or identities) that are located in vertically closest proximity (e.g., vertically closest) to each other. Further, features described as "horizontally adjacent" to each other refer to and encompass features of the disclosed identity (or identities) that are located horizontally closest (e.g., horizontally closest) to each other.

As used herein, the terms "comprising," "including," "having," and grammatical equivalents thereof are inclusive or open-ended terms that do not exclude additional unlisted elements or method steps, and also include the more limiting terms "consisting of …" and "consisting essentially of …" and grammatical equivalents thereof. As used herein, the term "may" with respect to materials, structures, features, or method acts indicates that such materials, structures, features, or method acts are contemplated for practicing embodiments of the present disclosure, and preferably such terms are used rather than the more limiting term "is" in order to avoid any implication that other compatible materials, structures, features, and methods may be used in combination therewith, should or must be excluded.

As used herein, spatially relative terms, such as "below," "lower," "bottom," "above," "upper," "top," "front," "rear," "left," "right," and the like, may be used for convenience in describing the relationship of one element or feature to another element or feature, as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of the material in addition to the orientation depicted in the figures. For example, if the materials in the figures are reversed, elements described as "below," "beneath," "under," or "on the bottom" other elements or features would then be oriented "above," or "on the top" of the other elements or features. The term "below" may thus encompass both an orientation of above and below, depending on the context in which the term is used, as will be apparent to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, or flipped) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one apparatus in order to facilitate the operation of one or more of the structure and the apparatus in a predetermined manner.

As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes the extent to which the given parameter, property, or condition satisfies a variance (e.g., within an acceptable manufacturing tolerance) as would be understood by one of ordinary skill in the art. By way of example, depending on the particular parameter, characteristic, or condition being substantially met, the parameter, characteristic, or condition may meet at least 90.0%, may meet at least 95.0%, may meet at least 99.0%, may meet at least 99.9%, or even meet 100.0%.

As used herein, reference to "about" or "approximately" a value of a particular parameter includes the value, and a person of ordinary skill in the art will appreciate that the degree of deviation from the value is within an acceptable tolerance of the particular parameter. For example, "about" or "approximately" with respect to a value may include an additional value that is in the range of 90.0 percent to 110.0 percent of the value, such as in the range of 95.0 percent to 105.0 percent of the value, in the range of 97.5 percent to 102.5 percent of the value, in the range of 99.0 percent to 101.0 percent of the value, in the range of 99.5 percent to 100.5 percent of the value, or in the range of 99.9 percent to 100.1 percent of the value.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable process including, but not limited to, spin-on coating, blanket coating, chemical vapor deposition ("CVD"), atomic layer deposition ("ALD"), plasma enhanced ALD, physical vapor deposition ("PVD") (including sputtering, evaporation, ionized PVD, and/or plasma enhanced CVD), or epitaxial growth. Depending on the particular material to be formed, the techniques for depositing or growing the material may be selected by one of ordinary skill in the art. Furthermore, unless the context indicates otherwise, the material removal described herein may be achieved by any suitable process including, but not limited to, etching (e.g., dry etching, wet etching, vapor phase etching), ion milling (ion milling), mill planarization, or other known methods.

Fig. 1A-1L are simplified partial cross-sectional views illustrating an embodiment of a method of forming a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device). It will be apparent to those of ordinary skill in the art, in conjunction with the description provided below, that the methods and structures described herein may be used in a variety of devices and electronic systems.

Referring to fig. 1A, a microelectronic device structure 100 may be formed to include a preliminary stacked structure 102, and a patterned mask structure 110 on or over the preliminary stacked structure 102. The preliminary stacked structure 102 includes a vertically alternating (e.g., in the Z-direction) sequence of first insulating structures 104 and second insulating structures 106 arranged in layers 108. Each of the layers 108 of the preliminary stacked structure 102 may include at least one of the first insulating structures 104 vertically adjacent to at least one of the second insulating structures 106. The preliminary stacked structure 102 may be formed to include any desired number of layers 108, such as greater than or equal to sixteen (16) layers 108, greater than or equal to thirty-two (32) layers 108, greater than or equal to sixty-four (64) layers 108, greater than or equal to one hundred twenty-eight (128) layers 108, or greater than or equal to two hundred fifty-six (256) layers 108.

The first insulating structure 104 of the layer 108 of the preliminary stacked structure 102 may be formed of at least one dielectric material and include at least oneA dielectric material, such as at least one dielectric oxide material (e.g., silicon oxide (SiO)_x) Phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, alumina (AlO)_x) Hafnium oxide (HfO)_x) Niobium oxide (NbO)_x) Titanium oxide (TiO)_x) Zirconium oxide (ZrO)_x) Tantalum oxide (TaO)_x) And magnesium oxide (MgO)_x) One or more of (a), at least one dielectric nitride material (e.g., silicon nitride (SiN))_y) At least one dielectric oxynitride material (e.g., silicon oxynitride (SiO))_xN_y) And at least one dielectric carbooxynitride material (e.g., silicon oxycarbonitride (SiO))_xC_zN_y) ) of the plurality of groups. Chemical formulas herein including one or more of "x", "y", and "z" (e.g., SiO_x，AlO_x，HfO_x，NbO_x，TiO_x，SiN_y，SiO_xN_y，SiO_xC_zN_y) A material that contains the average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) to each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Since the chemical formula represents relative atomic ratios versus relaxed chemical structure, the insulating structure 104 may include one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and the values of "x", "y", and "z" (if present) may or may not be integers. As used herein, the term "non-stoichiometric compound" means and includes compounds having an elemental composition that cannot be represented by a well-defined ratio of natural numbers and violates the law of definite ratios and the law of multiple ratios. Each of the first insulating structures 104 may individually comprise at least one insulating material that is substantially uniformly distributed or substantially non-uniformly distributed. As used herein, the term "homogeneously distributed" means that the amount of material does not change throughout different portions of the structure (e.g., different horizontal portions, different vertical portions). Conversely, as used herein, the term "heterogeneous distribution" means that the amount of material varies throughout different portions of the structure. In thatIn some embodiments, each of the first insulating structures 104 exhibits a substantially homogeneous distribution of electrically insulating material. In further embodiments, at least one of the first insulating structures 104 exhibits a substantially heterogeneous distribution of at least one electrically insulating material. One or more of the first insulating structures 104 may be formed of and include a stack (e.g., a laminate) of at least two different electrically insulating materials (e.g., at least two different dielectric materials), for example. In some embodiments, each of the first insulating structures 104 is formed of and includes a dielectric nitride material, such as SiN_y(e.g., Si)₃N₄). The first insulating structures 104 may each be substantially planar, and may each individually exhibit a desired thickness. Additionally, each of the first insulating structures 104 may be substantially identical to each other (e.g., exhibit substantially the same material composition, material distribution, size, and shape), or at least one of the first insulating structures 104 may be different from at least one other insulating structure in the first insulating structures 104 (e.g., exhibit one or more of a different material composition, a different material distribution, a different size, and a different shape). In some embodiments, each of the first insulating structures 104 is substantially identical to each other insulating structure in the first insulating structures 104.

The second insulating structure 106 of the layer 108 of the preliminary stacked structure 102 may be formed of and comprise at least one additional electrically insulating material. The material composition of the second insulating structure 106 and the first insulating structure 104 may be selected such that the first insulating structure 104 and the second insulating structure 106 may be selectively removed with respect to each other. The second insulating structure 106 may be selectively etchable relative to the first insulating structure 104 during common (e.g., collective, mutual) exposure to a first etchant, and the first insulating structure 104 may be selectively etchable relative to the second insulating structure 106 during common exposure to a second, different etchant. As used herein, a material is relative to another material if the material exhibits an etch rate that is at least about five times (5x), such as about ten times (10x), about twenty times (20x), or about forty times (40x), greater than the etch rate of the other materialThe material is "selectively etchable". The material composition of the second insulating structure 106 is different from the material composition of the first insulating structure 104. The second insulating structure 106 may comprise an additional electrically insulating material, such as at least one dielectric oxide material (e.g., SiO)_xPhosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO_x、HfO_x、NbO_x、TiO_x、ZrO_x、TaO_xAnd MgO_xOne or more of (a), at least one dielectric nitride material (e.g., SiN)_y) At least one dielectric oxynitride material (e.g., SiO)_xN_y) And at least one dielectric oxycarbonitride material (e.g., SiO)_xC_zN_y) One or more of (a). In some embodiments, each of the second insulating structures 106 is formed of and includes a dielectric oxide material, such as SiO_x(e.g., SiO)₂). Each of the second insulating structures 106 may individually comprise a substantially homogeneous distribution of the at least one additional electrically insulating material or a substantially heterogeneous distribution of the at least one additional electrically insulating material. In some embodiments, each of the second insulating structures 106 of the preliminary stack structure 102 exhibits a substantially homogeneous distribution of additional electrically insulating material. In additional embodiments, at least one of the second insulating structures 106 of the preliminary stacked structure 102 exhibits a substantially heterogeneous distribution of at least one additional electrically insulating material. The second insulating structure 106 may, for example, be individually formed of and include a stack (e.g., a laminate) of at least two different additional electrically insulating materials. The second insulating structures 106 may each be substantially planar, and may each individually exhibit a desired thickness.

With continued reference to fig. 1A, the patterned mask structure 110 may be formed of and include at least one material (e.g., at least one hard mask material) suitable for use as an etch mask to pattern portions of the preliminary stack structure 102 (e.g., portions of the layer 108, including portions of the first insulating structure 104 and portions of the second insulating structure 106) to form apertures (e.g., openings, vias, trenches) extending vertically (e.g., in the Z-direction) into the preliminary stack structure 102, as described in further detail below. By way of non-limiting example, the patterned mask structure 110 may be formed of and include one or more hard mask materials having etch selectivity relative to the material of the preliminary stack structure 102 (including the first and second insulating structures 104, 106). In some embodiments, the patterned mask structure 110 comprises polysilicon. The patterned mask structure 110 may be homogeneous (e.g., may comprise only one material layer), or may be heterogeneous (e.g., may comprise a stack exhibiting at least two different material layers). In addition, the patterned mask structure 110 may exhibit any thickness that permits the desired patterning of the preliminary stack structure 102 using the patterned mask structure 110, such as a thickness in a range from about 1 nanometer (nm) to about 1000 nm.

As shown in fig. 1A, the patterned mask structure 110 may include at least one opening 112 (e.g., aperture, via) extending vertically therethrough. The opening 112 may extend vertically (e.g., in the Z-direction) completely through the patterned mask structure 110, from an upper surface of the patterned mask structure 110 to an upper surface of the preliminary stack structure 102 (e.g., an upper surface of the second insulating structure 106 of the uppermost layer 108 of the preliminary stack structure 102).

The patterned mask structure 110 may be formed to exhibit any desired amount of openings 112. The amount of openings 112 included in the patterned mask structure 110 may depend, at least in part, on the desired amount and distribution of trenches to be formed in the preliminary stacked structure 102 using the patterned mask structure 110, which in turn may depend, at least in part, on the amount of the layer 108 included below the patterned mask structure 110. In some embodiments, the patterned mask structure 110 is formed to include a plurality (e.g., more than one) of openings 112.

The geometric configuration (e.g., shape, size), horizontal position (e.g., in the X-direction, in the Y-direction), and horizontal spacing of each opening 112 in the patterned mask structure 110 depends, at least in part, on the geometric configuration, horizontal position, and horizontal spacing of trenches that will be subsequently formed in the preliminary stacked structure 102 using the patterned mask structure 110, as described in further detail below. In some embodiments, each opening 112 exhibits substantially the same geometric configuration (e.g., substantially the same shape and substantially the same size) as each other opening 112, is regularly (e.g., uniformly, nonvariably) horizontally spaced (e.g., horizontally separated, horizontally spaced) from horizontally adjacent openings 112, and is substantially horizontally aligned with horizontally adjacent openings 112 in at least one horizontal direction. In additional embodiments, at least one opening 112 in the patterned mask structure 110 exhibits one or more of a different geometric configuration (e.g., a different shape, such as a non-rectangular horizontal cross-sectional shape), a different horizontal dimension, and/or a different horizontal pitch than at least one other opening 112. For example, at least one opening 112 may exhibit a different (e.g., larger, smaller) width in the X-direction and/or a different length in the Y-direction than at least one other opening 112. As another example, some horizontally adjacent openings 112 may be horizontally separated from each other by a first distance, and other horizontally adjacent openings 112 may be horizontally separated from each other by a second distance that is different from (e.g., less than, greater than) the first distance.

Referring next to fig. 1B, portions of at least one upper layer 108 (e.g., uppermost layer, top layer, uppermost layer in the Z-direction) of the preliminary stacked structure 102 exposed by the openings 112 in the patterned mask structure 110 may be removed to expose portions of the preliminary stacked structure 102 that are vertically underlying (e.g., vertically adjacent) to a relatively lower layer 108 (e.g., the second highest layer in the Z-direction) of the upper layer 108. The removal process may partially remove the second insulating structure 106 of the upper layer 108 and portions of the first insulating structure 104 exposed by the openings 112 in the patterned mask structure 110 to expose (e.g., expose) portions of the second insulating structure 106 that vertically underlie the relatively lower layer 108 of the upper layer 108.

As shown in fig. 1B, after the removal process, the remaining portion of the upper layer 108 of the preliminary stack structure 102 exposed within the opening 112 may terminate (e.g., end) at or substantially near a horizontal centerline 114 (e.g., in the X-direction) of the opening 112 in the patterned mask structure 110. Thus, newly exposed portions of the relatively lower layer 108 may beExtending horizontally (e.g., in the X-direction) from and between a horizontal centerline 114 and an outer horizontal boundary (e.g., in the X-direction) of the opening 112 in the patterned mask structure 110. In other words, after the removal process, the first width W of the remaining portion of the upper layer 108 of the preliminary stack structure 102 exposed within the opening 112₁May be substantially equal to the second width W of a newly exposed portion of a relatively lower layer 108 vertically underlying the upper layer 108₂. In additional embodiments, the remaining portion of the upper layer 108 of the preliminary stack structure 102 exposed within the opening 112 may terminate at a location that is horizontally offset (e.g., along the X-direction) from a horizontal centerline 114 (e.g., along the X-direction) of the opening 112 in the patterned mask structure 110. In such embodiments, a first width W of a remaining portion of upper layer 108 of preliminary stack structure 102 exposed within opening 112₁Can be different (e.g., greater than, less than) the second width W of a newly exposed portion of a relatively lower layer 108 vertically underlying the upper layer 108₂。

The portions of the upper layer 108 of the preliminary stack structure 102 that are exposed within the openings 112 in the patterned mask structure 110 may be removed using a conventional material removal process (e.g., a conventional photolithographic patterning process; a conventional etching process, such as a conventional anisotropic etching process), which is not described in detail herein.

Referring next to fig. 1C, the microelectronic device structure 100 may be subjected to one or more material removal processes (e.g., one or more cutting processes) to form at least one trench 116 (e.g., an opening, a blind via) extending vertically (e.g., in the Z-direction) into the preliminary stacked structure 102. As shown in fig. 1C, the trenches 116 within the preliminary stack structure 102 may be substantially confined within the horizontal boundaries of the openings 112 within the patterned mask structure 110. In embodiments in which the patterned mask structure 110 includes a plurality of openings 112, different trenches 116 may be formed to extend to different vertical depths from one another within the preliminary stacked structure 102. For example, at least one of the trenches 116 may extend vertically to a relatively lower depth within the preliminary stacked structure 102 than at least one other of the trenches 116. The vertical depth of the trenches 116 relative to each other may depend at least in part on the amount of layers 108 of the preliminary stacked structure 102, the amount of trenches 116 within the preliminary stacked structure 102, and the horizontal dimensions of the trenches 116. The trenches 116 may be configured to facilitate subsequent formation of vertically extending insulating structures in physical contact with at least some (e.g., each) of the layers 108 of the preliminary stacked structure 102, as described in further detail below.

As shown in fig. 1C, the trench 116 may include a first region 116A and a second region 116B. The second region 116B of the trench 116 may extend vertically (e.g., in the Z-direction) to a relatively lower depth within the preliminary stacked structure 102 than the first region 116A of the trench 116. For example, a first region 116A of the trench 116 extends vertically to and terminates at a relatively higher level 108 of the preliminary stacked structure 102; and the second region 116B of the trench 116 may extend vertically to and terminate at the relatively lower layer 108 of the preliminary stacked structure 102. The relatively higher layer 108 of the preliminary stacked structure 102 and the relatively lower layer 108 of the preliminary stacked structure 102 may be vertically adjacent to each other within the preliminary stacked structure 102. The first region 116A of the trench 116 may have the first width W previously described with reference to fig. 1B₁(e.g., in the X-direction), and the second region 116B of the trench 116 may have the second width W previously described with reference to fig. 1B₂(e.g., in the X direction). The first region 116A of the trench 116 may be horizontally adjacent to the second region 116B of the trench 116.

The trench 116 may include a lower vertical boundary 118 (e.g., bottom layer) and a horizontal boundary 120 (e.g., sides). The lower vertical boundary 118 of the trench 116 may have a non-planar topography resulting from the different vertical depths of the first region 116A of the trench 116 and the second region 116B of the trench 116. For example, a first portion 118A of the lower vertical boundary 118 of the trench 116 may be defined by the vertical depth of the first region 116A of the trench 116, and a second portion 118B of the lower vertical boundary 118 of the trench 116 may be defined by the vertical depth of the first region 116A of the trench 116. The first portion 118A and the second portion 118B of the lower vertical boundary 118 of the trench 116 may each be substantially horizontally flat, but may be vertically offset from each other (e.g., in the Z-direction). The second portion 118B of the lower vertical boundary 118 of the trench 116 may be horizontally adjacent (e.g., in the X-direction) to the first portion 118A of the lower vertical boundary 118 of the trench 116. Additionally, as depicted in fig. 1C, the horizontal boundaries 120 of the trench 116 may be substantially vertically flat.

As shown in fig. 1C, the trench 116 may be formed to terminate vertically (e.g., end vertically) at the second insulating structure 106 of two different layers 108 of the preliminary stacked structure 102 (e.g., two vertically adjacent layers 108 of the preliminary stacked structure 102). For example, the first region 116A of the trench 116 may terminate vertically at the second insulating structure 106 of the relatively higher layer 108 of the preliminary stacked structure 102; and the second region 116B of the trench 116 may terminate vertically at the second insulating structure 106 of the relatively lower layer 108 of the preliminary stacked structure 102. In other words, a first portion 118A of the lower vertical boundary 118 of the trench 116 may be defined by exposed portions of the second insulating structure 106 of the relatively higher layer 108 of the preliminary stacked structure 102; and a second portion 118B of the lower vertical boundary 118 of the trench 116 may be defined by exposed portions of the second insulating structure 106 of the relatively lower layer 108 of the preliminary stacked structure 102. In additional embodiments, the trench 116 may be formed to terminate vertically at the first insulating structure 104 of two different layers 108 of the preliminary stacked structure 102 (e.g., two vertically adjacent layers 108 of the preliminary stacked structure 102). For example, the first region 116A of the trench 116 may terminate vertically at the first insulating structure 104 of the relatively higher layer 108 of the preliminary stacked structure 102; and the second region 116B of the trench 116 may terminate vertically at the first insulating structure 104 of the relatively lower layer 108 of the preliminary stacked structure 102. In other words, a first portion 118A of the lower vertical boundary 118 of the trench 116 may be defined by exposed portions of the first insulating structure 104 of the relatively higher layer 108 of the preliminary stacked structure 102; and a second portion 118B of the lower vertical boundary 118 of the trench 116 may be defined by exposed portions of the first insulating structure 104 of the relatively lower layer 108 of the preliminary stacked structure 102.

Referring next to fig. 1D, first dielectric spacer structures 122-1 may be formed within the openings 112 in the patterned mask structure 110 and the trenches 116 in the preliminary stack structure 102. The first dielectric spacer structure 122-1 may partially (e.g., less than completely) fill each of the opening 112 and the trench 116, and may be formed within horizontal boundaries (e.g., in the X-direction and the Y-direction) of the trench 116 (and thus the opening 112 in the patterned mask structure 110) on exposed surfaces of the patterned mask structure 110 and the preliminary stack structure 102. For example, as shown in fig. 1D, a first dielectric spacer structure 122-1 may be formed at (e.g., coplanar with) the horizontal boundary 120 of the trench 116 directly horizontally adjacent (e.g., horizontally above) the patterned mask structure 110 and the side surfaces of the preliminary stacked structure 102, and may also be formed vertically adjacent (e.g., vertically above) the upper surface of the layer 108 of the preliminary stacked structure 102, defining the lower vertical boundary 118 (fig. 1C, including the first portion 118A and the second portion 118B thereof) of the trench 116. The first dielectric spacer structure 122-1 may extend substantially vertically across (e.g., in the Z-direction) and cover side surfaces of the patterned mask structure 110 and the preliminary stack structure 102 at (e.g., coplanar with) the horizontal boundary 120 of the trench 116, and may extend only partially horizontally across (e.g., in the X-direction and the Y-direction) and cover an upper surface of the layer 108 of the preliminary stack structure 102 to define the lower vertical boundary 118 of the trench 116 (fig. 1C).

As shown in fig. 1D, the first dielectric spacer structure 122-1 may include a first portion 122-1A and a second portion 122-1B. The first portion 122-1A may be formed within the horizontal boundaries of the first region 116A of the trench 116 and the second dielectric spacer structure 122-2 may be formed within the horizontal boundaries of the second region 116B of the trench 116. The second portion 122-1B may extend vertically (e.g., in the Z direction) to a lower vertical depth than the first portion 122-1A. The vertical depth of the first portion 122-1A may correspond to (e.g., be substantially the same as) the vertical depth of the first region 116A of the trench 116; and the vertical depth of the second portion 122-1B may correspond to (e.g., be substantially the same as) the vertical depth of the second region 116B of the trench 116. For example, the first portion 122-1A may extend vertically to and terminate at a relatively higher level 108, defining a first portion 118A (fig. 1C) of the lower vertical boundary 118 (fig. 1C) of the trench 116; and a second portion 122-1B may extend vertically to and terminate at a second portion 118B (fig. 1C) of the relatively lower layer 108, defining a lower vertical boundary 118 (fig. 1C) of the trench 116.

The first dielectric spacer structure 122-1 may be formed to exhibit a third width W₃(for example,in the X direction). Third width W₃May depend, at least in part, on the overall width of trench 116 (e.g., first width W described previously with reference to fig. 1C₁And a second width W₂Combinations of) and the desired configuration of the recessed structures to be formed within the horizontal boundaries of the trenches 116, as described in further detail below. By way of non-limiting example, the third width W₃May be in the range of from about 25 nanometers (nm) to about 500 nm.

The first dielectric spacer structure 122-1 may be formed of and include at least one dielectric material having a different etch selectivity from the first insulation structure 104 of the preliminary stack structure 102. The first dielectric spacer structure 122-1 may, for example, have a selective etch of the second insulating structure 106 substantially similar to the preliminary stack structure 102. Portions of the first dielectric spacer structure 122-1 may be used to protect (e.g., shield) portions of the preliminary stack structure 102 during subsequent processing acts (e.g., subsequent material removal acts, such as subsequent etching acts), as described in further detail below. By way of non-limiting example, the first dielectric spacer structure 122-1 may be formed from and include at least one oxygen-containing dielectric material, such as one or more of: dielectric oxide materials (e.g., SiO)_xPhosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO_x、HfO_x、NbO_xAnd TiO_xOne or more of (a), a dielectric oxynitride material (e.g., SiO)_xN_y) And dielectric oxycarbonitride materials (e.g., SiO)_xC_zN_y). The material composition of the first dielectric spacer structure 122-1 may be different from the material composition of the first insulating structure 104 of the preliminary stack structure 102. The material composition of the first dielectric spacer structure 122-1 may be substantially the same as or may be different from the material composition of the second insulating structure 106 of the preliminary stack structure 102. In some embodiments, the first dielectric spacer structure 122-1 is made of SiO_x(e.g., SiO)₂) Formed and comprising SiO_x。

The first dielectric spacer structures 122-1 may be formed by conformally forming (e.g., by one or more of a conventional ALD process and a conventional conformal CVD process) a dielectric material (e.g., a dielectric oxide material) inside and outside the trenches 116 on or over surfaces of the preliminary stack structure 102 and the patterned mask structure 110. Subsequently, the microelectronic device structure 100 may be subjected to at least one material removal (e.g., etching, such as anisotropic dry etching) process to form the first dielectric spacer structure 122-1 (including the first and second portions 122-1A and 122-1B thereof). The material removal process may substantially (e.g., completely) remove portions of the dielectric material outside the trenches 116 on or over the upper surfaces of the patterned mask structures 110, and may partially remove portions of the dielectric material at the lower vertical boundaries 118 (fig. 1C) of the trenches 116 on or over the surfaces of the preliminary stack structures 102. As shown in fig. 1D, the material removal process may also remove portions of the second insulating structure 106 of the layer 108 of the preliminary stacked structure 102 that define the lower vertical boundaries 118 (fig. 1C) of the trenches 116 to expose (e.g., expose) portions of the first insulating structure 104 of the layer 108 within the horizontal boundaries of the trenches 116. The exposed portion of the first insulating structure 104 of layer 108 may be horizontally bounded by the first dielectric spacer structure 122-1 within the horizontal boundaries of the trench 116.

Referring next to fig. 1E, a first dielectric liner structure 124-1 may be formed within the opening 112 in the patterned mask structure 110 and the remaining (e.g., unfilled) portion of the trench 116 in the preliminary stack structure 102. The first dielectric liner structure 124-1 may partially (e.g., less than completely) fill the remaining portions of each of the opening 112 and the trench 116, and may be formed within the horizontal boundaries (e.g., in the X-direction and the Y-direction) of the trench 116 (and thus the opening 112 in the patterned mask structure 110) on the exposed surfaces of the first dielectric spacer structure 122-1 and the preliminary stack structure 102. For example, the first dielectric liner structure 124-1 may be formed directly horizontally adjacent (e.g., horizontally on) the inside surface of the first dielectric spacer structure 122-1 (including the first and second portions 122-1A and 122-1B thereof), and the upper surface of the first insulating structure 104 of the layer 108 of the preliminary stacked structure 102 may also be formed directly vertically adjacent (e.g., vertically on) at the modified lower vertical boundary of the trench 116 formed in the processing stage previously described with reference to fig. 1D. The first dielectric liner structure 124-1 may extend substantially vertically across (e.g., in the Z-direction) and cover an inside surface of the first dielectric spacer structure 122-1.

As shown in fig. 1E, the first dielectric liner structure 124-1 may include a first portion 124-1A and a second portion 124-1B. The first portion 124-1A may be formed within the horizontal boundaries of the first region 116A of the trench 116 and the second dielectric liner structure 124-2 may be formed within the horizontal boundaries of the second region 116B of the trench 116. The first portion 124-1A may be formed directly horizontally adjacent to (e.g., horizontally above) the first portion 122-1A of the first dielectric spacer structure 122-1, and the second portion 124-1B may be formed directly horizontally adjacent to (e.g., horizontally above) the second portion 122-1B of the first dielectric spacer structure 122-1. The second portion 124-1B of the first dielectric liner structure 124-1 may extend vertically (e.g., in the Z-direction) to a vertical depth within the preliminary stack structure 102 that is relatively lower than the vertical depth of the first portion 124-1A of the first dielectric liner structure 124-1. The vertical depth of the first portion 124-1A of the first dielectric liner structure 124-1 may be greater than or equal to the vertical depth of the first portion 122-1A of the first dielectric spacer structure 122-1; and the vertical depth of the second portion 124-1B of the first dielectric liner structure 124-1 may be greater than or equal to the vertical depth of the second portion 122-1B of the first dielectric spacer structure 122-1. For example, the first portion 124-1A of the first dielectric liner structure 124-1 may extend vertically to and terminate at the first insulating structure 104 of the layer 108 of the preliminary stack structure 102 vertically adjacent to the lower vertical boundary of the first portion 122-1A of the first dielectric spacer structure 122-1; and the second portion 124-1B of the first dielectric liner structure 124-1 may extend vertically to and terminate at the first insulating structure 104 of another relatively lower layer 108 of the preliminary stack structure 102 vertically adjacent to the lower vertical boundary of the second portion 122-1B of the first dielectric spacer structure 122-1.

The first dielectric liner structure 124-1 may be formed to exhibit a fourth width W₄(e.g., in the X direction). A fourth width W₄May, for example, be substantially equal to the vertical height (e.g., in the Z-direction) of each of the first insulating structures 104 of the preliminary stacked structure 102. In additional embodiments, the fourth width W₄Different from (e.g., smaller than, larger than) the vertical height of one or more (e.g., each) of the first insulating structures 104 of the preliminary stacked structure 102.

The first dielectric liner structure 124-1 may be formed of and include at least one dielectric material having a different etch selectivity than the second insulating structure 106 of the preliminary stack structure 102. The first dielectric liner structure 124-1 may, for example, have an etch that is selective substantially similar to the first insulating structure 104 of the preliminary stack structure 102. By way of non-limiting example, if formed, the first dielectric liner structure 124-1 may be formed of at least one dielectric nitride material (e.g., SiN)_y) Forming and containing the at least one dielectric nitride material. The material composition of the first dielectric liner structure 124-1 may be different from the material composition of the first dielectric spacer structure 122-1 (fig. 1D) and the second insulating structure 106 of the preliminary stack structure 102. The material composition of the first dielectric liner structure 124-1 may be substantially the same as or may be different from the material composition of the first insulating structure 104 of the preliminary stack structure 102. In some embodiments, the first dielectric liner structure 124-1 is made of SiN_y(e.g., Si)₃N₄) Form and contain SiN_y。

The first dielectric liner structure 124-1 may be formed by conformally forming (e.g., by one or more of a conventional ALD process and a conventional conformal CVD process) additional dielectric material (e.g., a dielectric nitride material) on or over surfaces of the preliminary stack structure 102, the first dielectric spacer structure 122-1, and the patterned mask structure 110, inside and outside the trench 116. Subsequently, the microelectronic device structure 100 may be subjected to at least one material removal (e.g., etching, such as anisotropic dry etching) process to form the first dielectric liner structure 124-1 (including the first and second portions 124-1A and 124-1B thereof). The material removal process may substantially (e.g., completely) remove portions of the additional dielectric material on or over the upper surfaces of the patterned mask structure 110 and the first dielectric spacer structures 122-1, and may partially remove portions of the additional dielectric material on or over the surface of the preliminary stack structure 102 at the modified lower vertical boundaries of the trenches 116. As shown in fig. 1E, the material removal process may also remove portions of the first insulating structure 104 of the layer 108 of the preliminary stack structure 102 vertically adjacent to lower vertical boundaries of the first portion 122-1A and the second portion 122-1B of the first dielectric spacer structure 122-1 to expose (e.g., expose) portions of the second insulating structure 106 of the relatively vertically lower layer 108 within horizontal boundaries of the trench 116. The exposed portions of the second insulating structure 106 of the relatively vertical lower layer 108 may be horizontally bounded by the first dielectric liner structure 124-1 within the horizontal boundaries of the trench 116.

Referring next to fig. 1F, the microelectronic device structure 100 may be subjected to at least one additional material removal (e.g., etching, such as anisotropic dry etching) process to increase the vertical depth (e.g., in the Z-direction) of the remaining (e.g., unfilled) portions of the trench 116. The additional material removal process may increase the vertical depth of the remaining portions of the first region 116A of the trench 116, and may also increase the vertical depth of the remaining portions of the second region 116B of the trench 116. After the additional material removal process, the remaining portion of the second region 116B of the trench 116 may extend vertically to a relatively lower depth within the preliminary stacked structure 102 than the remaining portion of the first region 116A of the trench 116. The magnitude of the vertical offset between the lower vertical boundary of the first region 116A of the trench 116 and the lower vertical boundary of the second region 116B of the trench 116 may be substantially maintained at the end of the additional material removal process. For example, the additional material removal process may increase the vertical depth of each of the remaining portions of the first region 116A of the trench 116 and the remaining portions of the second region 116B of the trench 116 by a distance (e.g., in the Z-direction) that is substantially equal to the height (e.g., in the Z-direction) of a single (e.g., only one) layer 108 of the preliminary stacked structure 102. In other words, the additional material removal process may remove exposed portions of a single (e.g., only one) layer 108 of the preliminary stack structure 102 vertically adjacent to the modified lower vertical boundary of the first region 116A of the trench 116 at the end of the processing stage depicted in fig. 1E; and exposed portions of another single (e.g., only one) layer 108 of preliminary stacked structure 102 vertically adjacent to the modified lower vertical boundary of second region 116B of trench 116 at the end of the processing stage depicted in fig. 1E may also be removed.

As shown in fig. 1F, after the additional material removal process, remaining (e.g., unfilled) portions of the trench 116, including remaining portions of the first and second regions 116A, 116B thereof, may terminate vertically (e.g., end vertically) at the second insulating structures 106 of two different layers 108 of the preliminary stacked structure 102, e.g., two vertically adjacent layers 108 of the preliminary stacked structure 102. For example, the remaining portion of the first region 116A of the trench 116 may terminate vertically at the second insulating structure 106 of the relatively higher layer 108 of the preliminary stacked structure 102; and the remaining portion of the second region 116B of the trench 116 may terminate vertically at the second insulating structure 106 of the relatively lower layer 108 of the preliminary stacked structure 102. In additional embodiments, the remaining (e.g., unfilled) portions of the trench 116 may terminate vertically at the first insulating structures 104 of two different layers 108 of the preliminary stacked structure 102 (e.g., two vertically adjacent layers 108 of the preliminary stacked structure 102) after the additional material removal process. For example, the first region 116A of the trench 116 may terminate vertically at the first insulating structure 104 of the relatively higher layer 108 of the preliminary stacked structure 102; and the second region 116B of the trench 116 may terminate vertically at the first insulating structure 104 of the relatively lower layer 108 of the preliminary stacked structure 102.

Referring next to fig. 1G, a second dielectric spacer structure 122-2 may be formed within remaining (e.g., unfilled) portions of the opening 112 in the patterned mask structure 110 and in remaining deepened portions of the trench 116 in the preliminary stack structure 102. The second dielectric spacer structure 122-2 may partially (e.g., less than completely) fill the remaining portions of the opening 112 and the remaining deepened portions of the trench 116; and may be formed within the horizontal boundaries (e.g., in the X-direction and the Y-direction) of the trenches 116 (and thus the openings 112 in the patterned mask structure 110) on the exposed surfaces of the first dielectric liner structure 124-1 (fig. 1F) and the preliminary stack structure 102. For example, the second dielectric spacer structure 122-2 may be formed within the trench 116 directly horizontally adjacent to (e.g., horizontally above) the first dielectric liner structure 124-1 (fig. 1F, which includes the first portion 124-1A and the second portion 124-1B shown in fig. 1G) and the exposed interior side surfaces of the preliminary stacked structure 102, and may also be formed directly vertically adjacent to (e.g., vertically above) the upper surface of the second insulating structure 106 of the layer 108 of the preliminary stacked structure 102 at the modified lower vertical boundary of the trench 116 formed in the processing stage previously described with reference to fig. 1G. The second dielectric spacer structure 122-2 may extend substantially vertically across (e.g., in the Z-direction) and cover an inside surface of the first dielectric liner structure 124-1 (fig. 1F).

As shown in fig. 1G, the second dielectric spacer structure 122-2 may include a first portion 122-2A and a second portion 122-2B. The first portion 122-2A may be formed within the horizontal boundaries of the first region 116A of the trench 116 and the second portion 122-2B may be formed within the horizontal boundaries of the second region 116B of the trench 116. The first portion 122-2A of the second dielectric spacer structure 122-2 may be formed directly horizontally adjacent to (e.g., horizontally above) the first portion 124-1A of the first dielectric liner structure 124-1, and the second portion 122-2B may be formed directly horizontally adjacent to (e.g., horizontally above) the second portion 124-1B of the first dielectric liner structure 124-1. The second portion 122-2B of the second dielectric spacer structure 122-2 may extend vertically (e.g., in the Z-direction) to a lower vertical depth within the preliminary stacked structure 102 than the first portion 122-2A of the second dielectric spacer structure 122-2. The vertical depth of the first portion 122-2A of the second dielectric spacer structure 122-2 may be greater than the vertical depth of the first portion 124-1A of the first dielectric liner structure 124-1; and the vertical depth of the second portion 122-2B of the second dielectric spacer structure 122-2 may be greater than the vertical depth of the second portion 124-1B of the first dielectric liner structure 124-1. For example, a first portion 122-2A of the second dielectric spacer structure 122-2 may extend vertically to and terminate at the first insulating structure 104 of the relatively higher layer 108 of the preliminary stack structure 102; and a second portion 122-2B of the second dielectric spacer structure 122-2 may extend vertically to and terminate at the first insulating structure 104 of another relatively lower level 108 of the preliminary stacked structure 102 that is vertically adjacent to the relatively higher level 108 of the preliminary stacked structure 102.

In some embodiments, the second dielectric spacer structure 122-2 is formed to exhibit a third width W substantially equal to the first dielectric spacer structure 122-1 (FIG. 1D, including the first and second portions 122-1A and 122-1B shown in FIG. 1G)₃E.g., in the X direction). In additional embodiments, the second dielectric spacer structure 122-2 is formed to exhibit a third width W that is different from (e.g., greater than, less than)₃Is measured.

The second dielectric spacer structure 122-2 may be formed of and include at least one dielectric material having a different etch selectivity than the first insulating structure 104 and the first dielectric liner structure 124-1 (fig. 1F) of the preliminary stack structure 102. The second dielectric spacer structure 122-2 may, for example, have an etch that is selective substantially similar to the second insulating structure 106 and the first dielectric spacer structure 122-1 of the preliminary stack structure 102 (fig. 1D). By way of non-limiting example, the second dielectric spacer structure 122-2 may be formed from and include at least one oxygen-containing dielectric material, such as one or more of: dielectric oxide materials (e.g., SiO)_xPhosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO_x、HfO_x、NbO_xAnd TiO_xOne or more of (a), a dielectric oxynitride material (e.g., SiO)_xN_y) And dielectric oxycarbonitride materials (e.g., SiO)_xC_zN_y). The material composition of the second dielectric spacer structure 122-2 may be different from the material composition of the first insulating structure 104 and the first dielectric liner structure 124-1 (fig. 1F) of the preliminary stack structure 102. The material composition of the second dielectric spacer structure 122-2 may be substantially the same as or may be different from the material composition of the second insulating structure 106 and the first dielectric spacer structure 122-1 (fig. 1D) of the preliminary stack structure 102. In some embodiments, the second dielectric spacer structure 122-2 is made of SiO_x(e.g., SiO)₂) Formed and comprising SiO_x。

The second dielectric spacer structure 122-2 may be formed by conformally forming (e.g., by one or more of a conventional ALD process and a conventional conformal CVD process) a dielectric material (e.g., a dielectric oxide material) inside and outside the trench 116 on or over surfaces of the preliminary stack structure 102, the first dielectric spacer structure 122-1, the first dielectric liner structure 124-1, and the patterned mask structure 110. Subsequently, the microelectronic device structure 100 may be subjected to at least one material removal (e.g., etching, such as anisotropic dry etching) process to form the second dielectric spacer structure 122-2 (including the first and second portions 122-2A and 122-2B thereof). The material removal process may substantially (e.g., completely) remove portions of the dielectric material on or over the upper surfaces of the patterned mask structure 110, the first dielectric spacer structures 122-1, and the first dielectric liner structures 124-1; and portions of the dielectric material on or over the surface of the preliminary stack structure 102 at the modified lower vertical boundaries of the trenches 116 may be partially removed. As shown in fig. 1G, the material removal process may also remove portions of the second insulating structure 106 of the layer 108 of the preliminary stacked structure 102 defining the modified lower vertical boundary of the trench 116 to expose (e.g., expose) portions of the first insulating structure 104 of the layer 108 within the horizontal boundary of the trench 116. The exposed portion of the first insulating structure 104 of layer 108 may be horizontally bounded by the second dielectric spacer structure 122-2 within the horizontal boundaries of the trench 116.

Referring next to fig. 1H, after the processing stage described with reference to fig. 1G, the microelectronic device structure 100 may be subjected to additional processing acts similar to those previously described with reference to fig. 1E-1G to fill the remaining portions of the trench 116 (fig. 1G) with more dielectric liner structures 124 (e.g., in addition to the first dielectric liner structure 124-1) and more dielectric spacer structures 122 (e.g., in addition to the first dielectric spacer structure 122-1 and the second dielectric spacer structure 122-2) and form a lowland structure 126 vertically underlying and contacting the dielectric liner structure 124 and the dielectric spacer structures 122. As shown in fig. 1H, the recess 126 may comprise: a forward stair-step structure 128 comprising steps 132 including horizontal ends of the pairs of layers 108 of the preliminary stacked structure 102; an inverted stair-step structure 130 including an additional step 134 including horizontal ends of an additional pair of layers 108 of the preliminary stacked structure 102; and a central region 136 horizontally interposed between the forward stepped structure 128 and the reverse stepped structure 130. The central region 136 of the depression 126 may, for example, form an intersection region and a vertical end point for the forward step structure 128 and the reverse step structure 130. As described in further detail below, different dielectric spacer structures 122 and different dielectric liner structures 124 may be formed to physically contact mutually different steps 132 of the forward stepped structure 128 and mutually different additional steps 134 of the reverse stepped structure 130.

As shown in fig. 1H, the dielectric liner structure 124 (fig. 1G) formed within the horizontal boundary 120 of the trench 116 may comprise: a first dielectric liner structure 124-1 (including a first portion 124-1A and a second portion 124-1B thereof); a second dielectric liner structure 124-2 (including a first portion 124-2A and a second portion 124-2B thereof) that extends vertically relatively deeper into the preliminary stacked structure 102 than the first dielectric liner structure 124-1; a third dielectric liner structure 124-3 (including a first portion 124-3A and a second portion 124-3B thereof) that extends vertically relatively deeper into the preliminary stacked structure 102 than the second dielectric liner structure 124-2; and a fourth dielectric liner structure 124-4 (including a first portion 124-4A and a second portion 124-4B thereof) that extends vertically into the preliminary stacked structure 102 relatively deeper than the third dielectric liner structure 124-3. In additional embodiments, different amounts of dielectric liner structures 124 are formed within the horizontal boundaries 120 of the trenches 116 (fig. 1G). For example, greater than four (4) of the dielectric liner structures 124 (e.g., greater than or equal to ten (10), greater than or equal to twenty (20), greater than or equal to fifty (50)) may be formed within the horizontal boundaries 120 of the trenches 116 (fig. 1G), or less than four (4) of the dielectric liner structures 124 may be formed within the horizontal boundaries 120 of the trenches 116 (fig. 1G). The amount of dielectric liner structure 124 formed within the horizontal boundaries of the trench 116 (e.g., by processing acts similar to those previously described with reference to fig. 1E) may depend, at least in part, on the horizontal dimensions of the trench 116 (fig. 1G), the dielectric spacer structures 122, and the dielectric liner structure 124.

Still referring to fig. 1H, dielectric liner structure 124 may physically contact first insulating structure 104 of different layers 108 of preliminary stack structure 102 at step 132 and additional step 134 of depression 126. As shown in fig. 1H, the first portions 124-1A, 124-2A, 124-3A, 124-4A of the different dielectric liner structures 124 (e.g., the first dielectric liner structure 124-1, the second dielectric liner structure 124-2, the third dielectric liner structure 124-3, the fourth dielectric liner structure 124-4) may physically contact at least some of the additional steps 134 of the inverted stair-step structure 130 of the recessed structure 126; and the second portions 124-1B, 124-2B, 124-3B, 124-4B of the different dielectric liner structures 124 (e.g., the first dielectric liner structure 124-1, the second dielectric liner structure 124-2, the third dielectric liner structure 124-3, the fourth dielectric liner structure 124-4) may physically contact at least some of the steps 132 of the forward step structure 128 of the recess structure 126.

As depicted in fig. 1H, the dielectric liner structures 124 (fig. 1G) formed within the horizontal boundaries 120 of the trenches 116 may be individually positioned horizontally at the horizontal boundaries (e.g., in the X-direction, in the Y-direction) of the step 132 and the additional step 134 of the lowly-situated structure 126 that the dielectric liner structures 124 physically contact. In other words, the horizontal boundary of each dielectric liner structure 124 (e.g., an inner horizontal boundary located relatively closer to the central region 136 of the lowly-situated structure 126 than another outer horizontal boundary) may be substantially coplanar with the horizontal boundaries of the step 132 and the additional step 134 of the lowly-situated structure 126 (e.g., an inner horizontal boundary located horizontally relatively closer to the central region 136 of the lowly-situated structure 126 than other outer horizontal boundaries) that the dielectric liner structure 124 is in physical contact with.

The dielectric liner structures 124 may horizontally alternate with the dielectric spacer structures 122 within the horizontal boundaries 120 of the trenches 116 (fig. 1G). By way of non-limiting example, as shown in fig. 1H, a first dielectric liner structure 124-1 may be horizontally interposed between the first dielectric spacer structure 122-1 and the second dielectric spacer structure 122-2; the second dielectric liner structure 124-2 may be horizontally interposed between the second dielectric spacer structure 122-2 and the third dielectric spacer structure 122-3; a third dielectric liner structure 124-3 may be horizontally interposed between the third dielectric spacer structure 122-3 and the fourth dielectric spacer structure 122-4; and a fourth dielectric liner structure 124-4 may be horizontally interposed between the fourth dielectric spacer structure 122-4 and the fifth dielectric spacer structure 122-5. Each dielectric liner structure 124 may extend horizontally from and between dielectric spacer structures 122 horizontally adjacent to the dielectric liner structures 124.

Each of the dielectric liner structures 124 may exhibit a width (e.g., in the X-direction) that is substantially the same as each other of the dielectric liner structures 124, or at least one of the dielectric liner structures 124124 may exhibit a width that is different from at least one other of the dielectric liner structures 124. In some embodiments, the dielectric liner structures 124 each exhibit a width that is substantially equal to a vertical height (e.g., in the Z-direction) of one or more of the first insulating structures 104 of the preliminary stack structure 102 that the dielectric liner structures 124 physically contact, respectively. As a non-limiting example, the dielectric liner structures 124 may each exhibit the fourth width W, respectively, previously described with reference to the first dielectric liner structure 124-1₄(FIG. 1G). In additional embodiments, the at least one dielectric liner structure 124 exhibits a width that is different (e.g., smaller, larger) than a vertical height of one or more of the first insulating structures 104 of the preliminary stack structure 102 with which the dielectric liner structure 124 is in physical contact.

Still referring to fig. 1H, the dielectric spacer structure 122 formed within the horizontal boundaries 120 of the trench 116 (fig. 1G) may include: a first dielectric spacer structure 122-1 (including a first portion 122-1A and a second portion 122-1B thereof); a second dielectric spacer structure 122-2 (including a first portion 122-2A and a second portion 122-2B thereof) that extends vertically into the preliminary stacked structure 102 relatively deeper than the first dielectric spacer structure 122-1; a third dielectric spacer structure 122-3 (including a first portion 122-3A and a second portion 122-3B thereof) that extends vertically relatively deeper into the preliminary stacked structure 102 than the second dielectric spacer structure 122-2; a fourth dielectric spacer structure 122-4 (including a first portion 122-4A and a second portion 122-4B thereof) that extends vertically into the preliminary stacked structure 102 relatively deeper than the third dielectric spacer structure 122-3; and a fifth dielectric spacer structure 122-5 that extends vertically into the preliminary stacked structure 102 relatively deeper than the fourth dielectric spacer structure 122-4. In additional embodiments, different amounts of dielectric spacer structures 122 are formed within the horizontal boundaries 120 of the trenches 116 (fig. 1G). For example, greater than five (5) (e.g., greater than or equal to ten (10), greater than or equal to twenty (20), greater than or equal to fifty (50)) dielectric spacer structures 122 may be formed within the horizontal boundaries 120 of the trenches 116 (fig. 1G), or less than five (5) dielectric spacer structures 122 may be formed within the horizontal boundaries 120 of the trenches 116 (fig. 1G). The amount of dielectric spacer structures 122 formed within the horizontal boundaries 120 of the trenches 116 (e.g., by process actions similar to those previously described with reference to fig. 1E) may depend, at least in part, on the horizontal dimensions of the trenches 116 (fig. 1G), the dielectric spacer structures 122, and the dielectric liner structures 124.

Dielectric spacer structures 122 may be formed horizontally adjacent to dielectric spacer structures 122 over different steps 132 and additional steps 134 of recessed structures 126. As shown in fig. 1H, first portions 122-1A, 122-2A, 122-3A, 122-4A of different dielectric spacer structures 122 (e.g., first dielectric spacer structure 122-1, second dielectric spacer structure 122-2, third dielectric spacer structure 122-3, fourth dielectric spacer structure 122-4) may be formed over and within horizontal boundaries of at least some of the additional steps 134 of the inverted stair-step structure 130 of the lowly structure 126; and second portions 122-1B, 122-2B, 122-3B, 122-4B of different dielectric spacer structures 122 (e.g., first dielectric spacer structure 122-1, second dielectric spacer structure 122-2, third dielectric spacer structure 122-3, fourth dielectric spacer structure 122-4) may be formed over and within horizontal boundaries of at least some of the steps 132 of the forward stair-step structure 128 of the recess structure 126. The fifth dielectric spacer structure 122-5 may be formed over and within horizontal boundaries of the central region 136 of the recessed structure 126.

As previously described, the dielectric spacer structures 122 may alternate horizontally with the dielectric spacer structures 122 within the horizontal boundaries 120 of the trenches 116 (fig. 1G). By way of non-limiting example, as shown in fig. 1H, a first dielectric spacer structure 122-1 may be horizontally interposed between the first dielectric liner structure 124-1 and the preliminary stack structure 102 and the portion of the patterned mask structure 110 at the horizontal boundary 120 of the trench 116 (fig. 1G); a second dielectric spacer structure 122-2 may be horizontally interposed between the first dielectric liner structure 124-1 and the second dielectric liner structure 124-2; a third dielectric spacer structure 122-3 may be horizontally interposed between the second dielectric liner structure 124-2 and the third dielectric liner structure 124-3; a fourth dielectric spacer structure 122-4 may be horizontally interposed between the third dielectric liner structure 124-3 and the fourth dielectric liner structure 124-4; and a fifth dielectric spacer structure 122-5 may be horizontally interposed between the first portion 124-4A of the fourth dielectric liner structure 124-4 and the second portion 124-4B of the fourth dielectric liner structure 124-4.

Each of the dielectric spacer structures 122 may exhibit a width (e.g., in the X-direction) that is substantially the same as each other of the dielectric spacer structures 122, or at least one of the dielectric spacer structures 122 may exhibit a width that is different from at least one other of the dielectric spacer structures 122. In some embodiments, the dielectric spacer structures 122 (e.g., fifth dielectric spacer structure 122-5) positioned within the horizontal boundaries of the central region 136 of the recessed structure 126 exhibit a different width (e.g., a greater width, a lesser width) than one or more (e.g., each) of the other dielectric spacer structures 122. In additional embodiments, the dielectric spacer structures 122 (e.g., fifth dielectric spacer structure 122-5) positioned within horizontal boundaries of the central region 136 of the recessed structure 126 exhibit substantially the same width (e.g., third width W) as each other of the dielectric spacer structures 122₃(FIG. 1G)).

With continued reference to fig. 1H, the forward and reverse stair-step structures 128, 130 of the low-lying structure 126 may be horizontally opposite each other (e.g., in the X-direction) and may be partially vertically offset from each other (e.g., in the Z-direction) within the horizontal boundaries 120 of the trenches 116 (fig. 1G). A hatched line extending from the top of the forward stepped structure 128 (e.g., the vertically uppermost one of the steps 132) to the bottom of the forward stepped structure 128 (e.g., the vertically lowermost one of the steps 132) may have a positive slope, and another hatched line extending from the top of the reverse stepped structure 130 (e.g., the vertically uppermost one of the additional steps 134) to the bottom of the reverse stepped structure 130 (e.g., the vertically lowermost one of the additional steps 134) may have a negative slope. In addition, an upper boundary (e.g., an upper surface) of the step 132 of the forward stepped structure 128 may be vertically offset from an upper boundary (e.g., an upper surface) of the additional step 134 of the reverse stepped structure 130. In some embodiments, the upper boundary of the step 132 of the forward stair-step structure 128 is vertically offset from (e.g., vertically below) the upper boundary of the additional step 134 of the reverse stair-step structure 130 to which it is vertically closest by a distance equal to the thickness of one of the layers 108 of the preliminary stacked structure 102.

The individual steps 132 of the forward stepped structure 128 of the low-lying structure 126 may comprise horizontal ends of two vertically adjacent layers 108 of the preliminary stacked structure 102. In addition, the individual additional steps 134 of the inverted stair-step structure 130 of the low-lying structure 126 may also include horizontal ends of two vertically adjacent layers 108 of the preliminary stacked structure 102. The respective steps 132 of the low-lying structure 126 vertically adjacent to the respective additional steps 134 of the low-lying structure 126 may share the layer 108 of the preliminary stacked structure 102 with the respective additional steps 134. For example, one of the two vertically adjacent layers 108 of the preliminary stacked structure 102 associated with (e.g., defining) an individual step 132 may also be one of the two vertically adjacent layers 108 of the preliminary stacked structure 102 associated with an individual additional step 134 that is vertically adjacent to the individual step 132. The layer 108 shared by the respective step 132 and the respective additional step 134 vertically adjacent to the respective step 132 may be a vertically upper portion of the respective step 132 and a vertically lower portion of the respective additional step 134, or vice versa. As a non-limiting example, the uppermost additional step 134 of the inverted stair-step structure 130 may comprise the horizontal ends of two vertically adjacent layers 108 of the preliminary stacked structure 102; and the uppermost step 132 of the forward stair-step structure 128 may comprise horizontal ends of two additional vertically adjacent layers 108 of the preliminary stacked structure 102, wherein one of the two additional vertically adjacent layers 108 is the same layer 108 as one of the two vertically adjacent layers 108. A first of the two vertically adjacent layers 108 may form an upper portion of the uppermost additional step 134 and may physically contact the first portion 124-1A of the first dielectric liner structure 124-1; and a second of the two vertically adjacent layers 108 may form a lower portion of the uppermost additional step 134 and may not physically contact the first portion 124-1A of the first dielectric liner structure 124-1. The layer 108 forming the lower portion of the upper additional step 134 may in turn constitute a first of two additional vertically adjacent layers 108 and may form an upper portion of the uppermost step 132 in physical contact with the second portion 124-1B of the first dielectric liner structure 124-1; and a second of the two additional vertically adjacent layers 108 may form a lower portion of the uppermost step 132 and may not physically contact the second portion 124-1B of the first dielectric liner structure 124-1.

Referring next to fig. 1I, portions (e.g., upper portions) of the patterned mask structure 110 (fig. 1H) and the dielectric spacer structure 122 and the dielectric liner structure 124 outside the vertical boundaries of the trench 116 (fig. 1C) may be removed while maintaining other portions (e.g., lower portions) of the dielectric spacer structure 122 and the dielectric liner structure 124 within the vertical boundaries of the trench 116 (fig. 1C). As shown in fig. 1I, the removal process may expose an uppermost surface of the preliminary stack structure 102 of the microelectronic device structure 100. Uppermost boundaries (e.g., uppermost surfaces) of remaining portions (e.g., lower portions) of the dielectric spacer structures 122 and the dielectric liner structures 124 may be substantially coplanar with exposed uppermost surfaces of the preliminary stack structure 102. In other words, the uppermost boundaries (e.g., uppermost surfaces) of the dielectric spacer structures 122, the dielectric liner structures 124, and the preliminary stack structures 102 may form a substantially planar uppermost surface 138 of the microelectronic device structure 100 after the removal process.

The patterned mask structure 110 (fig. 1H) and portions (e.g., upper portions) of the dielectric spacer structure 122 and the dielectric liner structure 124 outside the vertical boundaries of the trench 116 (fig. 1C) may be removed using conventional processes (e.g., conventional etch processes, conventional planarization processes), which are not described in detail herein. For example, the patterned mask structure 110 (fig. 1H) and portions (e.g., upper portions) of the dielectric spacer structures 122 and the dielectric liner structures 124 outside the vertical boundaries of the trenches 116 (fig. 1C) may be removed using one or more of an etching process (e.g., a wet etching process) and a chemical-mechanical planarization (CMP) process.

Referring next to fig. 1J, a capping material 140 may be formed on or over the substantially planar uppermost surface 138 (fig. 1I) of the microelectronic device structure 100. The capping material 140 may extend horizontally continuously across the substantially planar uppermost surface 138 (fig. 1I) of the microelectronic device structure 100. The capping material 140 may cover (e.g., cap) an uppermost surface of the dielectric liner structure 124, and may facilitate replacement of the dielectric material of at least some of the dielectric liner structure 124 and the first insulating structure 104 of the preliminary stack structure 102 by one or more conductive materials through a so-called "replacement gate" or "gate-on-the-fly" processing action, as described in further detail below.

Capping material 140 may be formed of and include at least one dielectric material having a different etch selectivity than first insulating structure 104 and dielectric liner structure 124 of preliminary stack structure 102. The capping material 140 may, for example, have an etch that is selective substantially similar to the second insulating structure 106 and the dielectric spacer structures 122 of the preliminary stack structure 102. By way of non-limiting example, the capping material 140 may be formed from and include at least one oxygen-containing dielectric material, such as one or more of the following: dielectric oxide materials (e.g., SiO)_xPhosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO_x、HfO_x、NbO_xAnd TiO_xOne or more of (a), a dielectric oxynitride material (e.g., SiO)_xN_y) And a dielectric oxycarbonitride material(e.g., SiO)_xC_zN_y). The capping material 140 may have a material composition different from that of the first insulating structure 104 and the dielectric liner structure 124 of the preliminary stack structure 102. The capping material 140 may have a material composition that is substantially the same as or may be different from the material composition of the second insulating structure 106 and the dielectric spacer structure 122 of the preliminary stack structure 102. In some embodiments, capping material 140 is formed from SiO_x(e.g., SiO)₂) Form and contain SiO_x。

The capping material 140 may be formed using conventional processes (e.g., conventional deposition processes such as one or more of PVD, CVD, ALD, and spin coating; conventional material removal processes such as conventional polishing processes). Such processes are known in the art and therefore are not described in detail herein. In some embodiments, a dielectric material is conventionally deposited on or over the substantially planar uppermost surface 138 (fig. 1I) of the microelectronic device structure 100 to form a capping material 140, and then the capping material 140 is subjected to at least one polishing process (e.g., at least one buffing process) to mitigate (e.g., substantially remove) undesirable irregularities (e.g., deviations from planarity) at its uppermost surface. The uppermost surface of the lidding material 140 may be substantially planar.

Referring next to fig. 1K, a first portion (e.g., first portions 124-1A, 124-2A, 124-3A, 124-4A shown in fig. 1J) of a dielectric liner structure 124 (e.g., dielectric liner structures 124-1, 124-2, 124-3, 124-4 shown in fig. 1J) may be physically separated (e.g., physically separated) from a second portion (e.g., second portions 124-1B, 124-2B, 124-3B, 124-4B shown in fig. 1J) of the dielectric liner structure 124 (fig. 1J); and the dielectric material of at least some of the dielectric liner structures 124 (fig. 1J) and the first insulating structures 104 (fig. 1J) of the preliminary stack structure 102 (fig. 1J) may be at least partially replaced with a conductive material to form conductive structures 142 from the first insulating structures 104 (fig. 1J), conductive contact structures 144 from a first portion of the dielectric liner structures 124 (fig. 1J), and additional conductive contact structures 146 from a second portion of the dielectric liner structures 124 (fig. 1J). As shown in fig. 1K, the process may modify layers 108 (fig. 1J) of preliminary stacked structure 102 (fig. 1J) to form stacked structure 148, which includes a vertically alternating (e.g., in the Z-direction) sequence of conductive structures 142 and insulating structures 150 arranged in modified layer 152. The insulating structure 150 may correspond to a remaining portion (e.g., remaining portion, unremoved portion) of the second insulating structure 106 (fig. 1J) of the preliminary stacked structure 102 (fig. 1J). Modified layer 152 of stacked structure 148 may be formed from and correspond to layer 108 (fig. 1J) of preliminary stacked structure 102 (fig. 1J). Modified layers 152 of stacked structures 148 may each respectively include a conductive structure 142 vertically adjacent to insulating structure 150. In embodiments in which only a portion (e.g., less than all) of first insulating structure 104 (fig. 1J) of preliminary stacked structure 102 (fig. 1J) is replaced with conductive structure 142, modified layer 152 of stacked structure 148 may also include a remaining portion (e.g., remaining portion, unremoved portion) of first insulating structure 104 (fig. 1J) horizontally adjacent to conductive structure 142.

By removing (e.g., etching) regions of the dielectric liner structure 124 at the intersection of the first and second portions thereof, and then filling the resulting opening with at least one electrically insulating material having a different etch selectivity than the dielectric liner structure 124 and the first insulating structure 104 (fig. 1J) of the preliminary stack structure 102 (fig. 1J), the first portions (e.g., the first portions 124-1A, 124-2A, 124-3A, 124-4A shown in fig. 1J) of the dielectric liner structure 124 (e.g., the dielectric liner structures 124-1, 124-2, 124-3, 124-4A shown in fig. 1J) may be a portion of the dielectric liner structure 124 (fig. 1J) that is a portion of the dielectric liner structure 124 (e.g., the second portions 124-1B, 124-2B, 124-3B shown in fig. 1J), 124-4B) are physically separated. The electrically insulating material may, for example, have an etch that is selective to substantially similar second insulating structures 106 (fig. 1J) and dielectric spacer structures 122 of preliminary stack structure 102 (fig. 1J). The material composition of the electrically insulating material may be substantially the same as or may be different from the material composition of the second insulating structure 106 (fig. 1J) and the dielectric spacer structure 122 (fig. 1J). In some embodiments, the electrically insulating material is formed from SiO_x(e.g., SiO)₂) Form and contain SiO_x。

In some embodiments, the material removal process used to physically separate the first portion (e.g., first portions 124-1A, 124-2A, 124-3A, 124-4A shown in fig. 1J) and the second portion (e.g., second portions 124-1B, 124-2B, 124-3B, 124-4B shown in fig. 1J) of the individual dielectric liner structures 124 (fig. 1J) is controlled to substantially physically separate only the first portion and the second portion of the dielectric liner structure 124 from one another. The material removal process may, for example, form discrete openings that extend vertically through individual dielectric liner structures 124 but not through dielectric spacer structures 122 that are horizontally adjacent to the dielectric liner structures 124. The discrete openings may then be filled with an electrically insulating material to form discrete pillar structures (e.g., discrete cylindrical structures) that are horizontally interposed between the separated portions of the dielectric liner structures 124 in a first horizontal direction and horizontally interposed between horizontally adjacent dielectric spacer structures 122 in a second horizontal direction that is orthogonal to the first horizontal direction.

In additional embodiments, the material removal process to physically separate the first portions (e.g., first portions 124-1A, 124-2A, 124-3A, 124-4A shown in FIG. 1J) and the second portions (e.g., second portions 124-1B, 124-2B, 124-3B, 124-4B shown in FIG. 1J) of the individual dielectric liner structures 124 (FIG. 1J) is controlled to also control the first portions (e.g., first portions 122-1A, 122-2A, 122-3A, 122-4A shown in FIG. 1J) and the second portions (e.g., second portions 122-1B, 122-3A, 122-4A shown in FIG. 1J) of the individual dielectric spacer structures 122 (e.g., dielectric spacer structures 122-1, 122-2, 122-3, 122-4B shown in FIG. 1J), 122-2B, 122-3B, 122-4B) are physically separated from each other. The material removal process may, for example, form at least one linear opening (e.g., at least one trench) extending vertically through the respective dielectric liner structure 124 and the respective dielectric spacer structure 122 horizontally adjacent to the respective dielectric liner structure 124. The linear openings may then be filled with an electrically insulating material to form at least one linear pillar structure (described in further detail below with reference to fig. 2) (e.g., a horizontally elongated rectangular pillar structure) that is horizontally interposed in a first horizontal direction between the separated portions of the individual dielectric liner structures 124 and the separated portions of the individual dielectric spacer structures 122; and continuously extends horizontally in a second horizontal direction orthogonal to the first horizontal direction through the dielectric liner structures 124 and the dielectric spacer structures 122 horizontally adjacent to each other.

In addition to physically separating at least a first portion (e.g., first portions 124-1A, 124-2A, 124-3A, 124-4A shown in fig. 1J) and a second portion (e.g., second portions 124-1B, 124-2B, 124-3B, 124-4B shown in fig. 1J) of the individual dielectric liner structures 124 (fig. 1J), structures (e.g., pillar structures, linear pillar structures) formed between the separated portions of the individual dielectric liner structures 124 may also provide structural support to the preliminary stacked structure 102 (fig. 1J) during so-called "replacement gate" or "gate last" processing actions to form the conductive structures 142, the conductive contact structures 144, and the additional conductive contact structures 146. The structures may prevent undesirable layer deformation (e.g., layer twisting) and/or layer collapse, for example, during formation of conductive structures 142, conductive contact structures 144, and additional conductive contact structures 146. One or more additional support structures (e.g., pillar structures, such as dielectric pillar structures) may be formed at desired locations within preliminary stack structure 102 (fig. 1J) prior to the replacement gate processing action to provide further structural support to preliminary stack structure 102 (fig. 1J) during formation of conductive structures 142, conductive contact structures 144, and additional conductive contact structures 146.

With continued reference to fig. 1K, the amount and location (e.g., horizontal, vertical) of the conductive contact structure 144 may correspond to the amount and location of the first portion of the dielectric liner structure 124 (fig. 1J) used to form the conductive contact structure 144; and the amount and location (e.g., horizontal, vertical) of the additional conductive contact structures 146 may correspond to the amount and location of the second portion of the dielectric liner structure 124 (fig. 1J) used to form the additional conductive contact structures 146. As a non-limiting example, as shown in fig. 1K, the conductive contact structure 144 can include a conductive contact structure 144-1, a second conductive contact structure 144-2, a third conductive contact structure 144-3, and a fourth conductive contact structure 144-4 that correspond to the first portion 124-1A (fig. 1J) of the first dielectric liner structure 124-1 (fig. 1J), the first portion 124-2A (fig. 1J) of the second dielectric liner structure 124-2 (fig. 1J), the first portion 124-3A (fig. 1J) of the third dielectric liner structure 124-3 (fig. 1J), and the first portion 124-4A (fig. 1J) of the fourth dielectric liner structure 124-4 (fig. 1J), respectively. As another non-limiting example, as also shown in fig. 1K, the additional conductive contact structure 146 may include a first additional conductive contact structure 146-1, a second additional conductive contact structure 146-2, a third additional conductive contact structure 146-3, and a fourth additional conductive contact structure 146-4 corresponding to the second portion 124-1B (fig. 1J) of the first dielectric liner structure 124-1 (fig. 1J), the second portion 124-2B (fig. 1J) of the second dielectric liner structure 124-2 (fig. 1J), the second portion 124-3B (fig. 1J) of the third dielectric liner structure 124-3 (fig. 1J), and the second portion 124-4B (fig. 1J) of the fourth dielectric liner structure 124-4 (fig. 1J), respectively.

As shown in fig. 1K, conductive contact structures 144 may be integral and continuous with some of conductive structures 142 of modified stack structure 148, and additional conductive contact structures 146 may be integral and continuous with some other of conductive structures 142 of modified stack structure 148. For example, individual conductive contact structures 144 may be integral and continuous with individual conductive structures 142 of modified stack structure 148 at additional steps 134 of reverse stair-step structure 130 of low-lying structure 126, and individual additional conductive contact structures 146 may be integral and continuous with other individual conductive structures 142 of modified stack structure 148 at steps 132 of forward stair-step structure 128 of low-lying structure 126. The individual conductive contact structures 144 and the individual conductive structures 142 in physical contact therewith may constitute different portions of individual monolithic structures. As a non-limiting example, the first conductive contact structure 144-1 and one of the conductive structures 142 of the modified stack structure 148 in physical contact therewith (e.g., at the uppermost additional step 134 of the inverted stair-step structure 130) may together form a first monolithic structure comprising the first conductive contact structure 144-1 and the one of the conductive structures 142. In addition, the individual additional conductive contact structures 146 and the other individual conductive structures 142 in physical contact therewith may constitute different portions of other individual monolithic structures. As a non-limiting example, the first additional conductive contact structure 146-1 and the other of the conductive structures 142 of the modified stack structure 148 in physical contact therewith (e.g., at the uppermost step 132 of the forward stair-step structure 128) may together form a first additional monolithic structure that includes the first additional conductive contact structure 146-1 and the other of the conductive structures 142.

The conductive structures 142, the conductive contact structures 144, and the additional conductive contact structures 146 may each be respectively formed from and include at least one conductive material, such as one or more of a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide, and a conductively-doped semiconductor material. By way of non-limiting example, conductive structure 142, conductive contact structure 144, and additional conductive contact structure 146 may each be formed from and include, respectively, one or more of: tungsten (W) and tungsten nitride (WN)_y) Nickel (Ni), tantalum (Ta), tantalum nitride (TaN)_y) Tantalum silicide (TaSi)_x) Platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al), molybdenum (Mo), titanium (Ti), titanium nitride (TiN)_y) Titanium silicide (TiSi)_x) Titanium silicon nitride (TiSi)_xN_y) Titanium aluminum nitride (TiAl)_xN_y) Molybdenum nitride (MoN)_x) Iridium (Ir), iridium oxide (IrO)_z) Ruthenium (Ru), ruthenium oxide (RuO)_z) And conductively doped silicon. In some embodiments, conductive structure 142, conductive contact structure 144, and additional conductive contact structure 146 are each formed of and include tungsten (W).

With continued reference to fig. 1K, to form the modified stack structure 148 (including its conductive structure 142 and insulating structure 150), conductive contact structure 144, and additional conductive contact structure 146, slots (e.g., slits, trenches) may be formed extending vertically through the dielectric spacer structure 122, the dielectric liner structure 124 (fig. 1J), and the preliminary stack structure 102 (fig. 1J) to form discrete blocks. The slot and block may each extend in a first horizontal direction (e.g., the X-direction); and the slots and blocks may alternate with each other in a second horizontal direction (e.g., Y-direction) orthogonal to the first horizontal direction. The dielectric liner structure 124 (fig. 1J) and the first insulating structure 104 (fig. 1J) of the preliminary stack structure 102 (fig. 1J) may then be selectively removed (e.g., selectively etched and excavated), either completely or partially, through the slot. Subsequently, open volumes (e.g., void spaces) formed by the selective removal of the dielectric liner structure 124 (fig. 1J) and the first insulating structure 104 (fig. 1J) may be filled with a conductive material (e.g., tungsten) to form a conductive structure 142, a conductive contact structure 144, and an additional conductive contact structure 146. The slot may then be filled with at least one dielectric material.

Referring next to fig. 1L, a dielectric structure 154 may be formed on or over capping material 140; portions of dielectric structure 154 and capping material 140 can be removed (e.g., etched) to form openings (e.g., vias, apertures) that expose portions of conductive contact structures 144 and additional conductive contact structures 146; and conductive plug structures 156 may then be formed within the openings in contact (e.g., physical contact, electrical contact) with conductive contact structures 144 and additional conductive contact structures 146. The conductive plug structure 156 may facilitate electrical communication between additional conductive structures (e.g., conductive line structures, such as access line structures) formed over the recessed structure 126 (and, thus, additional structures and/or devices, such as one or more control devices, that are electrically coupled to the additional conductive structures) and the conductive contact structure 144 and the additional conductive contact structure 146.

Dielectric structure 154 may be formed of and include at least one dielectric material having a different etch selectivity than capping material 140. The dielectric structure 154 may act as a mask for patterning the capping material 140. Dielectric structure 154 may be selectively etched relative to capping material 140 during mutual exposure to a first etchant, and capping material 140 may be selectively etched relative to dielectric structure 154 during mutual exposure to a second, different etchant. The material composition of dielectric structure 154 is different from the material composition of capping material 140 and may include at least one dielectric oxide material (e.g., SiO)_xPhosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO_x、HfO_x、NbO_x、TiO_x、ZrO_x、TaO_xAnd MgO_xOne or more of (a), at least one dielectric nitride material (e.g., SiN)_y) At least one dielectric nitrogenOxide materials (e.g. SiO)_xN_y) And at least one dielectric oxycarbonitride material (e.g., SiO)_xC_zN_y) One or more of (a). In some embodiments, dielectric structure 154 is made of SiN_y(e.g., Si)₃N₄) Form and contain SiN_y. The dielectric structure 154 may be substantially homogeneous, or may be substantially heterogeneous. In some embodiments, the dielectric structure 154 is substantially homogeneous. In additional embodiments, the dielectric structure 154 is substantially heterogeneous. The dielectric structure 154 may be substantially planar and may exhibit a desired thickness (e.g., height in the Z-direction).

Conductive plug structure 156 can be formed of and include at least one conductive material, such as one or more of a metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), an alloy (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co and Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, steel, low carbon steel, stainless steel), a conductive metal-containing material (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), a conductively-doped semiconductor material (e.g., conductively-doped Si, conductively-doped Ge, conductively-doped SiGe). Each of conductive plug structures 156 may have substantially the same material composition, or at least one of conductive plug structures 156 may have a different material composition than at least one other of conductive plug structures 156.

Conductive plug structures 156 may each provide a desired horizontal position (e.g., in the X-direction and Y-direction) on or over one of conductive contact structures 144 or one of additional conductive contact structures 146, respectively. Conductive plug structures 156 may each contact a single (e.g., only one) conductive contact structure 144 or a single (e.g., only one) additional conductive contact structure 146, respectively. In some embodiments, each of conductive plug structures 156 is individually substantially horizontally centered on one of conductive contact structures 144 or one of additional conductive contact structures 146. In additional embodiments, one or more of conductive plug structures 156 are individually horizontally offset (e.g., in the X-direction and/or in the Y-direction) from the horizontal center of conductive contact structure 144 or additional conductive contact structure 146 with which they are in contact. Additionally, as shown in fig. 1L, in some embodiments, at least some of the conductive plug structures 156 are substantially horizontally aligned with one another. For example, at least some (e.g., all) of the conductive plug structures 156 that are horizontally adjacent to one another in a first horizontal direction (e.g., the X-direction) may be substantially aligned with one another in a second horizontal direction (e.g., the Y-direction) that is orthogonal to the first horizontal direction. In additional embodiments, at least some of the conductive plug structures 156 are offset from one another in multiple horizontal directions (e.g., X-direction and Y-direction). For example, at least some (e.g., all) of the conductive plug structures 156 that are horizontally adjacent to one another in a first horizontal direction (e.g., the X-direction) may be offset from one another in a second horizontal direction (e.g., the Y-direction) that is orthogonal to the first horizontal direction.

Dielectric structure 154 and conductive plug structure 156 may be formed using conventional processes (e.g., conventional material deposition processes, conventional photolithography processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein.

Thus, in accordance with an embodiment of the present disclosure, a method of forming a microelectronic device includes forming a preliminary stacked structure including a vertically alternating sequence of insulating structures and additional insulating structures arranged in layers. Each of the layers includes one of the insulating structures and one of the additional insulating structures. The trenches are formed to extend vertically into the preliminary stacked structure. A horizontally alternating sequence of dielectric spacer structures and dielectric liner structures is formed within the horizontal boundaries of the trench. At least some of the dielectric liner structures physically contact insulating structures of the preliminary stack structures that are different from one another. The dielectric material of the dielectric liner structure and the insulating structure of the preliminary stack structure are at least partially replaced by a conductive material.

Further, in accordance with an embodiment of the present disclosure, a microelectronic device includes a stack structure, a depression within the stack structure, and a conductive contact structure. The stacked structure includes a vertically alternating sequence of conductive structures and insulating structures arranged in layers. Each of the layers includes one of the conductive structures and one of the insulating structures. The low-lying structure includes: a forward stair step structure having a step comprising an edge of a layer; and a reverse stair step structure opposite the forward stair step structure and having an additional step comprising an additional edge of the layer. The conductive contact structure extends vertically at the step of the forward stair-step structure and the additional step of the reverse stair-step structure to an upper vertical boundary of at least some of the conductive structures of the stacked structure. The conductive contact structures are each integral and continuous with one of the conductive structures.

A microelectronic device structure according to embodiments of the present disclosure (e.g., the microelectronic device structure 100 described previously with reference to fig. 1L) may be included in embodiments of a microelectronic device of the present disclosure (e.g., a memory device, such as a 3D NAND flash memory device). For example, fig. 2 illustrates a simplified partial top view of a microelectronic device 200 including a microelectronic device structure 201. The microelectronic device structure 201 may be substantially similar to the microelectronic device structure 100 at the processing stage previously described with reference to fig. 1L.

Referring to fig. 2, a microelectronic device 200 includes a stacked structure 202 including a vertically alternating (e.g., in the Z-direction) sequence of conductive and insulating structures arranged in layers. The stack structure 202 may be substantially similar to the modified stack structure 148 previously described with reference to fig. 1K. As shown in fig. 2, the stacked structures 202 may be separated in the Y-direction by slots 203. The slots 203 may be filled with a dielectric material and correspond to the slots previously described with reference to fig. 1K with respect to forming the conductive structures 142, the conductive contact structures 144, and the additional conductive contact structures 146 by a so-called "replacement gate" or "gate last" processing action. The slots 203 may divide (e.g., in the Y-direction) the stacked structure 202 into a plurality of blocks 205. In addition, stack structure 202 includes a memory array region 207, and a distributed depression 209 horizontally adjacent (e.g., in the X-direction) to memory array region 207. As described in further detail below, the microelectronic device 200 also includes additional components (e.g., features, structures, devices) within boundaries of different horizontal regions (e.g., memory array region 207, distributed depression 209) of the stack structure 202.

Within the horizontal boundaries of the memory array region 207 of the stack structure 202, the microelectronic device 200 may include vertically extending pillar structures 211. The vertically extending pillar structures 211 may extend vertically (e.g., in the Z-direction), for example, from or proximate to the data lines 215 (e.g., digit lines, bit lines), through the memory array region 207 of the stacked structure 202, and to or proximate to the source structures 217 (e.g., source plates). In fig. 2, the source structure 217 is represented in dashed lines to indicate that the source structure 217 may be located vertically below the stack structure 202. Each of the vertically extending pillar structures 211 may include a semi-conductive pillar (e.g., a polysilicon pillar, a silicon germanium pillar) at least partially surrounded by one or more charge storage structures (e.g., a charge trapping structure, e.g., a charge trapping structure comprising oxide-nitride-oxide ("ONO") material, a floating gate structure). The intersection of the vertically extending pillar structures 211 of the layers of the stacked structure 202 (e.g., corresponding to the modified layer 152 previously described with reference to fig. 1K) and the conductive structures (e.g., corresponding to the conductive structures 142 previously described with reference to fig. 1K) may define vertically extending (e.g., in the Z-direction) memory cell strings 223 that are coupled in series with one another within the memory array region 207 of the stacked structure 202. In some embodiments, memory cell 223 formed at the intersection of the conductive structures and the vertically extending pillar structures of the layers of stacked structure 202 comprises a so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cell. In additional embodiments, memory cells 223 include so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells, or so-called "BETANOS" (band/barrier engineered TANOS) memory cells, each of which is a subset of MONOS memory cells. In further embodiments, memory cell 223 comprises a so-called "floating gate" memory cell that includes a floating gate (e.g., a metal floating gate) as the charge storage structure. The floating gate may be horizontally interposed between the vertically-extending pillar structures 211 of different layers of the stacked structure 202 and the central structure of the conductive structure. The microelectronic device 200 can include any desired amount and distribution of vertically extending pillar structures 211 within the memory array region 207 of the stack structure 202.

With continued reference to fig. 2, within the horizontal boundaries of the distributed depressions 209 of the stacked structure 202, the microelectronic device 200 may include depressions 226 distributed within the stacked structure 202. The dimples 226 may individually have a geometric configuration (e.g., shape and dimensions) substantially similar to that previously described with respect to dimples 126, including the geometric configuration of their forward step structures 128, reverse step structures 130 and central region 136 (fig. 1H-1L), except that at least some of the dimples 226 may be positioned at different elevations (e.g., vertical positions in the Z-direction) from one another within the stack 202. Each of the recessed structures 226 may have substantially the same geometric configuration (e.g., substantially the same shape and size, including substantially the same shape and size of its individual components, and substantially the same shape and size resulting from a combination of its different components) as each other of the recessed structures 226, except for at least some different elevations within the stacked structure 202. In additional embodiments, at least one of the recessed structures 226 has a different geometric configuration (e.g., a different shape and/or one or more different dimensions, including substantially different shapes and/or one or more different dimensions of one or more individual components thereof, and/or different shapes and/or one or more different dimensions resulting from combinations of different components thereof) than at least one other of the recessed structures 226.

As shown in fig. 2, the portion of the individual block 205 of the stack structure 202 within the distributed depression 209 of the stack structure 202 may include a section of the individual depression 226 separated (e.g., divided, segmented, isolated) from other sections of the individual depression 226 by the slot 203. For example, a first section 226A of an individual (e.g., a single, one) dimple 226 may be located within and extend partially (e.g., less than completely) horizontally across a first one of the blocks 205 of the stacked structure 202 (e.g., in the Y-direction), and a second section 226B of the individual dimple 226 may be located within and extend partially (e.g., less than completely) horizontally across a second one of the blocks 205 that is horizontally adjacent (e.g., in the Y-direction) to the first one of the blocks 205 (e.g., in the Y-direction). One of the slots 203 may be horizontally interposed (e.g., in the Y-direction) between a first section 226A of the respective depression 226 and a second section 226B of the respective depression 226. The individual blocks 205 of the stack 202 may include a first section 226A of a plurality of the dimples 226, and a second section 226B of a plurality of other dimples 226. As shown in fig. 2, within an individual block 205 of the stack 202, first segments 226A of the plurality of the recessed structures 226 may be substantially horizontally aligned with one another in a first horizontal direction (e.g., the X-direction), second segments 226B of a plurality of other of the recessed structures 226 may also be substantially horizontally aligned with one another in the first horizontal direction (e.g., the X-direction), and the first segments 226A of the plurality of the recessed structures 226 may be horizontally adjacent to the second segments 226B of the plurality of other of the recessed structures 226 in a second horizontal direction (e.g., the Y-direction) that is orthogonal to the first horizontal direction.

With continued reference to fig. 2, within an individual block 205 of the stacked structure 202, the wordline bridge regions 213 may extend horizontally from and continuously between segments of different divots 226 located within horizontal boundaries (e.g., in the X-direction and the Y-direction) of the block 205 of the stacked structure 202. As shown in fig. 2, for a given block 205 of stacked structures 202, its wordline bridge regions 213 may extend horizontally continuously from and between a first segment 226A and a second segment 226B of different recessed structures 226 located within the horizontal boundaries of the block 205. The word line bridge regions 213 may include portions of the conductive structures (e.g., corresponding to the conductive structures 142 previously described with reference to fig. 1K) of the stacked structure 202 that extend horizontally continuously from and between sections of the different recessed structures 226 and may be established during so-called "replacement gate" or "gate last" processing actions used to form the conductive structures of the stacked structure 202. The wordline bridge regions 213 facilitate appropriate wordline driving using the die center step position and configuration.

Still referring to fig. 2, within the individual blocks 205 of the stacked structure 202, the conductive contact structure 244 and the additional conductive contact structure 246 may be integral and continuous with the conductive structure of the stacked structure 202 at the steps (e.g., corresponding to the steps 132 previously described with reference to fig. 1H-1L) and the additional steps (e.g., corresponding to the additional steps 134 previously described with reference to fig. 1H-1L) of the sections (e.g., the first section 226A, the second section 226B) of the depression 226. The conductive contact structure 244 and the additional conductive contact structure 246 may correspond to the conductive contact structure 144 and the additional conductive contact structure 146 previously described with reference to fig. 1K. As shown in fig. 2, the dielectric spacer structure 222 may be horizontally interposed between and separating the horizontally adjacent conductive contact structure 244 and the horizontally adjacent additional conductive contact structure 246; and the additional dielectric structure 245 may be horizontally interposed between and separate the conductive contact structures 244 that are horizontally adjacent to the additional conductive contact structures 246. The dielectric spacer structure 222 may correspond to the dielectric spacer structure 122 previously described with reference to fig. 1I-1L; and the additional dielectric structures 245 may correspond to the discrete pillar structures and/or the linear pillar structures previously described with reference to fig. 1K.

Additionally, within individual bricks 205 of stacked structure 202, conductive plug structures 256 may contact (e.g., physically contact, electrically contact) conductive contact structures 244 and additional conductive contact structures 246. Conductive plug structure 256 may correspond to conductive plug structure 156 previously described with reference to fig. 1L. The conductive plug structures 256 may, for example, be connected (e.g., physically connected, electrically connected) to access lines 219 (e.g., word lines) of the microelectronic device 200. The access lines 219 may be formed of at least one conductive material and include at least one conductive material, such as one or more of a metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), an alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co and Ni and Fe-based alloy, Al-based alloy, Cu-based alloy, Mg-based alloy, Ti-based alloy, steel, low carbon steel, stainless steel), a conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide), and a conductive doped semiconductor material (e.g., conductive doped Si, conductive doped Ge, conductive doped SiGe).

Still referring to fig. 2, the microelectronic device 200 may also include at least one control unit 221 (e.g., a control device). The control unit 221 may include one or more of a string driver circuit, a pass gate, a circuit for selecting a conductive line, a circuit for amplifying a signal, and a circuit for sensing a signal. Control unit 221 may be electrically coupled to data line 215, source structure 217, and access line 219, for example. In some embodiments, control unit 221 is located vertically below (e.g., in the Z-direction) memory array region 207 of stack structure 202 and is substantially confined within the horizontal boundaries of the memory array region. In fig. 2, the control unit 221 is represented by a dotted line to indicate that the control unit 221 may be vertically located under the stack structure 202. The control unit 221 may be located vertically below the source structure 217 of the microelectronic device 200. In some embodiments, the control unit 221 includes CMOS circuitry. In some such embodiments, the control unit 221 may be characterized as having a "CMOS under array" ("CuA") configuration.

Referring next to fig. 3, a microelectronic device structure (e.g., the microelectronic device structure 100 described previously with reference to fig. 1L) according to an embodiment of the present disclosure may be included in additional embodiments of the microelectronic devices (e.g., additional memory devices, such as additional 3D NAND flash memory devices) of the present disclosure. For example, fig. 3 illustrates a simplified partial top view of a microelectronic device 300 including a microelectronic device structure 301. The microelectronic device structure 301 may be substantially similar to the microelectronic device structure 100 at the processing stage previously described with reference to fig. 1L. Throughout fig. 3 and the associated description below, features (e.g., structures, materials, regions) that are functionally similar to features of the microelectronic device 200 previously described with reference to fig. 2 are referred to with like reference numerals incremented by 100. To avoid repetition, not all of the features shown in fig. 3 are described in detail herein. Rather, unless otherwise described below, in fig. 3, features denoted by reference numerals incremented by 100 from those previously described with reference to fig. 2 will be understood to be substantially similar to those previously described.

As shown in fig. 3, within the horizontal boundaries of the distributed depressions 309 of the stack structure 302, the microelectronic device 300 may include depressions 326 having a different horizontal geometric configuration (e.g., different horizontal shape, different horizontal dimension) than the depressions 226 of the microelectronic device 200 previously described with reference to fig. 2. For example, individual dimples 326 within distributed dimple regions 309 can be configured such that different sections of individual dimples 326 extend horizontally substantially (e.g., completely) across individual blocks 305 of stacked structure 302 in a first horizontal direction (e.g., the Y-direction) and are separated from one another by slots 303 extending horizontally in a second horizontal direction (e.g., the X-direction) that is orthogonal to the first horizontal direction. For example, a first section 326A of an individual (e.g., a single, one) dimple structure 326 may be located within and extend substantially horizontally across a first one of the blocks 305 of the stacked structure 302 (e.g., in the Y-direction), and a second section 326B of an individual dimple structure 226 may be located within and extend substantially horizontally across a second one of the blocks 205 that is horizontally adjacent (e.g., in the Y-direction) to the first one of the blocks 205 (e.g., in the Y-direction). One of the slots 303 may be horizontally interposed (e.g., in the Y-direction) between the first section 326A of the respective depression 326 and the second section 326B of the respective depression 326. The first block 305 of the stacked structure 302 may include first sections 326A of a plurality of the recessed structures 326 that are separated from one another in the X-direction and each extend substantially horizontally across the first block 305 in the Y-direction; and a second block 305 horizontally adjacent to the first block 305 in the Y-direction may include a second section 326B of a plurality of the low-lying structures 326 that are separated from each other in the X-direction and each extend substantially horizontally across the second block 305 in the Y-direction.

As shown in fig. 3, given the different horizontal geometric configurations of the depressions 326 of the microelectronic device 300 relative to those of the depressions 226 (fig. 2) of the microelectronic device 200 (fig. 2), the individual blocks 305 of the stacked structure 302 are free of wordline bridge regions that are substantially similar to the wordline bridge regions 213 previously described with reference to fig. 2. Rather, since different segments (e.g., first segment 326A, second segment 326B) of the respective depression 326 extend substantially horizontally (e.g., in the Y-direction) across the respective block 305 of the stacked structure 302 associated therewith, such wordline bridge regions may not be present (e.g., omitted) in the block 305 of the stacked structure 302. The configuration of the microelectronic device 300 shown in fig. 3 facilitates proper wordline driving using the die end step location and configuration.

Thus, in accordance with an embodiment of the present disclosure, a memory device includes a stack structure, a depression structure, a conductive contact structure, and a memory cell string. The stacked structure has several layers each including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The lowered structures are positioned at different vertical depths from each other within the stacked structure. Each of the low-lying structures includes: a forward stair step structure having steps comprising horizontal ends of a group of layers; and an inverted stair step structure opposite the forward stair step structure and having additional steps comprising additional horizontal ends of the group of layers. Conductive contact structures extend vertically from at least some of the conductive structures of the stacked structure at the steps of the depression structure and the additional steps. The conductive contact structures are each integral and continuous with one of the conductive structures. The memory cell string extends vertically through the stacked structure.

Referring back to fig. 1L, in additional embodiments, the microelectronic device structure of the present disclosure is formed to have a different configuration than the microelectronic device structure 100 at the processing stage depicted in fig. 1L. By way of non-limiting example, fig. 4A-4C are simplified partial cross-sectional views illustrating methods of forming a microelectronic device structure 400, according to additional embodiments of the present disclosure. The method of forming the microelectronic device structure 400 up to the processing stage depicted in fig. 4A incorporates the processing acts and features previously described with respect to the formation of the microelectronic device structure 100 up to and including the processing stage previously described with reference to fig. 1E. The processing stages depicted in fig. 4A-4C and described in further detail below may, for example, include processing acts performed in place of and/or in combination with the processing acts previously described with reference to fig. 1F-1L to form the microelectronic device structure 100 previously described with reference to fig. 1L. Throughout fig. 4A-4C and the associated description below, features (e.g., structures, materials, regions) that are functionally similar to features of the microelectronic device structure 100 previously described with reference to one or more of fig. 1A-1L are referred to with like reference numerals incremented by 100. To avoid repetition, all of the features shown in fig. 4A to 4C will not be described in detail herein. Rather, in fig. 4A-4C, features denoted by reference numerals incremented by 100 from those of features previously described with reference to one or more of fig. 1A-1L will be understood to be substantially similar to the previously described features, unless described otherwise below.

As shown in fig. 4A, following formation of the first dielectric liner structure 424-1 (e.g., by processing acts substantially similar to those previously described with reference to fig. 1E), the microelectronic device structure 400 may be subjected to at least one additional material removal (e.g., etching, such as anisotropic dry etching) process to increase the vertical depth (e.g., in the Z-direction) of the remaining (e.g., unfilled) portions of the trench 416 formed in the preliminary stack structure 402. As described in further detail below, the additional material removal process may increase the vertical depth of the remaining portion of trench 416 by a relatively greater amount than the increase in vertical depth of the remaining portion of trench 116 previously described with reference to fig. 1F. The additional material removal process may increase the vertical depth of the remaining portions of the first region 416A of the trench 416, and may also increase the vertical depth of the remaining portions of the second region 416B of the trench 416. After the additional material removal process, the remaining portion of the second region 416B of the trench 416 may extend vertically to a relatively lower depth within the preliminary stacked structure 402 than the remaining portion of the first region 416A of the trench 416. The magnitude of the vertical offset between the lower vertical boundary of the first region 416A of the trench 416 and the lower vertical boundary of the second region 416B of the trench 416 may be substantially maintained at the end of the additional material removal process. For example, the additional material removal process may increase the vertical depth of each of the remaining portions of the first region 416A of the trench 416 and the remaining portions of the second region 416B of the trench 416 by a distance (e.g., in the Z-direction) that is greater than or equal to the combined height (e.g., in the Z-direction) of the at least two (e.g., at least three) layers 408 of the preliminary stacked structure 402. As shown in fig. 4A, in some embodiments, the additional material removal process increases the vertical depth of each of the remaining portions of first region 416A of trench 416 and the remaining portions of second region 416B of trench 416 by a distance substantially equal to the combined height of three (3) of layers 408 of preliminary stacked structure 402.

Referring next to fig. 4B, after the processing stage described with reference to fig. 4A, the microelectronic device structure 400 may be subjected to additional processing acts substantially similar to those previously described with reference to fig. 1D, 1E, and 4A to fill the remaining portions of the trench 416 (fig. 4A) with more dielectric liner structures 424 (e.g., in addition to the first dielectric liner structure 424-1) and more dielectric spacer structures 422 (e.g., in addition to the first dielectric spacer structure 422-1), and form a lowland structure 426 vertically underlying and contacting the dielectric liner structures 424 and the dielectric spacer structures 422. As shown in fig. 4B, the recess 426 may include: a forward stair-step structure 428 comprising steps 432 that each include horizontal ends of a plurality (e.g., greater than or equal to three (3), greater than or equal to four (4)) of the layers 408 of the preliminary stacked structure 402, respectively; an inverted stair-step structure 430 comprising additional steps 434 each respectively including a plurality (e.g., greater than or equal to three (3), greater than or equal to four (4)) of horizontal ends in the layer 408; and a central region 436 horizontally interposed between the forward stair-step structure 428 and the reverse stair-step structure 430. The central region 436 of the depression 426 may, for example, constitute an intersection region and a vertical termination point for the forward step structure 428 and the reverse step structure 430. In substantially the same manner as previously described for the dielectric spacer structure 122 and the different dielectric liner structure 124 with reference to fig. 1H, the different dielectric spacer structure 422 and the different dielectric liner structure 424 may be formed to physically contact a mutually different step 432 of the forward stair-step structure 428 and a mutually different additional step 434 of the reverse stair-step structure 430.

As shown in fig. 4B, in some embodiments, the individual steps 432 of the forward stair-step structures 428 of the lowly-lying structures 426 are formed to include horizontal ends of four (4) of the layers 408 of the preliminary stacked structure 402; and the individual additional steps 434 of the inverted stair-step structure 430 of the depression 426 are also formed to include the horizontal ends of four (4) of the layers 408 of the preliminary stacked structure 402. Individual steps 432 of a low-lying structure 426 vertically adjacent to individual additional steps 434 of a low-lying structure 426 may share multiple (e.g., three (3) layers 408 of preliminary stacked structure 402 with individual additional steps 434. For example, three (3) of the four (4) layers 408 of the preliminary stacked structure 402 associated with the individual step 432 may also be three (3) of the four (4) layers 408 of the preliminary stacked structure 402 associated with the individual additional step 434 that is vertically adjacent to the individual step 432. One of the three (3) layers 408 shared by the respective step 432 and the respective additional step 434 that is vertically adjacent to the respective step 432 may form a vertically upper portion of the respective step 432 and a vertically lower portion of the respective additional step 434, or vice versa. As a non-limiting example, the uppermost additional step 434 of the inverted stair-step structure 430 may comprise the horizontal ends of the first group of four (4) layers 408 of the preliminary stacked structure 402; and the uppermost step 432 of the forward stair-step structure 428 may comprise the horizontal ends of a second group of four (4) layers 408 of the preliminary stacked structure 102, wherein three (3) of the second group of four (4) layers 408 is identical to three (3) of the first group of four (4) layers 408. The relatively highest layer 408 of the first group of four (4) layers 408 may form an upper portion of the uppermost additional step 434 and may physically contact the first portion 424-1A of the first dielectric liner structure 424-1; and three (3) relatively lower layers 408 of the first group of four (4) layers 408 may form a lower portion of the uppermost additional step 434 and may not physically contact the first portion 424-1A of the first dielectric liner structure 424-1. Also, a relatively highest layer 408 of the three (3) relatively lower layers 408 that form a lower portion of the upper additional step 434 may constitute a relatively highest layer 408 of the second group of four (4) layers 408 and may form an upper portion of the uppermost step 432 that is in physical contact with the second portion 424-1B of the first dielectric liner structure 424-1; and three (3) relatively lower layers 408 of the second group of four (4) layers 408 may form a lower portion of the uppermost step 432 and may not physically contact the second portion 424-1B of the first dielectric liner structure 424-1.

Referring next to fig. 4C, after the stage of processing depicted in fig. 4B, the microelectronic device structure 400 may be subjected to additional processing acts substantially similar to those previously described with reference to fig. 1I-1L to arrive at the configuration of the microelectronic device structure 400 depicted in fig. 4C. Accordingly, the method of forming the microelectronic device structure 400 after the processing stage depicted in fig. 4B incorporates the processing stages and features previously described with respect to the formation of the microelectronic device structure 100 from the processing stage previously described with reference to fig. 1I to the processing stage previously described with reference to fig. 1L.

The microelectronic device structure 400 described with reference to fig. 4C may be included in an embodiment of a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device) of the present disclosure. As a non-limiting example, the microelectronic device structure 400 at the processing stage depicted in fig. 4C may be included in the microelectronic device 200 previously described with reference to fig. 2 as the microelectronic device structure 201 (fig. 2). In some such embodiments, the recessed structures 226 (fig. 2) may individually have a geometric configuration (e.g., shape and dimensions) substantially similar to that previously described with respect to the recessed structures 426, including the geometric configuration of their forward step structures 428, reverse step structures 430, and central region 436 (fig. 4B and 4C), except that at least some of the recessed structures 226 (fig. 2) may be positioned at different elevations (e.g., vertical positions in the Z-direction) from one another within the stacked structure 202. Additionally, within the individual blocks 205 (fig. 2) of the stacked structure 202 (fig. 2), the conductive contact structure 244 (fig. 2), the additional conductive contact structure 246 (fig. 2), and the dielectric spacer structure 222 (fig. 2) may correspond to the conductive contact structure 444, the additional conductive contact structure 446, and the dielectric spacer structure 422, respectively, of the microelectronic device structure 400 at the processing stage depicted in fig. 4C. Within an individual block 205 (fig. 2) of the stacked structure 202 (fig. 2), a first section 226A (fig. 2) of an individual (e.g., single, one) of the dimples 226 (fig. 2) can include a step 432 and an additional step 434 that are vertically offset (e.g., vertically above, vertically below) from a step 432 and an additional step 434 of a second section 226B (fig. 2) of an additional individual dimple 226 (fig. 2). The steps 432 of the forward stair-step structure 428 of the first section 226A (fig. 2) of the lowland structure 226 (fig. 2) may be vertically offset (e.g., vertically above or vertically below) one (1) layer 408 from the steps 432 of the forward stair-step structure 428 of the second section 226B (fig. 2) of the additional lowland structure 226 (fig. 2); and the additional step 434 of the inverted stair-step structure 440 of the first section 226A (fig. 2) of the low-lying structure 226 (fig. 2) may be vertically offset (e.g., vertically above or vertically below) one (1) layer 408 from the additional step 434 of the inverted stair-step structure 430 of the second section 226B (fig. 2) of the additional low-lying structure 226 (fig. 2).

And the additional steps 434 of the first section 226A of the low-lying structure 226 may each be vertically offset from the vertically adjacent steps 432 and the additional steps 434, respectively, of the second section 226B of the additional low-lying structure 226.

In further embodiments, the microelectronic device structure of the present disclosure is formed to have a different configuration than each of the microelectronic device structure 100 at the processing stage depicted in fig. 1L and the microelectronic device structure 400 at the processing stage depicted in fig. 4C. By way of non-limiting example, fig. 5A-5G are simplified partial cross-sectional views illustrating methods of forming a microelectronic device structure 500, according to additional embodiments of the present disclosure. The processing stages depicted in fig. 5A-5G and described in further detail below may, for example, include processing acts performed in place of and/or in combination with the processing acts previously described with reference to fig. 1A-1L to form the microelectronic device structure 100 previously described with reference to fig. 1L. Throughout fig. 5A-5G and the associated description below, features (e.g., structures, materials, regions) that are functionally similar to features of the microelectronic device structure 100 previously described with reference to one or more of fig. 1A-1L are referred to with like reference numerals incremented by 100. To avoid repetition, all of the features shown in fig. 5A to 5G will not be described in detail herein. Rather, in fig. 5A-5G, features denoted by reference numerals incremented by 100 from those of features previously described with reference to one or more of fig. 1A-1L will be understood to be substantially similar to the previously described features, unless described otherwise below.

Referring to fig. 5A, a microelectronic device structure 500 may be formed to include a preliminary stack structure 502 and a patterned mask structure 510 on or over the preliminary stack structure 502. The preliminary stacked structure 502 includes a vertically alternating (e.g., in the Z-direction) sequence of first insulating structures 504 and second insulating structures 506 arranged in a layer 508. The patterned mask structure 510 may include at least one opening 512 (e.g., aperture, via) extending vertically therethrough. The preliminary stack structure 502 (including the first and second insulating structures 504, 506 thereof) and the patterned mask structure 510 (including the opening 512 thereof) may be formed substantially similar to the preliminary stack structure 102 (including the first and second insulating structures 104, 106 thereof) and the patterned mask structure 110 (including the opening 112) respectively, as previously described herein with reference to fig. 1A.

Referring next to fig. 5B, the microelectronic device structure 500 may be subjected to one or more material removal processes (e.g., one or more cutting processes) to form at least one trench 516 (e.g., an opening, a blind via) extending vertically (e.g., in the Z-direction) into the preliminary stacked structure 502. As shown in fig. 5B, the trench 516 within the preliminary stack structure 502 may be substantially confined within the horizontal boundaries of the opening 512 within the patterned mask structure 510. In embodiments in which the patterned mask structure 510 includes a plurality of openings 512, different trenches 516 may be formed to extend to different vertical depths from one another within the preliminary stacked structure 502. For example, at least one of trenches 516 may extend vertically to a relatively lower depth within preliminary stacked structure 502 than at least one other of trenches 516. The vertical depth of the trenches 516 relative to each other may depend at least in part on the amount of layers 508 of the preliminary stacked structure 502, the amount of trenches 516 within the preliminary stacked structure 502, and the horizontal dimensions of the trenches 516. The trenches 516 may be configured to facilitate subsequent formation of vertically extending insulating structures in physical contact with at least some (e.g., each) of the layers 508 of the preliminary stacked structure 502, as described in further detail below.

As shown in fig. 5B, trench 516 can be formed to include a lower vertical boundary 518 (e.g., bottom layer) and a horizontal boundary 520 (e.g., sides). The lower vertical boundary 518 of the trench 516 may be formed to be substantially horizontally flat. For example, prior to forming the trench 516, the processing stages (with respect to the formation of the microelectronic device structure 100) previously described with reference to fig. 1B may be omitted. Thus, different horizontal regions of the trench 516 may all extend vertically (e.g., in the Z-direction) to substantially the same vertical height within the preliminary stacked structure 502. Additionally, as depicted in fig. 5B, the horizontal boundaries 520 of the trench 516 may be substantially vertically flat.

The trenches 516 in the preliminary stacked structure 502 may be formed to terminate vertically (e.g., end vertically) at the second insulating structures 506 of a single (e.g., only one) layer 508 of the preliminary stacked structure 502. In additional embodiments, the trench 516 in the preliminary stacked structure 502 may be formed to terminate vertically at the first insulating structure 504 of a single (e.g., only one) layer 508 of the preliminary stacked structure 502.

Referring next to fig. 5C, first dielectric spacer structures 522-1 may be formed within the openings 512 in the patterned mask structure 510 and the trenches 516 in the preliminary stack structure 502. The first dielectric spacer structure 522-1 may partially (e.g., less than completely) fill each of the opening 512 and the trench 516, and may be formed within horizontal boundaries (e.g., in the X-direction and the Y-direction) of the trench 516 (and thus the opening 512 in the patterned mask structure 510) on exposed surfaces of the patterned mask structure 510 and the preliminary stack structure 502. For example, as shown in fig. 5C, the first dielectric spacer structure 522-1 may be formed at (e.g., coplanar with) the horizontal boundary 520 of the trench 516 directly horizontally adjacent to (e.g., horizontally above) the patterned mask structure 510 and the side surfaces of the preliminary stack structure 502, and may also be formed vertically adjacent to (e.g., vertically above) the upper surface of the layer 508 of the preliminary stack structure 502 that defines the lower vertical boundary 518 (fig. 5B) of the trench 516. The first dielectric spacer structure 522-1 may extend substantially vertically across (e.g., in the Z-direction) and cover side surfaces of the patterned mask structure 510 and the preliminary stack structure 502 at (e.g., coplanar with) a horizontal boundary 520 of the trench 516, and may extend only partially horizontally across (e.g., in the X-direction and the Y-direction) and cover an upper surface of the layers 508 of the preliminary stack structure 502 that define a lower vertical boundary 518 (fig. 5B) of the trench 516. As shown in fig. 5C, the first dielectric spacer structure 522-1 may include a first portion 522-1A and a second portion 522-1B. First portion 522-1A and second portion 522-1B may extend vertically (e.g., in the Z-direction) to substantially the same depth as each other within preliminary stacked structure 502.

The first dielectric spacer structure 522-1 may have substantially the same horizontal dimensions (e.g., width) and material composition as the first dielectric spacer structure 122-1 previously described with reference to fig. 1D. Additionally, the first dielectric spacer structure 522-1 may be formed in substantially the same manner as the first dielectric spacer structure 122-1 previously described with reference to fig. 1D.

Referring next to fig. 5D, a first dielectric liner structure 524-1 may be formed within the opening 512 in the patterned mask structure 510 and the remaining (e.g., unfilled) portion of the trench 516 in the preliminary stack structure 502. The first dielectric liner structure 524-1 may partially (e.g., less than completely) fill the remaining portions of each of the opening 512 and the trench 516, and may be formed within the horizontal boundaries (e.g., in the X-direction and the Y-direction) of the trench 516 (and thus the opening 512 in the patterned mask structure 510) on the exposed surfaces of the first dielectric spacer structure 522-1 (fig. 5D) and the preliminary stack structure 502. For example, the first dielectric liner structure 524-1 may be formed directly horizontally adjacent to (e.g., horizontally on) the inner side surface of the first dielectric spacer structure 522-1, and may also be formed directly vertically adjacent to (e.g., vertically on) the upper surface of the first insulating structure 504 of the layer 508 of the preliminary stack structure 502 at a modified lower vertical boundary of the trench 516 formed in the processing stage previously described with reference to fig. 5C. The first dielectric liner structure 524-1 may extend substantially vertically across (e.g., in the Z-direction) and cover an inside surface of the first dielectric spacer structure 522-1.

As shown in fig. 5D, the first dielectric liner structure 524-1 may include a first portion 524-1A and a second portion 524-1B. The first portion 524-1A may be formed directly horizontally adjacent to (e.g., horizontally above) the first portion 522-1A of the first dielectric spacer structure 522-1, and the second portion 524-1B may be formed directly horizontally adjacent to (e.g., horizontally above) the second portion 522-1B of the first dielectric spacer structure 522-1. First portion 524-1A and second portion 524-1B may extend vertically (e.g., in the Z direction) to substantially the same depth as each other within preliminary stacked structure 502. The vertical depth of each of the first and second portions 524-1A and 524-1B of the first dielectric liner structure 524-1 may be greater than or equal to the vertical depth of the first dielectric spacer structure 522-1 (including the first and second portions 522-1A and 522-1B thereof). For example, the first portion 524-1A and the second portion 524-1B of the first dielectric liner structure 524-1 may each extend vertically to and terminate at the first insulating structure 504 of the layer 508 of the preliminary stack structure 502 vertically adjacent to the lower vertical boundary of the first dielectric spacer structure 522-1.

The first dielectric liner structure 524-1 may have substantially the same horizontal dimensions (e.g., width) and material composition as the first dielectric liner structure 124-1 previously described with reference to fig. 1E. Additionally, the first dielectric liner structure 524-1 may be formed in substantially the same manner as the first dielectric liner structure 124-1 previously described with reference to fig. 1E.

Referring next to fig. 5E, a second dielectric spacer structure 522-2 may be formed within the remaining (e.g., unfilled) portion of the opening 512 in the patterned mask structure 510 and in the remaining deepened portion of the trench 516 in the preliminary stack structure 502. The second dielectric spacer structure 522-2 may partially (e.g., less than completely) fill the remaining portion of the opening 512 and the remaining deepened portion of the trench 516; and may be formed within the horizontal boundaries (e.g., in the X-direction and the Y-direction) of the trenches 516 (and thus the openings 512 in the patterned mask structure 510) on exposed surfaces of the first dielectric liner structure 524-1 and the preliminary stack structure 502. For example, a second dielectric spacer structure 522-2 may be formed within the trench 516 directly horizontally adjacent to (e.g., horizontally on) the exposed inner side surfaces of the first dielectric liner structure 524-1 and the preliminary stack structure 502. An upper surface of the second insulating structure 506 of the second dielectric spacer structure 522-2, and also directly vertically adjacent to (e.g., vertically above) the layer 508 of the preliminary stack structure 502, is formed at a modified lower vertical boundary of the trench 516 formed in the processing stage previously described with reference to fig. 5D. The second dielectric spacer structure 522-2 may extend substantially vertically across (e.g., in the Z-direction) and cover an inside surface of the first dielectric liner structure 524-1.

As shown in fig. 5E, the second dielectric spacer structure 522-2 may include a first portion 522-2A and a second portion 522-2B. The first portion 522-2A of the second dielectric spacer structure 522-2 may be formed directly horizontally adjacent to (e.g., horizontally on) the first portion 524-1A of the first dielectric liner structure 524-1, and the second portion 522-2B may be formed directly horizontally adjacent to (e.g., horizontally on) the second portion 524-1B of the first dielectric liner structure 524-1. First portion 522-2A and second portion 522-2B may extend vertically (e.g., in the Z-direction) to substantially the same depth as each other within preliminary stacked structure 502. The vertical depth of each of the first and second portions 522-2A and 522-2B of the second dielectric spacer structure 522-2 may be greater than or equal to the vertical depth of the first dielectric liner structure 524-1 (including the first and second portions 524-1A and 524-1B thereof). For example, the first portion 522-2A and the second portion 522-2B of the second dielectric spacer structure 522-2 may each extend vertically to and terminate at the second insulating structure 506 of the layer 508 of the preliminary stack structure 502 vertically adjacent to the lower vertical boundary of the first dielectric liner structure 524-1.

The second dielectric spacer structure 522-2 may have substantially the same horizontal dimensions (e.g., width) and material composition as the second dielectric spacer structure 122-2 previously described with reference to fig. 1G. Additionally, the second dielectric spacer structure 522-2 may be formed in substantially the same manner as the second dielectric spacer structure 122-2 previously described with reference to fig. 1G.

Referring next to fig. 5F, after the stage of processing described with reference to fig. 5E, the microelectronic device structure 500 may be subjected to additional processing acts similar to those previously described with reference to fig. 5D and 5E to fill the remaining portions of the trench 516 (fig. 5E) with more dielectric liner structures 524 and more dielectric spacer structures 522 and form a depression 526 vertically underlying and contacting the dielectric liner structures 524 and dielectric spacer structures 522. As shown in fig. 5F, the recess 526 may comprise: a forward stair-step structure 528 comprising a step 532 including a horizontal end of the layer 508 of the preliminary stacked structure 502; an inverted stair-step structure 530 comprising an additional step 534 including an additional horizontal end of the layer 508 of the preliminary stacked structure 502; and a central region 536 horizontally interposed between the forward and reverse stepped structures 528 and 530. The central region 536 of the depression 526 may, for example, constitute an intersection region and a vertical termination point for the forward and reverse stair structures 528, 530. As described in further detail below, different dielectric spacer structures 522 and different dielectric liner structures 524 may be formed to physically contact mutually different steps 532 of forward stair-step structure 528 and mutually different additional steps 534 of reverse stair-step structure 530.

As shown in fig. 5F, dielectric liner structure 524 may physically contact first insulating structure 504 of different layers 508 of preliminary stack structure 502 at step 532 and additional step 534 of depression 526. As shown in fig. 5F, first portions 524-1A, 524-2A, 524-3A, 524-4A of different dielectric liner structures 524 (e.g., first dielectric liner structure 524-1, second dielectric liner structure 524-2, third dielectric liner structure 524-3, fourth dielectric liner structure 524-4) may physically contact at least some of the additional steps 534 of the reverse stepped structure 530 of the recessed structure 526; and second portions 524-1B, 524-2B, 524-3B, 524-4B of different dielectric liner structures 524 (e.g., first dielectric liner structure 524-1, second dielectric liner structure 524-2, third dielectric liner structure 524-3, fourth dielectric liner structure 524-4) may physically contact at least some of the steps 532 of the forward step structure 528 of the recess structure 526. Dielectric liner structure 524 may have horizontal positions and horizontal dimensions substantially similar to those of dielectric liner structure 124 previously described with reference to fig. 1H.

Dielectric spacer structures 522 may be formed horizontally adjacent to dielectric spacer structures 522 over different steps 532 and additional steps 534 of recessed structures 526. As shown in FIG. 5F, first portions 522-1A, 522-2A, 522-3A, 522-4A of different dielectric spacer structures 522 (e.g., first dielectric spacer structure 522-1, second dielectric spacer structure 522-2, third dielectric spacer structure 522-3, fourth dielectric spacer structure 522-4) may be formed over and within horizontal boundaries of at least some of the additional steps 534 of the inverted stair-step structure 530 of the lowly-recessed structure 526; and second portions 522-1B, 522-2B, 522-3B, 522-4B of different dielectric spacer structures 522 (e.g., first dielectric spacer structure 522-1, second dielectric spacer structure 522-2, third dielectric spacer structure 522-3, fourth dielectric spacer structure 522-4) may be formed over and within horizontal boundaries of at least some of the steps 532 of the forward stair-step structure 528 of the low-lying structure 526. A fifth dielectric spacer structure 522-5 may be formed over and within the horizontal boundaries of the central region 536 of the recessed structure 526. The dielectric spacer structures 522 may have horizontal positions and horizontal dimensions substantially similar to those of the dielectric spacer structures 122 previously described with reference to fig. 1H.

Still referring to fig. 5F, the steps 532 of the forward stair-step structures 528 of the lowly-situated structures 526 may each include a horizontal end of one (1) layer 508 of the preliminary stacked structure 502, respectively. In addition, the additional steps 534 of the inverted stair-step structure 530 of the low-lying structure 526 may also each include horizontal ends of one (1) layer 508 of the preliminary stacked structure 502, respectively. Individual steps 532 and individual additional steps 534 of substantially the same elevation (e.g., in the Z-direction) of lowered structures 526 within preliminary stacked structure 502 may share layers 508 of preliminary stacked structure 502 with one another. For example, the individual steps 532 (e.g., the uppermost step 532) of the forward stair-step structure 528 may comprise a first horizontal end of the individual layer 508 of the preliminary stacked structure 502; and an individual additional step 534 (e.g., the uppermost additional step 534) of the reverse stair-step structure 530 may be located at substantially the same vertical position as the individual step 532 of the forward stair-step structure 528, and may comprise a second horizontal end of the individual layer 508 of the preliminary stacked structure 502.

Referring next to fig. 5G, after the stage of processing depicted in fig. 5F, the microelectronic device structure 500 may be subjected to additional processing acts substantially similar to those previously described with reference to fig. 1I-1L to arrive at the configuration of the microelectronic device structure 500 depicted in fig. 5G. Accordingly, the method of forming the microelectronic device structure 500 after the processing stage depicted in fig. 5F incorporates the processing stages and features previously described with respect to the formation of the microelectronic device structure 100 from the processing stage previously described with reference to fig. 1I to the processing stage previously described with reference to fig. 1L.

The microelectronic device structure 500 described with reference to fig. 5G may be included in an embodiment of a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device) of the present disclosure. By way of non-limiting example, the microelectronic device structure 500 at the processing stage depicted in fig. 5G may be included in the microelectronic device 200 (fig. 2) as the microelectronic device structure 201 (fig. 2), or may be included in the microelectronic device 300 (fig. 3) as the microelectronic device structure 301 (fig. 3). In some such embodiments, the recessed structures 226 (fig. 2) or the recessed structures 326 (fig. 3) may individually have a geometric configuration (e.g., shape and dimensions) substantially similar to that previously described with respect to the recessed structures 526, including the geometric configuration of the forward stepped structures 528, reverse stepped structures 530, and central region 536 thereof (fig. 5F and 5G), except that at least some of the recessed structures 226 (fig. 2) or at least some of the recessed structures 326 (fig. 3) may be positioned at different elevations (e.g., vertical positions in the Z-direction) from one another within the stacked structure 202 (fig. 2) or the stacked structure 302 (fig. 3). Additionally, within the individual block 205 (fig. 2) of the stacked structure 202 (fig. 2) or the individual block 305 (fig. 3) of the stacked structure 302 (fig. 3), the conductive contact structure 244 (fig. 2) or the conductive contact structure 344 (fig. 3), the additional conductive contact structure 246 (fig. 2) or the additional conductive contact structure 346 (fig. 3), and the dielectric spacer structure 222 (fig. 2) or the dielectric spacer structure 322 (fig. 3) may correspond to the conductive contact structure 544, the additional conductive contact structure 546, and the dielectric spacer structure 522, respectively, of the microelectronic device structure 500 at the processing stage depicted in fig. 5G.

Microelectronic device structures (e.g., the microelectronic device structure 100 previously described with reference to fig. 1L; the microelectronic device structure 400 previously described with reference to fig. 4C; the microelectronic device structure 500 previously described with reference to fig. 5G) and microelectronic devices (e.g., the microelectronic device 200 previously described with reference to fig. 2; the microelectronic device 300 previously described with reference to fig. 3) according to embodiments of the present disclosure may be used in embodiments of electronic systems of the present disclosure. For example, fig. 6 is a block diagram of an illustrative electronic system 600 in accordance with an embodiment of the present disclosure. Electronic system 600 may include, for example, a computer or computer hardware component, a server or other network connection hardware component, a cellular telephone, a digital camera, a Personal Digital Assistant (PDA), a portable deviceA media (e.g., music) player, a tablet computer (e.g., with Wi-Fi or cellular functionality)OrTablet computers), electronic books, navigation devices, and the like. Electronic system 600 includes at least one memory device 602. The memory device 602 may include embodiments such as one or more of the microelectronic device structures and microelectronic devices previously described herein. The electronic system 600 may further include at least one electronic signal processor device 604 (often referred to as a "microprocessor"). The electronic signal processor device 604 may optionally include embodiments of one or more of the microelectronic device structures and microelectronic devices previously described herein. Although memory device 602 and electronic signal processor device 604 are depicted as two (2) separate devices in fig. 6, in additional embodiments, a single (e.g., only one) memory/processor device with the functionality of memory device 602 and electronic signal processor device 604 is included in electronic system 600. In such embodiments, the memory/processor device may include one or more of the microelectronic device structures and microelectronic devices previously described herein. The electronic system 600 may further include one or more input devices 606, such as a mouse or other pointing device, a keyboard, a touchpad, buttons, or a control panel, for entering information into the electronic system 600 by a user. Electronic system 600 may additionally include one or more output devices 608, such as a monitor, display, printer, audio output socket, and speakers, for outputting information (e.g., visual or audio output) to the user. In some embodiments, input device 606 and output device 608 may comprise a single touch screen device that may be used to input information to electronic system 600 and output visual information to a user. Input device 606 and output device 608 may be in electrical communication with one or more of memory device 602 and electronic signal processor device 604.

Thus, according to an embodiment of the present invention, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device. The memory device includes a microelectronic device structure including a stack structure, a depression structure, and a conductive contact structure. The stacked structure includes a vertically alternating sequence of conductive structures and insulating structures arranged in layers. The depression is within the stacked structure and includes opposing stepped structures each having a step including an edge of at least some of the layers. The conductive contact structure is integral and continuous with at least some of the conductive structures of the stacked structure at the step of the opposing step structure of the depression structure. Each of the conductive contact structures individually has an inner horizontal boundary that is substantially coplanar with an inner horizontal boundary of one of the steps of the opposing stair step structure.

The methods, structures (e.g., microelectronic device structures 100, 400, 500), devices (e.g., microelectronic devices 200, 300), and systems (e.g., electronic systems 600) of the present disclosure advantageously facilitate one or more of improved performance, reliability, and durability, lower cost, increased component miniaturization, improved pattern quality, and greater packaging density as compared to conventional structures, conventional devices, and conventional systems. The methods and structures of the present disclosure may alleviate problems associated with forming and processing conventional microelectronic devices that include stacked structures having stepped structures at their edges. For example, the methods and structures of the present disclosure do not suffer from the relatively small dimensional and pitch error tolerances associated with properly forming the stepped structures of conventional microelectronic device structures to receive the contact structures thereon. Additionally, the methods and structures of the present disclosure may reduce the risk of undesirable damage (e.g., contact punch-through) and undesirable current leakage and shorting, as compared to conventional methods and conventional structures.

Additional non-limiting example embodiments of the present disclosure are set forth below.

Example 1: a microelectronic device, comprising: a stacked structure comprising a vertically alternating sequence of conductive structures and insulating structures arranged in layers, each of the layers comprising one of the conductive structures and one of the insulating structures; a recessed structure within the stacked structure and comprising: a forward stair step structure having a step comprising an edge of the layer; and a reverse stair step structure opposite the forward stair step structure and having an additional step comprising an additional edge of the layer; and conductive contact structures extending vertically to upper vertical boundaries of at least some of the conductive structures of the stacked structure at the step of the forward stair-step structure and the additional step of the reverse stair-step structure, the conductive contact structures each being integral and continuous with one of the conductive structures.

Example 2: the microelectronic device of embodiment 1, wherein the conductive contact structure comprises: first conductive contact structures integral and continuous with some of the conductive structures of the stacked structure at the steps of the forward stair-step structure, each of the first conductive contact structures individually having a horizontal boundary substantially coplanar with a horizontal boundary of one of the steps; and second conductive contact structures integral and continuous with some other of the conductive structures of the stacked structure at the additional steps of the inverted stair-step structure, each of the first conductive contact structures individually having a horizontal boundary substantially coplanar with a horizontal boundary of one of the additional steps.

Example 3: the microelectronic device of one of embodiments 1 and 2, wherein a horizontal width of one or more of the conductive contact structures is substantially equal to a vertical height of one or more of the conductive structures integral with and continuous with the one or more of the conductive contact structures.

Example 4: the microelectronic device of any of embodiments 1-3, further comprising dielectric spacer structures on the steps of the forward stair-step structure and the additional steps of the reverse stair-step structure, the dielectric spacer structures horizontally alternating with the conductive contact structures.

Example 5: the microelectronic device of embodiment 4, wherein the dielectric spacer structure comprises: first dielectric spacer structures on the steps of the forward stair step structure and individually horizontally interposed between horizontally adjacent pairs of the conductive contact structures; and second dielectric spacer structures on the additional steps of the inverted stair-step structure and individually horizontally interposed between additional horizontally adjacent pairs of the conductive contact structures.

Example 6: the microelectronic device of any of embodiments 1-5, wherein an upper vertical boundary of each of the steps of the forward stair-step structure is vertically offset from an upper vertical boundary of each of the additional steps of the reverse stair-step structure.

Example 7: the microelectronic device of any of embodiments 1-6, wherein an upper surface of the step of the forward stair-step structure is vertically offset from an upper surface of the additional step of the reverse stair-step structure vertically closest thereto by a distance substantially equal to a vertical height of one of the layers of the stacked structure.

Example 8: the microelectronic device of any of embodiments 1-7, wherein the depression further comprises a central region horizontally interposed between the forward and reverse stair step structures, the central region having a partially non-planar lower vertical boundary extending horizontally from and between a bottom of the forward and reverse stair step structures.

Example 9: the microelectronic device of any of embodiments 1 through 8, wherein: each of the steps of the forward stair-step structure individually comprises a horizontal end of a pair of the layers of the stacked structure; and each of the additional steps of the inverted stair-step structure individually comprises a horizontal end of an additional pair of the layers of the stacked structure.

Example 10: the microelectronic device of any of embodiments 1 through 8, wherein: each of the steps of the forward stair-step structure individually comprises a horizontal end of a group of at least four of the layers of the stacked structure; and each of the additional steps of the inverted stair-step structure individually comprises a horizontal end of an additional group of at least four of the layers of the stacked structure.

Example 11: the microelectronic device of any of embodiments 1-5 and 8-10, wherein upper vertical boundaries of at least some of the steps of the forward stair-step structure are substantially coplanar with upper vertical boundaries of at least some of the additional steps of the reverse stair-step structure.

Example 12: the microelectronic device of any of embodiments 1-5 and 9-11, wherein the depression further comprises a central region horizontally interposed between the forward and reverse stair-step structures, the central region having a substantially flat lower vertical boundary extending horizontally from a bottom of the forward stair-step structure to a bottom of the reverse stair-step structure.

Example 13: the microelectronic device of any of embodiments 1-5 and 9-12, wherein: one of the steps of the forward stair step structure comprises a horizontal end of one of the layers of the stacked structure; and one of the additional steps of the inverted stair-step structure comprises an additional horizontal end of the one of the layers of the stacked structure.

Example 14: a method of forming a microelectronic device, comprising: forming a preliminary stacked structure comprising a vertically alternating sequence of insulating structures and additional insulating structures arranged in layers, each of the layers comprising one of the insulating structures and one of the additional insulating structures; forming a trench extending vertically into the preliminary stacked structure; forming a horizontally alternating sequence of dielectric spacer structures and dielectric liner structures within horizontal boundaries of the trench, at least some of the dielectric liner structures physically contacting mutually different insulating structures of the preliminary stack structure; and at least partially replacing the dielectric material of the dielectric liner structure and the insulating structure of the preliminary stack structure with a conductive material.

Example 15: the method of embodiment 14, wherein forming a horizontally alternating sequence of dielectric spacer structures and dielectric liner structures within horizontal boundaries of the trench comprises: forming a first dielectric spacer structure within the trench; forming a first dielectric liner structure within the trench and horizontally inward of the first dielectric spacer structure, the first dielectric liner structure physically contacting at least one of the insulating structures of the preliminary stack structure; forming a second dielectric spacer structure within the trench and horizontally inward of the first dielectric liner structure; and forming a second dielectric liner structure within the trench and horizontally inward of the second dielectric spacer structure, the second dielectric liner structure physically contacting at least one other of the insulating structures at a relatively lower vertical position within the preliminary stacked structure than the at least one of the insulating structures.

Example 16: the method of embodiment 15, wherein: forming a first dielectric liner structure within the trench comprises: forming a first portion of the first dielectric liner structure to physically contact a first one of the insulating structures; and forming a second portion of the first dielectric liner structure to physically contact a second one of the insulating structures vertically adjacent to the first one of the insulating structures; and forming a second dielectric liner structure within the trench comprises: forming a first portion of the second dielectric liner structure to physically contact a third one of the insulating structures vertically underlying the second one of the insulating structures; and forming a second portion of the second dielectric liner structure to physically contact a fourth one of the insulating structures vertically adjacent to the third one of the insulating structures.

Example 17: the method of any of embodiments 15 and 16, wherein: forming a first dielectric spacer structure within the trench comprises: forming a first portion of the first dielectric spacer structure to physically contact a first one of the additional insulating structures; and forming a second portion of the first dielectric spacer structure to physically contact a second one of the additional insulating structures vertically adjacent to the first one of the additional insulating structures; and forming a second dielectric spacer structure within the trench comprises: forming a first portion of the second dielectric spacer structure to physically contact a third one of the additional insulating structures that vertically underlies the second one of the additional insulating structures; and forming a second portion of the second dielectric spacer structure to physically contact a fourth one of the additional insulating structures vertically adjacent to the third one of the additional insulating structures.

Example 18: the method of embodiment 14, wherein forming a horizontally alternating sequence of dielectric spacer structures and dielectric liner structures within horizontal boundaries of the trench comprises forming a recess within the preliminary stack structure and within horizontal boundaries of the trench, the recess comprising: a forward stair-step structure having steps including horizontal ends of the layers, some portions of the dielectric liner structure being in physical contact with some of the insulating structures of the preliminary stack structure at the steps of the forward stair-step structure; and an inverted stair-step structure opposite the forward stair-step structure and having an additional step comprising an additional horizontal end of the layer, some other portion of the dielectric liner structure being in physical contact with some other of the insulating structures of the preliminary stack structure at the additional step of the inverted stair-step structure.

Example 19: the method of embodiment 18, wherein forming a low-lying structure comprises forming an upper surface of each of the steps of the forward stair-step structure to be vertically offset from an upper surface of each of the additional steps of the reverse stair-step structure.

Example 20: the method of embodiment 18, wherein forming a depression comprises forming upper surfaces of some of the steps of the forward stair step structure to be substantially coplanar with upper surfaces of some of the additional steps of the reverse stair step structure.

Example 21: the method of any of embodiments 18-20, wherein forming the recessed structure comprises: forming each of the steps of the forward stair step structure to individually include horizontal ends of groups of at least two of the layers of the preliminary stacked structure; and forming each of the additional steps of the inverted stair-step structure into a horizontal end of an additional group comprising at least two of the layers of the preliminary stacked structure, the additional group sharing at least one of the layers of the preliminary stacked structure with the group.

Example 22: a memory device, comprising: a stacked structure having layers each including a conductive structure and an insulating structure vertically adjacent to the conductive structure; -lowered structures positioned at vertical depths different from each other within the stacked structure, each of the lowered structures comprising: a forward stair step structure having steps comprising horizontal ends of the groups of layers; and a reverse stair step structure opposite the forward stair step structure and having additional steps comprising additional horizontal ends of the group of the layers; conductive contact structures extending vertically from at least some of the conductive structures of the stacked structure at the step and the additional step of the depression, the conductive contact structures each being integral and continuous with one of the conductive structures; and a memory cell string extending vertically through the stacked structure.

Example 23: the memory device of embodiment 22, wherein: the stacked structure is divided into an array of blocks, adjacent blocks of the array of blocks being separated from each other by dielectric-filled slots in a first horizontal direction and each extending in a second horizontal direction orthogonal to the first horizontal direction; and the depressions are individually divided between two or more of the adjacent blocks of the array of blocks, the dielectric-filled slots being horizontally interposed between different sections of the depressions.

Example 24: the memory device of embodiment 23, wherein at least some blocks of the array of blocks individually comprise wordline bridge regions extending horizontally from and between segments of some of the recessed structures that are horizontally adjacent to each other in the first horizontal direction.

Example 25: the memory device of any one of embodiments 22-24, further comprising: a data line overlying the stacked structure and electrically coupled to the string of memory cells; a source structure underlying the stack structure and electrically coupled to the string of memory cells; access lines electrically coupled to the conductive contact structures; and a control device electrically coupled to the source structure, the data line, and the access line.

Example 26: an electronic system, comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and including at least one microelectronic device structure, the microelectronic device structure comprising: a stacked structure comprising a vertically alternating sequence of conductive structures and insulating structures arranged in layers; a recessed structure within the stacked structure and comprising opposing stepped structures each having a step comprising an edge of at least some of the layers; and conductive contact structures integral with and continuous with at least some of the conductive structures of the stacked structure at the steps of the opposing stair step structures of the recessed structure, each of the conductive contact structures individually having an inner horizontal boundary substantially coplanar with an inner horizontal boundary of one of the steps of the opposing stair step structures.

While the disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims along with their legal equivalents.