阅读说明：本技术 一种14t抗辐照sram存储单元电路 (14T anti-radiation SRAM memory cell circuit ) 是由 赵强 董汉文 吕盼稂 朱志国 彭春雨 卢文娟 吴秀龙 蔺智挺 陈军宁 于 2021-08-31 设计创作，主要内容包括：本发明公开了一种14T抗辐照SRAM存储单元电路,PMOS晶体管P1和P2交叉耦合,且PMOS晶体管P1、P2作为上拉管,NMOS晶体管N3、N4和PMOS晶体管P5、P6作为下拉管；NMOS晶体管N1和PMOS晶体管P3构成一个反相器,NMOS晶体管N2和PMOS晶体管P4构成另一个反相器,且两个反相器交叉耦合；两个主存储节点Q与QN通过两个NMOS晶体管N5和N6分别与位线BL和BLB相连；两个冗余存储节点S0与S1通过两个PMOS晶体管P7与P8分别与位线BL和BLB相连。上述电路能够在牺牲较小单元面积的情况下大幅度提高单元的速度,并降低单元功耗和提高单元抗单粒子翻转的能力。(The invention discloses a 14T radiation-resistant SRAM memory cell circuit, wherein PMOS transistors P1 and P2 are cross-coupled, the PMOS transistors P1 and P2 are used as pull-up tubes, and NMOS transistors N3 and N4 and PMOS transistors P5 and P6 are used as pull-down tubes; the NMOS transistor N1 and the PMOS transistor P3 form an inverter, the NMOS transistor N2 and the PMOS transistor P4 form another inverter, and the two inverters are cross-coupled; two main storage nodes Q and QN are connected to bit lines BL and BLB through two NMOS transistors N5 and N6, respectively; the two redundant storage nodes S0 and S1 are connected to bit lines BL and BLB through two PMOS transistors P7 and P8, respectively. The circuit can greatly improve the speed of the unit under the condition of sacrificing smaller unit area, reduce the power consumption of the unit and improve the single event upset resistance of the unit.)

1. A 14T radiation-resistant SRAM memory cell circuit comprising six NMOS transistors, referenced in order as N1-N6, and eight PMOS transistors, referenced in order as P1-P8, wherein:

PMOS transistors P1 and P2 are cross-coupled, and PMOS transistors P1 and P2 are used as pull-up tubes, and NMOS transistors N3 and N4 and PMOS transistors P5 and P6 are used as pull-down tubes;

the NMOS transistor N1 and the PMOS transistor P3 form an inverter, the NMOS transistor N2 and the PMOS transistor P4 form another inverter, and the two inverters are cross-coupled;

two main storage nodes Q and QN are connected to bit lines BL and BLB through two NMOS transistors N5 and N6, respectively;

two redundant storage nodes S0 and S1 are connected to bit lines BL and BLB through two PMOS transistors P7 and P8, respectively;

wherein the two NMOS transistors N5, N6 are controlled by a word line WL; the two PMOS transistors P7, P8 are controlled by word line WLB;

two NMOS transistors N5, N6 and two PMOS transistors P7, P8 are used as transmission transistors, the circuit uses four transmission transistors for reading and writing, in the process of writing data, the bit lines BL and BLB write data to two main storage nodes Q and QN and two redundant storage nodes S0 and S1 through the transmission transistors N5, N6, P7 and P8, so that the 4 storage nodes S0, S1 and Q, QN are easier to write data, and the data writing speed and the writing noise tolerance of the circuit are improved.

2. The 14T radiation-resistant SRAM memory cell circuit of claim 1, wherein the specific connection relationship of the transistors in the circuit is as follows:

the bit line BL and NMOS transistor N5 are electrically connected to the source of PMOS transistor P7, the bit line BLB and NMOS transistor N6 are electrically connected to the source of PMOS transistor P8;

word line WL is electrically connected to the gates of NMOS transistors N5 and N6, and word line WLB is electrically connected to the gates of PMOS transistors P7 and P8;

the drain of the NMOS transistor N5 is electrically connected with the drain of the NMOS transistor N1, and the drain of the NMOS transistor N6 is electrically connected with the drain of the NMOS transistor N2;

the drain of the PMOS transistor P7 is electrically connected with the drain of the PMOS transistor P1, and the drain of the PMOS transistor P8 is electrically connected with the drain of the PMOS transistor P2;

the power supply VDD is electrically connected with the sources of the PMOS transistors P1 and P2, and the drains of the NMOS transistors N3 and N4 and the PMOS transistors P5 and P6 are grounded;

the drain of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P3, the source of the PMOS transistor P5, and the gate of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P4, the gate of the NMOS transistor N3;

the drain of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P4, the source of the PMOS transistor P6, and the gate of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P3, the gate of the NMOS transistor N4;

the drain of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N1, and the gate of the PMOS transistor P3 is electrically connected to the gate of the NMOS transistor N1, to the drain of the PMOS transistor P4;

the drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N2, and the gate of the PMOS transistor P4 is electrically connected to the gate of the NMOS transistor N2, to the drain of the PMOS transistor P3;

the source of the PMOS transistor P5 is electrically connected to the drain of the PMOS transistor P1, and the gate of the PMOS transistor P5 is electrically connected to the drain of the PMOS transistor P3;

the source of the PMOS transistor P6 is electrically connected to the drain of the PMOS transistor P2, and the gate of the PMOS transistor P6 is electrically connected to the drain of the PMOS transistor P4;

the drain of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor P3, and the gate of the NMOS transistor N1 is electrically connected to the gate of the PMOS transistor P3, the drain of the PMOS transistor P4, the gate of the PMOS transistor P6, and the drain of the NMOS transistor N2;

the drain of the NMOS transistor N2 is electrically connected to the drain of the PMOS transistor P4, and the gate of the NMOS transistor N2 is electrically connected to the gate of the PMOS transistor P4, the drain of the PMOS transistor P3, the gate of the PMOS transistor P5, and the drain of the NMOS transistor N1;

the drain of the NMOS transistor N3 is electrically connected to the source of the NMOS transistor N1, and the gate of the NMOS transistor N3 is electrically connected to the gate of the PMOS transistor P1, the drain of the PMOS transistor P2, and the source of the PMOS transistor P6;

the drain of the NMOS transistor N4 is electrically connected to the source of the NMOS transistor N2, and the gate of the NMOS transistor N4 is electrically connected to the gate of the PMOS transistor P2, the drain of the PMOS transistor P1, and the source of the PMOS transistor P5.

3. The 14T radiation-resistant SRAM memory cell circuit of claim 1, wherein the gate length of all MOS transistors in the circuit is 65nm, wherein:

the gate width of the PMOS transistors P1 and P2 is 560nm, and the gate width of the PMOS transistors P3 and P4 is 420 nm;

the gate widths of the NMOS transistors N1 and N2 are 420nm, and the gate widths of the NMOS transistors N3 and N4 are 280 nm;

the gate widths of the remaining transistors were all 140 nm.

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a 14T radiation-resistant SRAM memory cell circuit.

Background

With the advance of technology, Static Random Access Memory (SRAM) has been widely used in various aerospace electronics fields. Due to the higher integration level, the influence of Single Event Effects (abbreviated as SET) on the SRAM results in higher and higher probability of Single Event Upset (abbreviated as SEU). Single Event Upset (SEU) is a major reliability failure mechanism that can cause electronic systems to fail by temporarily changing stored values, and when a charged particle hits a sensitive node of an integrated circuit, the induced charge along its path can be effectively collected and accumulated by a drift process, and once the transient voltage pulse generated by the accumulated charge is higher than the switching threshold of the circuit, the stored value in the sensitive node will change, and SEU has become a non-negligible problem for researchers today.

In order to improve the SEU resistance of the unit, the prior art mainly comprises the following schemes:

1) fig. 1 is a schematic diagram of a DICE 12T circuit provided in the prior art, which has 4 storage nodes and 4 pipes. When an SEU occurs on each single storage node, the node is recovered by the rest of nodes. However, when an SEU occurs on any two storage nodes, the storage information of the circuit node will be inverted and cannot be recovered by itself, thereby causing error data to occur.

2) Fig. 2 is a schematic diagram of a prior art QUATRO 10T circuit structure, which has better SEU resistance than a conventional six-tube unit structure, but the unit has poor write capability and poor Hold Noise Margin (HSNM) and Read Static Noise Margin (RSNM).

3) Fig. 3 is a schematic diagram of an S4P8N circuit structure provided in the prior art, which is improved on the basis of a DICE circuit, so that the radiation resistance of the circuit is improved, but the layout area, the read delay, and the Static Noise Margin (SNM) of S4P8N are greatly sacrificed.

4) Fig. 4 is a schematic diagram of a RHPD-12T circuit structure provided by the prior art, which can resist partial double-node flipping based on single-node flipping. But at the expense of lower HSNM and RSNM.

5) Fig. 5 is a schematic diagram of a circuit structure of RHBD14T provided in the prior art, which employs a polarity reinforcement technique to reduce the number of sensitive nodes, but results in a larger read-write delay and a lower noise margin (SNM) value.

Disclosure of Invention

The invention aims to provide a 14T radiation-resistant SRAM memory cell circuit which can greatly improve the speed of a cell under the condition of sacrificing a small cell area, reduce the power consumption of the cell and improve the Single Event Upset (SEU) resistance of the cell.

The purpose of the invention is realized by the following technical scheme:

a 14T radiation resistant SRAM memory cell circuit comprising six NMOS transistors, referenced in order as N1-N6, and eight PMOS transistors, referenced in order as P1-P8, wherein:

PMOS transistors P1 and P2 are cross-coupled, and PMOS transistors P1 and P2 are used as pull-up tubes, and NMOS transistors N3 and N4 and PMOS transistors P5 and P6 are used as pull-down tubes;

the NMOS transistor N1 and the PMOS transistor P3 form an inverter, the NMOS transistor N2 and the PMOS transistor P4 form another inverter, and the two inverters are cross-coupled;

two main storage nodes Q and QN are connected to bit lines BL and BLB through two NMOS transistors N5 and N6, respectively;

two redundant storage nodes S0 and S1 are connected to bit lines BL and BLB through two PMOS transistors P7 and P8, respectively;

wherein the two NMOS transistors N5, N6 are controlled by a word line WL; the two PMOS transistors P7, P8 are controlled by word line WLB;

two NMOS transistors N5, N6 and two PMOS transistors P7, P8 are used as transmission transistors, the circuit uses four transmission transistors for reading and writing, in the process of writing data, the bit lines BL and BLB write data to two main storage nodes Q and QN and two redundant storage nodes S0 and S1 through the transmission transistors N5, N6, P7 and P8, so that the 4 storage nodes S0, S1 and Q, QN are easier to write data, and the data writing speed and the writing noise tolerance of the circuit are improved.

According to the technical scheme provided by the invention, the circuit can greatly improve the speed of the unit under the condition of sacrificing smaller unit area, reduce the power consumption of the unit and improve the single event upset resistance of the unit.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic diagram of a DICE 12T circuit provided in the prior art;

FIG. 2 is a schematic diagram of a QUATRO 10T circuit provided in the prior art;

fig. 3 is a schematic diagram of a circuit structure of S4P8N provided in the prior art;

FIG. 4 is a schematic diagram of an RHPD-12T circuit provided by the prior art;

fig. 5 is a schematic circuit structure diagram of an RHBD14T provided in the prior art;

FIG. 6 is a schematic diagram of a circuit structure of a 14T radiation-resistant SRAM memory cell according to an embodiment of the present invention;

FIG. 7 is a timing waveform diagram of a 14T irradiation-resistant SRAM memory cell circuit according to an embodiment of the present invention;

FIG. 8 shows a 14T irradiation-resistant SRAM memory cell circuit provided by an embodiment of the present invention at different times;

FIG. 9 is a comparison diagram of HSNM, RSNM and WSNM of a prior art SRAM cell circuit and a 14T radiation-resistant SRAM memory cell circuit provided by an embodiment of the present invention;

fig. 10 is a comparison graph of the failure times in 2000 monte carlo simulations for the main storage node to recover its initial state after being injected with a dual-exponential current source pulse at the same time in the SRAM cell circuit of the prior art and the 14T radiation-resistant SRAM cell circuit provided in the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, not all embodiments, and this does not limit the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

FIG. 6 is a schematic diagram of a circuit structure of a 14T radiation-resistant SRAM memory cell according to an embodiment of the present invention; wherein "T" in 14T represents a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the circuit mainly comprises six NMOS transistors and eight PMOS transistors, the six NMOS transistors are sequentially denoted as N1-N6, and the eight PMOS transistors are sequentially denoted as P1-P8, wherein:

PMOS transistors P1 and P2 are cross-coupled, and PMOS transistors P1 and P2 are used as pull-up tubes, and NMOS transistors N3 and N4 and PMOS transistors P5 and P6 are used as pull-down tubes;

the NMOS transistor N1 and the PMOS transistor P3 form an inverter, the NMOS transistor N2 and the PMOS transistor P4 form another inverter, and the two inverters are cross-coupled;

two main storage nodes Q and QN are connected to bit lines BL and BLB through two NMOS transistors N5 and N6, respectively;

two redundant storage nodes S0 and S1 are connected to bit lines BL and BLB through two PMOS transistors P7 and P8, respectively;

wherein the two NMOS transistors N5, N6 are controlled by a word line WL; the two PMOS transistors P7, P8 are controlled by word line WLB;

two NMOS transistors N5, N6 and two PMOS transistors P7, P8 are used as transmission transistors, the circuit uses four transmission transistors for reading and writing, in the process of writing data, the bit lines BL and BLB write data to two main storage nodes Q and QN and two redundant storage nodes S0 and S1 simultaneously through the transmission transistors N5, N6, P7 and P8, so that the 4 storage nodes S0, S1, Q and QN are easier to write data, and the data writing speed and the writing noise tolerance (WSNM) of the circuit are improved.

In a specific implementation, the specific connection relationship of the transistors in the circuit is as follows:

the bit line BL and NMOS transistor N5 are electrically connected to the source of PMOS transistor P7, the bit line BLB and NMOS transistor N6 are electrically connected to the source of PMOS transistor P8;

word line WL is electrically connected to the gates of NMOS transistors N5 and N6, and word line WLB is electrically connected to the gates of PMOS transistors P7 and P8;

the drain of the NMOS transistor N5 is electrically connected with the drain of the NMOS transistor N1, and the drain of the NMOS transistor N6 is electrically connected with the drain of the NMOS transistor N2;

the drain of the PMOS transistor P7 is electrically connected with the drain of the PMOS transistor P1, and the drain of the PMOS transistor P8 is electrically connected with the drain of the PMOS transistor P2;

the power supply VDD is electrically connected with the sources of the PMOS transistors P1 and P2, and the drains of the NMOS transistors N3 and N4 and the PMOS transistors P5 and P6 are grounded;

the drain of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P3, the source of the PMOS transistor P5, and the gate of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P4, the gate of the NMOS transistor N3;

the drain of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P4, the source of the PMOS transistor P6, and the gate of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P3, the gate of the NMOS transistor N4;

the drain of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N1, and the gate of the PMOS transistor P3 is electrically connected to the gate of the NMOS transistor N1, to the drain of the PMOS transistor P4;

the drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N2, and the gate of the PMOS transistor P4 is electrically connected to the gate of the NMOS transistor N2, to the drain of the PMOS transistor P3;

the source of the PMOS transistor P5 is electrically connected to the drain of the PMOS transistor P1, and the gate of the PMOS transistor P5 is electrically connected to the drain of the PMOS transistor P3;

the source of the PMOS transistor P6 is electrically connected to the drain of the PMOS transistor P2, and the gate of the PMOS transistor P6 is electrically connected to the drain of the PMOS transistor P4;

the drain of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor P3, and the gate of the NMOS transistor N1 is electrically connected to the gate of the PMOS transistor P3, the drain of the PMOS transistor P4, the gate of the PMOS transistor P6, and the drain of the NMOS transistor N2;

the drain of the NMOS transistor N2 is electrically connected to the drain of the PMOS transistor P4, and the gate of the NMOS transistor N2 is electrically connected to the gate of the PMOS transistor P4, the drain of the PMOS transistor P3, the gate of the PMOS transistor P5, and the drain of the NMOS transistor N1;

the drain of the NMOS transistor N3 is electrically connected to the source of the NMOS transistor N1, and the gate of the NMOS transistor N3 is electrically connected to the gate of the PMOS transistor P1, the drain of the PMOS transistor P2, and the source of the PMOS transistor P6;

the drain of the NMOS transistor N4 is electrically connected to the source of the NMOS transistor N2, and the gate of the NMOS transistor N4 is electrically connected to the gate of the PMOS transistor P2, the drain of the PMOS transistor P1, and the source of the PMOS transistor P5.

In addition, in a specific implementation process, gate lengths of all MOS transistors in the circuit may be 65nm, where:

the gate width of the PMOS transistors P1 and P2 is 560nm, and the gate width of the PMOS transistors P3 and P4 is 420 nm;

the gate widths of the NMOS transistors N1 and N2 are 420nm, and the gate widths of the NMOS transistors N3 and N4 are 280 nm;

the gate widths of the remaining transistors were all 140 nm.

Based on the circuit structure, the principle of the 14T radiation-resistant SRAM memory cell circuit provided by the embodiment of the present invention is as follows:

in the holding stage, the bit lines BL and BLB are precharged to high, the word line WL is low, the word line WLB is high, the initial state is maintained inside the circuit, and the circuit does not operate.

When in the read data phase, the bit lines BL and BLB are precharged to high level, the word line WL is high level, the word line WLB is low level, and the pass transistors N5, N6, P7 and P8 are turned on; if the cell circuit stores data of '0', Q-S0-0, QN-S1-1; then BL goes through discharge path 1: transistors P7 and P5, and discharge path 2: the transistors N5, N1, and N3 discharge to ground, so that the bit lines generate a voltage difference, and then data is read out through the sense amplifier; if the cell circuit stores data of '1', Q-S0-1 and QN-S1-0, then BLB passes through discharge path 1: transistors P6 and P8, and discharge path 2: the transistors N6, N2, and N4 discharge to ground, so that a bit line voltage difference is generated, and then data is read out through the sense amplifier.

In the data writing phase, the word line WL is at high level, the word line WLB is at low level, if BL is at high level and BLB is at low level, then '1' is written to the storage node Q point and S0 point through the pass transistors N5 and P7, respectively; if BL is low and BLB is high, '0' is written to the storage node QN point and S1 point through pass transistors N6 and P8, respectively. During the writing process, because data are written into the internal nodes Q \ S0 and QN \ S1 simultaneously through the transmission transistors N5 and P7 and N6 and P8, the data are written into the storage nodes more easily, so that the writing speed is greatly improved, and simultaneously, the power consumption of the circuit is reduced due to the great improvement of the writing speed.

When only the improvement of the radiation resistance of the circuit structure is considered, if the storage node of the circuit is bombarded by particles, because the circuit nodes S0 and S1 are both surrounded by PMOS transistors, according to the polarity reinforcement principle, space particles bombard sensitive node PMOS tubes, only 0-1 voltage pulse is generated at the node, and the pulse cannot influence the state of other transistors due to the existence of gate capacitance, so that the external nodes S0 and S1 effectively avoid the occurrence of inversion, and meanwhile, the stability of the data of the nodes S0 and S1 ensures that the internal nodes Q and QN can be restored to the initial state after the inversion, thereby improving the SEU resistance of the circuit, and if other non-critical nodes are bombarded by particles, the storage unit is more difficult to be influenced.

It is noted that those skilled in the art will recognize that embodiments of the present invention are not described in detail herein.

Fig. 7 is a timing waveform diagram of a 14T radiation-resistant SRAM memory cell circuit according to an embodiment of the present invention, where simulation conditions are: corner: TT; temperature:27 ℃; VDD: 1.2V. It is clear from the figure that the proposed radiation-resistant RHM-14T cell can perform normal read and write and hold operations.

Fig. 8 is a simulation diagram of transient waveforms of the 14T radiation-resistant SRAM memory cell circuit provided in the embodiment of the present invention, where different nodes are subjected to dual-exponential current source pulse injection at different times, where the simulation conditions are as follows: VDD: 1.2V. It can be seen from the figure that the proposed radiation-resistant RHM-14T cell can be restored to its initial state upon the occurrence of an SEU.

As shown in fig. 9, which is a comparison graph of HSNM, RSNM, and WSNM of the SRAM cell circuit in the prior art and the 14T radiation-resistant SRAM memory cell circuit provided in the embodiment of the present invention, simulation conditions are: corner: TT; temperature:27 ℃; VDD: 1.2V. As can be seen from the figure, the proposed HSNM, RSNM and WSNM of RHM-14T all have greater advantages than other comparative circuits.

Fig. 10 is a comparison graph of failure times in 2000 monte carlo simulations in which the main storage node of the SRAM cell circuit of the prior art and the 14T radiation-resistant SRAM cell circuit provided in the embodiment of the present invention recover their initial state after being injected with a dual-exponential current source pulse at the same time, where the simulation conditions are as follows: MC as Corner; temperature of 27 ℃; VDD is 1.2V. As can be seen in the figure, the proposed RHM-14T cell failed only 2 times in 2000 Monte Carlo simulations, similar to the DICE and S4P8N cell, but far superior to the Quatro, RHPD-12T and RHBD14T cells.

Table 1 is a circuit area, read-write time, and power consumption simulation comparison table of an SRAM cell circuit in the prior art and a 14T anti-irradiation SRAM memory cell circuit provided in the embodiments of the present invention, and the simulation conditions are: corner: TT; temperature:27 ℃; VDD: 1.2V. As can be seen from Table 1, the proposed RHM-14T cell has faster read and write speeds, smaller area and power consumption than most other comparative circuits.

TABLE 1

Unit cell	Area (μm)2)	Read delay (ps)	Write latency (ps)	Power consumption (μ W)
					DICE	7.35	60.8	27.3	7.785
Quatro	6.4	119.2	388.02	7.43
					S4P8N	10.24	82.4	34.4	7.73
RHPD-12T	7.68	57.5	20.4	10.45
					RHBD14T	8.45	165.3	496.5	6.79
RHM-14T	8.95	67.5	52.7	7.64

Table 2 is a comparison table of critical charges of SRAM unit circuits in the prior art and the 14T radiation-resistant SRAM memory unit provided by the embodiment of the invention, and the simulation conditions are Corner: TT; temperature of 27 ℃; VDD: 1.2V. As can be seen from Table 2, the proposed RHM-14T cell critical charge is only higher than that of the Quatro circuit.

TABLE 2

Circuit name	Critical charge (fC)
		Quatro	9.96
RHM-14T	19.1
		RHPD-12T	32.61
DICE	>50
		S4P8N	>50
RHBD14T	>50

In summary, the circuit according to the embodiment of the invention ensures the stability of the redundant nodes S0 and S1, thereby enhancing the anti-flipping capability of the nodes inside the circuit; meanwhile, the data writing speed and the writing noise tolerance (WSNM) of the unit are greatly improved, and simulation results show that compared with the existing four SRAM units, the circuit has more outstanding writing speed and noise tolerance compared with other four SRAMs.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims. The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.