阅读说明：本技术 存储器电路以及用于提供电平的方法 (Memory circuit and method for providing level ) 是由 李伯浩 李嘉富 史毅骏 于 2021-04-01 设计创作，主要内容包括：公开了一种电路,包括相互交叉耦合的第一晶体管和第二晶体管,使得第一晶体管的源极和第二晶体管的源极均连接至电源,第一晶体管的栅极在第一节点处连接至第二晶体管的漏极,第二晶体管的栅极在第二节点处连接至第一晶体管的漏极。该电路可通过第二晶体管和第三晶体管将配置为第一电平的电源直接耦合至存储器单元,从而向存储器单元提供字线电压的第一电平,并且通过第二晶体管和第三晶体管将配置为第二电平的电源直接耦合至存储器单元,从而向存储器单元提供字线电压的第二电平。本发明的实施例还公开了一种用于提供电平的方法。(A circuit is disclosed comprising a first transistor and a second transistor cross-coupled to each other such that a source of the first transistor and a source of the second transistor are both connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, and a gate of the second transistor is connected to the drain of the first transistor at a second node. The circuit may directly couple the power supply configured at the first level to the memory cell through the second transistor and the third transistor to provide the first level of the word line voltage to the memory cell, and directly couple the power supply configured at the second level to the memory cell through the second transistor and the third transistor to provide the second level of the word line voltage to the memory cell. The embodiment of the invention also discloses a method for providing the level.)

1. A memory circuit, comprising:

a first transistor and a second transistor cross-coupled to each other such that a first source/drain of the first transistor and a first source/drain of the second transistor are both connected to a power supply, a gate of the first transistor is connected to a second source/drain of the second transistor at a first node, a gate of the second transistor is connected to a second source/drain of the first transistor at a second node,

wherein the circuitry is configured to: providing a first level of a word line voltage to a memory cell when reading the memory cell and a second level of the word line voltage to the memory cell when writing the memory cell, and

wherein the circuitry is configured to: the power supply configured at a first level is directly coupled to the memory cell through the second and third transistors to thereby provide a first level of a word line voltage to the memory cell, and the power supply configured at a second level is directly coupled to the memory cell through the second and third transistors to thereby provide a second level of the word line voltage to the memory cell.

2. The memory circuit of claim 1, wherein the second level of the power supply is substantially higher than the first level of the power supply, and the second level of the word line voltage is substantially higher than the first level of the word line voltage.

3. The memory circuit of claim 1, wherein the third transistor is turned on by a first control signal configured at a first level when the first level of the word line voltage is provided to the memory cell, and the third transistor is turned on by the first control signal configured at a second level when the second level of the word line voltage is provided to the memory cell.

4. The memory circuit of claim 3, wherein when the first level of the word line voltage is provided to the memory cell, the voltage at the second node is reduced to the first level of the first control signal through a first discharge path, and the voltage at the first node is substantially equal to the first level of the power supply.

5. The memory circuit of claim 3, wherein when the second level of the word line voltage is provided to the memory cell, the voltage at the second node is reduced to the second level of the first control signal through a second discharge path, and the voltage at the first node is substantially equal to the second level of the power supply.

6. The memory circuit of claim 5, wherein the second discharge path includes a fourth transistor that is turned on by a first control signal configured to a second level, and wherein the voltage at the second node is clamped at the second level of the first control signal by the fourth transistor.

7. The memory circuit of claim 3, further comprising:

a fifth transistor;

a sixth transistor; and

a seventh transistor;

wherein a first source/drain of the fifth transistor is connected to the power supply and a second source/drain is connected to a first source/drain of the sixth transistor, and the fifth transistor is selectively turned on based on reading or writing the memory cell,

wherein a second source/drain of the sixth transistor is connected to a first source/drain power supply of the seventh transistor at a third node and the sixth transistor is gated by the power supply,

wherein the seventh transistor has a second source/drain connected to ground and the sixth transistor is gated by a reference voltage, an

Wherein a voltage at the third node determines the first level or the second level of the first control signal.

8. The memory circuit of claim 7, wherein the first level of the first control signal is equal to the first level of the power supply minus the reference voltage, and the second level of the first control signal is equal to the second level of the power supply minus the reference voltage.

9. A memory circuit, comprising:

a first transistor and a second transistor cross-coupled to each other such that a source of the first transistor and a source of the second transistor are both connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to the drain of the first transistor at a second node,

a third transistor having a source connected to the first node; and

a fourth transistor having a source connected to the second node,

wherein the circuitry is configured to: coupling a first level of the power supply to a drain of the third transistor through the second and third transistors to generate an output voltage at the drain of the third transistor at a first level, and coupling a second level of the power supply to a drain of the third transistor through the second and third transistors to generate an output voltage at the drain of the third transistor at a second level, the second level of the power supply being substantially higher than the first level of the output voltage.

10. A method for providing a level, the method comprising:

configuring a first transistor and a second transistor to be cross-coupled to each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, and a gate of the second transistor is connected to the drain of the first transistor at a second node;

in response to the power supply being configured at a first level, coupling the first level of the power supply directly to the first node and then across a turned-on third transistor to an output node; and is

In response to the power supply being configured at a second level substantially higher than the first level, the second level of the power supply is coupled directly to the first node and then coupled across a turned-on third transistor to the output node.

Technical Field

Embodiments of the invention relate to a memory circuit and a method for providing a level.

Background

The memory circuit typically includes a memory array including a plurality of memory cells coupled to word lines and bit line arrangements. Each memory cell is coupled to a corresponding pair of word and bit lines. There may be multiple memory cells coupled to a given word line and/or a given bit line. As used herein, the term "word line" is sometimes referred to as a "row" of the memory array; as used herein, the term "bit line" is sometimes referred to as a "column" of the same memory array.

Typically, a word line driver circuit (hereinafter "word line driver") is coupled to each word line in the memory circuit. Within a memory array, one word line is typically activated at a given time, and a respective memory cell coupled to the activated word line is accessed (e.g., read, written, or refreshed). At this point, other word lines in the memory circuit may remain inactive. The voltage on the activated word line is controlled by a word line driver coupled to the activated word line. The activated word line is selected by providing a word line address signal to a word line decoder in the memory circuit. A word line decoder selectively activates a word line driver coupled to the addressed word line.

Disclosure of Invention

According to an aspect of an embodiment of the present invention, there is provided a memory circuit including: a first transistor and a second transistor cross-coupled to each other such that a first source/drain of the first transistor and a first source/drain of the second transistor are both connected to a power supply, a gate of the first transistor is connected to a second source/drain of the second transistor at a first node, and a gate of the second transistor is connected to a second source/drain of the first transistor at a second node, wherein the circuit is configured to: providing a first level of a word line voltage to the memory cell when reading the memory cell and a second level of the word line voltage to the memory cell when writing the memory cell, and wherein the circuitry is configured to: the power supply configured at the first level is directly coupled to the memory cell through the second transistor and the third transistor to thereby supply the first level of the word line voltage to the memory cell, and the power supply configured at the second level is directly coupled to the memory cell through the second transistor and the third transistor to thereby supply the second level of the word line voltage to the memory cell.

According to another aspect of an embodiment of the present invention, there is provided a memory circuit including: a first transistor and a second transistor cross-coupled to each other such that a source of the first transistor and a source of the second transistor are both connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to the drain of the first transistor at a second node, a third transistor, a source of the third transistor is connected to the first node; and a fourth transistor having a source connected to the second node, wherein the circuit is configured to: the first level of the power supply is coupled to the drain of the third transistor through the second transistor and the third transistor to generate the output voltage of the first level at the drain of the third transistor, and the second level of the power supply is coupled to the drain of the third transistor through the second transistor and the third transistor to generate the output voltage of the second level at the drain of the third transistor, the second level of the power supply being substantially higher than the first level of the output voltage.

According to yet another aspect of embodiments of the present invention, there is provided a method for providing a level, the method including: configuring the first transistor and the second transistor to be cross-coupled to each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, and a gate of the second transistor is connected to the drain of the first transistor at a second node; in response to the power supply being configured at the first level, coupling the first level of the power supply directly to the first node and then across the turned-on third transistor to the output node; and in response to the power supply being configured to a second level substantially higher than the first level, coupling the second level of the power supply directly to the first node and then across the turned-on third transistor to the output node.

Drawings

Various embodiments of the present invention are best understood from the following detailed description when read with the accompanying drawing figures. Note that, according to standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a block diagram of a memory circuit, according to some embodiments.

FIG. 2 illustrates a schematic diagram of a memory cell including the memory circuit of FIG. 1 in accordance with some embodiments.

FIG. 3 illustrates a circuit diagram of a word line driver of the memory circuit of FIG. 1 in accordance with some embodiments.

FIG. 4 illustrates waveforms (including respective waveforms of various signals) when operating the wordline driver of FIG. 3, according to some embodiments.

Fig. 5 illustrates a circuit diagram of a control signal generation circuit coupled to (or integrated with) the word line driver of fig. 3 in accordance with some embodiments.

Fig. 6 illustrates a circuit diagram of a bias generation circuit coupled to (or integrated with) the control signal generation circuit of fig. 5, in accordance with some embodiments.

Fig. 7 illustrates a circuit diagram of another bias generation circuit coupled to (or integrated with) the control signal generation circuit of fig. 5, in accordance with some embodiments.

FIG. 8 illustrates a flow diagram of a method of operating the word line drivers of FIG. 3 in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "lower," "below," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein interpreted accordingly.

In the context of memory circuits (e.g., Resistive Random Access Memory (RRAM) circuits) rising, the word line voltage applied to a memory cell when writing the cell sometimes needs to be higher than the word line voltage applied when reading the cell. Using a higher word line voltage may advantageously improve the efficiency of writing to the memory cells, which in turn may improve various characteristics of the memory circuit, such as memory capacity (i.e., density), delay, cycle time, and retention time, among others. In this manner, the corresponding word line drivers may be configured to provide multiple levels of word line voltage.

In prior art solutions it is suggested to include a high voltage level shifter in the word line driver. However, such high voltage level shifters typically include at least one pair of cross-coupled transistors and a pair of mirror circuits coupled to the cross-coupled transistors, respectively, which may disadvantageously compromise area and/or cost in the overall design of the memory circuit. In addition, since the higher voltages applied to memory cells can damage the transistors associated with these cells over time, additional transistor management voltages are typically added during the output phase of the word line drivers. Often, one does not want to introduce these extra transistors into the wordline driver, especially considering that they have an impact on the overall design, at least in terms of cost and performance. For a region neutral design, the transistor impedance may be increased using a cascade arrangement. However, due to the number of transistors (typically greater than 4) making up the cascaded section, additional power is often required to partially bias the cascaded section in order to properly operate such cascaded section. Therefore, the existing word line drivers are not completely satisfactory.

Various embodiments of a wordline driver are provided that can provide at least two levels of wordline voltage while occupying half or less of the area of existing wordline drivers. For example, the word line drivers disclosed herein include a pair of cross-coupled transistors and do not include a mirror circuit coupled to the cross-coupled transistors. In this manner, the design of the word line drivers disclosed herein may be significantly simplified, which may advantageously reduce the corresponding area occupied by the word line drivers. Further, the word line driver disclosed in the present invention includes a cascade portion formed of at most two transistors. Thus, the disclosed wordline driver may consume less power than existing wordline drivers.

Embodiments of the disclosed word line drivers may be used in various memory circuits or components thereof to improve real-estate usage while maintaining performance. The memory circuit may include embedded memory (e.g., memory embedded within an IC) or stand-alone (e.g., discrete) memory (e.g., memory that is a primary element within an IC). Examples of memory include, but are not limited to, volatile, non-volatile, static, dynamic, read-only, random access, flash, one-time programmable, multi-time programmable, magnetic Phase Change Memory (PCM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), and the like. Embedded memory, such as microprocessors, digital processing devices, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), and the like, are included in larger functional blocks often referred to as logic circuits.

Generally, Integrated Circuit (IC) fabrication techniques provide at least two different types of transistors. Input/output (I/O) transistors are examples of the first class. The I/O transistors are designed to operate in a relatively high voltage environment (e.g., a nominal voltage of 1.7 volts). To withstand relatively high voltages without the gate oxide breaking down, I/O transistors are formed having a relatively thick gate oxide (e.g., greater than about 50 angstroms thick) and a relatively long channel length (e.g., about 2 times the length of a thin oxide transistor). Accordingly, a first type of transistor is capable of withstanding relatively high voltages and has a relatively thick gate oxide, which may be referred to herein as a "thick oxide transistor" or "thick oxide FET.

On the other hand, a second class of transistor examples provided by IC fabrication technology are logic transistors. Logic transistors are designed to operate in a lower voltage environment (e.g., a nominal voltage of 1.1 volts). Since the voltage applied to these transistors is lower than the voltage applied to the thick oxide transistors, the gate oxide of the logic transistors need not be as thick as the gate oxide of thick oxide devices. For example, the gate oxide thickness of a typical logic transistor may be about 10-12 angstroms and the channel length shorter (e.g., at a minimum specified lithographic dimension). Accordingly, transistors of the second type are capable of withstanding relatively low voltages and have a relatively thin gate oxide, which may be referred to herein as "thin oxide transistors" or "thin oxide FETs". According to various embodiments of the present disclosure, each of the transistors included in the word line drivers of the present disclosure may be a thin oxide transistor, which will be discussed in further detail below.

FIG. 1 shows a block diagram of an example memory circuit 100, in accordance with various embodiments. The memory circuit 100 includes a memory array 102, a Bit Line (BL) driver 106, and a Word Line (WL) driver 108. It should be understood that the embodiment of the memory circuit 100 shown in fig. 1 is simplified and, thus, the memory circuit 100 may include one or more other blocks (or circuits) while remaining within the scope of the present invention. For example, memory circuit 100 may include one or more multiplexers coupled between memory array 102 and BL driver 106 and between memory array 102 and WL driver 108, one or more input/output circuits (sense amplifiers), and so on.

Still referring to FIG. 1, in more detail, the memory array 102 includes a plurality of memory cells (e.g., 102-1) arranged in a column and row configuration. Each of the memory cells is arranged in an interaction of a respective one of the plurality of columns and a respective one of the plurality of rows. Each column may correspond to a BL and each row may correspond to a WL. As such, each memory cell is coupled to a respective BL and WL pair such that one or more other circuits (e.g., BL drivers, WL drivers, etc.) can access the memory cell through the BL and WL pair. For example, in FIG. 1, memory cell 102-1 is coupled to BL driver 106 through BL 116-1 and WL 118-1, BL 116-1 and WL 118-1 being one of a plurality of BL's (116-1, 116-2, 116-3 … 116-N) and one of a plurality of WL's (118-1, 118-2, 118-3 … 118-M), respectively, where N may correspond to a plurality of columns of memory array 102 and M may correspond to a plurality of rows of memory array 102.

Continuing with the above example, BL driver 106 and WL driver 108 may access memory cell 102-1 by asserting (e.g., activating) BL 116-1 and WL 118-1, respectively, based on the column address and the row address. In some embodiments, in response to asserting BL 116-1, BL driver 106 may apply a BL signal (e.g., BL signal 117) to memory cell 102-1 via asserted BL 116-1, the signal level of which is determined based on the logic state that memory cell 102-1 is writing or presenting. In response to assertion of WL 118-1, WL driver 108 may apply a WL signal (e.g., WL signal 119) to memory cell 102-1 via asserted WL 118-1, the signal level of which is determined according to whether memory cell 102-1 is being written to or being presented. According to some embodiments, each of the BL signal 117 and the WL signal 119 may be a voltage signal, and thus, the respective signal level may be a voltage level. In some other embodiments, the BL signal 117 and the WL signal 119 may be current signals, while remaining within the scope of the present invention.

As described above, the memory driver 108 disclosed in the present invention can be used for various memories. As a representative example, FIG. 2 illustrates in a schematic diagram that memory cell 102-1 comprises an RRAM memory cell. It should be understood that memory cell 102-1 may comprise any other type of memory cell (e.g., MRAM memory cells, DRAM memory cells, etc.) while remaining within the scope of the present invention. As shown in FIG. 2, memory cell 102-1 includes a resistor 120 having a variable resistance and a transistor 122 coupled in series to resistor 120. In some embodiments, the resistor 120 may form a multilayer stack, wherein the resistance of the resistor 120 varies with the voltage applied to the resistor 120. In general, the transistor 122 coupled in series to the resistor 120 is referred to as a "select transistor" or "enable transistor" and the circuit is configured to enable a conduction path through the coupling resistor 120.

Memory cell 102-1 is formed as a three terminal device that is coupled to 3 signal lines and acts as an RRAM cell. For example, one end of resistor 120 is not coupled to the drain of transistor 122, but is connected to BL 116-1, the gate of transistor 122 is connected to WL 118-1, and the source of transistor 122 is connected to source line 130. As such, memory cell 102-1 may be accessed via a signal line.

For example, when writing to memory cell 102-1, WL driver 108 may configure WL signal 119 to a first level (hereinafter "write level"), and then apply WL signal 119 to the gate of transistor 122 via WL 118-1. In response, BL driver 106 may configure BL signal 117 to a certain level depending on whether a high logic state or a low logic state is written to memory cell 102-1, and then apply BL signal 117 to resistor 120 via BL 116-1. On the other hand, when reading memory cell 102-1, WL driver 108 may configure WL signal 119 to a second level (hereinafter "read level"), and then apply WL signal 119 to the gate of transistor 122 via WL 118-1. In response, BL driver 106 may configure BL signal 117 to a certain level and then apply BL signal 117 to resistor 120 via BL 116-1. In some embodiments, WL driver 108 may configure the write level to be substantially higher than the read level to increase the efficiency of writing to memory cell 102-1.

Fig. 3 illustrates an example circuit diagram of the WL driver 108 according to various embodiments. The WL driver 108 is configured to: receives a plurality of control signals 311, 313, 315, 317, and 319 (each discussed below) and provides a WL signal 321 based on the respective signal levels of the control signals. Such WL signals 321 may be provided to the memory cells via the respective WLs for reading or writing to the memory cells, which are substantially similar to WL signals 119, as discussed above for fig. 1 and 2. It should be understood that the embodiment of the WL driver 108 shown in fig. 3 is simplified and, thus, the WL driver 108 may include one or more other components to perform the respective function(s) while remaining within the scope of the present invention. For example, the WL driver 108 may include one or more decoders configured to indicate which coupled WL is asserted based on the received row address, thereby applying the generated WL signal 321 via the asserted WL.

Still referring to fig. 3, in more detail, the WL driver 108 includes a transistor MP0, a transistor MP1, a transistor MP2, a transistor MP3, a transistor MP4, a transistor MN1, a transistor MN2, a transistor MN3, a transistor MN4, a transistor MN5, and a transistor MN6, and an inverter 302. In some embodiments, each of the transistors MP 1-MP 4 comprises a p-type metal oxide semiconductor field effect transistor (pMOSFET), and each of the transistors MN 1-MN 6 comprises an n-type metal oxide semiconductor field effect transistor (nMOSFET). It should be understood that each of the transistors MP 1-MP 4 and MN 1-MN 6 may include various other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.), while remaining within the scope of the present invention. The transistor MP 1-the transistor MP 4-the transistor MN 1-the transistor MN 6-and the inverter 302 are coupled to each other between the first power supply 301 and the second power supply 303, which will be discussed below.

For example, the transistor MP1 and the transistor MP2 are cross-coupled to each other. Specifically, the source of the transistor MP1 and the source of the transistor MP2 are connected to the power supply 301, the gate of the transistor MP1 is connected to the drain of the transistor MP2 at the node Y, and the gate of the transistor MP2 is connected to the drain of the transistor MP1 at the node X. Further, the drain of the transistor MP1 and the source of the transistor MP3 are connected at a node X. The drain of the transistor MP2 and the source of the transistor MP4 are connected at a node Y. The control signal 313 gates each of the transistor MP3 and the transistor MP 4. The drain of the transistor MP3 is connected to the drain of the transistor MN 2. The drain of transistor MP4 is connected to the drain of transistor MN3 at node Z. The control signal 315 gates each of the transistor MN2 and the transistor MN 3. A source of the transistor MN2 is coupled to a source of the transistor MN4 and to a drain of the transistor MN 6. The control signals 317 and 319 gate the transistor MN4 and the transistor MN6, respectively. The source of transistor MN6 is connected to power supply 303. The source of the transistor MN3 is connected to the drain of the transistor MN 5. The source of transistor MN3 is coupled to power supply 303. Inverter 302 is configured to: receives control signal 319 at its input and provides a logical inverse of control signal 319 at its output to the gate of transistor MN 5. The drain of the transistor MN4 is connected to the source of the transistor MN 1. Control signal 315 also gates transistor MN 1. The drain of the transistor MN1 is connected to the drain of the transistor MP 0. Control signal 311 also gates transistor MP 0. The source of the transistor MP0 is connected to the power supply 301.

The operation of the example WL driver 108 shown in fig. 3 is described in connection with the waveform diagram 400 of fig. 4. In fig. 4, respective example signal levels of the control signal 311, the control signal 313, the control signal 317, and the control signal 319, the power supply 301, and the WL signal 321 are shown. Each of the control signal 311, the control signal 313, the control signal 317, the control signal 319, and the power supply 301 varies between two signal levels over time, causing the WL signal 321 generated by the WL driver 108 to be at a read level and a write level, respectively. In various embodiments, the write level is substantially greater than the read level. In various embodiments, the control signal 315 (not shown in fig. 4) may remain in a high logic state, thereby keeping the transistor MN1, the transistor MN2, and the transistor MN3 conductive during generation of the read level and the write level of the WL signal 321. In various embodiments, the difference between the power supply 301 and the control signal 313 may remain fixed during generation of the read level and the write level of the WL signal 321.

From time t0 to time t1, control signal 317 is provided at a high logic state ("logic 1"). In some embodiments, when the control signal 317 is configured as a logic 1, the WL driver 108 circuit may be configured to provide the WL signal 321 at a read level. Thus, the WL driver 108 may provide such WL signal 321 to the memory cell when reading the memory cell. During the time from time t0 to time t1, power supply 301 may be configured to a first level (e.g., about 1 volt); control signal 313 has been provided at a first level (e.g., about 0 volts); providing a control signal 319 at a low logic state ("logic 0"); and provides control signal 311 at logic 1. Additional transistor management voltages are typically added during the output phase of the word line drivers. With control signal 313 configured at about 0 volts, transistor MP3 and transistor MP4 are turned on, which enables the voltage at node X to discharge (e.g., decrease) to about 0 volts (substantially equal to the signal level of control signal 313) in response to the voltage at node X forming a discharge path (propagating through or from node X), as will be discussed below.

In some embodiments, a time period in which the control signal 319 is logic 0 and the control signal 317 is logic 1 (e.g., a time period from time t0 to time t 1) may be sometimes referred to as a read standby period. In the read standby period, the WL driver 108 may not have converted the WL signal 321 to the read level yet, e.g., the WL signal 321 remains at 0 volts. When transistor MP4 is turned on, transistor MP1 may be turned on while cross-coupled transistor MP2 is turned off, which causes the voltage at node X to be substantially equal to the first level of power supply 301 (e.g., about 1 volt).

From time t1 to time t2, the control signal 319 will transition from a logic 0 to a logic 1, which in turn may transition the WL signal 321 from approximately 0 volts to the read level. In some embodiments, the read level of the WL signal 321 may be substantially equal to the first level of the power supply 301. For example, transistor MN6 is turned on in response to control signal 319 transitioning to a logic 1. Upon turning on the transistor MN6, a discharge path 351 may be formed from the node X to the power supply 303 (e.g., ground) via the transistor MN1, the transistor MN4, and the transistor MN6, thereby reducing the voltage at the node X from approximately 1v to a signal level substantially equal to the control signal 313 (e.g., approximately 0 volts). As such, transistor MP2 may be turned on while cross-coupled transistor MP1 is turned off, thereby coupling the first level (e.g., about 1 volt) of power supply 301 to node Y. Since transistor MP4 has been turned on by control signal 313 (configured to about 0 volts), the first level of power supply 301 may be provided to node Z, which may cause WL signal 321 to increase to substantially equal the first level of power supply 301 (e.g., about 1 volt). Referring again to the control signal 319 converted to logic 1, the transistor MN5 (gated by the logically inverted control signal 319) is turned off. As such, a discharge path from node Z to power supply 303 (ground) via transistor MN3 and transistor MN5 is not established, which may effectively couple the first level of power supply 301 to node Z.

From time t2 to time t3, the signal levels of control signal 311, control signal 313, control signal 317, control signal 319, and power supply 301 may remain unchanged. As such, during the time period from time t2 to time t3, WL driver 108 may provide WL signal 321 at a read level. In some embodiments, the period may be predetermined according to the type of memory cell coupled to the WL driver 108.

From time t3 to time t4, transitioning control signal 319 from logic 1 to logic 0, WL driver 108 may stop providing WL signal 321, e.g., providing WL signal 321 at approximately 0 volts. Specifically, when the control signal 319 is at logic 0, the transistor MN6 is turned off, thereby disconnecting the discharge path 351, which gradually turns off the transistor MP2, stopping the WL signal 321 supplied at the non-zero level. In some embodiments, after providing the WL signal 321 at a non-zero level (e.g., at time t3), the transistor MP0 may be turned on by transitioning the control signal 311 from a logic 1 to a logic 0. As such, the first level of power supply 301 may be coupled to node X by turning on transistor MP0, which may pull the voltage at node X from about 0 volts to about 1 volt. Therefore, the transistor MP2 can be turned off more quickly, which can advantageously reduce the power consumption of the WL driver 108. The control signal 311 may remain at logic 0 for a relatively short time. For example, the period from time t4 to time t5 is about 1-2 nanoseconds, after time t5, the control signal 311 is converted back to a logic 1.

From time t6 to time t7, control signal 317 is transitioned from logic 1 to logic 0. In some embodiments, when the control signal 317 is configured as a logic 0, the WL driver 108 may be configured to provide the WL signal 321 at a write level. Thus, when writing to a memory cell, WL driver 108 may provide such WL signal 321 to the memory cell. During the time from time t6 to time t7, power supply 301 is configured to increase to a second level (e.g., about 2 volts); configure control signal 313 to increase to a second level (e.g., about 1 volt); control signal 319 remains at logic 0; the control signal 311 remains at logic 1. When the configuration control signal 313 is about 1 volt, the transistor MP3 and the transistor MP4 remain conductive such that the voltage at node X is discharged (e.g., reduced) to about 1 volt (substantially equal to the signal level of the control signal 313) in response to forming a discharge path (propagating through or from node X). From time t7 to time t8, the control signal 319 remains at logic 0, keeping the transistor MN6 off. That is, a discharge path from junction X to ground via transistor MN6 cannot be established.

In some embodiments, the control signal 319 is logic 0 and the control signal 317 is logic 0, and this period (e.g., the period from time t7 to time t 8) may sometimes be referred to as a write standby period. During the write standby period, the WL driver 108 may not have converted the WL signal 321 to the write level yet, e.g., the WL signal 321 remains at 0 volts. While transistor MP4 remains on, transistor MP1 may be turned on while cross-coupled transistor MP2 is turned off, which causes the voltage at node X to be substantially equal to the second level of power supply 301 (e.g., about 2 volts).

From time t8 to time t9, the control signal 319 again transitions from a logic 0 to a logic 1, which in turn may transition the WL signal 321 from approximately 0 volts to the write level. In some embodiments, the write level of the WL signal 321 may be substantially equal to the second level of the power supply 301. For example, transistor MN6 is turned on in response to control signal 319 transitioning to a logic 1. When transistor MN6 is turned on, a discharge path 355 may be formed from node X to power supply 303 (e.g., ground) via transistor MN2 and transistor MN6 (control signal 317 configured as a logic 0, while transistor MN4 is turned off), thereby pulling the voltage at node X from about 2 volts down to a signal level substantially equal to control signal 313 (e.g., about 1V). As such, transistor MP2 may still be turned on (because the second level of power supply 301 is about 2 volts) while cross-coupled transistor MP1 is turned off, resulting in the second level of power supply 301 (e.g., about 2 volts) being coupled to node Y. With the control signal 313 configured to be about 1 volt, the second level of the power supply 301 may be provided to the node Z when the transistor MP4 is turned on, which causes the WL signal 321 to increase to substantially equal the second level of the power supply 301 (e.g., about 2 volts) at time t 10. Referring again to the control signal 319 converted to logic 1, the transistor MN5 (gated by the logically inverted control signal 319) is turned off. As such, a discharge path from node Z to power supply 303 (e.g., ground) via transistor MN3 and transistor MN5 is not established, which may effectively couple the second level of power supply 301 to node Z.

As described above, each transistor of the WL driver 108 includes a thin oxide transistor, which may provide better performance, but may be subject to oxide breakdown when the voltage across the respective oxide becomes large. With the configuration shown in fig. 3, although a relatively large voltage (e.g., 2 volts for WL signal 321) is provided by the transistors (e.g., transistors MP2 and MP4) of the output stage of WL driver 108, these transistors are still immune to oxide breakdown. This is because transistor MP3 will be clamped to a voltage at node X of about 1 volt, which causes the respective voltages across the source/drain and gate of transistor MP2 and the source/drain and gate of transistor MP4 to be about 1 volt, rather than a relatively large voltage (e.g., 2 volts) configured at power supply 301.

From time t10 to time t11, the signal levels of control signal 311, control signal 313, control signal 317, control signal 319, and power supply 301 may remain unchanged. As such, during the period from time t10 to time t11, WL driver 108 may provide WL signal 321 at the write level. In some embodiments, the period may be predetermined according to the type of memory cell coupled to the WL driver 108.

From time t11 to time t12, when control signal 319 transitions from logic 1 to logic 0, WL driver 108 may stop providing WL signal 321, i.e., provide WL signal 321 at approximately 0 volts. Specifically, when the control signal 319 is at logic 0, the transistor MN6 is turned off, thereby disconnecting the discharge path 355, which gradually turns off the transistor MP2, stopping the WL signal 321 being provided at a non-zero level. In some embodiments, after WL signal 321 is provided at a non-zero level (e.g., at time t11), transistor MP0 may be turned on by transitioning control signal 311 from a logic 1 to a logic 0. As such, the second level of power supply 301 may be coupled to node X by turning on transistor MP0, which may pull the voltage at node X from about 1 volt to about 2 volts. Therefore, the transistor MP2 can be turned off more quickly, which can advantageously reduce the power consumption of the WL driver 108. The control signal 311 may remain at logic 0 for a relatively short time. For example, the period from time t12 to time t13 is about 1-2 nanoseconds, and after time t13, the control signal 311 is converted back to logic 1.

In some embodiments, the transistor MP3 and the transistor MP4 may constitute a cascade circuit. To bias the cascode circuit, the WL driver 108 may provide the control signal 313 based on the reference voltage using a control signal generation circuit including a source follower, as disclosed herein. The control signal generation circuit 500 may be coupled to the WL driver 108 or otherwise integrated with the WL driver 108. In some embodiments, the source follower may use the reference voltage and the signal level of the power supply 301 to determine the signal level of the control signal 313. Fig. 5 illustrates an example circuit diagram of a control signal generation circuit 500 according to various embodiments.

As shown, the control signal generation circuit 500 includes a transistor MP5, a transistor MN7, and a transistor MN 8. In some embodiments, transistor MP5 comprises a pMOSFET, and each of transistor MN7 and transistor MN8 comprises an nMOSFET. It is understood that each of the transistors MP5 and MN 7-MN 8 may include various other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.), while remaining within the scope of the present invention. The transistor MP5 and the transistor MN 7-the transistor MN8 are coupled to each other between the power supply 301 and the power supply 303, as will be discussed below.

For example, the source of the transistor MP5 is connected to the power supply 301, the drain of the transistor MP5 is connected to the drain of the transistor MN7, and the transistor MP5 is gated by the control signal 317. The source of transistor MN7 and the drain of transistor MN8 are connected at node a, transistor MN7 is gated by supply 301, the source of transistor MN8 is connected to supply 303, and transistor MN8 is gated by reference voltage Vin.

In some embodiments, transistor MN7 may function as a source follower, and transistor MN8 may provide a reference voltage to the source follower. A power supply 301 (received at the gate of transistor MN 7) may be used as an input to the source follower, providing a control signal 313 as an output at node a (at the source of transistor MN 7). As such, the signal level of control signal 313 may be determined as: the reference voltage Vin is subtracted from the signal level of the power supply 301 (control signal 313 equals power supply 301-reference voltage Vin). This is because when the transistor MN7 and the transistor MN8 are turned on by the power supply 301 and the reference voltage Vin, respectively (for example, in a saturation region), the voltage of the gate and the source of the transistor MN7 (power supply 301 — control signal 313) is equal to the voltage between the gate and the source of the transistor MN8 (reference voltage Vin). That is, the power supply 301-control signal 313 is equal to the reference voltage Vin, from which the relationship: the signal level of the control signal 313 is equal to the signal level of the power supply 301 minus the reference voltage Vin. According to various embodiments, the reference voltage Vin may be configured between about 1 volt to about 1.3 volts. Based on the above discussion, the maximum voltage present at the source/drain of each of cascode transistor MP3 and transistor MP4 (fig. 3) may be advantageously limited to the level of reference voltage Vin, e.g., about 1 volt to about 1.3 volts.

In particular, when reading a memory cell coupled to the WL driver 108, a control signal 317 of logic 1 is provided, as discussed above with reference to fig. 4. In response, the transistor MP5 of the control signal generation circuit 500 is turned off. Thus, the voltage at node A (the signal level of control signal 313) is pulled down to power supply 303 (e.g., ground), i.e., the first level (about 1 volt) of power supply 301 — the reference voltage Vin (about 1 volt). On the other hand, when writing to the memory cell, a logic 0 of control signal 317 is provided (and power supply 301 is configured to a second level, about 2 volts), which turns on transistor MP 5. When transistor MP5 is turned on, the second level of power supply 301 can be coupled to the drain of transistor MN7 such that the voltage at node a is equal to the second level of power supply 301 minus the reference voltage Vin, e.g., about 1 volt.

Fig. 6 illustrates an example circuit diagram of a bias generation circuit 600 that generates a reference voltage according to various embodiments. The bias generation circuit 600 may be coupled to the control signal generation circuit 500 or otherwise integrated with the control signal generation circuit 500. As shown, the bias generation circuit 600 includes an operational amplifier 602, a transistor 604 (e.g., pMOSFET), a first transistor 606, a second transistor 608, and a multiplexer 610. The components of the bias generation circuit 600 are coupled to each other between a first power supply 601 (e.g., an input/output supply voltage) and a second power supply 603 (e.g., ground). The operational amplifier 602 has two inputs 602A (e.g., inverting inputs) and 602B (e.g., non-inverting inputs) and one output 602C. Input 602A is configured to: receiving a bandgap voltage 605, input 602B is connected to node X, and output 602C is connected to the gate of transistor 604. The source of transistor 604 is connected to a power supply 601, the drain of transistor 604 is coupled to a power supply 603 via a resistor 606 and a resistor 608, and node X is connected between the two. Further, by varying the ratio of the resistance value of resistor 606 to the resistance value of resistor 608, the voltage at node X may be changed from a first value to a second value (e.g., about 1 volt to about 1.3 volts). The multiplexer 610 is configured to: one of the ranges from the first value to the second value is selected as the reference voltage Vin.

Fig. 7 shows an example circuit diagram of another bias generation circuit 700 for generating a reference voltage Vin according to various embodiments. The bias generation circuit 700 may be coupled to the control signal generation circuit 500 or otherwise integrated with the control signal generation circuit 500. As shown, the bias generation circuit 700 includes a current source 702 and a transistor 704 (e.g., an nMOSFET). The gate and drain of transistor 704 are connected to each other, which is sometimes referred to as a "diode-connected" transistor, which causes transistor 704 to operate in saturation mode. A source of transistor 704 is connected to power source 701 (e.g., ground). The current source 702 is configured to: a constant current approximately equal to the saturation current flowing through transistor 704 is provided to diode-connected transistor 704. As such, the bias generation circuit 700 may provide a stable reference voltage Vin based on the current.

Fig. 8 shows a flowchart of an example method 800 for operating a WL driver to provide at least two levels of a WL signal, in accordance with various embodiments. For example, as disclosed herein, the WL driver 108 may perform the operations of the method 800, providing at least two levels of the WL signal (e.g., 119 discussed in fig. 1-2, 321 discussed in fig. 3-4). As such, an embodiment of the following method 800 is described in conjunction with fig. 1-3. The illustrated embodiment of the method 800 is merely an example. Thus, it is understood that any of the various changes to the operation of the method 800 may be omitted, reordered, and/or added while remaining within the scope of the present invention.

According to various embodiments, the method 800 begins with operation 802: the first transistor and the second transistor are configured to be cross-coupled to each other. As such, a source (e.g., MP1 of fig. 3) of the first transistor and a source (e.g., MP2 of fig. 3) of the second transistor are connected to a power supply (e.g., 301 of fig. 3), a gate of the first transistor is connected to a drain of the second transistor at a first node (e.g., node Y of fig. 3), and a gate of the second transistor is connected to the drain of the first transistor at a second node (e.g., node X of fig. 3). Continuing with the above example, each of the first transistor MP1 and the second transistor MP2 may be coupled to a portion of the cascode circuit. For example, in fig. 3, the first transistor MP1 is coupled at its drain to the transistor MP 3; also, the second transistor MP2 is coupled at its drain to the transistor MP4, wherein the transistor MP3 and the transistor MP4 may serve as a cascade circuit of the output stage of the WL driver 108.

According to various embodiments, the method 800 proceeds to operation 804: the first level of the power supply is directly coupled to the first node and then coupled to the output node across the turned-on third transistor. Continuing with the above example, power supply 301 may be configured to a first level (e.g., 1 volt). In response, WL driver 108 may directly couple the first level of power supply 301 to node Y and then to the output node (e.g., node Z of fig. 3) across the conducting transistor (e.g., MP 4). In some embodiments, each of the transistor MP3 and the transistor MP4 is turned on by a control signal (e.g., 313 of fig. 3), so that the transistor MP3 and the transistor MP4 may remain turned on according to the varying levels of the power supply 301. For example, when the power supply 301 is configured to a first level (e.g., 1 volt), the control signal 313 may be configured to about 0 volts, enabling the node X to discharge to ground, thereby turning on the transistor MP2, and then coupling the first level of the power supply 301 to the output node Z through the transistor MP2 (and the already turned on transistor MP 4). Accordingly, the first level of the power supply 301 may be provided as the WL signal 321 to the output node Z.

According to various embodiments, the method 800 proceeds to operation 806 by coupling the second level of the power supply directly to the first node and then to the output node across the turned-on third transistor. Continuing with the above example, the power supply 301 may be configured to a second level (e.g., 2 volts). In response, WL driver 108 may directly couple the second level of power supply 301 to node Y and then across the turned-on transistor (e.g., MP4) to the output node (e.g., node Z of fig. 3). In some embodiments, each of the transistor MP3 and the transistor MP4 is turned on by a control signal (e.g., 313 of fig. 3), so that the transistor MP3 and the transistor MP4 may remain turned on according to the varying levels of the power supply 301. For example, when the power supply 301 is configured to a second level (e.g., 2 volts), the control signal 313 may be configured to about 1 volt, discharging the node X to about 1 volt, thereby still turning on transistor MP2, and then coupling the second level of the power supply 301 to the output node Z through transistor MP2 (and transistor MP4 that has been turned on). Accordingly, the second level of the power supply 301 may be provided as the WL signal 321 to the output node Z. It is beneficial to vary the signal level of the control signal 313 according to the signal level of the power supply 301 because when the WL driver 108 is configured to provide a relatively large output voltage, the transistors of the WL driver 108 in the output phase (e.g., transistor MP3 and transistor MP4) do not experience a relatively large voltage difference between the respective oxides.

In one aspect of the invention, a circuit includes: a first transistor and a second transistor cross-coupled to each other such that a source/drain of the first transistor and a source/drain of the second transistor are both connected to a power supply, a gate of the first transistor is connected to a source/drain of the second transistor at a first node, and a gate of the second transistor is connected to the source/drain of the first transistor at a second node. The circuit is configured to: a first level of a word line voltage is provided to the memory cell when the memory cell is read and a second level of the word line voltage is provided to the memory cell when the memory cell is written. The circuit is configured to: the power supply configured at the first level is directly coupled to the memory cell through the second transistor and the third transistor to thereby supply the first level of the word line voltage to the memory cell, and the power supply configured at the second level is directly coupled to the memory cell through the second transistor and the third transistor to thereby supply the second level of the word line voltage to the memory cell.

In the above circuit, the second level of the power supply is substantially higher than the first level of the power supply, and the second level of the word line voltage is substantially higher than the first level of the word line voltage.

In the above circuit, when the first level of the word line voltage is supplied to the memory cell, the third transistor is turned on by the first control signal configured as the first level, and when the second level of the word line voltage is supplied to the memory cell, the third transistor is turned on by the first control signal configured as the second level.

In the above circuit, when the first level of the word line voltage is supplied to the memory cell, the voltage at the second node is lowered to the first level of the first control signal through the first discharge path, and the voltage at the first node is substantially equal to the first level of the power supply.

In the above circuit, when the second level of the word line voltage is supplied to the memory cell, the voltage at the second node is lowered to the second level of the first control signal through the second discharge path, and the voltage at the first node is substantially equal to the second level of the power supply.

In the above circuit, the second discharge path includes a fourth transistor that is turned on by the first control signal configured at the second level, and wherein the voltage at the second node is clamped at the second level of the first control signal by the fourth transistor.

In the above circuit, further comprising: a fifth transistor; a sixth transistor; and a seventh transistor; wherein a first source/drain of the fifth transistor is connected to a power supply and a second source/drain is connected to a first source/drain of the sixth transistor, and the fifth transistor is selectively turned on based on reading or writing the memory cell, wherein a second source/drain of the sixth transistor is connected to a first source/drain power supply of the seventh transistor at a third node and the sixth transistor is gated by the power supply, wherein the seventh transistor has the second source/drain grounded and the sixth transistor is gated by a reference voltage, and wherein a voltage at the third node determines the first level or the second level of the first control signal.

In the above circuit, the first level of the first control signal is equal to the first level of the power supply minus the reference voltage, and the second level of the first control signal is equal to the second level of the power supply minus the reference voltage.

In the above circuit, when the power supply is at the first level or the second level, a voltage difference of the first source/drain and the gate of the second transistor and a voltage difference of the first source/drain and the gate of the third transistor are both substantially equal to the reference voltage.

In the above circuit, further comprising: and an eighth transistor having a first source/drain connected to the power supply, a gate connected to the second control signal, and a second source/drain connected to the second node, wherein, after the first level of the word line voltage or the second level of the word line voltage is supplied to the memory cell, the eighth transistor is turned on by the second control signal to couple the power supply to the second node through the turned-on eighth transistor, thereby turning off the second transistor.

In the above circuit, each of the first transistor, the second transistor, and the third transistor includes a p-type metal oxide semiconductor field effect transistor (pMOSFET).

In another aspect of the invention, a circuit includes: a first transistor and a second transistor cross-coupled to each other such that a source of the first transistor and a source of the second transistor are both connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, and a gate of the second transistor is connected to the drain of the first transistor at a second node. The circuit includes a third transistor having a source connected to the first node. The circuit includes a fourth transistor having a source connected to the second node. The circuit is configured to: the first level of the power supply is coupled to the drain of the third transistor through the second transistor and the third transistor to generate the output voltage of the first level at the drain of the third transistor, and the second level of the power supply is coupled to the drain of the third transistor through the second transistor and the third transistor to generate the output voltage of the second level at the drain of the third transistor. The second level of the power supply is substantially higher than the first level of the power supply. The second level of the power supply is substantially higher than the first level of the output voltage.

In the above circuit, when the first level output voltage is generated, each of the third transistor and the fourth transistor is turned on by the first control signal configured to the first level, and when the second level output voltage is generated, each of the third transistor and the fourth transistor is turned on by the first control signal configured to the second level.

In the above circuit, a voltage difference between the first control signal and the power supply is fixed.

In the above circuit, when the first level output voltage is generated, the voltage at the second node is dropped to the first level of the first control signal through the first discharge path, and the voltage at the first node is substantially equal to the first level of the voltage.

In the above circuit, when the second level output voltage is generated, the voltage at the second node is dropped to the second level of the first control signal through the second discharge path including the fourth transistor, and the voltage at the first node is substantially equal to the second level of the voltage.

In the above circuit, the voltage at the second node is clamped at the second level of the first control signal by the fourth transistor.

In the above circuit, the output voltage is provided as a word line voltage to a memory cell coupled to the circuit.

In yet another aspect of the invention, a method comprises: the first transistor and the second transistor are configured to be cross-coupled to each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, and a gate of the second transistor is connected to the drain of the first transistor at a second node. The method comprises the following steps: in response to the power supply being configured at the first level, the first level of the power supply is coupled directly to the first node and then coupled across the turned-on third transistor to the output node. The method comprises the following steps: in response to a power supply configured to a second level substantially higher than the first level, the second level of the power supply is coupled directly to the first node and then coupled to the output node across the turned-on third transistor.

In the above method, when the power supply is configured to the first level, the third transistor is turned on by the control signal configured to the first level, and when the power supply is configured to the second level, the third transistor is turned on by the control signal configured to the second level.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.