阅读说明：本技术 静电放电器件和包括该静电放电器件的静电放电保护电路 (Electrostatic discharge device and electrostatic discharge protection circuit including the same ) 是由 金锡震 李美珍 全燦熙 于 2021-03-05 设计创作，主要内容包括：提供一种具有小尺寸、低导通电压和低导通电阻的静电放电(ESD)器件以及包括该ESD器件的ESD保护电路。ESD器件包括：阱,形成在衬底中,以具有第一导电类型；有源区域,被限定在衬底的上部；多个鳍,在第一方向上延伸,以具有从衬底突出的结构；第一导电杂质区域,使用第一导电杂质形成；第二导电杂质区域,使用第二导电杂质形成；以及鳍切割隔离区域,在第一方向上设置在第一导电杂质区域与第二导电杂质区域之间,以切割每一个鳍,其中,鳍切割隔离区域的底表面高于有源区域的底表面。(An electrostatic discharge (ESD) device having a small size, a low on-voltage, and a low on-resistance, and an ESD protection circuit including the ESD device are provided. The ESD device includes: a well formed in the substrate to have a first conductive type; an active region defined in an upper portion of the substrate; a plurality of fins extending in a first direction to have a structure protruding from a substrate; a first conductive impurity region formed using a first conductive impurity; a second conductive impurity region formed using a second conductive impurity; and a fin cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction to cut each fin, wherein a bottom surface of the fin cut isolation region is higher than a bottom surface of the active region.)

1. An electrostatic discharge (ESD) device comprising:

a well formed in a substrate, the well having a first conductive type and having an active region formed at an upper portion of the substrate;

a plurality of fins extending across the well in a first direction in a protruding manner from the substrate, the plurality of fins being spaced apart from each other in a second direction perpendicular to the first direction;

a first conductive impurity region formed by doping a portion of each of the plurality of fins with a first conductive impurity;

a second conductive impurity region formed by doping a portion of each of the plurality of fins with a second conductive impurity having a second conductivity type different from the first conductivity type, the second conductive impurity region being disposed apart from the first conductive impurity region in the first direction; and

a fin cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction in each of the plurality of fins to cut each of the plurality of fins into at least a first fin portion and a second fin portion,

wherein a bottom surface of the fin cut isolation region is higher than a bottom surface of the active region.

2. The ESD device of claim 1, wherein a bottom surface of the fin cut isolation region is higher than a top surface of the substrate.

3. The ESD device of claim 1, wherein a first portion of the active area under the first fin portion and a second portion of the active area under the second fin portion are connected to each other by a third portion of the active area under the fin cut isolation region.

4. The ESD device of claim 1, further comprising a plurality of gate lines disposed apart from each other in the first direction to cover a portion of each of the plurality of fins and extending in the second direction,

wherein each of the first conductive impurity region and the second conductive impurity region is disposed between two gate lines adjacent to each other in the first direction.

5. The ESD device of claim 4, wherein a lower portion of the fin cut isolation region is filled with an isolation insulating layer,

a first portion of a first gate line of the plurality of gate lines and a first portion of a second gate line of the plurality of gate lines are disposed in the fin cut isolation region,

the first portion of the first gate line and the first portion of the second gate line cover a side surface of the corresponding fin and a top surface of the isolation insulating layer, an

In the fin cut isolation region, a first portion of the first gate line and a first portion of the second gate line are separated from each other without a third gate line between the first gate line and the second gate line.

6. The ESD device of claim 5, wherein, in the fin-cut isolation region, a distance between the first gate line and the second gate line in the first direction is 100nm or less.

7. The ESD device of claim 1, further comprising a contact contacting each of the first and second conductive impurity regions,

wherein the contact is configured to apply one of a power supply voltage, a signal voltage, or a ground voltage.

8. The ESD device of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type, and

the ESD device has a P-type diode structure, wherein the second conductive impurity region is disposed at the center of each of the plurality of fins, and the first conductive impurity region is disposed at both sides of the second conductive impurity region in the first direction, or

The ESD device has an N-type diode structure, wherein the first conductive impurity region is disposed at a center of each of the plurality of fins, and the second conductive impurity regions are disposed at both sides of the first conductive impurity region in the first direction.

9. The ESD device of claim 8, wherein the ESD device has a stripe structure in which each of the first and second conductive impurity regions extends in the second direction, or

The ESD device has a ring structure in which the second conductive impurity region surrounds the first conductive impurity region in a ring shape, or the first conductive impurity region surrounds the second conductive impurity region in a ring shape.

10. The ESD device of claim 1, comprising a fully-wrapped-gate GAA structure or a multi-bridge channel, MBC, structure.

11. An electrostatic discharge (ESD) device comprising:

a well formed in a substrate, the well having a first conductivity type;

a plurality of fins extending across the well in a first direction in a protruding manner from the substrate, the plurality of fins being spaced apart from each other in a second direction perpendicular to the first direction;

a first conductive impurity region formed by doping a portion of each of the plurality of fins with a first conductive impurity;

a second conductive impurity region formed by doping a portion of each of the plurality of fins with a second conductive impurity having a second conductivity type different from the first conductivity type, the second conductive impurity region being disposed apart from the first conductive impurity in the first direction;

a fin cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction in each of the plurality of fins to cut each of the plurality of fins into at least a first fin portion and a second fin portion;

a plurality of gate lines disposed to be separated from each other in the first direction to cover a portion of each of the plurality of fins and to extend in the second direction; and

a contact contacting each of the first conductive impurity region and the second conductive impurity region,

wherein an active region is formed on an upper portion of the well, an

Wherein a first portion of the active region under the first fin portion and a second portion of the active region under the second fin portion are connected to each other through a third portion of the active region under the fin cut isolation region.

12. The ESD device of claim 11, wherein one of the first conductive impurity region, the second conductive impurity region, and the fin cut isolation region is disposed between two of the plurality of gate lines that are adjacent to each other in the first direction.

13. The ESD device of claim 11, wherein the first conductivity type is N-type and the second conductivity type is P-type,

the ESD device has a P-type diode structure or an N-type diode structure, and

the contact is configured to apply one of a power supply voltage, a signal voltage, or a ground voltage.

14. The ESD device of claim 13, wherein the ESD device has a stripe structure in which each of the first and second conductive impurity regions extends in the second direction, or

The ESD device has a ring structure in which the second conductive impurity region surrounds the first conductive impurity region in a ring shape, or the first conductive impurity region surrounds the second conductive impurity region in a ring shape.

15. The ESD device of claim 11, wherein a bottom surface of the fin cut isolation region corresponds to a top surface of the active region, and

a bottom surface of the fin cut isolation region is higher than a bottom surface of the active region.

16. An electrostatic discharge (ESD) protection circuit, comprising:

at least two ESD devices disposed on a substrate; and

a pad disposed on the substrate and connected to the at least two ESD devices and configured to apply a signal voltage to a protection target device protected by the at least two ESD devices, wherein each of the at least two ESD devices includes:

a well formed in the substrate, the well having a first conductivity type and having an active region formed at an upper portion of the substrate;

a plurality of fins extending across the well in a first direction in a protruding manner from the substrate, the plurality of fins being spaced apart from each other in a second direction perpendicular to the first direction;

a first conductive impurity region formed by doping a portion of each of the plurality of fins with a first conductive impurity;

a second conductive impurity region formed by doping a portion of each of the plurality of fins with a second conductive impurity having a second conductivity type different from the first conductivity type, the second conductive impurity region being disposed apart from the first conductive impurity in the first direction; and

a fin cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction in each of the plurality of fins to cut each of the plurality of fins into at least a first fin portion and a second fin portion,

wherein a bottom surface of the fin cut isolation region is higher than a bottom surface of the active region.

17. The ESD protection circuit of claim 16, wherein each of the at least two ESD devices further comprises a plurality of gate lines disposed apart from each other in the first direction to cover a portion of each of the plurality of fins and extending in the second direction,

each of the first conductive impurity region, the second conductive impurity region, and the fin cut isolation region is disposed between two gate lines adjacent to each other in the first direction among the plurality of gate lines.

18. The ESD protection circuit of claim 16, wherein the at least two ESD devices include a first ESD device having a P-type diode structure and a second ESD device having an N-type diode structure,

the first ESD device is provided between the pad and a power supply terminal to which a power supply voltage is applied, and

the second ESD device is disposed between the pad and a ground terminal to which a ground voltage is applied.

19. The ESD protection circuit of claim 18, wherein the first conductivity type is N-type and the second conductivity type is P-type,

each of the at least two ESD devices further includes a contact contacting each of the first conductive impurity region and the second conductive impurity region,

in the first ESD device, the second conductive impurity region is disposed at a center of each of the plurality of fins, and the first conductive impurity regions are disposed at both sides of the second conductive impurity region in the first direction,

in the second ESD device, the first conductive impurity region is disposed at a center of each of the plurality of fins, and the second conductive impurity regions are disposed at both sides of the first conductive impurity region in the first direction,

applying the power supply voltage to the first conductive impurity region of the first ESD device through the power supply terminal and the contact, and applying the signal voltage to the second conductive impurity region of the first ESD device through the pad and the contact, an

The signal voltage is applied to the first conductive impurity region of the second ESD device through the pad and the contact, and the ground voltage is applied to the second conductive impurity region of the second ESD device through the ground terminal and the contact.

20. The ESD protection circuit of claim 16, wherein each of the at least two ESD devices has a stripe structure, wherein each of the first and second conductive impurity regions extends in the second direction, or

Each of the at least two ESD devices has a ring structure in which the second conductive impurity region surrounds the first conductive impurity region in a ring shape, or the first conductive impurity region surrounds the second conductive impurity region in a ring shape, and

a first portion of the active region under the first fin portion and a second portion of the active region under the second fin portion are connected to each other by a third portion of the active region under the fin cut isolation region.

Technical Field

The present inventive concept relates to an electrostatic discharge (ESD) device, and more particularly, to an ESD device including a fin structure and an ESD protection circuit including the ESD device.

Background

The semiconductor device may be exposed to static electricity having a transient voltage of 3,000V for various reasons. When a semiconductor device is exposed to static electricity, a gate insulating layer of a transistor of the semiconductor device may be broken down, or a bonding spike may occur in metal-silicon bonding of the transistor, resulting in breakdown or damage of the semiconductor device. Therefore, the static electricity may adversely affect the reliability of the semiconductor device. An ESD device or an ESD protection circuit is applied to an electronic device to prevent a semiconductor device from being damaged by static electricity. However, with the recent high integration of electronic devices, the chip size is gradually reduced, and thus research is being conducted to reduce the size of an ESD device or an ESD protection circuit while maintaining resistance against static electricity.

Disclosure of Invention

The present inventive concept provides an electrostatic discharge (ESD) device having a small size, a low on-voltage, and a low on-resistance, and an ESD protection circuit including the ESD device.

According to an aspect of the present disclosure, there is provided an electrostatic discharge (ESD) device including: a well formed in the substrate, the well having a first conductive type and having an active region formed at an upper portion of the substrate; a plurality of fins extending across the well in a first direction in a protruding manner from the substrate, the plurality of fins being spaced apart from each other in a second direction perpendicular to the first direction; a first conductive impurity region formed by doping a portion of each of the plurality of fins with a first conductive impurity; a second conductive impurity region formed by doping a portion of each of the plurality of fins with a second conductive impurity having a second conductivity type different from the first conductivity type, the second conductive impurity region being disposed to be separated from the first conductive impurity region in the first direction; and a fin cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction in each of the plurality of fins to cut each of the plurality of fins into at least a first fin portion and a second fin portion, wherein a bottom surface of the fin cut isolation region is higher than a bottom surface of the active region.

According to an aspect of the present disclosure, there is provided an electrostatic discharge (ESD) device including: a well formed in the substrate, the well having a first conductivity type; a plurality of fins extending across the well in a first direction in a protruding manner from the substrate, the plurality of fins being spaced apart from each other in a second direction perpendicular to the first direction; a first conductive impurity region formed by doping a portion of each of the plurality of fins with a first conductive impurity; a second conductive impurity region formed by doping a portion of each of the plurality of fins with a second conductive impurity having a second conductivity type different from the first conductivity type, the second conductive impurity region being disposed to be separated from the first conductive impurity region in the first direction; a fin cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction in each of the plurality of fins to cut each of the plurality of fins into at least a first fin portion and a second fin portion; a plurality of gate lines disposed to be separated from each other in the first direction to cover a portion of each of the plurality of fins and extending in a second direction; and a contact contacting each of the first conductive impurity region and the second conductive impurity region, wherein the active region is formed at an upper portion of the well, and wherein a first portion of the active region under the first fin portion and a second portion of the active region under the second fin portion are connected to each other through a third portion of the active region under the fin cut isolation region.

According to another aspect of the present disclosure, there is provided an electrostatic discharge (ESD) protection circuit including: at least two ESD devices disposed on a substrate; and a pad disposed on the substrate and connected to the at least two ESD devices and configured to apply a signal voltage to a protection target device protected by the at least two ESD devices, wherein each of the at least two ESD devices includes: a well formed in the substrate, the well having a first conductive type and having an active region formed at an upper portion of the substrate; a plurality of fins extending across the well in a first direction in a protruding manner from the substrate, the plurality of fins being spaced apart from each other in a second direction perpendicular to the first direction; a first conductive impurity region formed by doping a portion of each of the plurality of fins with a first conductive impurity; a second conductive impurity region formed by doping a portion of each of the plurality of fins with a second conductive impurity having a second conductivity type different from the first conductivity type, the second conductive impurity region being disposed to be separated from the first conductive impurity region in the first direction; and a fin cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction in each of the plurality of fins to cut each of the plurality of fins into at least a first fin portion and a second fin portion, wherein a bottom surface of the fin cut isolation region is higher than a bottom surface of the active region.

According to an aspect of the present disclosure, there is provided a method of manufacturing an electrostatic discharge (ESD) device, the method including: forming a well having a first conductivity type in a substrate; forming an active region at an upper portion of a substrate; providing a plurality of fins extending across the well in a first direction in a protruding manner from the substrate, the plurality of fins being spaced apart from each other in a second direction perpendicular to the first direction; doping a portion of each of the plurality of fins with a first conductive impurity to form a first conductive impurity region; doping a portion of each of the plurality of fins with a second conductive impurity having a second conductivity type different from the first conductivity type to form a second conductive impurity region disposed apart from the first conductive impurity region in the first direction; and cutting each of the plurality of fins into at least a first fin portion and a second fin portion, and forming a fin cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction in each of the plurality of fins, wherein a bottom surface of the fin cut isolation region is higher than a bottom surface of the active region.

Drawings

Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is an equivalent circuit diagram of an electrostatic discharge (ESD) protection circuit according to an example embodiment;

fig. 2A to 2D are plan views showing the shape of impurity regions of the ESD device in the ESD protection circuit of fig. 1;

fig. 3A is a plan view of an ESD device having a P-type diode structure in the ESD protection circuit of fig. 1, fig. 3B is a sectional view taken along I-I ' in fig. 3A, fig. 3C is a sectional view taken along II-II ' in fig. 3A, and fig. 3D is a sectional view taken along III-III ' in fig. 3A;

fig. 4 is a graph illustrating on-voltage characteristics and on-resistance characteristics of an ESD device having the P-type diode structure of fig. 3A to 3D and an ESD device having a related art P-type diode structure;

fig. 5 is a cross-sectional view of an ESD device with an N-type diode structure in the ESD protection circuit of fig. 1;

fig. 6 is a graph illustrating on-voltage characteristics and on-resistance characteristics of an ESD device having the N-type diode structure of fig. 5 and an ESD device having a related art N-type diode structure;

fig. 7 to 9 are cross-sectional views of ESD devices with P-type diode structures according to example embodiments;

fig. 10A to 10C are perspective and cross-sectional views of an ESD device with a P-type diode structure according to an example embodiment;

fig. 11 is a perspective view of an ESD device with a P-type diode structure according to an example embodiment; and

fig. 12A and 12B are cross-sectional views illustrating a process of manufacturing an ESD device having the P-type diode structure of fig. 3A to 3D according to example embodiments;

fig. 13A to 13C are cross-sectional views illustrating a process of manufacturing an ESD device having the P-type diode structure of fig. 3A to 3D according to example embodiments;

fig. 14A to 14C are cross-sectional views illustrating a process of manufacturing an ESD device having the P-type diode structure of fig. 3A to 3D according to example embodiments;

fig. 15A and 15B are cross-sectional views illustrating a process of manufacturing an ESD device having the P-type diode structure of fig. 3A to 3D according to example embodiments; and

fig. 16 is a cross-sectional view illustrating a process of manufacturing an ESD device having the P-type diode structure of fig. 3A to 3D according to an example embodiment.

Detailed Description

Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. Like reference numerals refer to like elements, and a repetitive description thereof will be omitted.

Fig. 1 is an equivalent circuit diagram of an electrostatic discharge (ESD) protection circuit 1000 according to an embodiment.

Referring to fig. 1, an ESD protection circuit 1000 according to an embodiment may include an ESD device 100 and a pad 200. The ESD device 100 and the pad 200 may be formed on a substrate (see 101 of fig. 3B) along with the protection target device 2000. A signal voltage may be applied to the protection target device 2000 through the pad 200.

According to an example embodiment, ESD device 100 may include at least two ESD devices, e.g., a first ESD device 100-1 and a second ESD device 100-2. According to example embodiments, the first ESD device 100-1 of the ESD device 100 may have a P-type diode structure, and the second ESD device 100-2 of the ESD device 100 may have an N-type diode structure. However, the present disclosure is not limited thereto, and the first ESD device 100-1 of the ESD device 100 may have an N-type diode structure, and the second ESD device 100-2 of the ESD device 100 may have a P-type diode structure. According to an example embodiment, the ESD device 100 may include a plurality of first ESD devices 100-1 and a plurality of second ESD devices 100-2. The plurality of first ESD devices 100-1 may be connected in parallel to each other, and the plurality of second ESD devices 100-2 may be connected in parallel to each other.

According to example embodiments, the ESD device 100 may include a fin structure, and may include a fin cut isolation region for junction separation between an anode and a cathode (see FC of fig. 3A to 3D). Accordingly, since the ESD device 100 includes the fin structure and the fin cut isolation region FC, the ESD device 100 may have a small size, a low on-voltage, and a low on-resistance. The detailed structure and various example embodiments of the ESD device 100 will be described in more detail with reference to fig. 3A to 3D, fig. 5 to 9, fig. 10A to 10C, and fig. 11. Further, detailed description of the circuit connection relationship and the function of the ESD protection circuit 1000 will be described with reference to fig. 3A to 3D, fig. 5 to 9, fig. 10A to 10C, and fig. 11.

According to an example embodiment, the pad 200 may be connected to an anode terminal of the first ESD device 100-1 of the ESD protection circuit 1000, and the power supply voltage Vdd may be connected to a cathode terminal of the first ESD device 100-1. In addition, the ground voltage Vss may be connected to an anode terminal of the second ESD device 100-2 of the ESD protection circuit 1000, and the pad 200 may be connected to a cathode terminal of the second ESD device 100-2. As a result, the pad 200 may be commonly connected to the anode terminal of the first ESD device 100-1 and the cathode terminal of the second ESD device 100-2. In addition, the pad 200 may be connected to the protection target device 2000 so that a signal voltage is applied to the protection target device 2000.

The ESD protection circuit 1000 having such a structure in fig. 1 can protect the protection target device 2000 by the following operation when sudden static electricity occurs. That is, when positive (+) static electricity is applied, the positive (+) static electricity may flow in a positive direction of the first ESD device 100-1 and may be discharged to a terminal to which the power supply voltage Vdd is applied, and when negative (-) static electricity is applied, the negative (-) static electricity may flow in a positive direction of the second ESD device 100-2 and may be discharged to a terminal to which the ground voltage Vss is applied. Here, the concept of protecting the protection target device 2000 by the ESD protection circuit 1000 may be understood as a concept that: the ESD current path is formed only between the pad 200 and the power supply voltage Vdd terminal or between the pad 200 and the ground voltage Vss terminal, and the ESD current path is not formed toward the protection target device 2000, that is, the current of static electricity does not flow to the protection target device 2000.

As a result, the ESD protection circuit 1000 may include the ESD device 100, and thus, only when transient static electricity occurs, the static electricity may be discharged through the ESD device 100, thereby protecting the protection target device 2000 from the static electricity. As shown in fig. 1, in order to more safely protect the protection target device 2000 from static electricity, a resistance device 300 having a resistance of an appropriate level may be added to the front end with respect to the protection target device 2000. The resistive device 300 may be provided to protect elements of the target device 2000. However, according to an embodiment, the resistance device 300 may be provided as an element of the ESD protection circuit 1000 in consideration of the function of the resistance device 300.

The protection target device 2000 may include various electronic devices that need to be protected from static electricity. For example, the protection target device 2000 may include various memory devices such as a Dynamic Random Access Memory (DRAM) and a flash memory, a logic device configuring a controller, and various semiconductor devices such as an interface device for data communication. According to example embodiments, the ESD protection circuit 1000 may include a fin field effect transistor (FinFET) structure, and based thereon, the protection target device 2000 may further include a semiconductor device including a FinFET. That is, the ESD protection circuit 1000 and the protection target device 2000 may be simultaneously formed on the substrate through a FinFET process.

According to example embodiments, based on the ESD characteristics of the protection target device 2000, models in which the protection target device 2000 is damaged may be classified into a Human Body Model (HBM) and a Charged Device Model (CDM). Here, the HBM may represent a case where a charged person causes static electricity in the protection target device 2000 to damage the protection target device 2000, and the CDM may represent a case where the protection target device 2000 is charged and the protection target device 2000 causes static electricity in a conductor (such as a human body or metal) to damage the protection target device 2000. The ESD protection circuit 1000 according to example embodiments may be used for all HBM and CDM.

According to example embodiments, the ESD device 100 may include a P-type impurity region and an N-type impurity region each having a fin structure, and may include a fin cut isolation region for junction separation between the P-type impurity region and the N-type impurity region, and thus, the ESD device 100 may have a small size, a low on-voltage, and a low on-resistance. Therefore, according to example embodiments, the ESD protection circuit 1000 including the ESD device 100 having such a structure may enable an ESD protection circuit having a good Power Performance Area (PPA). Therefore, a very reliable electronic device including the ESD protection circuit can be provided.

Fig. 2A to 2D are plan views showing the shape of impurity regions of the ESD device in the ESD protection circuit 1000 of fig. 1.

Referring to fig. 2A, an ESD device 100 according to example embodiments may include a first ESD device 100-1 having a P-type diode structure, and the first ESD device 100-1 may include a plurality of impurity regions 110 and a well 103. Referring to fig. 2C, the ESD device 100 according to another example embodiment may include a second ESD device 100-2 having an N-type diode structure, and the second ESD device 100-2 may include a plurality of impurity regions 120 and a well 103. Here, the plurality of impurity regions 110 and 120 may be represented by, for example, 10¹⁹/cm³Or a higher P + region or N + region highly doped with a P-type impurity or an N-type impurity. As shown, the first ESD device 100-1 or the second ESD device 100-2 may have a ring structure in which the outer impurity region 120 or 110 surrounds the inner impurity region 110 or 120 in a tetragonal ring shape. For example, the first ESD device 100-1 may have a structure of: p-type impurity region 110 is disposed at the inner center of the structure and outer N-type impurity region 120 surrounds P-type impurity region 110 in a quadrangular ring shape. Further, the second ESD device 100-2 may have a structure of: an N-type impurity region 120 is disposed at the inner center of the structure and an outer P-type impurity region 110 surrounds the N-type impurity region 120 in a tetragonal ring shape.

The well 103 may be an N-type well. The well 103 may be, for example, at 10¹⁶/cm³Or lower concentrations of N-regions doped with N-type impurities. The P-type impurity region 110 and the well 103 may have impurities of different conductivity types, and thus, a PN junction may be formed. The shape of the vertical cross section of each of the impurity regions 110 and 120 and the well 103 can be seen in fig. 3B to 3D. For example, the impurity regions 110 and 120 may be disposed at an upper portion of the well 103. The impurity regions 110 and 120 and the upper portion of the well 103 may be defined as an active region (see ACT of fig. 3A to 3D). The upper portion of the well 103 provided with the source region ACT may be, for example, an N0 region, the N0 region being 10¹⁶/cm³Or higher, is doped with an N-type impurity and the doping concentration of the N0 region is higher than that of the N-region.

In fig. 2A and 2C, impurity regions 110 and 120 of ESD device 100 may have an inner square shape and an outer square ring shape, but the shape of impurity regions 110 and 120 of ESD device 100 is not limited thereto. For example, the impurity regions 110 and 120 of the ESD device 100 may have an inner rectangular shape and an outer rectangular ring shape, or may have an inner elliptical shape and an outer elliptical ring shape.

Referring to fig. 2B, the ESD device 100 according to example embodiments may include a first ESD device 100-1 having a P-type diode structure, and the first ESD device 100-1 may include a plurality of impurity regions 110 and a well 103. Referring to fig. 2D, the ESD device 100 according to another example embodiment may include a second ESD device 100-2 having an N-type diode structure, and the second ESD device 100-2 may include a plurality of impurity regions 120 and a well 103. As shown, each of the first and second ESD devices 100-1 and 100-2 may have a stripe structure having a stripe shape in which impurity regions 110 and 120 extend in the second direction (y direction) and are separated from each other in the first direction (x direction). For example, in the first ESD device 100-1, the P-type impurity regions 110 may be disposed in a strip shape extending in the second direction (y-direction) at a central portion of the first ESD device 100-1, and the N-type impurity regions 120 may be disposed in a strip shape extending in the second direction (y-direction) at both outsides of the P-type impurity regions 110. Further, in the second ESD device 100-2, the N-type impurity region 120 may be disposed in a strip shape extending in the second direction (y-direction) at a central portion of the second ESD device 100-2, and the P-type impurity regions 110 may be disposed in a strip shape extending in the second direction (y-direction) at both outsides of the N-type impurity region 120.

In the ESD device 100 having the stripe shape, based on the planar structure of the well 103 including the impurity regions 110 and 120, a width Wx of the ESD device 100 in the first direction (x direction) and a width Wy of the ESD device 100 in the second direction (y direction) may be defined, and an area of the ESD device 100 may be defined by multiplying the width Wx of the ESD device 100 in the first direction (x direction) by the width Wy of the ESD device 100 in the second direction (y direction) (i.e., Wx Wy). In addition, a horizontal area of the impurity region 110 or 120 disposed at a central portion of the ESD device 100 may be defined as an effective area of the ESD device 100. Further, in the ring-shaped ESD device 100 of fig. 2A and 2B, the area of the ESD device 100 may be defined by the total area of the well 103, and the effective area of the ESD device 100 may be defined by the horizontal area of the impurity region 110 or 120 disposed at the central portion of the ESD device 100. The widths Wx and Wy, the area, and the effective area of the ESD device 100 will be described in more detail with reference to the graph of fig. 4.

Fig. 3A to 3D are a plan view and a sectional view of an ESD device having a P-type diode structure in the ESD protection circuit of fig. 1. Fig. 3B is a sectional view taken along line I-I ' of fig. 3A, fig. 3C is a sectional view taken along line II-II ' of fig. 3A, and fig. 3D is a sectional view taken along line iii-iii ' of fig. 3A. The description given above with reference to fig. 1 and fig. 2A to 2D will be omitted or will be briefly given below.

Referring to fig. 3A through 3D, an ESD device 100-1 according to an example embodiment may include a substrate 101, a well 103, a fin F, P type impurity region 110, an N type impurity region 120, a fin cut isolation region FC, a gate line 130, and a contact 140. As shown in fig. 3A, the ESD device 100-1 according to an example embodiment may have a stripe structure. However, the ESD device 100-1 according to an example embodiment is not limited to a stripe structure. For example, the ESD device 100-1 according to an example embodiment may have a ring structure.

The substrate 101 may be, for example, a P-type substrate. The well 103 may be formed in the substrate 101, and as described above, the well 103 may be an N-type well. The well 103 may be formed on an upper portion of the substrate 101 and may be separated from other peripheral devices by an isolation structure 107 defining the well 103. Here, the other device may include other ESD devices configured as an ESD protection circuit (see 1000 of fig. 1), and may include a protection target device (see 2000 of fig. 1) protected by the ESD protection circuit 1000. An active region ACT may be defined in an upper portion of the well 103.

A plurality of fins F may be formed on the substrate 101. The plurality of fins F may have a structure protruding from the substrate 101, and may be separated from each other in the second direction (y direction in fig. 3A) to extend in the first direction (x direction). Referring to fig. 3C, the bottom surface of the fin F may correspond to the top surface Sf of the substrate 101 and may have a first height H1. The bottom surface of the active region ACT of the well 103 may have a basic height H0 and may be lower than the first height H1.

The P-type impurity region 110 may be formed at an upper portion of the fin F. Further, the P-type impurity region 110 may be disposed in a central portion of the fin F in the first direction (x-direction). The N-type impurity region 120 may also be formed on the upper portion of the fin F. The N-type impurity region 120 may be disposed in a portion of the fin F away from the center in the first direction (x-direction). That is, the N-type impurity region 120 may be disposed outside either side of the P-type impurity region 110. Accordingly, the ESD device 100-1 according to an example embodiment may have a P-type diode structure.

In the ESD device 100-1 according to an example embodiment, the P-type impurity region 110 and the N-type impurity region 120 may be formed at an upper portion of the fin F. However, the range of each of the P-type impurity region 110 and the N-type impurity region 120 is not limited thereto. For example, according to an embodiment, the P-type impurity region 110 and the N-type impurity region 120 may be formed to extend from an upper portion of the fin F to a lower portion of the fin F or from an upper portion of the fin F to an upper portion of the active region ACT.

The fin cut isolation region FC may be formed to extend in the second direction (y-direction). The fin cutting isolation region FC may cut the fin F to isolate the P-type impurity region 110 from the N-type impurity region 120 in the first direction (x-direction). That is, the fin cut isolation region FC may be between the P-type impurity region 110 and the N-type impurity region 120 in the first direction (x-direction). A lower portion of the fin cut isolation region FC may be filled with an isolation insulating layer 105. Further, as shown in fig. 3C and 3D, an isolation insulating layer 105 may be formed over the substrate 101 except for the top surface of the fin F and all top surfaces of the fin cut isolation region FC. That is, the isolation insulating layer 105 may be formed between the fins F and on the substrate 101 corresponding to the outside of the fins F in the second direction (y direction).

The bottom surface FCb of the fin cut isolation region FC may have a second height H2. As shown in fig. 3D, the second height H2 may be higher than the first height H1, which is the height of the top surface Sf of the substrate 101H 1. However, according to example embodiments, the thickness of the fin removed in the fin cutting process may vary, and thus, the height of the bottom surface FCb of the fin cutting isolation region FC may vary. The bottom surface FCb of the fin cut isolation region FC will be described in more detail with reference to fig. 7 and 8.

For reference, in the related art ESD device, a Shallow Trench Isolation (STI) structure or a Deep Trench Isolation (DTI) structure may be formed for junction separation between the P-type impurity region 110 and the N-type impurity region 120. The STI or DTI structure may be substantially formed by enabling to divide the depth of the active area ACT. Thus, the bottom surface of the STI or DTI structure may be below the base height H0, which is the bottom surface of the active region ACT, H0. Here, the STI structure and the DTI structure may be distinguished from each other by performing the trench forming process one or more times, and the DTI structure on which the trench process is performed two or more times may be deeper than the STI structure on which the trench process is performed one time.

On the other hand, in the ESD device 100-1 according to the example embodiment, the fin cut isolation region FC may be formed by removing only the fin F, and thus, all or a portion of the active region ACT under the fin F may be maintained. According to example embodiments, the fin cut isolation region FC may be formed by removing only a portion of the fin F. Accordingly, the ESD device 100-1 according to an example embodiment may have a structure of: the fins F adjacent to each other in the first direction (x direction) are connected to each other by the active region ACT thereunder, and may have, for example, a structure incorporating the active region ACT.

A plurality of gate lines 130 may be formed on the substrate 101. The plurality of gate lines 130 may extend in the second direction (y direction) to cover a portion of the fin F, and may be separated in the first direction (x direction). As shown in fig. 3B, the gate lines 130 may include a first gate line 130a and a second gate line 130B, the first gate line 130a being disposed only on the fin F in the first direction (x-direction), the second gate line 130B being disposed at a portion corresponding to the fin F and the fin cut isolation region FC. The first gate line 130a may cover the top surface of the fin F and both side surfaces of the fin F in the second direction (y-direction). The second gate line 130b may cover a top surface of the fin F, one side surface of the fin F in the first direction (x-direction), and both side surfaces of the fin F in the second direction (y-direction). Here, one side surface of the fin F in the first direction (x direction) may correspond to one side surface FCs of the fin cut isolation region FC.

The gate line 130 may have a first width W1 in a first direction (x-direction). The first width W1 may be, for example, about 70 nm. The first width W1 of the gate line 130 is not limited to this value. The widths of the first and second gate lines 130a and 130b in the first direction (x-direction) may be substantially the same. In other words, each of the first and second gate lines 130a and 130b may have a first width W1 in the first direction (x-direction).

The gate line 130 may include a conductive material in which polycrystalline silicon or single crystal silicon is doped with a metal material such as aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), or the like. In addition, the gate line 130 may include a metal. For example, the gate line 130 may include titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), and tantalum carbide (TaC). The gate line 130 may include a single layer or a plurality of layers.

In the ESD device 100-1 according to an example embodiment, unlike a gate line of a general transistor, the gate line 130 may be maintained in a floating state without being connected to an electrode terminal. In other words, the gate line 130 may be a dummy gate line that does not perform an electrical function. The gate line 130 may perform a function of a mask in a doping process of forming the P-type impurity region 110 and the N-type impurity region 120.

In fig. 3B to 3D, a gate insulating layer may be between the gate line 130 and the fin F. According to example embodiments, the gate insulating layer may cover the entire top and side surfaces of the fin F except only portions where the contacts 140 are connected with the impurity regions 110 and 120. In addition, according to an embodiment, the gate insulating layer may be omitted on the basis that the gate line 130 does not perform an electrical function.

In the ESD device 100-1 according to an example embodiment, the fin cut isolation region FC may have a second width W2 in the first direction (x-direction). The second width W2 may be, for example, 100nm or less. In general, the width of the fin cut isolation region FC in the first direction (x-direction) may be defined as a distance between fins F adjacent to each other in the first direction (x-direction). However, as shown in fig. 3B, when a portion of the second gate line 130B is included in the fin cut isolation region FC, the width of the fin cut isolation region FC in the first direction (x-direction) may be defined as a distance between the second gate lines 130B adjacent to each other in the first direction (x-direction). In the ESD 100-1 according to example embodiments, since the second width W2 of the fin cut isolation region FC is 100nm or less (e.g., about 80nm) and is very small, a separate gate line may not be provided in the fin cut isolation region FC.

For reference, in the related art ESD device, since the STI or DTI structure is formed by making it possible to divide the depth of the active region ACT, a sufficient distance in the first direction (x direction) must be secured to form the trench of the STI or DTI. For example, the width of the STI or DTI structure of the related art ESD device in the first direction (x-direction) may be about 230 nm. Further, when the width of the STI or DTI structure in the first direction (x direction) is wide, a separate gate line may be provided on the top surface of the STI or DTI structure to extend. As a detailed example, when the width of the gate line 130 is about 70nm, one additional gate line may be disposed at a central portion of the top surface of the STI or DTI structure having a width of about 230nm in the first direction (x-direction), and may maintain an interval of about 80nm with respect to the gate line adjacent thereto.

A contact 140 may be formed on the P-type impurity region 110 and the N-type impurity region 120. The P-type impurity region 110 may be electrically connected to the pad 200 through the contact 140, and the N-type impurity region 120 may be electrically connected to a terminal for applying a power supply voltage Vdd. When the gate insulating layer is on the top surface of the fin F, the contact 140 may be connected to the P-type impurity region 110 and the N-type impurity region 120 in a structure passing through the gate insulating layer. Further, according to the embodiment, the N-type impurity region 120 may be electrically connected to a terminal for applying the ground voltage Vss through the contact 140.

The ESD device 100-1 according to example embodiments may include a P-type impurity region 110 and an N-type impurity region 120 each formed in a fin (F) structure, and may include a fin cut isolation region FC for junction separation between the P-type impurity region 110 and the N-type impurity region 120, and thus, may have a small size, a low on-voltage, and a low on-resistance. The small size, low on-voltage and low on-resistance of the ESD device 100-1 according to an example embodiment will be described in more detail with reference to fig. 4.

Fig. 4 is a graph illustrating on-voltage characteristics and on-resistance characteristics of the ESD device having the P-type diode structure of fig. 3A to 3D and the ESD device having the related art P-type diode structure. The x-axis represents a voltage applied to a region between P-type impurity region 110 and N-type impurity region 120, and the y-axis represents a current based on the application of the voltage. The thick straight line "DTI" denotes a related art ESD device including a DTI structure, and the thin straight line "FC" denotes an ESD device including a fin cut isolation region FC according to an example embodiment. Here, the on voltage may represent a voltage that allows a current to start flowing based on application of the voltage, and the on resistance may correspond to a resistance after the conduction, and for example, may correspond to a value obtained by dividing the voltage by the current after the conduction.

Referring to fig. 4, the related art ESD device may have an on-voltage of about 1.56V, and may have an on-resistance of about 0.33 Ω. On the other hand, the ESD device 100-1 according to an example embodiment may have an on-voltage of about 1.25V, and may have an on-resistance of about 0.3 Ω. As a result, the turn-on voltage and the turn-on resistance of the ESD device 100-1 according to the example embodiment may be lower than those of the related art ESD device.

The related art ESD device for experiments may have 450 μm²And may have an area of 6 μm²The effective area of (a). Here, the area and the effective area are as described above with reference to fig. 2B and 2D. On the other hand, the ESD device 100-1 according to an example embodiment may have a 406 μm²And may have an area of 6 μm²The effective area of (a). As a result, the active area of the ESD device 100-1 according to example embodiments may be the same as that of the related art ESD device, and the on-voltage and the on-resistance may be greater than that of the related art ES deviceThe on-voltage and on-resistance of the D device are low. Further, the total area of the ESD device 100-1 according to example embodiments may be smaller than that of the related art ESD device, and thus, may contribute to reducing the size of the ESD protection circuit (see 1000 of fig. 1). As a result, the ESD device 100-1 according to an example embodiment may enable the ESD protection circuit 1000 in which a Power Performance Area (PPA) is good.

Fig. 5 is a cross-sectional view of an ESD device having an N-type diode structure in the ESD protection circuit 1000 of fig. 1. The description given above with reference to fig. 1 to 4 will be omitted or will be briefly given below.

Referring to fig. 5, an ESD device 100-2 according to an example embodiment may have an N-type diode structure, and thus, may be different from the ESD device 100-1 of fig. 3A to 3D. In detail, in the ESD device 100-2 according to an example embodiment, the N-type impurity region 120 may be formed at an upper portion of the fin F. In addition, the N-type impurity region 120 may be disposed in a central portion of the fin F in the first direction (x-direction). In addition, the P-type impurity region 110 may be disposed at an upper portion of the fin F. The P-type impurity region 110 may be disposed in a portion of the fin F away from the center in the first direction (x-direction). That is, the P-type impurity regions 110 may be disposed at both outer portions of the N-type impurity region 120.

In the ESD device 100-2 according to an example embodiment, the well 103a may be an N-type well, and may be formed only under the N-type impurity region 120. However, according to an embodiment, the well 103a may be omitted. The ESD device 100-2 according to example embodiments may have an N-type diode structure, the N-type impurity region 120 may be electrically connected to the pad 200 through the contact 140, and the P-type impurity region 110 may be electrically connected to a terminal for applying the ground voltage Vss through the contact 140. The ESD device 100-2 according to an example embodiment may have a bar type structure or a ring type structure.

In addition, fin cut isolation region FC and gate line 130 are the same as described for ESD device 100-1 shown in fig. 3A to 3D.

Fig. 6 is a graph illustrating on-voltage characteristics and on-resistance characteristics of the ESD device having the N-type diode structure of fig. 5 and the ESD device having the related art N-type diode structure. The concepts of x-axis, y-axis, "DTI", "FC", on-voltage and on-resistance are as described above with reference to the graph of FIG. 4.

Referring to fig. 6, the related art ESD device may have an on-voltage of about 1.44V, and may have an on-resistance of about 0.35 Ω. On the other hand, the ESD device 100-2 according to an example embodiment may have an on-voltage of about 1.25V, and may have an on-resistance of about 0.31 Ω. As a result, the turn-on voltage and the turn-on resistance of the ESD device 100-2 according to the example embodiment may be lower than those of the related art ESD device.

The related art ESD device for experiment may have 433 μm²And may have an area of 92 μm²The effective area of (a). On the other hand, the ESD device 100-2 according to an example embodiment may have a 405 μm²And may have an area of 128 μm²The effective area of (a). As a result, the active area of the ESD device 100-2 according to example embodiments may be larger than that of the related art ESD device, and the on-voltage and the on-resistance may be lower than those of the related art ESD device. Further, the total area of the ESD device 100-2 according to example embodiments may be smaller than that of the related art ESD device, and thus, may contribute to reducing the size of the ESD protection circuit (see 1000 of fig. 1). As a result, the ESD device 100-2 according to an example embodiment may enable the PPA to be a good ESD protection circuit 1000.

For reference, as the effective area becomes wider, the on-resistance can be easily reduced. In addition, when the current path between P-type impurity region 110 and N-type impurity region 120 increases, the on-voltage may increase. Therefore, when the effective area is wide and the distance between the P-type impurity region 110 and the N-type impurity region 120 is short, the operation characteristics of the ESD device can be enhanced. When a current path is formed in the horizontal direction like a planar transistor, the turn-on voltage may decrease but the leakage may increase.

In the related art ESD device, when an STI or DTI structure is included, the width of the STI or DTI is large and the depth is deep, a current path between the P-type impurity region and the N-type impurity region may be long, and thus, an on-voltage may be relatively high. On the other hand, since the ESD device 100-1 or 100-2 according to example embodiments includes the fin cut isolation region FC having a narrow width and a shallow depth, a current path between the P-type impurity region 110 and the N-type impurity region 120 may be short, and thus, an on-voltage may be relatively low. Further, as described above, the fin cut isolation region FC may be formed by removing only a portion of the fin F, and thus, all or a portion of the active region ACT below the fin F may be maintained. Accordingly, the ESD device 100-1 or 100-2 according to example embodiments may have a structure of: the fins F adjacent to each other in the first direction (x direction) are connected to each other by the active region ACT thereunder, and may have, for example, a structure incorporating the active region ACT.

Fig. 7 to 9 are cross-sectional views of ESD devices with P-type diode structures according to example embodiments, and may each correspond to fig. 3B. The description given above with reference to fig. 1 to 6 will be omitted or will be briefly given below.

Referring to fig. 7, an ESD device 100a-1 according to example embodiments may be different from the ESD device 100-1 of fig. 3A to 3D in terms of the depth of a fin cut isolation region FC'. In detail, in the ESD device 100a-1 according to an example embodiment, the second height H2 ' as the height of the bottom surface FC ' b of the fin cut isolation region FC ' may be substantially the same as the first height H1 as the height of the top surface (see Sf of fig. 3C) of the substrate 101. In other words, in the ESD device 100a-1 according to example embodiments, the fin cut isolation region FC' may be formed by removing the fin F protruding from the top surface Sf of the substrate 101 in the third direction (z direction).

Referring to fig. 8, an ESD device 100b-1 according to an example embodiment may be different from the ESD device 100-1 of fig. 3A to 3D in terms of the depth of a fin cut isolation region FC ″. In detail, in the ESD device 100b-1 according to an example embodiment, the second height H2 ″ as the height of the bottom surface FC "b of the fin cut isolation region FC ″ may be less than the first height H1 as the height of the top surface Sf of the substrate 101. In other words, in the ESD device 100b-1 according to example embodiments, the fin cut isolation region FC ″ may be formed by removing the fin F protruding from the top surface Sf of the substrate 101 in the third direction (z direction) and a portion of the upper portion of the active region ACT below the fin F.

Referring to fig. 9, an ESD device 100c-1 according to an example embodiment may be different from the ESD device 100-1 of fig. 3A to 3D in terms of a structure of a gate line 130'. In detail, in the ESD device 100c-1 according to an example embodiment, the gate line 130' may be disposed only on the upper surface of the fin F in the first direction (x-direction), and may not be disposed on the fin cut isolation region FC. In other words, in the ESD device 100c-1 according to example embodiments, unlike the ESD device 100-1 of fig. 3A to 3D, the second gate line 130b structure covering the fin F and the fin cut isolation region FC in the first direction (x direction) may not be formed. Therefore, as shown in fig. 9, the second width W2, which is the width of the fin cut isolation region FC in the first direction (x direction), may be defined as the distance between the side surfaces of the fins F adjacent to each other in the first direction (x direction), and may be defined as the distance between the two side surfaces FCs of the fin cut isolation region FC, for example.

According to an embodiment, in the ESD devices 100a-1, 100b-1 and 100c-1 of fig. 7 to 9, the N-type impurity region 120 may be electrically connected to a terminal for applying the ground voltage Vss through the contact 140.

Fig. 10A to 10C are perspective and cross-sectional views of an ESD device having a P-type diode structure according to an embodiment, and may correspond to fig. 3B and 3C. The description given above with reference to fig. 1 to 9 will be omitted or will be briefly given below.

Referring to fig. 10A through 10C, an ESD device 100D-1 according to an example embodiment may include a Gate All Around (GAA) structure, and thus, may be different from the ESD device 100-1 of fig. 3A through 3D. To provide a more detailed description, as shown in fig. 10A, the ESD device 100d-1 according to an example embodiment may have a GAA structure in which the gate line 130c completely surrounds four surfaces of the nanowire NW. For reference, fig. 10A is a perspective view conceptually illustrating a three-dimensional (3D) shape of the ESD device 100D-1 according to an example embodiment. Fig. 10B and 10C correspond to cross-sectional views of ESD device 100d-1 according to example embodiments, in which six gate lines 130C separated from each other in the first direction (x-direction) may be disposed, and three nanowires NW separated from each other in the second direction (y-direction) and surrounded by the gate lines 130C may be disposed.

The fin F may be formed to have a certain height in the third direction (z direction), and then a middle portion of the fin F may be removed, thereby forming the nanowire NW. In other words, the nanowire NW may correspond to the upper end portion of the initial fin F. According to example embodiments, two or more middle portions of the fin F in the third direction (z direction) may be removed, and thus, two or more nanowires NW separated from each other in the third direction (z direction) may be formed.

In the ESD device 100d-1 according to example embodiments, a portion of the upper portion of the fin F and the nanowire NW may be cut by the fin cut isolation region FC, and thus, the P-type impurity region 110a and the N-type impurity region 120a may be separated from each other in the first direction (x-direction). As shown in fig. 10B, the P-type impurity region 110a or the N-type impurity region 120a may be formed by doping a portion of the upper portion of the fin F and a portion of the nanowire NW with a P-type impurity or an N-type impurity. The contact 140a may be formed in a structure in which the contact 140a contacts the impurity regions of the nanowire NW and the fin F together.

As a result, the ESD device 100D-1 according to example embodiments may be substantially the same as the ESD device 100-1 of fig. 3A through 3D, except that the nanowire NW is disposed to be separated from the upper portion of the fin F. In other words, as shown in fig. 10B and 10C, when the nanowire NW is connected to the fin F in the third direction (z direction), it can be seen that the structure of the ESD device 100d-1 according to the example embodiment is substantially the same as the structure shown in fig. 3B and 3C. For reference, the space between the fin F and the nanowire NW may be filled together with a process of filling the upper portion of the isolation insulating layer 105 of the fin cutting isolation region FC.

Fig. 11 is a perspective view of an ESD device having a P-type diode structure according to an example embodiment, and conceptually illustrates a 3D shape of an ESD device 100e-1 according to an example embodiment as in fig. 10A. The description given above with reference to fig. 10A to 10C will be omitted or will be briefly given below.

Referring to fig. 11, an ESD device 100e-1 according to an example embodiment may include a multi-bridge channel (MBC) structure, and thus, may be different from the ESD device 100d-1 of fig. 10A to 10C. To provide a more detailed description, as shown in fig. 11, the ESD device 100e-1 according to an example embodiment may have an MBC structure in which the gate line 130c completely surrounds four surfaces of the nanosheet NS. The nanosheets NS may have the structure of a sheet. According to example embodiments, the width of the nanosheets NS in the second direction (y-direction) may be several times (or several tens of times) the thickness of the nanosheets NS in the third direction (z-direction), and thus, may be structurally different from the nanowire. As the width of the nanosheet NS in the second direction (y-direction) increases, the width of the fin F thereunder in the second direction (y-direction) may increase corresponding to the nanosheet NS. In addition, the number of gate lines 130C and nano-sheets NS, the method of forming the nano-sheets NS, the structure of each of the P-type impurity region and the N-type impurity region, and the structure of the contact are as described above with reference to fig. 10A to 10C showing the ESD device 100 d-1.

Fig. 12A to 12B, 13A to 13C, 14A to 14C, 15A to 15B, and 16 are cross-sectional views illustrating a process of manufacturing an ESD device having the P-type diode structure of fig. 3A to 3D according to example embodiments. Each of fig. 12A, 13A, 14A, 15A, and 16 may correspond to fig. 3B, each of fig. 12B, 13B, 14B, and 15B may correspond to fig. 3C, and each of fig. 13C and 14C may correspond to fig. 3D. A process of manufacturing the ESD device will be described below with reference to fig. 12A to 12B, fig. 13A to 13C, fig. 14A to 14C, fig. 15A to 15B, and fig. 16 in conjunction with fig. 3A to 3D, and the description given above with reference to fig. 1 to 11 will be omitted or will be briefly given below.

Referring to fig. 12A and 12B, a well 103 may be formed on a substrate 101. The well 103 may be an N-type well, and may be formed by doping an N-type impurity to a certain depth on the substrate 101. As shown by the dotted line, an active region ACT may be defined in an upper portion of the well 103. For example, the active area ACT may be at H0Over the area. The doping concentration of the active region ACT may be higher than other portions of the well 103. For example, as described above, when the well 103 is a well of 10¹⁶/cm³Or less doped with N-type impurities, the active region ACT may be one in which 10 is doped¹⁶/cm³Or a higher doping concentration of N0 region doped with an N type impurity. However, the doping concentration of each of the well 103 and the active region ACT is not limited to this value.

After forming the well 103, an isolation structure 107 defining an ESD device may be formed on the substrate 101. The isolation structure 107 may include an insulating layer such as an oxide, nitride, or oxynitride.

Subsequently, a mask pattern extending in the first direction (x direction) may be formed on the top surface of the substrate 101. The mask pattern may include, for example, a lower mask pattern and an upper mask pattern. In addition, the lower mask pattern may be formed of a hard mask layer such as an oxide or nitride, and the upper mask pattern may include a photoresist. According to example embodiments, each of the lower and upper mask patterns may be formed of a hard mask layer. After forming the mask pattern, an upper portion of the substrate 101 may be etched by using the mask pattern as a mask, thereby forming a plurality of fins F extending in the first direction (x direction) and separated from each other in the second direction (y direction). After forming fin F, top surface Sf of substrate 101 may have a first height H1. According to example embodiments, the lower mask pattern may remain on the top surface of each of the fins F. For reference, a section corresponding to fig. 3D may be substantially the same as fig. 12B, and thus, a sectional view thereof is omitted.

Referring to fig. 13A to 13C, after forming the fins F, fin cut isolation regions FC for dividing each of the fins F into a plurality of portions (e.g., three portions) may be formed in the first direction (x-direction). The fin cut isolation region FC may extend in the second direction (y-direction). Therefore, as shown in fig. 13C, the fin F may be removed in the second direction (y direction). As described above, the fin cut isolation region FC may have the second width W2 in the first direction (x direction), and the second width W2 may be small, for example, may be 100nm or less. The bottom surface FCb of the fin cut isolation region FC may have a second height H2, and may be slightly higher than the first height H1, which is the height of the top surface Sf of the substrate 101H 1. However, according to an embodiment, the bottom surface FCb of the fin cut isolation region FC may be substantially the same as the height of the top surface Sf of the substrate 101, or may be lower than the height of the top surface Sf of the substrate 101.

Referring to fig. 14A to 14C, an insulating material for the isolation insulating layer 105 may be deposited on the entire surface of the substrate 101 and may be planarized. The planarization may be performed by a Chemical Mechanical Polishing (CMP) process and/or an etching process such as etch back. The lower mask pattern remaining on the top surface of each of the fins F may be used as an etch stop layer in the planarization process. By performing the planarization process, the insulating material for the isolation insulating layer may be filled into the region between the fins F adjacent to each other in the second direction (y direction) and into the fin cut isolation region FC in the first direction (x direction), and the top surface of the insulating material for the isolation insulating layer may be substantially coplanar with the top surface of the lower mask pattern.

Subsequently, the isolation insulating layer 105 may be formed by removing the insulating material for the isolation insulating layer 105 to a certain depth using the lower mask pattern as a mask. The isolation insulating layer 105 may be formed to have an appropriate thickness based on a separation function between the fins F in the second direction (y direction) and a junction separation function between the P-type impurity region 110 and the N-type impurity region 120 in the first direction (x direction). The isolation insulating layer 105 may be formed, and then, the lower mask pattern may be removed.

According to an embodiment, in association with forming the isolation insulating layer 105, when an etch selectivity of an insulating material for the isolation insulating layer with respect to the lower mask pattern is high, a planarization process may be omitted, and the isolation insulating layer 105 may be immediately formed through an etch back process. Further, according to the embodiment, when the etching selectivity of the insulating material for the isolation insulating layer with respect to the fin F is high, the isolation insulating layer 105 may be formed by an etch back process without a lower mask pattern.

Referring to fig. 15A and 15B, after forming the isolation insulating layer 105, a dielectric layer covering the entire surface of the resultant material on the substrate 101 may be formed to have a certain thickness. For example, the dielectric layer may cover the top surface of the isolation insulating layer 105 and both side surfaces and the top surface of each of the fins F. According to example embodiments, the dielectric layer may later configure the gate insulating layer of the (configure) gate line 130. The gate line 130 may not perform a basic electrical function, and thus, according to example embodiments, the dielectric layer may be omitted.

After forming the dielectric layer, a conductive layer covering the entire surface of the resulting material of the substrate 101 may be formed and planarized. The material of the conductive layer may be the same as described for the gate line 130 in the ESD device 100-1 of fig. 3A to 3D. Subsequently, a mask pattern may be formed on the top surface of the planarized conductive layer. The mask patterns may have a structure including mask patterns extending in the second direction (y-direction) and separated from each other in the first direction (x-direction). The mask pattern may include: a first mask pattern disposed on the conductive layer corresponding to only the fin F in a first direction (x direction); and a second mask pattern disposed on the conductive layer corresponding to the fin F and the fin cut isolation region FC.

Subsequently, the gate line 130 may be formed by etching the conductive layer by using the mask pattern as a mask. The gate line 130 may have a structure including gate lines extending in the second direction (y-direction) to correspond to the mask pattern and spaced apart from each other in the first direction (x-direction), and may cover a top surface and both side surfaces of each of the fins F. In addition, as described above, the gate line 130 may include the first gate line 130a and the second gate line 130 b. The first gate line 130a may be arranged only on the upper surface of the fin F in the first direction (x-direction) to correspond to the first mask pattern. The second gate line 130b may be disposed on the upper surfaces of the fin F and the fin cut isolation region FC to correspond to the second mask pattern.

In forming the gate lines 130, the dielectric layer on the fin F and the isolation insulating layer 105 may be removed, and the top surface of the isolation insulating layer 105 and the top surface of the fin F between the adjacent gate lines 130 may be exposed in the first direction (x direction). According to an embodiment, when the gate line 130 is formed, the dielectric layer on the fin F and the isolation insulating layer 105 may be maintained without being removed. In this case, after the gate lines 130 are formed, a dielectric layer may be maintained on the top surface of the isolation insulating layer 105 and the top surface of the fin F between the adjacent gate lines 130. For reference, after the gate line 130 is formed, a cross-section corresponding to fig. 3D may be substantially the same as fig. 14C. Therefore, the sectional view thereof is omitted.

Referring to fig. 16, after forming the gate line 130, a P-type impurity region 110 and an N-type impurity region 120 may be formed. In more detail, first, a first mask pattern covering the other fin F portion except the fin F portion where the P-type impurity region 110 is to be formed may be formed. Subsequently, an ion implantation process of implanting P-type impurities into the exposed portion of the fin F may be performed by using the first mask pattern as a mask, thereby forming the P-type impurity region 110. Subsequently, the first mask pattern may be removed, a second mask pattern covering only the P-type impurity region 110 may be formed, and an ion implantation process of implanting N-type impurities into the exposed fin F portion may be performed by using the second mask pattern as a mask, thereby forming the N-type impurity region 120.

The gate line 130 may be used as a mask together with the first mask pattern or the second mask pattern in the ion implantation process. Accordingly, as shown in fig. 16, the portion of the fin F under the gate line 130 may not be doped. However, a portion of the lower portion of the gate line 130 may be doped with a corresponding impurity by diffusion. Accordingly, the P-type impurity region 110 and the N-type impurity region 120 may be formed in the first direction (x-direction) up to a portion slightly inward from the side surface of the gate line 130.

After forming P-type impurity region 110 and N-type impurity region 120, contact 140 connected to each of P-type impurity region 110 and N-type impurity region 120 may be formed, and thus, ESD device 100-1 of fig. 3A to 3D may be completed. An insulating material layer covering all the resultant materials on the substrate 101 may be formed, an interlayer insulating layer may be formed by planarizing the insulating material layer, a mask pattern may be formed on the interlayer insulating layer, a contact hole may be formed by an etching process using the mask pattern, and the contact 140 may be formed by filling a conductive material into the contact hole.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.