阅读说明：本技术 一种高计算准确度、低硬件开销单变量随机电路及其配置方法 (Single-variable random circuit with high calculation accuracy and low hardware overhead and configuration method thereof ) 是由 钟坤材 钱炜慷 于 2021-09-03 设计创作，主要内容包括：本发明涉及一种高计算准确度、低硬件开销单变量随机电路及其配置方法,其中电路由n比特随机源、n比特重排列元件、n比特反信号选取元件产生的n比特随机数和n比特输入X进行比较产生一个值为的随机比特流,基于所述值为的随机比特流,通过d-1个D触发器,产生另外d-1个值为的随机比特流,通过所述d比特重排列元件重排列d个的随机比特流的输入顺序；由n比特随机源、比特信号选取元件、m比特重排列元件、m比特反信号选取元件产生m个值为且互相独立的随机比特流；由随机计算核心电路基于所述d个值为的随机比特流、m个值为且互相独立的随机比特流计算并输出最终计算结果。有益效果是高计算准确度、低硬件开销。(The invention relates to a single variable random circuit with high calculation accuracy and low hardware overhead and a configuration method thereof, wherein the circuit is generated by comparing an n-bit random number generated by an n-bit random source, an n-bit rearrangement element and an n-bit inverse signal selection element with an n-bit input X to generate a value of Based on said value of By D-1D flip-flops to generate a further D-1 value of By the d-bit rearrangement element, rearranging d pieces of the random bit stream The input order of the random bit stream of (a); the n-bit random source, the bit signal selection element, the m-bit rearrangement element, and the m-bit inverse signal selection element generate m values And mutually independent random bit streams; calculating, by a random computation core circuit, based on the d values as Of a random bit stream of m values of And mutually independent random bit streams are calculated and a final calculation result is output. The method has the advantages of high calculation accuracy and low hardware overhead.)

1. A single variable random circuit with high calculation accuracy and low hardware overhead is characterized in that: comprising an n-bit random source for generating d values ofAn n-bit rearrangement element, an n-bit inverse signal selection element, a comparator, D-1D flip-flops, and a D-bit rearrangement element for generating m values ofA bit signal selection element, an m-bit rearrangement element, an m-bit inverse signal selection element and a random computation core circuit of the random bit stream which are independent of each other; an n-bit random number generated by an n-bit random source, an n-bit rearrangement element, an n-bit inverse signal selection element, and an n-bit input X-input comparator to generate a value ofBased on said value ofBy means of said D-1D flip-flops, to generate a further D-1 value ofBy said d-bit rearranging element rearranging d values toThe input order of the random bit stream of (a); the n-bit random source, the bit signal selection element, the m-bit rearrangement element, and the m-bit inverse signal selection element generate m valuesAnd mutually independent random bit streams; the random computation core circuit is based on d values asOf a random bit stream of m values ofAnd mutually independent random bit streams are calculated and a final calculation result is output.

2. A high computational accuracy, low hardware overhead univariate random circuit according to claim 1, wherein: the univariate random circuit with high calculation accuracy and low hardware overhead is a random circuit for realizing the univariate function of 0.5cos (pi x) +0.5 with high calculation accuracy and low hardware overhead, said one n-bit random source is an 8-bit linear feedback shift register, said one n-bit rearrangement element is an 8-bit rearrangement element, the n-bit inverse signal selecting element is an 8-bit inverse signal selecting element, the D-1D flip-flops are 3D flip-flops, said one d-bit rearrangement element is a 4-bit rearrangement element, said one m-bit rearrangement element is a 6-bit rearrangement element, the m-bit inverse signal selection element is a 6-bit inverse signal selection element, and the random computation core circuit is a univariate function 0.5cos (pi x) +0.5 random computation core circuit.

3. A configuration method of a single-variable random circuit with high calculation accuracy and low hardware overhead is characterized by comprising the following steps:

the definition and assumption used by the configuration method of the single-variable random circuit with high calculation accuracy and low hardware overhead are as follows: for a bit signal selection element that selects m bits from n bits, the set of possible configurations is B, and the ith configuration is B_iThe number of elements in the B set isSuppose B₁Selecting the 1 st to the mth bit to output; for a k-bit rearrangement element that rearranges k bits, the set of possible configurations is R^kThe ith configuration mode isThen R is^kThe number of elements of the set is k! Suppose thatAndrespectively representing the inversion of k bits and the keeping of the original sequence of the k bits; for k-bit inverted signal selecting element for selecting and inverting several bits from k bits, the set of possible configuration modes is C^kThe ith configuration mode isThen C is^kThe number of elements of the set is 2^kSuppose thatRepresenting that k bits are all inverted; the set of the configuration modes of the n-bit random source is L, and the ith configuration mode is L_iAssuming that the number of elements in the set is l;

the configuration method of the single variable random circuit with high calculation accuracy and low hardware overhead uses the definition and the hypothesis to optimize the bit signal selection element, the n-bit rearrangement element, the m-bit rearrangement element, the d-bit rearrangement element, the n-bit inverse signal selection element and the m-bit inverse signal selection element of the single variable random circuit with high calculation accuracy and low hardware overhead according to any one of claim 1 or claim 2, so that the calculation accuracy of the single variable random circuit with high calculation accuracy and low hardware overhead is improved.

4. The method of claim 3, wherein the method is an iterative optimization configuration method, and wherein the iterative optimization configuration method comprises the following steps:

s1, initializing configuration, using L₁Configuring n-bit random source using B₁Configuring bit signal selection elements usingConfiguring n-bit inverse signal selection elements usingConfiguring m-bit inverse signal selection elements usingConfiguring n-bit rearrangement elements usingConfiguring m-bit rearrangement elements usingD bit rearrangement elements are configured and marked as the optimal configuration mode of the corresponding elements;

s2, obtaining initial calculation accuracy MAE through simulation based on the optimal configuration mode_minAnd assign it to MAE_prev；

S3, assigning i to 1;

s4, assignment j ═ 1;

s5, assigning k to 1;

s6, randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; using L_rConfiguring n-bit random source, configuring bit signal selection element using Bi, usingConfiguring n-bit inverse signal selection elements usingConfiguring m-bit inverse signal selection elements, and configuring other elements in an optimal configuration mode;

s7, based on the configuration of the step S6, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration L of the n-bit random source, the bit signal selection element, the n-bit inverse signal selection element and the m-bit inverse signal selection element_r、B_i、Andupdating MAE_minIs MAE; k is k + 1;

s8, if k is less than or equal to 2^mJumping to step S6, otherwise, proceeding to the next step;

S9、j＝j+1；

s10, if j is less than or equal to 2ⁿJumping to step S5, otherwise, proceeding to the next step;

S11、i＝i+1；

s12, ifJumping to step S4, otherwise, proceeding to the next step;

s13, assigning i to 1;

s14, randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; randomly generating an integer k in the range of 1 ≦ k ≦ m! (ii) a Using L_rConfiguring random sources, usingConfiguring n-bit rearrangement elements usingConfiguring m-bit rearrangement elements, and configuring other elements in an optimal configuration mode;

s15, based on the configuration of the step S14, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration of the n-bit random source, the n-bit rearrangement element and the m-bit rearrangement element_r，Andupdating MAE_minIs MAE; i is i + 1;

s16, if i ≦ n! Jumping to step S14, otherwise, proceeding to the next step;

s17, assigning i to 1;

s18, randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; randomly generating an integer k in the range of 1 ≦ k ≦ n! (ii) a Using L_rConfiguring n-bit random sources usingConfiguring n-bit rearrangement elements usingConfiguring m-bit rearrangement elements, and configuring other elements in an optimal configuration mode;

s19, based on the configuration of the step S18, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration of the n-bit random source, the n-bit rearrangement element and the m-bit rearrangement element_r，Andupdating MAE_minIs MAE; i is i + 1;

s20, if i is less than or equal to m! Jumping to step S18, otherwise, proceeding to the next step;

s21, assigning i to 1;

522. use ofConfiguring d-bit rearrangement elements, and configuring other elements in an optimal configuration mode;

s23, based on the configuration of the step S22, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration of the d-bit rearrangement elementUpdating MAE_minIs MAE; i is i + 1;

s24, if i ≦ d! Jumping to step 22, otherwise, performing the next step;

s25, if MAE_min＜MAE_prevUpdate the MAE_prevIs MAE_minJump to step S3, otherwise, end the whole processAnd finally, obtaining the optimal configuration mode of all the elements.

5. A high computational accuracy, low hardware overhead single variable random circuit configuration method as claimed in claim 3, said configuration method being a fast configuration method characterized by: in the fast configuration method of the single variable random circuit with high calculation accuracy and low hardware overhead, the configuration modes of a bit signal selection element, an m-bit rearrangement element and an m-bit inverse signal selection element are determined by the configuration modes of an n-bit rearrangement element and an n-bit inverse signal selection element; assuming that the ith bit of the random number input by the comparator is the p-th bit of the n-bit random source through the n-bit rearrangement element and the n-bit inverse signal selection element_iAn output bit, and the inverse signal of the ith bit is selected from a_iDetermination of the signal a_i1 stands for negation, a_i0 stands for unchanged; the configuration of the bit signal selection element, the m-bit rearrangement element and the m-bit inverse signal selection element will realize the ith value asBy the p-th of an n-bit random source_n-i+1An output bit is generated, the ith value isIs inversely signaled bySignal determination; the method comprises the following specific steps:

p1, initialization configuration, using L₁Configuring n-bit random source using B₁Configuring bit signal selection elements usingConfiguring n-bit inverse signal selection elements usingConfiguring m-bit inverse signal selection elements usingConfiguring n-bit rearrangement elements usingConfiguring m-bit rearrangement elements usingD bit rearrangement elements are configured and marked as the optimal configuration mode of the corresponding elements;

p2, based on the configuration of step P1, the simulation obtains an initial computational accuracy MAE_minAnd assign it to MAE_prev；

P3, assignment i ═ 1;

p4, randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; using L_rConfiguring random sources, usingConfiguring n-bit reverse signal selection element, determining the configuration of bit signal selection element, m-bit rearrangement element and m-bit reverse signal selection element based on the configuration of n-bit rearrangement element and n-bit reverse signal selection element, and marking as B_x、Andthe other elements are configured in their optimal configuration;

p5, based on the configuration of the step P4, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration L of the n-bit random source, the bit signal selection element, the n-bit inverse signal selection element, the m-bit rearrangement element and the m-bit inverse signal selection element_r、B_x、Andupdating MAE_minIs MAE; i is i + 1;

p6 if i is less than or equal to 2ⁿJumping to the step P4, otherwise, proceeding to the next step;

p7, assignment i ═ 1;

p8, randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; using L_rConfiguring n-bit random sources usingConfiguring n-bit rearrangement elements, determining the configuration of the bit signal selection element, the m-bit rearrangement element and the m-bit inverse signal selection element based on the configuration of the n-bit rearrangement elements and the n-bit inverse signal selection element, and marking as B_x、Andthe other elements are configured in their optimal configuration;

p9, based on the configuration of the step P8, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration L of the n-bit random source, the bit signal selection element, the n-bit rearrangement element, the m-bit rearrangement element and the m-bit inverse signal selection element_r、B_x、Andupdating MAE_minIs MAE; i is i + 1;

p10, if i ≦ n! Jumping to the step P8, otherwise, proceeding to the next step;

p11, assignment i ═ 1;

p12, useConfiguring d-bit rearrangement elements, and configuring other elements in an optimal configuration mode;

p13, based on the configuration of the step P12, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration of the d-bit rearrangement elementUpdating MAE_minIs MAE; i is i + 1;

p14, if i ≦ d! Jumping to the step P12, otherwise, proceeding to the next step;

p15 if MAE_min＜MAE_prevUpdate the MAE_prevIs MAE_minAnd jumping to a step P3, otherwise, ending the whole flow, and obtaining the final optimal configuration mode of all the elements.

[ technical field ] A method for producing a semiconductor device

The invention relates to the technical field of digital circuit design, in particular to a single-variable random circuit with high calculation accuracy and low hardware overhead and a configuration method thereof.

[ background of the invention ]

Random calculation is a novel calculation technology, adopts random bit stream coding data and uses a traditional circuit to calculate, and has the advantages of small calculation circuit area, high fault tolerance and the like. Random computing circuits (hereinafter referred to as random circuits) are an emerging digital circuit technology for encoding and computing numerical values by using random bit sequences, and have the advantage of realizing complex computation with simple circuits. The common random circuit is mainly formed by sequentially connecting a random number generator, a probability conversion circuit, a random calculation core circuit and a random-to-binary conversion circuit in series, wherein input variables are processed by the random circuit, and calculation results are output. The univariate random circuit is a random calculation circuit for realizing a univariate function. The traditional single-variable random circuit consists of d random sources with n bits, 1 random source with m bits, d comparators and a random computation core circuit. Fig. 1 is a schematic diagram of a conventional single variable random circuit structure. As shown in FIG. 1, d random sequence generators are composed of d random sources of n bits and d comparators, and generate d valuesAnd mutually independent random bit streams; 1 random source of m bits generates m values ofAnd mutually independent random bit streams; the random computation core circuit is implemented by a combinational logic circuit with d + m inputs. In order to improve the calculation accuracy, related documents and inventions adopt some strategies. FIG. 2 is a 10 bit univariate random access memorySchematic diagram of circuit rearrangement elements. As shown in FIG. 2, rearrangement can be used to improve the computational Accuracy as described in the references [ J.H.Anderson, Y.Hara-Azu and S.Yamashita, "Effect of LFSR feeding, screening and Feedback Polynomial storage Computing Access" in Design, Automation and Test in Europe Conference, pp.1550-1555, 2016 ]. FIG. 3 is a schematic diagram of a single variable random circuit structure employing rearranged elements. As shown in fig. 3, a rearranged univariate random circuit is applied. Although such a design can achieve high calculation accuracy, the circuit still needs d +1 random sources and d comparators, and the hardware overhead is large, so that the circuit has no practical value.

FIG. 4 is a schematic diagram of a bit signal selecting element, and FIG. 5 is a schematic diagram of an inverse signal selecting element. As shown in fig. 4 and 5, the bit signal selection and inverse signal selection components are components used in circuit design.

Aiming at the problems of the traditional single-variable random circuit, the invention carries out technical improvement on the single random circuit and the configuration method thereof.

[ summary of the invention ]

The invention aims to provide a single variable random circuit with high calculation accuracy and low hardware overhead.

In order to achieve the purpose, the technical scheme adopted by the invention is a single-variable random circuit with high calculation accuracy and low hardware overhead, which comprises an n-bit random source and is used for generating d values ofAn n-bit rearrangement element, an n-bit inverse signal selection element, a comparator, D-1D flip-flops, and a D-bit rearrangement element for generating m values ofAnd a bit signal selecting element, an m-bit rearranging element, and an m-bit inverse signal selecting element of the random bit stream independent of each other, and a random computation coreA core circuit; an n-bit random number generated by an n-bit random source, an n-bit rearrangement element, an n-bit inverse signal selection element, and an n-bit input X-input comparator to generate a value ofBased on said value ofBy means of said D-1D flip-flops, to generate a further D-1 value ofBy said d-bit rearranging element rearranging d values toThe input order of the random bit stream of (a); the n-bit random source, the bit signal selection element, the m-bit rearrangement element, and the m-bit inverse signal selection element generate m valuesAnd mutually independent random bit streams; the random computation core circuit is based on d values asOf a random bit stream of m values ofAnd mutually independent random bit streams are calculated and a final calculation result is output.

Preferably, the single variable random circuit with high computational accuracy and low hardware overhead comprises an 8-bit linear feedback shift register as a random source for generating 4 values ofAn 8-bit rearrangement element, an 8-bit inverse signal selection element, a random bit stream ofA comparator, 3D flip-flops, and a 4-bit rearrangement element for generating 6 values ofA bit signal selecting element, a 6-bit rearrangement element and a 6-bit inverse signal selecting element of the random bit stream which are mutually independent, and a random calculation core circuit for realizing a univariate function of 0.5cos (pi x) + 0.5; an 8-bit random number generated by an 8-bit linear feedback shift register, an 8-bit rearrangement element, an 8-bit inverse signal selection element, and an 8-bit input X-input comparator to generate a value ofBased on said value ofBy means of said 3D flip-flops, to generate a further 3 values ofBy said 4-bit rearrangement element rearranging 4 values toThe input order of the random bit stream of (a); the 8-bit linear feedback shift register, the bit signal selection element, the 6-bit rearrangement element and the 6-bit inverse signal selection element generate 6 valuesAnd mutually independent random bit streams; the random computation core circuit is based on 4 values asOf a random bit stream of 6 valuesAnd mutually independent random bit stream calculation and outputAnd finally calculating a result.

It is still another object of the present invention to provide a configuration method of a single-variable random circuit with high computational accuracy and low hardware overhead.

In order to achieve the above another object, the technical solution adopted by the present invention is a configuration method of a single-variable random circuit with high computational accuracy and low hardware overhead, wherein the configuration method of the single-variable random circuit with high computational accuracy and low hardware overhead uses the following definitions and assumptions: for a bit signal selection element that selects m bits from n bits, the set of possible configurations is B, and the ith configuration is B_iThe number of elements in the B set isSuppose B₁Selecting the 1 st to the mth bit to output; for a k-bit rearrangement element that rearranges k bits, the set of possible configurations is R^kThe ith configuration mode isThen R is^kThe number of elements of the set is k! Suppose thatAndrespectively representing the inversion of k bits and the keeping of the original sequence of the k bits; for k-bit inverted signal selecting element for selecting and inverting several bits from k bits, the set of possible configuration modes is C^kThe ith configuration mode isThen C is^kThe number of elements of the set is 2^kSuppose thatRepresenting that k bits are all inverted; the set of the configuration modes of the n-bit random source is L, and the ith configuration modeIs L_iAssuming that the number of elements in the set is l;

the configuration method of the single variable random circuit with high calculation accuracy and low hardware overhead optimizes the configuration modes of the bit signal selection element, the n-bit rearrangement element, the m-bit rearrangement element, the d-bit rearrangement element, the n-bit inverse signal selection element and the m-bit inverse signal selection element of the single variable random circuit with high calculation accuracy and low hardware overhead by using the definition and the hypothesis, so that the calculation accuracy of the single variable random circuit with high calculation accuracy and low hardware overhead is improved.

Preferably, the configuration method of the single-variable random circuit with high computational accuracy and low hardware overhead is an iterative optimization configuration method, and includes the following steps:

s1, initializing configuration, using L₁Configuring n-bit random source using B₁Configuring bit signal selection elements usingConfiguring n-bit inverse signal selection elements usingConfiguring m-bit inverse signal selection elements usingConfiguring n-bit rearrangement elements usingConfiguring m-bit rearrangement elements usingD bit rearrangement elements are configured and marked as the optimal configuration mode of the corresponding elements;

s2, obtaining initial calculation accuracy MAE through simulation based on the optimal configuration mode_minAnd assign it to MAE_prev；

S3, assigning i to 1;

s4, assignment j ═ 1;

s5, assigning k to 1;

s6, randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; using L_rConfiguring n-bit random source using B_iConfiguring bit signal selection elements usingConfiguring n-bit inverse signal selection elements usingConfiguring m-bit inverse signal selection elements, and configuring other elements in an optimal configuration mode;

s7, based on the configuration of the step S6, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration L of the n-bit random source, the bit signal selection element, the n-bit inverse signal selection element and the m-bit inverse signal selection element_r、B_i、Andupdating MAE_minIs MAE; k is k + 1;

s8, if k is less than or equal to 2^mJumping to step S6, otherwise, proceeding to the next step;

S9、j＝j+1；

s10, if j is less than or equal to 2ⁿJumping to step S5, otherwise, proceeding to the next step;

S11、i＝i+1；

s12, ifJumping to step S4, otherwise, proceeding to the next step;

s13, assigning i to 1;

s14, randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; randomly generating an integer k in the range of 1 ≦ k ≦ m! (ii) a Using L_rConfiguring random sources, usingConfiguring n-bit rearrangement elements usingConfiguring m-bit rearrangement elements, and configuring other elements in an optimal configuration mode;

s15, based on the configuration of the step S14, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration of the n-bit random source, the n-bit rearrangement element and the m-bit rearrangement element_r，Andupdating MAE_minIs MAE; i is i + 1;

s16, if i ≦ n! Jumping to step S14, otherwise, proceeding to the next step;

s17, assigning i to 1;

s18, randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; randomly generating an integer k in the range of 1 ≦ k ≦ n! (ii) a Using L_rConfiguring n-bit random sources usingConfiguring n-bit rearrangement elements usingConfiguring m-bit rearrangement elements, and configuring other elements in an optimal configuration mode;

s19, based on the configuration of the step S18, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration of the n-bit random source, the n-bit rearrangement element and the m-bit rearrangement element_r，Andupdating MAE_minIs MAE; i is i + 1;

s20, if i is less than or equal to m! Jumping to step S18, otherwise, proceeding to the next step;

s21, assigning i to 1;

s22, useConfiguring d-bit rearrangement elements, and configuring other elements in an optimal configuration mode;

s23, based on the configuration of the step S22, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration of the d-bit rearrangement elementUpdating MAE_minIs MAE; i is i + 1;

s24, if i ≦ d! Jumping to step 22, otherwise, performing the next step;

s25, if MAE_min＜MAE_prevUpdate the MAE_prevIs MAE_minAnd jumping to the step S3, otherwise, ending the whole process, and obtaining the final optimal configuration mode of all the elements.

Preferably, in the configuration method for the univariate random circuit with high calculation accuracy and low hardware overhead, the configuration method is a rapid configuration method; in the fast configuration method of the single variable random circuit with high calculation accuracy and low hardware overhead, the configuration modes of a bit signal selection element, an m-bit rearrangement element and an m-bit inverse signal selection element are determined by the configuration modes of an n-bit rearrangement element and an n-bit inverse signal selection element; assuming that the ith bit of the random number input by the comparator is the p-th bit of the n-bit random source through the n-bit rearrangement element and the n-bit inverse signal selection element_iAn output bit, and the inverse signal of the ith bit is selected from a_iDetermination of the signal a_i1 stands for negation，a_i0 stands for unchanged; the configuration of the bit signal selection element, the m-bit rearrangement element and the m-bit inverse signal selection element will realize the ith value asBy the p-th of an n-bit random source_n-i+1An output bit is generated, the ith value isIs inversely signaled bySignal determination; the method comprises the following specific steps:

p1, initialization configuration, using L₁Configuring n-bit random source using B₁Configuring bit signal selection elements usingConfiguring n-bit inverse signal selection elements usingConfiguring m-bit inverse signal selection elements usingConfiguring n-bit rearrangement elements usingConfiguring m-bit rearrangement elements usingD bit rearrangement elements are configured and marked as the optimal configuration mode of the corresponding elements;

p2, based on the configuration of step P1, the simulation obtains an initial computational accuracy MAE_minAnd assign it to MAE_prev；

P3, assignment i ═ 1;

p4, randomly generating oneAn integer r in the range of 1. ltoreq. r. ltoreq.l; using L_rConfiguring random sources, usingConfiguring n-bit reverse signal selection element, determining the configuration of bit signal selection element, m-bit rearrangement element and m-bit reverse signal selection element based on the configuration of n-bit rearrangement element and n-bit reverse signal selection element, and marking as B_x、Andthe other elements are configured in their optimal configuration;

p5, based on the configuration of the step P4, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration L of the n-bit random source, the bit signal selection element, the n-bit inverse signal selection element, the m-bit rearrangement element and the m-bit inverse signal selection element_r、B_x、Andupdating MAE_minIs MAE; i is i + 1;

p6 if i is less than or equal to 2ⁿJumping to the step P4, otherwise, proceeding to the next step;

p7, assignment i ═ 1;

p8, randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; using L_rConfiguring n-bit random sources usingConfiguring n-bit rearrangement elements, determining the configuration of the bit signal selection element, the m-bit rearrangement element and the m-bit inverse signal selection element based on the configuration of the n-bit rearrangement elements and the n-bit inverse signal selection element, and marking as B_x、Andthe other elements are configured in their optimal configuration;

p9, based on the configuration of the step P8, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration L of the n-bit random source, the bit signal selection element, the n-bit rearrangement element, the m-bit rearrangement element and the m-bit inverse signal selection element_r、B_x、Andupdating MAE_minIs MAE; i is i + 1;

p10, if i ≦ n! Jumping to the step P8, otherwise, proceeding to the next step;

p11, assignment i ═ 1;

p12, useConfiguring d-bit rearrangement elements, and configuring other elements in an optimal configuration mode;

p13, based on the configuration of the step P12, obtaining the calculation accuracy MAE of the circuit through analog simulation; if MAE < MAE_minUpdating the optimal configuration of the d-bit rearrangement elementUpdating MAE_minIs MAE; i is i + 1;

p14, if i ≦ d! Jumping to the step P12, otherwise, proceeding to the next step;

p15 if MAE_min＜MAE_prevUpdate the MAE_prevIs MAE_minJumping to step P3, otherwise ending the whole flow to obtain the final product of all elementsThe configuration is preferred.

Compared with the prior art, the invention has the following beneficial effects: the problem of high hardware overhead of the traditional univariate random circuit design is solved, the hardware overhead of the univariate random circuit is reduced by inserting a D trigger, and bit signal selection, rearrangement and anti-signal selection are applied to improve the calculation accuracy of the circuit; specifically, (1) by inserting a D trigger, the number of random sources and comparators is reduced, the hardware overhead of the circuit is greatly reduced, and 70-76% of hardware overhead reduction can be realized; (2) by adopting bit signal selection, rearrangement and inverse signal selection and applying two configuration algorithms for configuration, high circuit calculation accuracy is realized, which is similar to or better than that of the prior art.

[ description of the drawings ]

Fig. 1 is a schematic diagram of a conventional single variable random circuit structure.

Fig. 2 is a schematic diagram of a 10-bit rearrangement element.

FIG. 3 is a schematic diagram of a single variable random circuit structure employing rearranged elements.

Fig. 4 is a schematic diagram of a bit signal selection element.

FIG. 5 is a schematic diagram of an inverse signal selection element.

FIG. 6 is a schematic diagram of a single-variable random circuit with high computational accuracy and low hardware overhead.

FIG. 7 is a diagram of a conventional random circuit structure for implementing the univariate function 0.5cos (π x) + 0.5.

FIG. 8 is a schematic diagram of a random circuit structure for implementing the univariate function 0.5cos (π x) +0.5 with high computational accuracy and low hardware overhead.

[ detailed description ] embodiments

The invention is further described with reference to the following examples and with reference to the accompanying drawings.

Example 1

The embodiment realizes a single variable random circuit with high calculation accuracy and low hardware overhead and a configuration method thereof.

The embodiment of the single variable random circuit with high calculation accuracy and low hardware overhead aims to solve the problem of high hardware overhead of the traditional single variable random circuit design. The hardware overhead of the single-variable random circuit is reduced by inserting the D trigger, and meanwhile, the calculation accuracy of the circuit is improved by using bit signal selection, rearrangement and anti-signal selection, so that the single-variable random circuit architecture design with high calculation accuracy and low hardware overhead is realized.

FIG. 6 is a schematic diagram of a single-variable random circuit with high computational accuracy and low hardware overhead. As shown in fig. 6, the single variable random circuit with high computational accuracy and low hardware overhead only includes an n-bit random source, a comparator, D-1D flip-flops, a bit signal selection element, an n-bit rearrangement element, an m-bit rearrangement element, a D-bit rearrangement element, an n-bit inverse signal selection element, an m-bit inverse signal selection element, and a random computation core circuit, wherein the bit signal selection element, the rearrangement element, and the inverse signal selection element do not generate hardware overhead. The working principle of the single variable random circuit with high calculation accuracy and low hardware overhead is as follows:

1) generating a value ofBased on which, through D-1D flip-flops, further D-1 values are generated asA random bit stream of (a);

2) generating m values asAnd mutually independent random bit streams;

3) rearranging d values into d values by d-bit rearranging elementsThe input order of the random bit stream of (a);

4) the random computation core circuit computes and outputs a final result based on the d + m input random bit streams.

The embodiment provides two configuration methods for reasonably configuring a bit signal selection element, an n-bit rearrangement element, an m-bit rearrangement element, a d-bit rearrangement element, an n-bit inverse signal selection element and an m-bit inverse signal selection element. In this embodiment, a configuration method of a single-variable random circuit with high computational accuracy and low hardware overhead is provided, where the relevant definitions and assumptions are as follows:

1) for a bit signal selection element that selects m bits from n bits, the set of possible configurations is B, and the ith configuration is B_iIt is obvious that the number of elements of the B set isSuppose B₁Representing the selection of the 1 st to the mth bit outputs.

2) For a k-bit rearrangement element that rearranges k bits, the set of possible configurations is R^kThe ith configuration mode isIt is clear that R^kThe number of elements of the set is k! . Suppose thatAndrespectively representing inverting k bits and keeping k bits in the order as they are.

3) For k-bit inverted signal selecting element for selecting and inverting several bits from k bits, the set of possible configuration modes is C^kThe ith configuration mode isIs obviously C^kThe number of elements of the set is 2^k. Suppose thatRepresenting that the k bits are all inverted.

4) The set of the configuration modes of the n-bit random source is L, and the ith configuration mode is L_iLet the number of elements in the set be l.

The first configuration method of the univariate random circuit with high calculation accuracy and low hardware overhead in the embodiment is an iterative optimization method, and specifically comprises the following steps:

1) initial configuration, using L₁Configuring n-bit random source using B₁Configuring bit signal selection elements usingConfiguring n-bit inverse signal selection elements usingConfiguring m-bit inverse signal selection elements usingConfiguring n-bit rearrangement elements usingConfiguring m-bit rearrangement elements usingConfiguring a d-bit rearrangement element. Note the optimal arrangement of these arrangements to the corresponding elements.

2) Based on the configuration, the simulation obtains the initial calculation accuracy MAE_minAnd assign it to MAE_prev。

3) The assignment i is 1.

4) The assignment j equals 1.

5) The assignment k is 1.

6) Randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; using L_rConfiguring n-bit random source using B_iConfiguring bit signal selection elements usingConfiguring n-bit inverse signal selection elements usingAnd configuring the m-bit inverse signal selection element, and configuring other elements in an optimal configuration mode.

7) Based on the configuration, the calculation accuracy MAE of the circuit is obtained through analog simulation; if MAE < MAE_minUpdating the optimal configuration L of the n-bit random source, the bit signal selection element, the n-bit inverse signal selection element and the m-bit inverse signal selection element_r、B_i、Andupdating MAE_minIs MAE; k is k + 1.

8) If k is less than or equal to 2^mJump to 6), otherwise proceed to the next step.

9)j＝j+1。

10) If j is less than or equal to 2ⁿJump to 5), otherwise proceed to the next step.

11)i＝i+1。

12) If it is notJump to 4), otherwise proceed to next step.

13) The assignment i is 1.

14) Randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; randomly generating an integer k in the range of 1 ≦ k ≦ m! (ii) a Using L_rConfiguring n-bit random sources usingConfiguring n-bit rearrangement elements usingThe m-bit rearrangement elements are configured, and the other elements are configured in the optimal configuration mode.

15) Based on the configuration, the calculation accuracy MAE of the circuit is obtained through analog simulation; if MAE < MAE_minUpdating the optimal configuration of the n-bit random source, the n-bit rearrangement element and the m-bit rearrangement element_r，Andupdating MAE_minIs MAE; i ═ i + 1.

16) If i ≦ n! Jump to 14), otherwise proceed to the next step.

17) The assignment i is 1.

18) Randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; randomly generating an integer k in the range of 1 ≦ k ≦ n! (ii) a Using L_rConfiguring random sources, usingConfiguring n-bit rearrangement elements usingThe m-bit rearrangement elements are configured, and the other elements are configured in the optimal configuration mode.

19) Based on the configuration, the calculation accuracy MAE of the circuit is obtained through analog simulation; if MAE < MAE_minUpdating the optimal configuration of the n-bit random source, the n-bit rearrangement element and the m-bit rearrangement element_r，AndupdatingMAE_minIs MAE; i ═ i + 1.

20) If i is less than or equal to m! Jump to 18), otherwise proceed to the next step.

21) The assignment i is 1.

22) Use ofThe d-bit rearrangement elements are configured, and other elements are configured in the optimal configuration mode.

23) Based on the configuration, the calculation accuracy MAE of the circuit is obtained through analog simulation; if MAE < MAE_minUpdating the optimal configuration of the d-bit rearrangement elementUpdating MAE_minIs MAE; i ═ i + 1.

24) If i ≦ d! Jump to 22), otherwise proceed to the next step.

25) If MAE_min＜MAE_prevUpdate the MAE_prevIs MAE_minAnd jumping to 3), otherwise, ending the whole process, and obtaining the final optimal configuration mode of all the elements.

In this embodiment, a second configuration method of a single-variable random circuit with high calculation accuracy and low hardware overhead is a fast method, in which the configuration modes of a bit signal selection element, an m-bit rearrangement element and an m-bit inverse signal selection element are determined by the configuration modes of an n-bit rearrangement element and an n-bit inverse signal selection element. Assuming that the ith bit of the random number input by the comparator is the p-th bit of the n-bit random source through the n-bit rearrangement element and the n-bit inverse signal selection element_iAn output bit, and the inverse signal of the bit is selected from a_iSignal determination (a)_i1 stands for negation, a_i0 stands for constant). The configuration of the bit signal selection element, the m-bit rearrangement element and the m-bit inverse signal selection element will realize the ith value asIs composed of n bitsP th of random source_n-i+1An output bit is generated, the ith value isOf a random bit stream ofAnd (4) signal determination.

The second configuration method of the univariate random circuit with high calculation accuracy and low hardware overhead of the embodiment has the following concrete steps:

1) initial configuration, using L₁Configuring n-bit random source using B₁Configuring bit signal selection elements usingConfiguring n-bit inverse signal selection elements usingConfiguring m-bit inverse signal selection elements usingConfiguring n-bit rearrangement elements usingConfiguring m-bit rearrangement elements usingConfiguring a d-bit rearrangement element. Note the optimal arrangement of these arrangements to the corresponding elements.

2) Based on the configuration, the simulation obtains the initial calculation accuracy MAE_minAnd assign it to MAE_prev。

3) The assignment i is 1.

4) Randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; using L_rConfiguring random sources, usingConfiguring n-bit reverse signal selection element, determining the configuration of bit signal selection element, m-bit rearrangement element and m-bit reverse signal selection element based on the configuration of n-bit rearrangement element and n-bit reverse signal selection element, and marking as B_x、Andthe other elements are configured in their optimal configuration.

5) Based on the configuration, the calculation accuracy MAE of the circuit is obtained through analog simulation; if MAE < MAE_minUpdating the optimal configuration L of the n-bit random source, the bit signal selection element, the n-bit inverse signal selection element, the m-bit rearrangement element and the m-bit inverse signal selection element_r、B_x、Andupdating MAE_minIs MAE; i ═ i + 1.

6) If i is less than or equal to 2ⁿAnd jumping to 4), otherwise, carrying out the next step.

7) The assignment i is 1.

8) Randomly generating an integer r, wherein the range of r is more than or equal to 1 and less than or equal to l; using L_rConfiguring n-bit random sources usingConfiguring n-bit rearrangement elements, determining the configuration of the bit signal selection element, the m-bit rearrangement element and the m-bit inverse signal selection element based on the configuration of the n-bit rearrangement elements and the n-bit inverse signal selection element, and marking as B_x、Andthe other elements are configured in their optimal configuration.

9) Based on the configuration, the calculation accuracy MAE of the circuit is obtained through analog simulation; if MAE < MAE_minUpdating the optimal configuration L of the n-bit random source, the bit signal selection element, the n-bit rearrangement element, the m-bit rearrangement element and the m-bit inverse signal selection element_r、B_x、Andupdating MAE_minIs MAE; i ═ i + 1.

10) If i ≦ n! Jump to 8), otherwise proceed to the next step.

11) The assignment i is 1.

12) Use ofThe d-bit rearrangement elements are configured, and other elements are configured in the optimal configuration mode.

13) Based on the configuration, the calculation accuracy MAE of the circuit is obtained through analog simulation; if MAE < MAE_minUpdating the optimal configuration of the d-bit rearrangement elementUpdating MAE_minIs MAE; i ═ i + 1.

14) If i ≦ d! Jump to 12), otherwise proceed to the next step.

15) If MAE_min＜MAE_prevUpdate the MAE_prevIs MAE_minAnd jumping to 3), otherwise, ending the whole process, and obtaining the final optimal configuration mode of all the elements.

Compared with the prior art, the single variable random circuit with high calculation accuracy and low hardware overhead and the configuration method thereof have the technical effects that:

1) by inserting the D trigger, the number of random sources and comparators is reduced, the hardware overhead of the circuit is greatly reduced, and compared with the prior art, the hardware overhead reduction of 70-76% can be realized.

2) By adopting bit signal selection, rearrangement and inverse signal selection and applying two configuration algorithms for configuration, high circuit calculation accuracy is realized, and compared with the prior art, the circuit calculation accuracy is similar to or better than that in the prior art.

Example 2

The embodiment realizes a random circuit for realizing the univariate function 0.5cos (pi x) +0.5 with high calculation accuracy and low hardware overhead and a configuration method thereof. The random circuit and the configuration method thereof for realizing the univariate function 0.5cos (pi x) +0.5 with high calculation accuracy and low hardware overhead are realized based on the embodiment 1, wherein the univariate function is 0.5cos (pi x) + 0.5.

FIG. 7 is a diagram of a conventional random circuit structure for implementing the univariate function 0.5cos (π x) + 0.5. As shown in FIG. 7, the conventional random computational core routing documents for random Circuits implementing the univariate function 0.5cos (π x) +0.5 [ Xuesong Pen and Weikang Qian, "" Stostationary Circuit Synthesis by Cube Assignment, "" in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.37, No.12, pp.3109-3122, and dec.2018 ] require 4 valuesWith a random bit stream input of 6 valuesA random bit stream input of (a); n is 8; to generate 10 random bit streams, conventional random circuits that implement the univariate function 0.5cos (π x) +0.5 employ 4 random sources of 8 bits, 4 comparators, and 1 random source of 6 bits. In this embodiment, a linear feedback shift register is used as a random source. The conventional 8-bit linear feedback shift register for a random circuit implementing a univariate function of 0.5cos (π x) +0.5 generates an 8-bit random binary number per clock,it is compared with the input X in a comparator, which outputs a 1 if the random binary number is less than X, and outputs a 0 as the valueThe random bit stream of (2) is input to the circuit. The 6-bit random source generates a 6-bit 0/1 signal as 6 values per clockThe random bit stream of (2) is input to the circuit. After 255 clocks, the result of outputting random bit stream is summed and divided by 256, and the calculation result of the random circuit for traditionally realizing univariate function 0.5cos (pi x) +0.5 is obtained

FIG. 8 is a schematic diagram of a random circuit structure for implementing the univariate function 0.5cos (π x) +0.5 with high computational accuracy and low hardware overhead. As shown in fig. 8, the univariate function of the random circuit for realizing the univariate function 0.5cos (pi x) +0.5 with high calculation accuracy and low hardware overhead is 0.5cos (pi x) +0.5, and only an 8-bit linear feedback shift register, a bit signal selection element, an 8-bit rearrangement element, a 6-bit rearrangement element, a 4-bit rearrangement element, an 8-bit inverse signal selection element, a 6-bit inverse signal selection element, a comparator and 3D flip-flops are applied, that is, 4 values are generatedWith a random bit stream input of 6 valuesIs input to the random bit stream. In this embodiment, the output of the linear feedback shift register of the random circuit for realizing the univariate function 0.5cos (π X) +0.5 with high calculation accuracy and low hardware overhead is recombined with the 8-bit inverse signal selection element through the 8-bit rearrangement element, and after comparing with the input X, a value ofA random bit stream of (a); the random bit stream passes through 3D flip-flops to generate 3 other valuesA random bit stream of (a); these 4 values areThe random bit stream is input to a random computation core circuit through a 4-bit rearrangement element and then input to a random computation core circuit through corresponding input ports. In addition, in this embodiment, the bit signal selecting element of the random circuit for realizing the univariate function 0.5cos (π x) +0.5 with high calculation accuracy and low hardware overhead selects 6 bit signals from the 8-bit output of the linear feedback shift register, and then the 6 bit signals are recombined by the 6-bit rearrangement element and the 6-bit inverse signal selecting element, and finally 6 values are generated asThe random bit stream of (2) is input to the circuit. In terms of hardware cost, the random circuit for calculating the univariate function 0.5cos (pi x) +0.5, which is implemented by the embodiment, has a circuit area of 93.72 square microns, which is much smaller than 323.65 square microns of the circuit area of the conventional design, and the area is reduced by 71%. The Standard Cell Library used here is Nannate Standard45nm Cell Library [ https: org/open-cell-library/]. In terms of calculation accuracy, the average absolute value error of the circuit implemented in the embodiment is 0.0034 and 0.0037 under the configuration of the iterative optimization method and the fast method, respectively. Conventional designs were configured based on the same time, with corresponding mean absolute errors of 0.0030 and 0.0036. It is clear that the computational accuracy of the two designs is very similar.

Therefore, through the optimal design and reasonable configuration of the single-variable random circuit with high calculation accuracy and low hardware overhead and the configuration method thereof, the hardware overhead of the single-variable random circuit is reduced on a large scale on the basis of keeping the calculation accuracy still high, and the high calculation accuracy and the low hardware overhead are realized. Compared with the traditional design, the single-variable random circuit with high calculation accuracy and low hardware overhead and the configuration method thereof have strong application effect and application prospect.

It will be understood by those skilled in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing associated hardware, and the program may be stored in any computer-readable storage medium, where the storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and additions can be made without departing from the principle of the present invention, and these should also be considered as the protection scope of the present invention.