阅读说明：本技术 Io pad金属结构版图及其设计方法 (IO PAD metal structure layout and design method thereof ) 是由 熊剑锋 于 2021-08-25 设计创作，主要内容包括：本发明公开了一种IO PAD金属结构版图及其设计方法,包括第一金属结构、第二金属结构、第三金属结构、第四金属结构、背栅和接触孔,第一金属结构位于第一注入区和第二注入区,第二金属结构位于第一注入区和第二注入区内,在同一注入区内第二金属结构与第一金属结构沿第一方向间隔排布,第三金属结构位于第一接入点区域、第二接入点区域和第三接入点区域内,第三金属结构与第一金属结构连接,第一接入点区域、第一注入区、第二接入点区域、第二注入区和第三接入点区域沿第二方向依次排布,背栅设置在第一金属结构的底部,接触孔设置在第一金属结构和第二金属结构下方。本发明能够兼容多种封装打线需求,提高设计效率。(The invention discloses an IO PAD metal structure layout and a design method thereof, comprising a first metal structure, a second metal structure, a third metal structure, a fourth metal structure, a back gate and a contact hole, wherein the first metal structure is positioned in a first injection region and a second injection region, the second metal structure is positioned in the first injection region and the second injection region, the second metal structure and the first metal structure are arranged at intervals in the same injection region along a first direction, the third metal structure is located in a first access point region, a second access point region and a third access point region, the third metal structure is connected with the first metal structure, the first access point region, the first injection region, the second access point region, the second injection region and the third access point region are sequentially arranged along a second direction, the back gate is arranged at the bottom of the first metal structure, and the contact hole is arranged below the first metal structure and the second metal structure. The invention can be compatible with various packaging and routing requirements and improve the design efficiency.)

1. An IO PAD metal structure layout, comprising:

a first metal structure (101) located in the first implant region (201) and the second implant region (202);

the second metal structures (102) are positioned in the first injection region (201) and the second injection region (202), and the second metal structures (102) and the first metal structures (101) are arranged at intervals along a first direction in the same injection region;

a third metal structure (103) located in a first access point region (203), a second access point region (204), and a third access point region (205), where the third metal structure (103) is connected to the first metal structure (101), and the first access point region (203), the first injection region (201), the second access point region (204), the second injection region (202), and the third access point region (205) are sequentially arranged along a second direction;

a back gate disposed at a bottom of the first metal structure (101);

a contact hole disposed below the first metal structure (101) and the second metal structure (102).

2. The IO PAD metal structure layout according to claim 1, further comprising a fourth metal structure (106), wherein the fourth metal structure (106) is disposed in the first implanted region (201) and the second implanted region (202), and is connected to the second metal structure (102).

3. The IO PAD metal structure layout according to claim 1, wherein the metal levels of the first metal structure (101) and the second metal structure (102) are both 3 layers.

4. The IO PAD metal structure layout according to claim 1 or 3, wherein the metal level of the third metal structure (103) is 2 levels.

5. The IO PAD metal structure layout according to claim 1 or 2, further comprising a windowed metal connected with a metal structure within at least one of the first access point region (203), the second access point region (204) or the third access point region (205).

6. The IO PAD metal structure layout of claim 5, wherein the number of said windowing metals is 1, 2 or 3.

7. A design method of an IO PAD metal structure layout is characterized by comprising the following steps:

drawing the IO PAD metal structure layout of claim 1;

determining the number and the positions of windows according to the packaging routing requirements;

determining a layout scheme according to the number and the positions of the windows;

distributing the metal levels of each metal structure under the condition that the metal levels can meet the layout scheme;

and carrying out layout wiring and verification under the condition of meeting the ESD design requirement.

8. The design method of the IO PAD metal structure layout according to claim 7, wherein before determining the number and position of the windows according to the package wire bonding requirement, the method further comprises the steps of: and performing LVS verification and DRC verification on the IO PAD metal structure layout in a virtual connection mode.

9. The design method of IO PAD metal structure layout according to claim 7 or 8, wherein the layout scheme includes selecting one or two of the first access point region (203), the second access point region (204) and the third access point region (205) as windowing access points.

10. The method for designing the IO PAD metal structure layout according to claim 7, wherein the number of the windows is 1, 2 or 3.

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to an IO PAD metal structure layout and a design method thereof.

Background

In a chip, an IO PAD is a short for Input/Output PAD (Input/Output PAD), and is a chip pin processing module, which can process a signal at a chip pin and send the processed signal to the inside of the chip, and can process a signal Output from the inside of the chip and send the processed signal to the chip pin. A core structure of an ESD protection portion of a common IO PAD circuit is shown in fig. 1, which includes a PMOS transistor and an NMOS transistor, where a source terminal and a substrate of the PMOS transistor are connected to a power supply VDD, a drain terminal is connected to IO, a source terminal and a substrate of the NMOS transistor are grounded VSS, and the drain terminal is connected to IO. In the chip design process, the layout design of the IO PAD and the package routing requirement affect each other, and the layout of the IO PAD also affects the design of other part analog layouts and the design of a digital PR (Place Route), so that the layout of the IO PAD is required not to allow the frame of the layout to be changed after the layout is completed. In the existing design method of the IO PAD metal structure layout, if the situation that the packaging requirements cannot be met occurs in the packaging evaluation stage, the packaging routing scheme or the IO PAD metal structure layout may need to be modified. According to the difference of the modification range, the workload is increased by 1 day to 1 month, thereby causing the design inefficiency.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the IO PAD metal structure layout and the design method thereof provided by the invention can be compatible with various packaging and routing requirements, and the design efficiency is improved.

On the first hand, the IO PAD metal structure layout comprises a first metal structure, a second metal structure and a third metal structure, wherein the first metal structure is positioned in a first injection region and a second injection region; the second metal structures are positioned in the first injection region and the second injection region, and the second metal structures and the first metal structures are arranged at intervals along a first direction in the same injection region; the third metal structure is positioned in a first access point area, a second access point area and a third access point area, the third metal structure is connected with the first metal structure, and the first access point area, the first injection area, the second access point area, the second injection area and the third access point area are sequentially arranged along a second direction; a back gate disposed at a bottom of the first metal structure; a contact hole disposed under the first metal structure and the second metal structure.

The IO PAD metal structure layout provided by the embodiment of the invention at least has the following beneficial effects:

the IO PAD metal structure layout has strong compatibility, can meet various windowing layout schemes, has less changed content and short adjustment time if the packaging routing scheme needs to be changed in the chip design process, and is favorable for improving the design efficiency.

According to some embodiments of the invention, the IO PAD metal structure layout further includes a fourth metal structure disposed in the first and second implanted regions and connected to the second metal structure.

According to some embodiments of the invention, the metal levels of the first metal structure and the second metal structure are both 3 layers.

According to some embodiments of the invention, the metal level of the third metal structure is 2 layers.

According to some embodiments of the invention, the IO PAD metal structure layout further comprises a windowing metal, the windowing metal being connected with a metal structure in at least one of the first access point region, the second access point region, or the third access point region by a metal.

According to some embodiments of the invention, the number of windowed metal is 1, 2 or 3.

In a second aspect, the method for designing the layout of the IO PAD metal structure according to the embodiment of the present invention includes the steps of:

drawing the IO PAD metal structure layout;

determining the number and the positions of windows according to the packaging routing requirements;

determining a layout scheme according to the number and the positions of the windows;

distributing the metal levels of each metal structure under the condition that the metal levels can meet the layout scheme;

and carrying out layout wiring and verification under the condition of meeting the ESD design requirement.

The design method of the IO PAD metal structure layout provided by the embodiment of the invention at least has the following beneficial effects: the IO PAD metal structure layout has strong compatibility, can meet various windowing layout schemes, has less change content and short adjustment time if the packaging routing scheme needs to be changed in the chip design process, and is favorable for improving the design efficiency.

According to some embodiments of the present invention, before determining the number and the position of the windows according to the package routing requirement, the method further comprises the steps of: and performing LVS verification and DRC verification on the IO PAD metal structure layout in a virtual connection mode.

According to some embodiments of the invention, the layout scheme comprises selecting one or two of the first access point region, the second access point region and the third access point region as windowing access points.

According to some embodiments of the invention, the number of fenestrations is 1, 2 or 3.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a schematic diagram of a core structure of an ESD protection portion of a conventional IO PAD circuit;

FIG. 2 is a layout of an IO PAD metal structure according to an embodiment of the present invention;

fig. 3 is a schematic diagram of an access point region of the IO PAD metal structure layout shown in fig. 2;

FIGS. 4-7 are schematic diagrams of windowed layout schemes of an IO PAD metal structure layout according to an embodiment of the present invention;

fig. 8 is a schematic cross-sectional structure diagram of windowing metal of the IO PAD metal structure layout according to the embodiment of the present invention;

fig. 9 is a flowchart of the steps of the design method of the layout of the IO PAD metal structure.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

In the description of the present invention, "a plurality" means one or more, "a plurality" means two or more, and greater than, less than, more than, etc. are understood as excluding the present number, and "greater than", "lower than", "inner", etc. are understood as including the present number. If the description of "first", "second", etc. is used for the purpose of distinguishing technical features, it is not intended to indicate or imply relative importance or to implicitly indicate the number of indicated technical features or to implicitly indicate the precedence of the indicated technical features.

In the description of the present invention, unless otherwise explicitly limited, the terms "disposed," "connected," and the like are to be construed broadly, and those skilled in the art can reasonably determine the specific meaning of the above-mentioned terms in the present invention by combining the detailed contents of the technical solutions.

Example 1

Referring to fig. 2 and fig. 3, the present embodiment discloses an IO PAD metal structure layout, including a first metal structure 101, a second metal structure 102, a third metal structure 103, a fourth metal structure 106, a back gate, and a contact hole, for convenience of understanding, taking the core structure of the ESD protection portion in the IO PAD circuit shown in fig. 1 as an example, where fig. 2 is a layout of the core structure of the ESD protection portion in the IO PAD circuit shown in fig. 1. In the layout, the first metal structure 101 and the second metal structure 102 are both located in a first implantation region 201 and a second implantation region 202, wherein the first implantation region 201 is a P implantation region and the second implantation region 202 is an N implantation region, or the first implantation region 201 is an N implantation region and the second implantation region 202 is a P implantation region. The second metal structures 102 and the first metal structures 101 are arranged at intervals along the first direction in the same implantation region, and the third metal structures 103 are located in the first access point region 203, the second access point region 204 and the third access point region 205. The third metal structure 103 is connected to the first metal structure 101, the first access point region 203, the first injection region 201, the second access point region 204, the second injection region 202, and the third access point region 205 are sequentially arranged along a second direction, and the first direction and the second direction of this embodiment are perpendicular to each other in the layout plane. The back gate is disposed at the bottom of the first metal structure 101 and the contact hole is disposed below the first metal structure 101 and the second metal structure 102.

In the embodiment, windowing (window) access points are reserved in the first access point region 203, the second access point region 204, and the third access point region 205 of the layout of the IO PAD metal structure, that is, 3 windowing access points are reserved in total, wherein, in the chip design process, once the metal level meets the ESD protection requirement, the heights of the fourth metal structure 106 and the third metal structure 103 located in the first access point region 203 and the third access point region 205 may be adjusted, so that the metal structures are optimized, that is, the occupied area is relatively small, the overcurrent capacity is relatively large, and the ESD resistance is relatively small. When windowing design is carried out, reference can be made to fig. 4-7 for a windowing layout scheme, arrows in the drawings indicate connection lines from windowing to access points, the number of layouts is as many as 11, the number of windowing is as many as 3, and the number of windowing access points is as many as 3.

Referring to fig. 3, in some examples, the IO PAD metal structure layout further includes a fourth metal structure 106, and the fourth metal structure 106 is disposed in the first and second implantation regions 201 and 202 and connected to the second metal structure 102. In the chip design process, if the packaging and routing scheme needs to be changed, only the fourth metal structure 106 needs to be adjusted and the window is opened, so that the content of the change is less, the adjustment time is short, and the design efficiency is favorably improved. Two windows with large distance can be opened on an IO PAD, for example, as shown in fig. 6 (d), assuming that the two windows are window a and window B, respectively, wire bonding can be performed on window a, and window B is idle, so as to satisfy the packaging scheme of the first chip, and wire bonding can be performed on window a and window B, so as to satisfy the packaging scheme of the second chip. If the layout scheme shown in (d) of fig. 6 is used at multiple positions of the chip, multiple chip packaging schemes can be compatible finally, so that one chip is multipurpose, the chip design cost is greatly reduced, the use range of the chip is increased, and the packaging diversity is favorably realized. In addition, referring to fig. 4 to 7, a plurality of windows are opened on the IO PAD, one of which is used for testing, which can facilitate later chip testing and verification, and is beneficial to improving the efficiency of chip testing and verification.

The IO PAD metal structure layout of the embodiment has strong applicability, and the structure can be applicable as long as the total number of metal layers is greater than or equal to four layers. For example, fig. 4 (a), 5 (c), and 6 (d) may be used when the metal layer has only four layers. In some examples, the metal levels of the first metal structure 101 and the second metal structure 102 are both 3 layers, that is, the first metal structure 101 and the second metal structure 102 are connected in parallel by a first layer metal (i.e., the M1 layer), a second layer metal (i.e., the M2 layer), and a third layer metal (i.e., the M3 layer). The length of the second metal structure 102 is equal to the finger width (finger width) of the MOS transistor, and the width is the width capable of accommodating the metal hole; the length of the first metal structure 101 is equal to the finger width of the MOS transistor, and the width is equal to the pitch of the second metal structure 102 minus twice the minimum metal pitch. The metal level of the third metal structure 103 is 2 layers, wherein the third metal structure 103 is formed by connecting the second layer of metal (i.e., the M2 layer) and the third layer of metal (i.e., the M3 layer) in parallel, and the fourth metal structure 106 is formed by at least two middle layers or one top layer of metal. In this embodiment, the third metal structures 103 connect the first metal structures 101 in parallel, and provide a windowing access point, and the width of the third metal structures 103 at the windowing access point is required to meet the ESD design requirements. It should be noted that the first metal structure 101, the second metal structure 102, and the third metal structure 103 are all basic metal structures, and the highest metal level used is M3 level.

Referring to fig. 4 to 7, the IO PAD metal structure layout further includes a windowing metal, and the windowing metal is connected to a metal structure in at least one of the first access point region 203, the second access point region 204, or the third access point region 205 through a metal. Wherein, the number of the windowing metal is 1, 2 or 3. The layout of the IO PAD metal structure of this embodiment can be compatible with various layout schemes for windowing, and has high compatibility, where, referring to fig. 8, the windowing metal includes a top metal 301 and a next top metal 302, and the top metal 301 and the next top metal 302 are connected through a metal hole 303.

Example 2

Referring to fig. 9, an embodiment of the present invention discloses a method for designing an IO PAD metal structure layout, including the steps of:

s100, please refer to fig. 2, drawing an IO PAD metal structure layout, where a specific structure of the layout may refer to embodiment 1, which is not described again in this embodiment; it should be noted that, when the layout of the IO PAD metal structure is drawn, the fourth metal structure 106 is not drawn temporarily, and is drawn after the layout scheme is determined subsequently.

S200, determining the number and the positions of the windows according to the packaging and routing requirements.

It should be noted that, the number and the positions of the windows are determined according to the package routing requirement, and the method further includes the following steps: the IO PAD metal structure Layout can be verified through verification of LVS (Layout Vs simulation) and DRC (Design road Check) in a virtual connection mode on the IO PAD metal structure Layout, and errors of Layout Design are reduced.

And S300, determining a layout scheme according to the number and the positions of the windows.

Referring to fig. 4 to 7, the layout scheme includes selecting one or two of the first access point region 203, the second access point region 204, and the third access point region 205 as windowing access points, where the number of the windowing access points is 1, 2, or 3, so that various windowing layout schemes can be implemented, and the layout scheme has high compatibility and can implement packaging diversity.

S400, distributing the metal levels of the metal structures under the condition that the metal levels can meet the layout scheme, returning to the step S300 to re-determine the layout scheme if the metal levels cannot meet the layout scheme, and only adjusting the fourth metal structure 106 and windowing, so that the modification content is less, the modification time is short, and the design efficiency is improved.

S500, carrying out layout wiring and verification under the condition of meeting the ESD design requirement, and returning to the step S400 to redistribute the metal level of the metal structure when the ESD design requirement is not met.

The IO PAD metal structure layout has strong compatibility, can meet various windowing layout schemes, only needs to adjust the fourth metal structure 106 and window if a packaging routing scheme needs to be changed in the chip design process, has less change content and short adjustment time, and is beneficial to improving the design efficiency. The traditional design method needs to spend 1-2 weeks before package evaluation, and the layout modification needs to spend 1-2 weeks after package evaluation, namely, 2-4 weeks in total, while the design method of the embodiment spends 1-2 weeks in IO PAD layout design, and the total time is about half of the time used by the traditional design method.

Because the IO PAD metal structure layout can be compatible with the packaging and routing requirements, and the packaging and routing evaluation is completed before the IO PAD metal structure layout is designed, the final IO PAD metal structure layout design can meet the optimal packaging and routing scheme, and the optimal packaging and routing scheme can be reserved. In addition, the IO PAD metal structure layout of this embodiment remains unchanged in each subsequent step from the drawing, and only the fourth metal structure 106 and the windowing position need to be adjusted, so that the risk of major modification of the IO PAD metal structure layout is reduced, and the design efficiency is improved. Even after the IO PAD metal structure layout is completed, the change of the packaging routing scheme can not cause the change of the frame of the IO PAD metal structure layout.

It is worth to be noted that, in the whole chip design process, the design method of the embodiment does not limit the design work of the packaging routing, does not affect the design of the analog layout near the IO PAD metal structure layout, and does not affect the design work of the digital PR, thereby achieving the effect of small related impact.

The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.