阅读说明：本技术 集成芯片及其制备方法 (Integrated chip and preparation method thereof ) 是由 任奇伟 左丰国 刘琦 于 2021-09-02 设计创作，主要内容包括：本申请提供一种集成芯片及其制备方法。该集成芯片包括可编程门阵列单元,集成有第一键合区域和与第一键合区域连接的可编程门阵列；第一动态存储阵列单元集成有第二键合区域和与第二键合区域连接的第一动态存储阵列；可编程门阵列单元和第一动态存储阵列单元通过第一键合区域和第二键合区域层叠键合,可编程门阵列通过第一键合区域和第二键合区域连接第一动态存储阵列单元；测试模块集成于可编程门阵列单元或第一动态存储阵列单元,并连接可编程门阵列或第一动态存储阵列,用于对第一动态存储阵列进行测试、修复。该集成芯片不仅具有逻辑可编程的能力,且有效增加了互连数量；同时可为逻辑部分提供高带宽、高能效比、低延时的大容量存储访问。(The application provides an integrated chip and a preparation method thereof. The integrated chip comprises a programmable gate array unit, a first bonding region and a programmable gate array connected with the first bonding region are integrated; the first dynamic storage array unit is integrated with a second bonding region and a first dynamic storage array connected with the second bonding region; the programmable gate array unit and the first dynamic storage array unit are in laminated bonding through a first bonding region and a second bonding region, and the programmable gate array is connected with the first dynamic storage array unit through the first bonding region and the second bonding region; the test module is integrated in the programmable gate array unit or the first dynamic storage array unit, connected with the programmable gate array or the first dynamic storage array and used for testing and repairing the first dynamic storage array. The integrated chip not only has the logic programmable capability, but also effectively increases the interconnection quantity; meanwhile, the high-bandwidth, high-energy-efficiency and low-delay mass storage access can be provided for the logic part.)

1. An integrated chip, comprising:

the programmable gate array unit is integrated with a first bonding region and a programmable gate array connected with the first bonding region;

the first dynamic memory array unit is integrated with a second bonding region and a first dynamic memory array connected with the second bonding region; the programmable gate array unit and the first dynamic memory array unit are bonded in a stacking mode through the first bonding region and the second bonding region, and the programmable gate array unit is connected with the first dynamic memory array unit through the first bonding region and the second bonding region;

the test module is integrated in the programmable gate array unit or the first dynamic storage array unit, and is connected with the programmable gate array or the first dynamic storage array and used for testing and repairing the first dynamic storage array.

2. The integrated chip of claim 1, wherein the test module is integrated with the programmable gate array unit; the test module is connected with the first bonding region and further connected with the first dynamic storage array and used for testing and repairing the first dynamic storage array.

3. The integrated chip of claim 2, wherein the programmable gate array cell comprises: the device comprises a first physical interface module and a test interface module;

the first physical interface module is connected with the first bonding region, the test module is connected with the first physical interface module,

the test interface module is connected with the test module and used for being connected with a test bus, and the test module tests and repairs the first dynamic storage array according to a test signal received by the test bus.

4. The integrated chip of claim 3, wherein the programmable gate array cell further comprises: the device comprises a multipath selection module and a control module;

the multi-path selection module is connected with the first physical interface module, and the control module and the test module are connected with the multi-path selection module.

5. The integrated chip of claim 1, wherein the test module is integrated with the first dynamic memory array unit; the test module is connected with the second bonding region and further connected with the first dynamic storage array and used for testing and repairing the first dynamic storage array.

6. The integrated chip of claim 5, wherein the programmable gate array cell comprises: the device comprises a first physical interface module and a test interface module;

the first physical interface module is connected with the first bonding area, the test module is connected with the second bonding area, the test interface module is connected with the first physical interface module and is used for being connected with a test bus, and the test module tests and repairs the first dynamic storage array according to a test signal received by the test bus.

7. The integrated chip of claim 5, wherein the first dynamic memory array unit comprises: a test interface module;

the test module is connected with the second bonding region and the test interface module, the test interface module is used for connecting a test bus, and the test module tests and repairs the first dynamic storage array according to a test signal received by the test bus.

8. The integrated chip of any one of claims 1 to 7, wherein the programmable gate array unit comprises: a protection module and an interface module;

the protection module is connected with the first bonding region and the interface module, the interface module is used for receiving external signals and/or outputting signals of the first dynamic storage array, and the protection module is used for protecting the programmable gate array unit so as to prevent the programmable gate array unit from being damaged by the external signals.

9. The integrated chip of claim 8, wherein the first dynamic memory array unit comprises: the first driving module, the first level conversion module, the second level conversion module and the first buffer;

the input end of the first driving module is connected with the first level conversion module, and the output end of the first driving module is connected with the second bonding area;

the input end of the first buffer is connected with the second bonding area, and the output end of the first buffer is connected with the second level conversion module.

10. The integrated chip of any one of claims 1 to 7, wherein the programmable gate array unit comprises: the second driving module, the second buffer, the third level conversion module and the fourth level conversion module;

the input end of the second driving module is connected with the third level conversion module, and the output end of the second driving module is connected with the first bonding area;

the input end of the second buffer is connected with the first bonding area, and the output end of the second buffer is connected with the fourth level conversion module.

11. The integrated chip of claim 10, wherein the first dynamic memory array unit comprises: a third driving module and a third buffer;

the output end of the third driving module is connected with the second bonding area, and the input end of the third buffer is connected with the second bonding area.

12. The integrated chip of claim 1, wherein the first dynamic memory array unit includes at least two layers, at least two layers of the first dynamic memory array unit are stacked and bonded on one side of the programmable gate array unit, and two adjacent first dynamic memory array units are stacked and bonded through respective second bonding regions.

13. A method for manufacturing an integrated chip, comprising:

preparing a programmable gate array unit and a first dynamic storage array unit, wherein a test unit is prepared on the programmable gate array unit or the first dynamic storage array unit; the first surface of the programmable gate array unit comprises a first protective layer, and the first surface of the first dynamic storage array unit comprises a second protective layer;

removing the first protective layer and the second protective layer;

preparing a first bonding area on the first surface of the programmable gate array unit, and preparing a second bonding area on the first surface of the first dynamic storage array unit;

and bonding the first bonding region and the second bonding region, and further bonding and connecting the programmable gate array unit and the first dynamic storage array unit.

14. The method of claim 13, wherein the step of forming a first bonding region on the first surface of the programmable gate array unit and a second bonding region on the first surface of the first dynamic memory array unit comprises:

preparing a first dielectric layer on the first surface of the programmable gate array unit, and preparing a second dielectric layer on the first surface of the first dynamic storage array unit;

preparing a first through hole on the first dielectric layer, and preparing a second through hole on the second dielectric layer;

wherein the first through hole is aligned with the second through hole when the first bonding area is bonded with the second bonding area.

15. The method of manufacturing an integrated chip of claim 13, further comprising:

preparing a second dynamic storage array unit; the first surface of the second dynamic storage array unit comprises a third protective layer;

removing the third protective layer;

preparing a third bonding area on the first surface of the second dynamic storage array unit, and preparing a fourth bonding area on the second surface of the first dynamic storage array unit;

and bonding the third bonding region and the fourth bonding region, and further bonding and connecting the first dynamic storage array unit and the second dynamic storage array unit.

16. The method for manufacturing an integrated chip according to claim 15, wherein the step of manufacturing a third bonding region on the first surface of the second dynamic memory array unit and a fourth bonding region on the second surface of the first dynamic memory array unit comprises:

preparing a third dielectric layer on the first surface of the second dynamic memory array unit, and preparing a fourth dielectric layer on the second surface of the first dynamic memory array unit;

preparing a third via on the third dielectric layer and a fourth via on the fourth dielectric layer;

wherein the third through hole is aligned with the fourth through hole when the third bonding region is bonded with the fourth bonding region.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to an integrated chip and a preparation method thereof.

Background

With the rapid increase of the application computing scale, the bandwidth and power consumption overhead of memory access become important factors limiting the development of the scaled computing circuit.

Disclosure of Invention

According to the integrated chip and the preparation method thereof, the integrated chip can realize high-bandwidth, low-power consumption and low-delay large-capacity storage access of storage access.

In order to solve the technical problem, the application adopts a technical scheme that: an integrated chip is provided. The integrated chip comprises a programmable gate array unit, a first dynamic storage array unit and a test module; the programmable gate array unit is integrated with a first bonding area and a programmable gate array connected with the first bonding area; the first dynamic storage array unit is integrated with a second bonding region and a first dynamic storage array connected with the second bonding region; the programmable gate array unit and the first dynamic storage array unit are in laminated bonding through a first bonding region and a second bonding region, and the programmable gate array is connected with the first dynamic storage array unit through the first bonding region and the second bonding region; the test module is integrated in the programmable gate array unit or the first dynamic storage array unit, and the test module is connected with the programmable gate array or the first dynamic storage array and is used for testing and repairing the first dynamic storage array.

The testing module is integrated in the programmable gate array unit; the test module is connected with the first bonding region and further connected with the first dynamic storage array and used for testing and repairing the first dynamic storage array.

Wherein, the gate array unit able to programme includes: the device comprises a first physical interface module and a test interface module; the first physical interface module is connected with the first bonding area, the testing module is connected with the first physical interface module, the testing interface module is connected with the testing module and used for being connected with the testing bus, and the testing module tests and repairs the first dynamic storage array according to a testing signal received by the testing bus.

Wherein, the gate array unit able to programme still includes: the device comprises a multipath selection module and a control module;

the multi-path selection module is connected with the first physical interface module, and the control module and the test module are connected with the multi-path selection module.

The test module is integrated in the first dynamic storage array unit; the test module is connected with the second bonding region and further connected with the first dynamic storage array and used for testing and repairing the first dynamic storage array.

Wherein, the gate array unit able to programme includes: the device comprises a first physical interface module and a test interface module; the first physical interface module is connected with the first bonding area, the testing module is connected with the second bonding area, the testing interface module is connected with the first physical interface module and used for being connected with the testing bus, and the testing module tests and repairs the first dynamic storage array according to the testing signal received by the testing bus.

Wherein the first dynamic memory array unit comprises: a test interface module; the test module is connected with the second bonding area and the test interface module, the test interface module is used for being connected with the test bus, and the test module tests and repairs the first dynamic storage array according to the test signals received by the test bus.

Wherein, the gate array unit able to programme includes: a protection module and an interface module; the protection module is connected with the first bonding area and the interface module, the interface module is used for receiving external signals and/or outputting signals of the first dynamic storage array, and the protection module is used for protecting the programmable gate array unit so as to prevent the programmable gate array unit from being damaged by the external signals.

Wherein the first dynamic memory array unit comprises: the first driving module, the first level conversion module, the second level conversion module and the first buffer; the input end of the first driving module is connected with the first level conversion module, and the output end of the first driving module is connected with the second bonding area; the input end of the first buffer is connected with the second bonding area, and the output end of the first buffer is connected with the second level conversion module.

Wherein, the gate array unit able to programme includes: the second driving module, the second buffer, the third level conversion module and the fourth level conversion module; the input end of the second driving module is connected with the third level conversion module, and the output end of the second driving module is connected with the first bonding area; the input end of the second buffer is connected with the first bonding area, and the output end of the second buffer is connected with the fourth level conversion module.

Wherein the first dynamic memory array unit comprises: a third driving module and a third buffer; the output end of the third driving module is connected with the second bonding area, and the input end of the third buffer is connected with the second bonding area.

The first dynamic storage array unit comprises at least two layers, the at least two layers of first dynamic storage array units are in laminated bonding on one side of the programmable gate array unit, and two adjacent first dynamic storage array units are in laminated bonding connection through respective second bonding areas.

In order to solve the above technical problem, another technical solution adopted by the present application is: a method for fabricating an integrated chip is provided. The method comprises the following steps: preparing a programmable gate array unit and a first dynamic storage array unit, wherein a test unit is prepared on the programmable gate array unit or the first dynamic storage array unit; the first surface of the programmable gate array unit comprises a first protective layer, and the first surface of the first dynamic storage array unit comprises a second protective layer; removing the first protective layer and the second protective layer; preparing a first bonding area on the first surface of the programmable gate array unit, and preparing a second bonding area on the first surface of the first dynamic storage array unit; and bonding the first bonding region and the second bonding region, and further bonding and connecting the programmable gate array unit and the first dynamic storage array unit.

The steps of preparing a first bonding region on the first surface of the programmable gate array unit and preparing a second bonding region on the first surface of the first dynamic memory array unit include: preparing a first dielectric layer on the first surface of the programmable gate array unit, and preparing a second dielectric layer on the first surface of the first dynamic storage array unit; preparing a first through hole on the first dielectric layer and preparing a second through hole on the second dielectric layer; wherein the first through hole is aligned with the second through hole when the first bonding region is bonded with the second bonding region.

Wherein, still include: preparing a second dynamic storage array unit; the first surface of the second dynamic memory array unit comprises a third protective layer; removing the third protective layer; preparing a third bonding area on the first surface of the second dynamic storage array unit and preparing a fourth bonding area on the second surface of the first dynamic storage array unit; and bonding the third bonding region and the fourth bonding region, and further bonding and connecting the first dynamic storage array unit and the second dynamic storage array unit.

The step of preparing a third bonding region on the first surface of the second dynamic memory array unit and a fourth bonding region on the second surface of the first dynamic memory array unit comprises: preparing a third dielectric layer on the first surface of the second dynamic memory array unit, and preparing a fourth dielectric layer on the second surface of the first dynamic memory array unit; preparing a third through hole on the third dielectric layer and preparing a fourth through hole on the fourth dielectric layer; and when the third bonding area and the fourth bonding area are bonded, the third through hole and the fourth through hole are aligned.

The integrated chip and the preparation method thereof provided by the application enable a programmable gate array unit to be integrated with a first bonding area and a programmable gate array connected with the first bonding area by arranging the programmable gate array unit; meanwhile, the first dynamic storage array unit is integrated with a second bonding region and a first dynamic storage array connected with the second bonding region by arranging the first dynamic storage array unit, and the programmable gate array unit and the first dynamic storage array unit are bonded in a stacking mode through the first bonding region and the second bonding region, so that the programmable gate array of the programmable gate array unit can be connected with the first dynamic storage array unit through the first bonding region and the second bonding region; meanwhile, a three-dimensional heterogeneous integrated structure is realized, so that the programmable gate array unit and the first dynamic storage array unit are integrated into a single chip, the integrated chip not only has the logic programmable capability, but also effectively increases the interconnection quantity; meanwhile, the high-bandwidth, high-energy-efficiency and low-delay mass storage access can be provided for the logic part. In addition, the test module is integrated on the programmable gate array unit or the first dynamic storage array unit, so that the test module is connected with the programmable gate array or the first dynamic storage array, and the first dynamic storage array is tested and repaired through the test module.

Drawings

FIG. 1 is a simplified three-dimensional structure of an integrated chip according to an embodiment of the present application;

fig. 2 is a schematic plan view of an integrated chip according to an embodiment of the present application;

FIG. 3 is a simplified three-dimensional structure diagram of an integrated chip corresponding to FIG. 2 according to an embodiment of the present application;

FIG. 4 is a schematic plan view of an integrated chip according to another embodiment of the present application;

FIG. 5 is a schematic plan view of an integrated chip according to yet another embodiment of the present application;

FIG. 6 is a schematic structural diagram of a bidirectional circuit from an interface module to a first DRAM cell according to an embodiment of the present application;

fig. 7 is a schematic physical structure diagram of an integrated chip according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a bidirectional interface circuit in two adjacent units in an integrated chip according to an embodiment of the present application;

FIG. 9 is a flowchart of a method for fabricating an integrated chip according to an embodiment of the present application;

FIG. 10 is a diagram illustrating a product structure of a programmable gate array unit, a first dynamic memory array unit or a second dynamic memory array unit according to an embodiment of the present application;

FIG. 11 is a sub-flowchart of step S13 in FIG. 9;

FIG. 12 is a schematic structural diagram illustrating the formation of a dielectric layer and a via on a programmable gate array unit, a first dynamic memory array unit or a second dynamic memory array unit according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a product after being processed in step S14 according to an embodiment of the present application;

FIG. 14 is a flow chart of a method for fabricating an integrated chip according to another embodiment of the present application;

FIG. 15 is a sub-flowchart of step S17 of FIG. 14;

FIG. 16 is a schematic structural diagram illustrating a first dynamic memory array unit being thinned and a second conductive via being formed according to an embodiment of the present application;

fig. 17 is a schematic structural diagram of a product after being processed in step S17 according to an embodiment of the present application;

FIG. 18 is a flow chart of a method for fabricating an integrated chip according to yet another embodiment of the present application;

fig. 19 is a schematic structural diagram of a product after being processed in step S19 according to an embodiment of the present application.

Description of the reference numerals

An integrated chip 10; a programmable gate array unit 11; a test module 11 a; a multiplex selection module 11 b; a control module 11 c; a first physical interface module 11 d; a test interface module 11 e; a random access memory 11 f; displaying the lookup table 11 g; a first substrate 111; a first active layer 112; a first metal layer 113; a first dielectric layer 114; a first through hole 115; a first conductive via 116; a conductive bump 117; a first protective layer 118; a first dynamic memory array unit 12; a second substrate 121; a second active layer 122; a second metal layer 123; a second dielectric layer 124; a second through-hole 125; a fourth dielectric layer 126; a fourth through hole 127; a second conductive via 128; the second protective layer 129; a first input circuit 131; a first output circuit 132; a protection module 133; an interface module 134; a third input buffer 1321; a third level shifter 1322; a fourth level conversion module 1331; a third driver module 1332; a bidirectional interface circuit 14; a first interface circuit 141; a third level shift module 1411; a fourth level shift module 1412; a second drive module 1413; a second buffer 1414; a third drive module 1415; a second input buffer 1416; a second interface circuit 142; a second dynamic memory array unit 15; a third substrate 151; a third active layer 152; a third metal layer 153; a third dielectric layer 154; a third through hole 155; a third protective layer 156.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first", "second" and "third" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any indication of the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. All directional indications (such as up, down, left, right, front, and rear … …) in the embodiments of the present application are only used to explain the relative positional relationship between the components, the movement, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indication is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The present application will be described in detail with reference to the accompanying drawings and examples.

Referring to fig. 1, fig. 1 is a schematic diagram of a three-dimensional structure of an integrated chip according to an embodiment of the present application; in the present embodiment, an integrated chip 10 is provided. The integrated chip 10 includes a programmable gate array unit 11 and a first dynamic memory array unit 12. The programmable gate array unit 11 and the first dynamic memory array unit 12 may be semiconductor material wafers.

The programmable gate array unit 11 is integrated with a first bonding area and a plurality of programmable gate arrays connected with the first bonding area; the first dynamic memory array unit 12 integrates a second bonding region and a plurality of first dynamic memory arrays connected with the second bonding region; at least part of the programmable gate array unit 11 and the first dynamic storage array unit 12 are stacked and bonded together through a first bonding region and a second bonding region in a three-dimensional heterogeneous integration manner, so that the programmable gate array is connected with the first dynamic storage array unit 12 through the first bonding region and the second bonding region, and a three-dimensional heterogeneous integration structure is realized, and thus the programmable gate array unit 11 and the first dynamic storage array unit 12 are integrated into a single chip, so that the integrated chip 10 has not only a logic programmable capability, but also the number of interconnections is effectively increased compared with a 2.5D packaging technology; meanwhile, the existence of the silicon intermediate layer is avoided, the power consumption of reading and writing data is effectively reduced, and high-bandwidth, high-energy-efficiency-ratio and low-delay large-capacity storage access can be provided for the logic part.

Referring to fig. 2 and fig. 3, fig. 2 is a schematic plan view of an integrated chip according to an embodiment of the present application; FIG. 3 is a simplified three-dimensional structure diagram of an integrated chip corresponding to FIG. 2 according to an embodiment of the present application; the programmable gate array unit 11 or the first dynamic storage array unit 12 is integrated with a Test module (DFT) 11a, and the Test module 11a is connected to the programmable gate array or the first dynamic storage array and is used For testing and repairing the first dynamic storage array unit 12.

In a specific embodiment, referring to fig. 2 and 3, the test module 11a is integrated in the programmable gate array unit 11; the test module 11a is connected to the first bonding region, and further connected to the first dynamic storage array, and is used for testing and repairing the first dynamic storage array. In this embodiment, the programmable gate array unit 11 further includes a multiplexer module 11b (MUX), a control module 11c (Memory Controller, MC), a first physical interface module 11d, and a test interface module 11e, which are connected to the first bonding area.

The first physical interface module 11d is connected to the first bonding region, the test module 11a is connected to the first physical interface module 11d, the test interface module 11e is connected to the test module 11a, and the test interface module 11e is configured to be connected to the test bus. In a specific embodiment, the test bus is connected to the test interface module 11e, the test interface module 11e is connected to the test module 11a, the test interface module 11e is configured to convert a signal received by the test bus into an internal test command, the test module 11a is further connected to the first physical interface module 11d, and the test module 11a is configured to generate an internal test stimulus, so as to test and repair the first dynamic storage array. The test module 11a and the control module 11c are connected to the multiplexer module 11b, and the multiplexer module 11b is connected to the first physical interface module 11d, so as to selectively communicate the test module 11a or the control module 11c with the first physical interface module 11d, and further communicate with the first dynamic storage array unit 12. In a specific embodiment, the first dynamic memory array unit 12 is also integrated with a physical interface, and the first physical interface module 11d is connected to the physical interface on the first dynamic memory array unit 12 through the first bonding region and the second bonding region to implement the connection between the programmable gate array unit 11 and the first dynamic memory array unit 12.

In this embodiment, the programmable gate array unit 11 may further include a configuration bus, a Random Access Memory (RAM) 11f, and a Look-Up Table (LUT) 11 g; the configuration bus is connected with a Look-Up-Table (LUT) 11g and connected with the control module 11c through the LUT; the RAM is connected with the configuration bus; in the specific implementation process, the multi-path selection module 11b gates the test module 11a and passes the test of the first dynamic storage array unit 12; then repairing the first dynamic storage array unit 12 according to the test result; then, recording and marking whether the first dynamic storage array unit 12 is repaired to a perfect state through EFUSE programming; after the first dynamic storage array unit 12 is repaired to be intact, the multi-path selection module 11b is switched to the control module 11c path, the configuration bus starts the programmable gate array unit 11 to work, and the programmable gate array unit 11 can normally access the first dynamic storage array unit 12 through the control module 11 c.

In another embodiment, referring to fig. 4, fig. 4 is a schematic plan view of an integrated chip provided in another embodiment of the present application; the test module 11a is integrated in the first dynamic memory array unit 12; the test module 11a is connected to the second bonding region and further connected to the first dynamic storage array, and is configured to test and repair the first dynamic storage array.

In this embodiment, as one implementation, the programmable gate array unit 11 further includes: a first physical interface module 11d, a test interface module 11e and a test bus. That is, in this embodiment, the test interface module 11e is still integrated in the programmable gate array unit 11; in this embodiment; the first physical interface module 11d is connected to the first bonding region, the test module 11a is connected to the second bonding region, the test interface module 11e is connected to the first physical interface module 11d and is configured to be connected to a test bus, and the test module 11a tests and repairs the first dynamic storage array according to a test signal received by the test bus.

As another implementation, referring to fig. 5, fig. 5 is a schematic plan view of an integrated chip provided in another embodiment of the present application; the first dynamic memory array unit 12 includes: a test interface module 11 e; the test module 11a is connected to the second bonding region and the test interface module 11e, the test interface module 11e is used for connecting to the test bus, and the test module 11a tests and repairs the first dynamic storage array according to the test signal received by the test bus. That is, in this embodiment, the test module 11a and the test interface module 11e are both integrated in the first dynamic storage array unit 12, so as to complete the test and repair of the first dynamic storage array unit 12 in the preparation process of the first dynamic storage array unit 12; in this embodiment, the test interface module 11e and the test module 11a are not led out to the outside of the chip through the programmable gate array unit 11.

It is understood that in the embodiments corresponding to fig. 4 and 5, the programmable gate array may not include the multiplexer module 11b, so as to reduce the production cost.

Specifically, referring to fig. 6 and fig. 7, fig. 6 is a schematic structural diagram of an input/output circuit on a first dynamic memory array unit according to an embodiment of the present application; fig. 7 is a schematic physical structure diagram of an integrated chip according to an embodiment of the present application. The programmable gate array unit 11 may include a first substrate 111, a first active layer 112, a first metal layer 113, and a first dielectric layer 114, which are sequentially stacked; wherein, the first active layer 112 is stacked on one side surface of the first substrate 111; a first metal layer 113 is stacked on the surface of the first active layer 112 facing away from the first substrate 111; the first dielectric layer 114 is disposed on a side surface of the first metal layer 113 facing away from the first active layer 112; in the embodiment, the first dielectric layer 114 is formed with a first via 115 penetrating through the first surface and the second surface thereof, so that the first metal layer 113 is led out of a side surface of the first dielectric layer 114 away from the first metal layer 113 through the first via 115; in a specific embodiment, the number of the first metal layers 113 may be multiple, and the multiple first metal layers 113 may be connected by stacking dielectric layers. In a specific embodiment, the programmable gate array is specifically integrated in the first active layer 112 of the programmable gate array cell 11.

The first dynamic memory array unit 12 may include a second substrate 121, a second active layer 122, a second metal layer 123 and a second dielectric layer 124, which are sequentially stacked; wherein, the second active layer 122 is stacked on one side surface of the second substrate 121; the second metal layer 123 is stacked on a surface of the second active layer 122 facing away from the second substrate 121; the second dielectric layer 124 is disposed on a side surface of the second metal layer 123 facing away from the second active layer 122; in the embodiment, the second dielectric layer 124 has a second via 125 penetrating through the second surface and the second surface thereof, so as to lead the second metal layer 123 out of a side surface of the second dielectric layer 124 away from the second metal layer 123 through the second via 125; the number of the second metal layers 123 may be multiple, and the multiple second metal layers 123 may be connected in a stacked manner through dielectric layers; in a specific embodiment, the first dielectric layer 114 of the programmable gate array unit 11 and the second dielectric layer 124 of the first dynamic memory array unit 12 are connected in a stacked manner, and the first via 115 and the second via 125 are aligned to realize the connection of the first metal layer 113 and the second metal layer 123. In an embodiment, the first dynamic memory array is integrated in the second active layer 122 of the programmable gate array unit 11.

The first substrate 111 and the second substrate 121 are made of the same material, and may be a semiconductor substrate, such as a silicon substrate or a germanium substrate; the first dielectric layer 114 and the first dielectric layer 114 may be made of the same material, and may be silicon oxide. The first metal layer 113 and the second metal layer 123 may be back end of line (BEOL) metallization layers, for example, the material of the first metal layer 113 and the second metal layer 123 may be at least one of aluminum-copper alloy, aluminum, germanium, and copper, and preferably, may be copper. A conductive layer is disposed in the first via 115 to connect the first metal layer 113 and the second metal layer 123; the conductive layer may specifically be copper.

In an embodiment, see fig. 6 and 7; the programmable gate array cell 11 further includes an electrostatic discharge (ESD) 133 and an interface module 134.

Wherein the protection module 133 connects the first bonding region and the interface module 134. In a specific embodiment, the protection module 134 may be specifically disposed on the programmable gate array unit 11, and is specifically disposed on the first active layer 112 on the programmable gate array unit 11, and compared to a scheme in which the protection module 133 is disposed on the first dynamic storage array unit 12, the protection module 133 is closer to the interface module 134, so that the programmable gate array unit 11 can be effectively protected to prevent an external signal from damaging the programmable gate array unit 11. The interface module 134 is used for receiving external signals and/or outputting signals of the first dynamic storage array.

In this embodiment, the first dynamic memory array unit 12 further includes a first level shift module 1331, a first driving module 1332, a first buffer 1321 and a second level shift module 1322 disposed on the second active layer 122. The input end of the first driving module 1332 is connected to the first level shift module 1331, the output end of the first driving module 1332 is connected to the second bonding region, and the first driving module 1332 and the first level shift module 1331 form the first output circuit 132 of the first dynamic memory array unit 12, so as to output the signal of the first dynamic memory array to the interface module 134 of the programmable gate array unit 11. The input terminal of the first buffer 1321 is connected to the second bonding region, the output terminal of the first buffer 1321 is connected to the second level shifter 1322, and the first buffer 1321 and the second level shifter 1322 form the first input circuit 131 of the first dynamic memory array unit 12, so as to transmit the signal input from the interface module 134 of the programmable gate array unit 11 to the first dynamic memory array unit 12. In particular embodiments, the programmable gate array and the first dynamic memory array are in particular in communication with the interface module 134 via respective physical interfaces.

It is understood that, in the specific embodiment, referring to fig. 7, an input/output circuit is also provided on the programmable gate array unit 11 to transmit the signal received from the interface module 134 to the programmable gate array unit 11 and output the signal of the programmable gate array unit 11 from the interface module 134; the structure and function of the input/output circuit on the programmable gate array unit 11 are the same as or similar to those of the input/output circuit on the programmable gate array unit 11 in the prior art, and the same or similar technical effects can be achieved.

Referring to fig. 7 and fig. 8, fig. 8 is a schematic diagram of a circuit structure in two adjacent units in an integrated chip according to an embodiment of the present application; in this embodiment, the integrated chip 10 further includes a bidirectional interface circuit 14; the bidirectional interface circuit 14 is disposed in the programmable gate array unit 11 and the first dynamic memory array unit 12, and is used for the programmable gate array unit 11 to send signals to the first dynamic memory array unit 12, and for the first dynamic memory array unit 12 to send signals to the programmable gate array unit 11.

Specifically, referring to fig. 8, the bidirectional interface circuit 14 includes a first interface circuit 141 and a second interface circuit 142; the first interface circuit 141 is used for the programmable gate array unit 11 to send signals to the first dynamic memory array unit 12; the second interface circuit 142 is used for the first dynamic memory array unit 12 to send signals to the programmable gate array unit 11.

In this embodiment, the programmable gate array unit 11 further includes a third level shifter module 1411, a fourth level shifter module 1412, a second driver module 1413 and a second buffer 1414 disposed on the first active layer 112. An input end of the second driving module 1413 is connected to the third level shifter module 1411, and an output end of the second driving module 1413 is connected to the first bonding region. An input of the second buffer 1414 is connected to the first bonding region, and an output of the second buffer 1414 is connected to the fourth level shifting module 1412. The first dynamic memory array unit 12 further includes a third driving module 1415 and a third buffer 1416 disposed on the second active layer 122. The output of the third drive module 1415 is connected to the second bonding region and the input of the third buffer 1416 is connected to the second bonding region.

In a particular embodiment, the third level shifter module 1411 and the second driver module 1413 are coupled to the third buffer 1416 via the first and second bonding regions to form the first interface circuit 141. In a particular embodiment, the second drive module 1413 is coupled to the third bumper 1416, particularly via the first via 115 and the second via 125. The third driving module 1415 is connected to the second buffer 1414 through the first and second bonding regions, and further connected to the fourth level shifter module 1412 to form the second interface circuit 142. In a particular embodiment, the third drive module 1415 is coupled to the second buffer 1414, particularly through the first via 115 and the second via 125.

The first interface circuit 141 and the second interface circuit 142 are respectively configured to include only one level conversion module, and compared with a scheme in which the first interface circuit 141 and the second interface circuit 142 respectively include two level conversion modules, the size can be reduced, and the core voltage can be used for signal transmission, and compared with the external interface voltage for signal transmission, the power consumption can be effectively reduced.

In a specific embodiment, referring to fig. 1, fig. 2 or fig. 7, the number of layers of the first dynamic memory array unit 12 is at least two, at least two layers of the first dynamic memory array units 12 are stacked and bonded on one side surface of the programmable gate array unit 11, and two adjacent first dynamic memory array units 12 are stacked and bonded through respective second bonding regions. In at least two layers of the first dynamic storage array units 12, except for the layer of the first dynamic storage array unit 12 directly bonded to the programmable gate array unit 11, the protection modules 133 of the input/output circuits on other first dynamic storage array units 12 and the interface modules 134 connected with the protection modules 133 are also arranged on the programmable gate array unit 11; the first input circuit 131 and the first output circuit 132 on the other first dynamic memory array units 12 are connected to the protection module 133 arranged on the programmable gate array unit 11 through the layer of first dynamic memory array units 12 directly bonded to the programmable gate array unit 11.

Furthermore, the other first dynamic memory array units 12 and the programmable gate array unit 11 are also formed with interface circuits for inputting and outputting signals with the programmable gate array unit 11; the specific structures and functions of the input/output circuit and the interface circuit according to this embodiment may be referred to the above description, and may achieve the same or similar technical effects, which are not described herein again.

The number of layers of the first dynamic memory array unit 12 is taken as two layers as an example; and another first dynamic memory array unit 12 except the first dynamic memory array unit 12 of the layer directly bonded with the programmable gate array unit 11 is called a second dynamic memory array unit 15.

The second dynamic memory array unit 15 is stacked on a surface of the first dynamic memory array unit 12, which is away from the programmable gate array unit 11; the functions of the specific structure of the second dynamic memory array unit 15 can be referred to the structure and functions of the first dynamic memory array unit 12, and can achieve the same or similar technical effects, which are not described herein again.

The second dynamic memory array unit 15 includes a second input circuit (not shown) and a second output circuit (not shown). The second input circuit is disposed in the second dynamic storage array unit 15, connected to the interface module 134, and configured to send a signal input from the interface module 134 to the second dynamic storage array unit 15; specifically, the second input circuit may be connected to the interface module 134 through the first dynamic memory array unit 12; and the structure of the second input circuit may be the same as the first input circuit 131, which is described in the above text.

The second output circuit is disposed on the second dynamic memory array unit 15, and is connected to the interface module 134, for outputting the signal of the second dynamic memory array unit 15 from the interface module 134. Specifically, the second output circuit may be connected to the interface module 134 through the first dynamic memory array unit 12; and the structure of the second output circuit may be the same as the first output circuit 132, which is described in the above text.

Further, in this embodiment, the second dynamic memory array unit 15 may further include a third interface circuit and a fourth interface circuit (not shown); the third interface circuit is arranged in the second dynamic storage array unit 15, connected to the bidirectional interface circuit 14 of the integrated chip 10, and configured to send a signal to the second dynamic storage array unit 15 by the programmable gate array unit 11 or the first dynamic storage array unit 12; the fourth interface circuit is disposed on the second dynamic memory array unit 15, connected to the bidirectional interface circuit 14 of the integrated chip 10, and configured to send a signal to the programmable gate array unit 11 or the first dynamic memory array unit 12 from the second dynamic memory array unit 15.

In the integrated chip 10 provided in this embodiment, by setting the programmable gate array unit 11, the programmable gate array unit 11 includes a first bonding region and a programmable gate array connected to the first bonding region; meanwhile, by setting the first dynamic storage array unit 12, the first dynamic storage array unit 12 is made to include a second bonding region and a first dynamic storage array connected with the second bonding region, and the programmable gate array unit 11 and the first dynamic storage array unit 12 are made to be bonded in a stacked manner through the first bonding region and the second bonding region, so that the programmable gate array of the programmable gate array unit 11 can access the first dynamic storage array unit 12 through the first bonding region and the second bonding region; meanwhile, a three-dimensional heterogeneous integrated structure is realized, so that the programmable gate array unit 11 and the first dynamic storage array unit 12 are integrated into a single chip, the integrated chip 10 not only has the logic programmable capability, but also effectively increases the interconnection quantity; meanwhile, the high-bandwidth, high-energy-efficiency and low-delay mass storage access can be provided for the logic part. In addition, the test module 11a is integrated on the programmable gate array unit 11 or the first dynamic storage array unit 12, so that the test module 11a is connected with the programmable gate array or the first dynamic storage array, and the test module 11a is used for testing and repairing the first dynamic storage array.

In an embodiment, the integrated chip 10 can be manufactured by the following method for manufacturing an integrated chip.

Referring to fig. 9, fig. 9 is a flowchart illustrating a method for manufacturing an integrated chip according to an embodiment of the present application; in this embodiment, a method for manufacturing an integrated chip is provided, where the method includes:

step S11: and preparing a programmable gate array unit and a first dynamic storage array unit.

Wherein, a test unit 11a is prepared on the programmable gate array unit 11 or the first dynamic storage array unit 12; the first surface of the programmable gate array unit 11 includes a first protection layer 118, and the first surface of the first dynamic memory array unit 12 includes a second protection layer 129.

Specifically, referring to fig. 7 and fig. 10, fig. 10 is a schematic diagram of a product structure of a programmable gate array unit 11 and a first dynamic storage array unit 12 according to an embodiment of the present disclosure; the programmable gate array cell 11 includes a first substrate 111, a first active layer 112, and a first metal layer 113, which are sequentially stacked. The first protection layer 118 is disposed on a surface of the first metal layer 113 facing away from the first active layer 112. In an embodiment, electronic components such as the protection module 133, the third level shifter module 1411, the second driver module 1413, the second buffer 1414, and the fourth level shifter module 1412 may be disposed on the first active layer 112, and are electrically connected to the first metal layer 113.

The first dynamic memory array unit 12 includes a second substrate 121, a second active layer 122, and a second metal layer 123 stacked in this order. The second protection layer 129 is disposed on a side surface of the second metal layer 123 away from the second active layer 122. Electronic components such as a second input buffer 1416 and a third driving module 1415 are disposed on the second active layer 122.

The first protective layer 118 and the second protective layer 129 may be plastic films or inert materials such as silicon oxide disposed on the metal layer by plating or laminating; other specific structural descriptions of the programmable gate array unit 11 and the first dynamic memory array unit 12 can be found above.

Step S12: and removing the first protective layer and the second protective layer.

Specifically, when the first protective layer 118 and the second protective layer 129 are plastic films, the protective layers can be directly peeled off, which is taken as an example in the present application; when the first protective layer 118 and the second protective layer 129 are inert materials plated or laminated on the metal layer, the first protective layer 118 and the second protective layer 129 may be removed by mechanical polishing, grinding, etching, or the like.

Step S13: a first bonding region is formed on the first surface of the programmable gate array unit and a second bonding region is formed on the first surface of the first dynamic memory array unit.

Specifically, referring to fig. 11, fig. 11 is a sub-flowchart of step S13 in fig. 9. Step S13 specifically includes:

step S131: a first dielectric layer is prepared on the first surface of the programmable gate array unit, and a second dielectric layer is prepared on the first surface of the first dynamic storage array unit.

Specifically, the first dielectric layer 114 may be formed on a surface of the first metal layer 113 facing away from the first active layer 112, and the second dielectric layer 124 may be formed on a surface of the second metal layer 123 facing away from the second active layer 122 by lamination. The first dielectric layer 114 and/or the second dielectric layer 124 may be a prepreg.

Step S132: a first via is formed on the first dielectric layer and a second via is formed on the second dielectric layer.

Specifically, a laser drilling or mechanical drilling method may be adopted to form a first via 115 in the first dielectric layer 114, where the first via 115 extends to the first metal layer 113; thereafter, a metal layer is plated in the first via hole 115 or the first via hole 115 is subjected to a copper deposition process to form a conductive via hole, which is in communication with the first metal layer 113. Similarly, laser drilling or mechanical drilling may be used to form a second via 125 in the second dielectric layer 124, where the second via 125 extends to the second metal layer 123; thereafter, a metal layer is plated in the second via hole 125 or the second via hole 125 is subjected to a copper deposition process to form a conductive via hole, which is in communication with the second metal layer 123. The metal layer may be a copper layer. Specifically, the structure of the programmable gate array unit 11 or the first dynamic storage array unit 12 after the processing of step S132 can be specifically referred to fig. 12; fig. 12 is a schematic structural diagram of forming a dielectric layer and a via hole on a programmable gate array unit, a first dynamic memory array unit, or a second dynamic memory array unit according to an embodiment of the present application.

Step S14: and bonding the first bonding region and the second bonding region, and further bonding and connecting the programmable gate array unit and the first dynamic storage array unit.

Specifically, the structure of the product after the processing in step S14 can be seen in fig. 13, and fig. 13 is a schematic view of the structure of the product after the processing in step S14 according to an embodiment of the present disclosure. Specifically, the first dielectric layer 114 and the second dielectric layer 124 are connected in a stacked manner to realize three-dimensional heterogeneous integration of the programmable gate array unit 11 and the first dynamic memory array unit 12. Wherein, when the first bonding area is bonded with the second bonding area, the first via 115 is aligned with the second via 125 to realize the interconnection of the programmable gate array unit 11 and the first dynamic storage array unit 12. At least part of the programmable gate array unit 11 and the first dynamic storage array unit 12 are stacked and bonded, so that the programmable gate array in the programmable gate array unit 11 is connected with the first dynamic storage array unit 12, and a three-dimensional heterogeneous integrated structure is realized, so that the programmable gate array unit 11 and the first dynamic storage array unit 12 are integrated into a single chip, and the integrated chip 10 has the logical programmable capability and effectively increases the interconnection number; in addition, by disposing the protection module 134 on the programmable gate array unit 11, the protection module 133 is closer to the interface module 134 than the protection module 133 is disposed on the first dynamic storage array unit 12, and the programmable gate array unit 11 can be effectively protected.

In an embodiment, referring to fig. 14, fig. 14 is a flowchart of a method for manufacturing an integrated chip according to another embodiment of the present application; another method for manufacturing an integrated chip is provided, which is different from the method for manufacturing an integrated chip provided in the first embodiment, and the method further includes:

step S15: and preparing a second dynamic storage array unit.

Wherein the first surface of the second dynamic memory array unit 15 includes a third passivation layer 156. Specifically, referring to fig. 10, the second dynamic memory array unit 15 includes a third substrate 151, a third active layer 152, and a third metal layer 153, which are sequentially stacked. The third passivation layer 156 is specifically disposed on a surface of the third metal layer 153 facing away from the third active layer 152. In a specific embodiment, the specific structure and function of the second dynamic memory array unit 15 may be the same as or similar to the specific structure and function of the first dynamic memory array unit 12, and reference may be made to the above description related to the first dynamic memory array unit 12, which is not repeated herein.

Step S16: and removing the third protective layer.

The specific implementation process of step S16 may be the same as or similar to the specific implementation process of removing the first protection layer 118 or the second protection layer 129 in step S12, and the same or similar technical effects may be achieved, which is not described herein again. In this embodiment, step S15 and step S16 may be performed before step S13, and the sequence of step S11 and step S12 is not limited.

Step S17: and preparing a third bonding area on the first surface of the second dynamic memory array unit and preparing a fourth bonding area on the second surface of the first dynamic memory array unit.

Specifically, referring to fig. 15, fig. 15 is a sub-flowchart of step S17 in fig. 14. Step S16 specifically includes:

step S171: and preparing a third dielectric layer on the first surface of the second dynamic memory array unit, and preparing a fourth dielectric layer on the second surface of the first dynamic memory array unit.

The specific implementation process of step S171 may refer to the specific implementation process of step S131, and the same or similar technical effects may be achieved, which are not described herein again.

In a specific implementation process, before the step of forming the fourth dielectric layer 126 on a side surface of the second substrate 121 facing away from the second active layer 122, the method further includes: thinning the second substrate 121; the specific structure of the first dynamic memory array unit 12 after the processing in this step can be seen in fig. 16, where fig. 16 is a schematic structural diagram illustrating that the first dynamic memory array unit is thinned and a second conductive via is formed according to an embodiment of the present disclosure; then forming a second conductive via 128 on the second substrate 121 and the second active layer 122, wherein the second conductive via 128 is connected with the second metal layer 123, and the second metal layer 123 is led out of the second substrate 121; in a particular embodiment, the fourth via 127 is electrically connected to the second metal layer 123 through the second conductive via 128.

Specifically, the second substrate 121 may be thinned by one or a combination of wet etching, grinding, chemical mechanical grinding, and the like. The thickness of the second substrate 121 after thinning can be 0.5-300 micrometers, for example, 0.5 micrometer, 10 micrometers, 50 micrometers, 200 micrometers, etc.; of course, the thickness of the thinned second substrate 121 may also be less than 0.5 micrometers or greater than 300 micrometers, which may be selected according to the performance requirements and the product type of the integrated chip 10 to be produced.

The second conductive via 128 is filled with a metal, such as copper; the second conductive via 128 penetrates through the second substrate 121 and the second active layer 122 to be electrically connected to the second metal layer 123, and the second metal layer 123 is led out of one side surface of the second substrate 121 far away from the second active layer 122; specifically, the specific manufacturing method of the second conductive via 128 can be manufactured by the TSV process in the prior art, and can achieve the same or similar technical effects, which are not described herein again.

Step S172: a third via is prepared on the third dielectric layer and a fourth via is prepared on the fourth dielectric layer.

Specifically, the product structure after processing in step S172 can be specifically referred to in fig. 12. The specific implementation process of step S172 may refer to the specific implementation process of step S132, and the same or similar technical effects may be achieved, which are not described herein again. The third via 155 is electrically connected to the third metal layer 153, and the fourth via 127 is electrically connected to the second metal layer 123.

Step S18: and bonding the third bonding region and the fourth bonding region, and further bonding and connecting the first dynamic storage array unit and the second dynamic storage array unit.

Specifically, the structure of the product after the processing in step S18 can be seen in fig. 17, where fig. 17 is a schematic view of the structure of the product after the processing in step S17 according to an embodiment of the present application; in a particular embodiment, the third through-hole 155 is aligned with the fourth through-hole 127 when the third bonding region is bonded with the fourth bonding region.

Specifically, the third dielectric layer 154 and the fourth dielectric layer 126 are connected in a stacked manner to realize three-dimensional heterogeneous integration of the first dynamic memory array unit 12 and the second dynamic memory array unit 15. Specifically, after the first dynamic memory array unit 12 and the second dynamic memory array unit 15 are bonded, the third through hole 155 and the fourth through hole 127 are correspondingly connected to achieve connection of the electronic components on the first dynamic memory array unit 12 and the second dynamic memory array unit 15.

Specifically, referring to fig. 18, fig. 18 is a flowchart of a method for manufacturing an integrated chip according to another embodiment of the present application; the preparation method of the integrated chip further comprises the following steps:

step S19: and forming a conductive bump communicated with the first metal layer on the first substrate so as to lead the first metal layer out of the surface of one side of the first substrate, which is far away from the first active layer.

Specifically, the structure of the product after the processing in step S19 can be seen in fig. 19, and fig. 19 is a schematic view of the structure of the product after the processing in step S19 according to an embodiment of the present application. In a specific implementation process, step S19 may specifically include: thinning the first substrate 111; then, a first conductive via 116 penetrating through the first substrate 111 and the first active layer 112 is formed, and the first conductive via 116 is connected to the first metal layer 113 to lead the first metal layer 113 out of the first substrate 111; and then, forming a conductive bump 117 on the surface of the first substrate 111 on the side away from the first active layer 112, wherein the conductive bump 117 is connected with the first conductive via 116, and further leading out the first metal layer 113 to the surface of the first substrate 111 through the conductive bump 117. Specifically, the specific processes of the thinning process and the opening of the first conductive via 116 may refer to the related description in the step S161, and the same or similar technical effects may be achieved, which is not described herein again.

Of course, it is understood that when the integrated chip 10 includes only the programmable gate array unit 11 and the first dynamic memory array unit 12, the step S19 can be performed after the step S13; when the integrated chip 10 includes a plurality of second dynamic memory array units 15, the plurality of second dynamic memory array units 15 may be sequentially bonded to a side surface of the second dynamic memory array unit 15 away from the first dynamic memory array unit 12 in a manner that the second dynamic memory array unit 15 is bonded to the first dynamic memory array unit 12, and step S19 may be performed after the plurality of second dynamic memory array units 15 are bonded.

In the method for manufacturing an integrated chip provided in this embodiment, the programmable gate array unit 11 and the first dynamic storage array unit 12 are respectively manufactured; then removing the first protection layer 118 of the programmable gate array unit 11 and the second protection layer 129 of the first dynamic storage array unit 12; then, bonding the programmable gate array unit 11 and the first dynamic storage array unit 12, so that the programmable gate array of the programmable gate array unit 11 can access the first dynamic storage array unit 12 through the first bonding region and the second bonding region; meanwhile, a three-dimensional heterogeneous integrated structure is realized, so that the programmable gate array unit 11 and the first dynamic storage array unit 12 are integrated into a single chip, the prepared integrated chip 10 not only has the logic programmable capability, but also the interconnection quantity is effectively increased; meanwhile, the high-bandwidth, high-energy-efficiency and low-delay mass storage access can be provided for the logic part. In addition, the test module 11a is integrated on the programmable gate array unit 11 or the first dynamic storage array unit 12, so that the test module 11a is connected with the programmable gate array or the first dynamic storage array, and the test module 11a is used for testing and repairing the first dynamic storage array.

It should be noted that the units referred to in the present application may be dies or wafers. And in particular embodiments, the programmable gate array unit may include a plurality of programmable gate arrays, each of which may include a plurality of programmable sub-units; the dynamic memory array unit can comprise a plurality of dynamic memory arrays, and each dynamic memory array can comprise a plurality of dynamic memory sub-units.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.