阅读说明：本技术 半导体装置和系统以及形成方法 (Semiconductor device and system and method of formation ) 是由 J·D·霍普金斯 N·M·洛梅利 J·B·德胡特 D·法兹尔 于 2019-10-09 设计创作，主要内容包括：本申请涉及半导体装置和系统,以及形成方法。装置、系统和结构包含布置于层的一或多个层面中的材料的竖直交替层的堆叠。其中可形成沟道支柱的沟道开口延伸穿过所述堆叠。所述支柱包含横向延伸到所述沟道开口的“底切部分”中的“肩部部分”,所述底切部分沿着所述堆叠的所述层面中的至少一个的至少一下部层限定。(The present application relates to semiconductor devices and systems, and methods of forming. Devices, systems, and structures include a stack of vertically alternating layers of material arranged in one or more levels of layers. A channel opening, in which a channel post may be formed, extends through the stack. The pillars include "shoulder portions" that extend laterally into "undercut portions" of the channel openings, which are defined along at least a lower layer of at least one of the levels of the stack.)

1. A method of forming a semiconductor device, the method comprising:

forming a stack of vertically alternating layers of insulating material and other material over a base material, a sacrificial material disposed in the base material, and a soft plug material disposed in the sacrificial material;

forming an opening extending through the stack and through the cork material, leaving a residue of the cork material along sidewalls of the opening;

forming a liner in the opening;

exposing a portion of the sacrificial material through the liner;

removing the remnants of the sacrificial material and the soft plug material without removing the liner to define a gap between sidewalls of the liner and the base material, the gap exposing a portion of a lower layer of the stack;

etching into the portion of the lower layer of the stack to define an undercut portion in the lower layer of the stack; and

removing the liner to form a channel opening extending through the stack and into the base material, the channel opening exposing a source region of the base material at a base of the channel opening, the channel opening being defined by a sidewall including the undercut portion.

2. The method of claim 1, wherein forming a liner in the opening comprises conformally forming polysilicon in the opening.

3. The method of claim 1, wherein etching into the portion of the lower layer of the stack to define an undercut portion in the lower layer of the stack comprises isotropically etching into the portion of the lower layer of the stack.

4. The method of claim 1, further comprising, after forming the liner in the opening and before exposing a portion of the sacrificial material through the liner:

filling the opening with a filler material;

removing an upper portion of the filler material to form a recess;

forming another cork material in the recess;

forming another stack of vertically alternating layers over the stack of vertically alternating layers and the another soft plug material; forming a further opening extending through the further stack and through the further cork material, leaving a further residue of the further cork material along a sidewall of the further opening;

forming another pad in the another opening; and

exposing a portion of the filler material through the other liner.

5. The method of claim 4, further comprising:

removing the residue of the filler material and the another cork material without removing the liner or the another liner to define another gap between the another liner and the liner, the another gap exposing a portion of a lower layer of the another stack of the vertically alternating layers; and

etching into the portion of the lower layer of the other stack to define another undercut portion in the lower layer of the other stack.

6. The method of claim 5, wherein etching into the portion of the lower layer of the stack and etching into the portion of the lower layer of the other stack are carried out simultaneously.

7. A method of forming a semiconductor device, the method comprising:

forming a first level of vertically alternating layers of insulating and other materials over a base material and a sacrificial material disposed in the base material;

forming an opening extending through the first level and into the sacrificial material;

forming a liner and a filler material within the opening;

forming a second level of vertically alternating layers of the insulating material and the other material over the first level, the liner, and the filler material;

forming another opening extending through the second level to the fill material within the opening;

forming another liner within the another opening;

exposing a portion of the filler material through the other liner;

removing the filler material and the sacrificial material to form an extended opening exposing at least a portion of a lower layer of each of the first level and the second level without removing the liner or another liner;

isotropically etching the portion of the lower layer of each of the first and second levels to define an undercut portion; and

removing the liner and the other liner to form a channel opening defined by a sidewall including the undercut portion.

8. The method of claim 7, wherein forming a first level of vertically alternating layers of insulating and other materials over a base material and a sacrificial material disposed in the base material comprises forming a first level of vertically alternating layers of oxide and nitride materials over the base material and a sacrificial material comprising tungsten.

9. The method of claim 7, wherein:

forming a liner and a fill material within the opening comprises forming a polysilicon liner and an oxide fill material within the opening; and

forming another liner within the another opening includes forming another polysilicon liner within the another opening.

10. A system, comprising:

a three-dimensional array of memory devices comprising a stack of insulating layers interleaved with word line layers and comprising a channel pillar extending through the stack to a source region, the channel pillar having a sidewall defining a curved surface along at least a portion of the sidewall:

at least one processor coupled to the three-dimensional array of memory devices; and

at least one peripheral device in operable communication with the at least one processor.

11. The system of claim 10, further comprising CMOS circuitry disposed below the source region.

12. The system of claim 10, wherein the curved surface along the at least a portion of the sidewall defines a narrower width of the channel strut at an upper elevation of the curved surface and a wider width of the channel strut at a lower elevation of the curved surface.

13. The system of claim 10, wherein the sidewall of the trench leg defines at least another curved surface along at least another portion of the sidewall.

14. The system of claim 10, wherein the curved surface of the sidewall is laterally adjacent to an insulating material of an insulating layer of the stacked insulating layers.

15. An electronic device, comprising:

a three-dimensional array of memory devices, the three-dimensional array comprising:

a layer stack of insulating layers interleaved with the word line layers; and

at least one pillar extending through the layer stack to a source region, the at least one pillar comprising a channel material structure comprising an inclined portion above a shoulder portion extending laterally proximate to at least one lower layer of the layer stack.

16. The electronic device of claim 15, wherein:

the three-dimensional array further comprises another layer stack of another insulating layer interleaved with another word line layer over the layer stack;

the at least one pillar further extends through the other layer stack; and

the channel material structure further includes another shoulder portion above the sloped portion that extends laterally proximate to at least one lower layer of the another layer stack.

17. The electronic device of claim 16, wherein the channel material structure further comprises another sloped portion above the another shoulder portion.

18. The electronic device of claim 15, wherein the at least one pillar further comprises a cell material interposed between the channel material structure and the layer stack.

19. An electronic device, comprising:

a stacked structure comprising layers of insulating material vertically interleaved with layers of conductive material; and

a support post extending through the stacked structure and into a substrate material, the support post comprising:

channel material along sidewalls of the pillars, the channel material extending through the cell material to reach source regions under the stack, the channel material defining laterally extending shoulder portions near a lowermost layer of the stack structure.

20. The electronic device of claim 19, wherein the channel material further defines another laterally extending shoulder portion above the laterally extending shoulder portion.

Technical Field

In various embodiments, the present disclosure generally relates to structures having at least one stack of vertically alternating layers of material and high aspect ratio openings extending through the at least one stack. More particularly, the present disclosure relates to structures for forming semiconductor memory devices having multiple stacked layers, such as three-dimensional (3D) semiconductor memory devices (e.g., 3D NAND memory devices), formed with high aspect ratio openings extending into layers of a common channel region, such as a single channel, and methods of forming semiconductor memory devices.

Background

The memory provides data storage for the electronic system. Flash memory is one of a variety of memory types and has many uses in modern computers and devices. A typical flash memory device may include a memory array having a large number of charge storage devices (e.g., memory cells, such as non-volatile memory cells) arranged in rows and columns. In a flash memory of the NAND architecture type, the storage devices arranged in a column are coupled in series, and the first storage device of the column is coupled to a bit line. In "two-dimensional NAND" (which may also be referred to herein as "2D NAND"), the storage devices are arranged in rows and columns along a horizontal surface. In "three-dimensional NAND" (which may also be referred to herein as "3D NAND") -a type of vertical memory, not only are the storage devices arranged in rows and columns in a horizontal array, but also the layers of the horizontal array are stacked on top of each other (e.g., as vertical strings of storage devices) to provide a "three-dimensional array" of storage devices.

To build a three-dimensional array, multiple layers of material are deposited in sequence. The result may be a vertically alternating stack of layers of insulating material and layers comprising conductive material. The insulating material vertically alternates with the storage devices (e.g., memory cells) in the layer comprising the conductive material.

The storage devices may each include a Control Gate (CG) and a charge storage structure, such as a Floating Gate (FG) or Charge Trap (CT), configured to store electrons or holes accumulated thereon. Information is represented by the amount of electrons or holes stored by the cell. The stack may further include a barrier material, such as a nitride, in an inter-gate dielectric (IGD) comprising a composite of oxide-nitride-oxide ("ONO"), where the IGD may be between the charge storage structure and the CG.

In 3D NAND, access lines, which may also be referred to as "word lines," may each operatively connect storage devices corresponding to respective conductive materials (including rows of a three-dimensional array). The access line is coupled to, and in some cases is formed at least in part by, the CG of the memory device.

The channel openings extend through the stack of vertically alternating layers to the underlying material (e.g., source material), and a single continuous region of channel material may be formed in each channel opening to contact the underlying material at the bottom of the opening. As such, pillars are formed in the channel openings, each pillar having a single channel region that extends vertically along a three-dimensional array of charge storage devices (e.g., memory cells).

Ideally, the channel opening would be formed to define vertical walls (e.g., walls extending at a 90 degree angle relative to the upper surface of the underlying material). However, in reality, forming the trench opening by etching results in the sidewalls tapering from the widest opening width at the uppermost elevation to the narrowest opening width at the deepest elevation. As three-dimensional semiconductor devices, such as with 3D NAND architectures, are "scaled up" to include higher density of storage devices per horizontal footprint on a semiconductor chip, such as with more and more layers built on top of each other, it becomes more challenging to form a common channel opening through the layers with sufficient exposure of underlying material at the bottom of the opening. Correspondingly, forming trench pillars within deeper openings becomes more challenging.

Disclosure of Invention

A semiconductor device is disclosed. The semiconductor device includes a stack of vertically alternating layers over a base material. The vertically alternating layers include vertically alternating layers of insulation and word lines. Sidewalls of the stack define an opening extending through the stack and into the base material, exposing a source region of the base material at a base of the opening. The sidewall includes at least one undercut portion defined in at least one lower layer of the stack of vertically alternating layers.

A method of forming a semiconductor device is also disclosed. The method includes forming a stack of vertically alternating layers of insulating material and other materials over a base material, a sacrificial material disposed in the base material, and a soft plug material disposed in the sacrificial material. An opening is formed extending through the stack and through the cork material, leaving a residue of the cork material along sidewalls of the opening. A liner is formed in the opening. A portion of the sacrificial material is exposed through the liner. The remnants of the sacrificial material and the soft plug material are removed without removing the liner to define a gap between the liner and the sidewalls of the base material. The gap exposes a portion of the lower layers of the stack. The portion of the lower layer of the stack is etched to define an undercut portion in the lower layer of the stack. The liner is removed to form a channel opening extending through the stack and into the substrate material. The channel opening exposes a source region of the base material at a base of the channel opening. The channel opening is defined by a sidewall that includes an undercut portion.

Also disclosed is a method of forming a semiconductor device, the method comprising forming a first level of vertically alternating layers of insulating and other materials over a base material and a sacrificial material disposed in the base material. An opening is formed through the first level and into the sacrificial material. A liner and a fill material are formed within the opening. A second level of vertically alternating layers of insulating and other materials is formed over the first level, the liner, and the fill material. Another opening is formed extending through the second level to the fill material within the other opening. Another liner is formed within the other opening, and a portion of the fill material is exposed through the other liner. The filler material and the sacrificial material are removed to form an extended opening exposing at least a portion of the lower layer of each of the first level and the second level without removing the liner or another liner. The portion of the lower layer of each of the first and second levels is isotropically etched to define an undercut portion. The liner and another liner are removed to form a channel opening defined by a sidewall that includes an undercut portion.

A semiconductor device is also disclosed. The semiconductor device includes a stack of vertically alternating layers over a base material and over CMOS circuit components. The vertically alternating layers include layers comprising insulating material vertically interleaved with layers comprising word lines. The channel pillar extends through the stack and into the base material to a source region at the base of the channel pillar. The sidewalls of the channel posts define shoulder portions laterally adjacent to at least a lower layer of the stack of vertically alternating layers.

A system is also disclosed that includes a three-dimensional array of memory devices that includes a stack of insulating layers interleaved with word line layers and includes channel pillars extending through the stack to source regions. The channel strut has a sidewall defining a curved surface along at least a portion of the sidewall. At least one processor is coupled to a three-dimensional array of memory devices. At least one peripheral device is in operable communication with the at least one processor.

Drawings

Figure 1 is a cross-sectional front elevation schematic illustration of the structure of a storage array having a 3D NAND architecture, according to an embodiment of the present disclosure.

Fig. 2 through 16 are cross-sectional front elevation schematic illustrations during various processing stages of fabricating the structure of fig. 1, according to embodiments of the present disclosure.

Fig. 17 through 22 are cross-sectional front elevation schematic illustrations during various processing stages of fabricating the structure of fig. 1, wherein fig. 17 is after the stage shown in fig. 4 and fig. 22 is before the stage shown in fig. 13, according to another embodiment of the present disclosure.

Fig. 23 is a cross-sectional front elevation schematic illustration of the structure of a memory device Array having a 3D NAND architecture including CMOS under Array (CuA) components, according to an embodiment of the present disclosure.

Fig. 24 is an enlarged illustration of block a from fig. 23 according to another embodiment of the present disclosure.

Fig. 25 is a simplified block diagram of a semiconductor device including an array of memory devices having a structure in accordance with one or more embodiments of the present disclosure.

Fig. 26 is a simplified block diagram of a system implemented in accordance with one or more embodiments of the present disclosure.

Detailed Description

Devices, systems, and structures in accordance with embodiments of the present disclosure include a stack of vertically alternating layers of material arranged in one or more levels of layers. Channel pillars are formed in channel openings that extend through the one or more levels of the stack to underlying source material. The pillars include "shoulder portions" that extend laterally into "undercut portions" of the channel openings, which are defined along at least a lower layer of at least one of the stacked layers. During fabrication, forming the undercut portion effectively opens up what would otherwise be a narrowing portion of the channel opening (e.g., a "throat point" or "bottleneck"). This enables a larger width to access the lowermost area of the channel opening and expose the underlying source material during fabrication. It also accommodates the material forming the pillars in the channel openings. As such, a greater width at the bottom of the channel opening may be exposed without having to increase the width at the top of the channel opening. In devices, systems, and structures having multiple levels of layers through which a single channel pillar communicates, each level may be formed to exhibit an undercut portion along its lower layer such that the resulting single channel pillar defines multiple shoulder portions, each shoulder portion adjacent to an undercut lower layer of the level. Vertical scaling of the three-dimensional structure is achieved with each undercut portion widening what would otherwise be a narrower neck portion.

Structures according to embodiments herein include a stack of vertically alternating layers of various materials. More specifically, "stack" includes interleaving "insulating layers" with "word line layers. As used herein, the term "insulating layer" means and refers to layers that comprise insulating material in a stacked manner. As used herein, the term "word line layer" means a layer in the stack that includes the conductive material of the access lines, at least in the completed structure, and that is disposed vertically between a pair of insulating layers, e.g., one below and one above.

As used herein, the term "level" means and includes a plurality of vertically alternating layers of insulating layers and word lines.

As used herein, the term "stack deck" means a plurality of deck layers vertically disposed with respect to each other.

As used herein, the term "high aspect ratio" means a ratio of height (vertical dimension) to width (horizontal dimension) that is greater than 40: 1.

As used herein, the term "opening" means a volume that extends through another region or material, leaving a gap in that region or material. Unless otherwise described, the "openings" do not have to be evacuated of material. That is, the "opening" need not be a void space. An "opening" formed in a region or material may include regions or materials of the region or material other than those in which the opening is formed. Also, the "exposed" area or material within the opening need not be in contact with the atmosphere or a non-solid environment. A region or material that is "exposed" within an opening may contact or be adjacent to another region or material disposed within the opening.

As used herein, the term "sacrificial material" means and includes material that is formed during the fabrication process but is removed prior to completion of the fabrication process.

As used herein, the term "substrate" means and includes the base material or other construction on which components, such as components within a memory cell, are formed. The substrate may be a semiconductor substrate, a base semiconductor material on a support structure, a metal electrode, or a semiconductor substrate having one or more materials, structures, or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate including semiconductive material. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") substrates or silicon-on-glass ("SOG") substrates, epitaxial layers of silicon on a base semiconductor foundation, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si-Ge)_1-xGe_xWhere x is, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), among others. Furthermore, when reference is made to a "substrate" in the following description, previous process steps may have been utilized to form materials, regions, or junctions in the base semiconductor structure or foundation.

As used herein, the term "horizontal" means and includes a direction parallel to the major surface of the substrate where the material or structure in question is located. The width and length of the respective zones or materials may be defined as the dimensions in the horizontal plane.

As used herein, the term "vertical" means and includes a direction perpendicular to the major surface of the substrate where the material or structure in question is located. The height of the respective region or material may be defined as the dimension in the vertical plane.

As used herein, the term "thickness" means and includes a dimension in a linear direction perpendicular to the closest surface of a proximate material or region of different composition.

As used herein, the term "between" is a spatial relationship term used to describe the relative disposition of one material, region or sub-region with respect to at least two other materials, regions or sub-regions. The term "between" can encompass both the placement of one material, region or sub-region immediately adjacent to other materials, regions or sub-regions, and the placement of one material, region or sub-region immediately adjacent to other materials, regions or sub-regions.

As used herein, the term "proximate" is a spatial relationship term used to describe one material, region or sub-region disposed near another material region or sub-region. The term "proximate" includes being disposed indirectly adjacent, immediately adjacent, and internally.

As used herein, the terms "about" and "approximately" when used in reference to a numerical value of a particular parameter include the numerical value, and a person of ordinary skill in the art will appreciate that the degree of deviation from the numerical value is within an acceptable tolerance of the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include an additional numerical value that is within 90.0% to 110.0% of the numerical value, such as within 95.0% to 105.0% of the numerical value, within 97.5% to 102.5% of the numerical value, within 99.0% to 101.0% of the numerical value, within 99.5% to 100.5% of the numerical value, or within 99.9% to 100.1% of the numerical value.

As used herein, reference to an element being "on" or "over" another element means and includes the element being directly on top of, adjacent (e.g., laterally adjacent, vertically adjacent) to, under, or in direct contact with the other element. It also includes the element being indirectly on top of, adjacent to (e.g., laterally adjacent, vertically adjacent), under or near another element with other elements present therebetween. In contrast, when an element is referred to as being "directly on" or "directly adjacent" to another element, there are no intervening elements present.

As used herein, other spatial relationship terms, such as "below," "lower," "bottom," "above," "upper," "top," and the like, may be used for convenience of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Unless otherwise specified, spatial relationship terms are intended to encompass different orientations of the material in addition to the orientation depicted in the figures. For example, if the materials in the figures are reversed, elements described as "below" or "beneath" or "on the bottom" other elements or features would then be oriented "above" or "on the top" of the other elements or features. Thus, the term "below" can encompass both an orientation of above and below, depending on the context in which the term is used, as will be apparent to one of ordinary skill in the art. The materials may be otherwise oriented (rotated 90 degrees, inverted, etc.) and the spatial relationship descriptors used herein interpreted accordingly.

As used herein, the terms "comprises," "comprising," and/or "including" specify the presence of stated features, regions, stages, operations, elements, materials, components, and/or groups, but do not preclude the presence or addition of one or more other features, regions, stages, operations, elements, materials, components, and/or groups thereof.

As used herein, "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

The illustrations presented herein are not intended to be actual views of any particular material, structure, feature, component, apparatus, system, or stage of manufacture, but are merely idealized representations which are employed to describe embodiments of the present disclosure.

Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes or regions as illustrated, but may include deviations in shapes that result, for example, from manufacturing techniques. For example, a region shown or described as a box may have rough and/or non-linear features. In addition, the sharp corners shown may be rounded. Thus, the materials, features, and regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a material, feature, or region and are not intended to limit the scope of the present claims.

The following description provides specific details such as material types and processing conditions in order to provide a thorough description of embodiments of the disclosed apparatus and methods. However, it will be understood by those of ordinary skill in the art that the embodiments of the apparatus and methods may be practiced without these specific details. Indeed, embodiments of the apparatus and methods may be practiced in conjunction with conventional semiconductor fabrication techniques employed in the industry.

The manufacturing processes described herein do not form a complete process flow for processing semiconductor device structures. The remainder of the process flow is known to those of ordinary skill in the art. Accordingly, only the methods and semiconductor device structures necessary to understand embodiments of the present devices, structures, systems, and methods are described herein.

Unless the context indicates otherwise, the materials described herein can be formed by any suitable technique, including, but not limited to, spin coating, blanket coating, chemical vapor deposition ("CVD"), atomic layer deposition ("ALD"), plasma enhanced ALD, physical vapor deposition ("PVD") (e.g., sputtering), or epitaxial growth. Depending on the particular material to be formed, the techniques for depositing or growing the material may be selected by one of ordinary skill in the art.

Unless the context indicates otherwise, removal of materials described herein may be achieved by any suitable technique, including, but not limited to, etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, abrasive planarization, or other known methods.

Reference will now be made to the drawings in which like numerals refer to like elements throughout. The drawings are not necessarily to scale.

FIG. 1 illustrates an embodiment of a structure 100 of a memory device array having a 3D NAND architecture. The structure 100 includes a stack 102 of vertically alternating layers of material. The layers of the stack 102 include insulating layers 104 interleaved with word line layers 106.

In some embodiments, the insulating layer 104 of the stack 102 includes an insulating material 105 (e.g., an oxide (e.g., silicon oxide)) and the word line layer 106 includes a different material 107. The different materials 107 of the word line layer 106 may include materials for access lines (e.g., word lines (e.g., tungsten (W))), for control gates, for control gate blocking insulators, and for charge storage regions. In some embodiments, the stack 102 may include a stack of oxide and nitride materials, a stack of oxide and polysilicon materials, or a stack of oxide and metal materials, wherein the insulating material 105 comprises an oxide material (e.g., silicon oxide) and the different material 107 of the word line layer 106 comprises a nitride, polysilicon, or metal material.

The layers of the stack 102 are arranged in multiple levels. A lower first level 108 and an upper second level 110 are shown. Each of the first level 108 and the second level 110 includes a plurality of alternating insulation layers 104 and word line layers 106. Although two levels are shown, the multiple levels may include a greater number of levels. In other embodiments, only a single level may be included.

Fig. 1 shows each of the first deck 108 and the second deck 110 as having a total of eight alternating layers, four insulation layers 104 and four word line layers 106 in each of the first deck 108 and the second deck 110. However, each of the deck layers 108/110 can have more or less than eight layers 104/106. Also, although fig. 1 shows deck 108/110 as having the same number of layers 104/106, in other embodiments first deck 108 may have fewer or more layers than the number of layers 104/106 in second deck 110.

The stack 102 is disposed over a base material 112, which may comprise, consist essentially of, or consist of polysilicon. At least a region of the base material 112 may be doped to provide a source region 114. The dopant used may include at least one of phosphorous or arsenic. The source region 114 including dopants may be an isolation region, as shown in fig. 1; alternatively, dopants may be included along a wider region of the base material 112 to extend the source regions 114 by a larger lateral width (not shown in fig. 1).

A channel opening 116 (e.g., trench, hole) extends vertically through stack 102 and into base material 112 to expose a portion (e.g., "exposed portion" 118) of source region 114. Sidewalls 120 of the channel opening 116 are lined with a cell material 122. The cell material 122 may include a tunnel insulator (e.g., a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), a combination of an oxide and a nitride (e.g., an oxide-nitride-oxynitride (ONO) material), or one or more of polysilicon). In subsequent processing, channel material may be formed in the remaining space of channel opening 116 contacting exposed portion 118 of source region 114 and extending vertically from source region 114 and up through stack 102.

Channel opening 116 defines an undercut portion of the lower layer adjacent to each of levels 108/110. For example, the undercut portion 124 of the first deck 108 is adjacent to a lower layer of the first deck 108 (e.g., the insulating layer 104 closest to the base material 112); and the undercut portion 126 of the second level 110 is adjacent to a lower layer of the second level 110 (e.g., the insulating layer 104 disposed on top of the first level 108).

Undercut portions 124/126 result from the removal of a portion of the material of at least the lower layer of respective level 108/110. As such, undercut portions 124/126 are effectively carved into at least the edges of the lower layer, and the portions of sidewalls 120 formed by the edges of the lower layer of respective levels 108/110 are not tapered continuing in alignment with the taper of the upper layer that does not define undercut portions 124/126. In fact, the slope of sidewall 120 defined by the edge of layer 104/106 changes from narrowing channel opening 116 to increasing channel opening 116 at an elevation above the lower surface of the undercut lower layer.

In some embodiments, the portion of the sidewall 120 defining the undercut portion 124/126 may be curved. The curvature of undercut portion 124/126 may curve inward (from a wider width to a narrower width) along the height of undercut portion 124/126.

Cell material 112 may conform to these undercut portions 124/126 such that cell material 112 also exhibits undercut portions. As such, the width of channel opening 116 widens (e.g., becomes wider and wider as the depth increases) along undercut portion 124/126. Accordingly, the sidewalls 120 may taper in width with increasing depth along the height of the second level 110, expand along the undercut portion 126 of the second level 110, taper again in width with increasing depth along the height of the first level 108, expand again along the undercut portion 124 of the first level 108, and then taper again in width with increasing depth along the remaining portion of the trench opening 116 extending into the base material 112.

Although fig. 1 shows undercut portion 124/126 being defined in only a lower layer (e.g., insulating layer 104) of each of levels 108/110, in other embodiments, undercut portion 124/126 may be defined to encompass at least a portion of the next layers above, for example, the lowest wordline layer 106 of each of levels 108/110, and the like.

The inclusion of undercut portion 124/126 provides a wider opening at a corresponding elevation in channel opening 116 to allow easier access to expose exposed portion 118 of source region 114. For example, the undercut portion 124 of the first deck 108 may define an opening width W₁And the undercut portion 126 of the second layer 110 may define an opening width W₂. Width W of the openings₁/W₂The narrowest width along the channel opening 116 is wider than it would be without the undercut portions 124, 126. As such, even if stack 102 is formed from a large number of layers 104/106, the wider exposed portion 118 of source region 114 may not be covered during fabrication.

Accordingly, a semiconductor device is disclosed that includes a stack of vertically alternating layers over a base material. The vertically alternating layers include vertically alternating layers of insulation and word lines. Sidewalls of the stack define an opening extending through the stack and into the base material, exposing a source region of the base material at a base of the opening. The sidewall includes at least one undercut portion defined in at least one lower layer of the stack of vertically alternating layers.

Referring to fig. 2 through 16, various stages in a method of fabricating the structure 100 of fig. 1 are shown. The structure 200 illustrated in fig. 2 may be fabricated by forming a region of sacrificial material 228 within the base material 112 over the source regions 114. For example, a portion of the base material 112 may be removed (e.g., etched) to define an opening that exposes a region of the base material 112, into which a dopant may be implanted to form the source region 114. Sacrificial material 228 may be formed into the openings.

The sacrificial material 228 may be formulated to act as a stop for a subsequent etch stage. The sacrificial material 228 may comprise, for example, an oxide material (e.g., aluminum oxide), a high-k dielectric material (e.g., magnesium oxide, hafnium magnesium oxide), a metal material (e.g., tungsten (W)), or a combination thereof.

A portion of the sacrificial material 228 may then be removed (e.g., etched) to define a recess into which a soft plug material 230 may be formed to fill the opening. The soft plug material 230 is also a sacrificial material having a different composition than the sacrificial material 228 that provides the stop so that the sacrificial material 228 can be later removed, thereby removing the soft plug material 230. In embodiments where sacrificial material 228 comprises an oxide, soft plug material 230 may comprise an oxide other than the oxide of sacrificial material 228.

The insulating material 105 of the insulating layer 104 and the material 107 of the word line layer 106 may then be formed (e.g., deposited) in an alternating sequence to form a first level 108 of the stack 102 (fig. 1). In some embodiments, the material 107 of the word line layer 106 may comprise a nitride material at this stage that will later be at least partially removed and replaced with a conductive material for forming word lines. In other embodiments, the material 107 of the word line layer 106 already includes conductive material for at least one word line at this stage in the fabrication process.

First level 108 is formed over base material 112, soft plug material 230, and sacrificial material 228. In some embodiments, the lower layers of the first level 108 may be formed directly on the upper surfaces of the base material 112, the soft plug material 230, and the sacrificial material 228. In other embodiments, an intermediate region may be formed therebetween.

An opening 232 may then be formed (e.g., by anisotropic etching) to extend through the first level 108 and through the soft plug material 230, stopping on the sacrificial material 228, such that a portion 234 is exposed at the base of the opening 232. Left along sidewalls 236 of sacrificial material 228 is a residue 238 of soft plug material 230.

Referring to fig. 3, the pad 340 is conformally formed asOpening 232 (fig. 2) is lined. The gasket 340 may define about(about 4nm) and(about 15nm) between(about 10 nm)).

The liner 340 comprises a material formulated such that the sacrificial material 228, the soft plug material 230, and the insulating material 105 can be at least partially removed without removing the liner 340. For example, the liner 340 may comprise, consist essentially of, or consist of polysilicon, metal, germanium (Ge), silicon germanium (SiGe), or nitride, depending on the composition of the sacrificial material 228, the soft plug material 230, and the insulating material 105 to be selectively etched in a later stage. For example, in embodiments in which the sacrificial material 228 comprises tungsten (W), the soft plug material 230 comprises an oxide, and the insulating material 105 comprises an oxide, the liner 340 may comprise, consist essentially of, or consist of polysilicon.

In some embodiments, liner 340 may be formed directly on the material of first layer 108, the soft plug material 230 of residue 238, and portion 234 (fig. 2) of sacrificial material 228. In other embodiments, one or more intermediate materials may be between. For example, an oxide liner formed (e.g., grown) by in-situ steam generation (ISSG) may be formed prior to forming liner 340.

Referring to fig. 4, a portion of the liner 340 (which may be referred to in the art as "punch-through") may be removed (e.g., anisotropically etched) to expose a portion 434 of the sacrificial material 228 at the base of the opening 432.

The opening 432 can then be filled to form the structure 500 shown in fig. 5 by forming (e.g., depositing) a fill material 536, which can be another sacrificial material. The fill material 536 comprises a material formulated to provide an etch stop during subsequent processing. Which may comprise, consist essentially of, or consist of any of the materials described above with respect to sacrificial material 228. The fill material 536 and the sacrificial material 228 may have the same or different compositions. For example, in some embodiments, the sacrificial material 228 may comprise, consist essentially of, or consist of tungsten (W), and the fill material 536 may comprise an oxide (e.g., aluminum oxide).

Referring to fig. 6, an upper portion of the fill material 536 can be removed (e.g., etched) to form a recess having a depth D into which another soft plug material 630 can be formed to fill the recess. The further cork material 630 may comprise, consist essentially of, or consist of any of the materials described above for the cork material 230.

The depth D may measure a height of one to about five of the layers 104/106 of the first deck 108. For example, the depth D may extend about the height of two layers (e.g., the height of the uppermost word line layer 106 and the uppermost insulating layer 104), as shown in fig. 6. The dimension of the depth D may be adapted to provide sufficient etchant exposure to a portion of the lower layers of the second level 110 (fig. 1), as described further below.

Referring to fig. 7, a second level 110 may be formed over the first level 108 to form a structure 700. The second deck 110 covers the cork material 630, wherein a lower layer of the second deck 110 is formed directly on an upper surface of the cork material 630, an upper surface of the liner 340 and an upper surface of an upper layer of the first deck 108. The insulating material 105 of the insulating layer 104 and the material 107 of the word line layer 106 may be formed (e.g., sequentially deposited) in the same manner as described above with respect to forming the first level 108.

Referring to fig. 8, an opening 832 is formed (e.g., by anisotropic etching) through layer 104/106 of second level 110 and into soft plug material 630. The openings 832 may be formed in substantially the same manner as the openings 232 (fig. 2) are formed, with the fill material 536 acting as an etch stop material. A residue 838 of the cork material 630 may remain along the sidewall portion 836 of the liner 340, wherein the portion 834 of the fill material 536 is exposed.

Referring to fig. 9, another liner 940 is conformally formed to line the opening 832 (fig. 8). The gasket 940 may include any of the materials used for the gasket 340 described aboveAnd by any of the processes described above for forming the liner 340. As such, liner 940 may be formed directly adjacent to the material of second level 110, the residue 838 of cork material 630, and portion 834 of fill material 536 (fig. 8). Alternatively, one or more materials (e.g., an oxide material grown by ISSG) may be disposed between liner 940 and the other materials. In some embodiments, the pads 940 in the openings 832 (fig. 8) in the second deck 110 may have the same composition as the pads 340 in the openings 232 (fig. 2) in the first deck 108. In other embodiments, the composition may be different. The liner 940 may define about(about 4nm) and(about 15nm) between(about 10 nm)).

In a manner similar to that described above for fig. 4, a portion of another liner 940 can be removed (e.g., etched ("stamped")), as shown in fig. 10, to expose a portion 1034 of the fill material 536 at the base of the opening 1032. A residue 838 of the cork material 630 may not be exposed in the opening 1032 due to the protection of the other liner 940.

The structure 1000 formed by the process stage of fig. 10 may then be exposed to an etchant selective to the fill material 536 and the sacrificial material 228 (relative to the materials of the soft plug materials 230, 630 and the liners 340, 940). For example, in embodiments in which the fill material 536 comprises alumina, the sacrificial material 228 comprises tungsten (W), and the liners 340, 940 comprise polysilicon, the etchant may comprise, for example, but is not limited to, hydrofluoric acid, hot hydrofluoric acid, ammonia-peroxide mixture (APM), or sulfuric acid (H), H₂SO₄) And hydrogen peroxide (H)₂O₂) To remove both the fill material 536 and the sacrificial material 228 while leaving the pads 340, 940. In some embodiments, the etchantThe chemistry may be adjusted during removal to first remove the fill material 536, and then remove the sacrificial material 228 after adjustment.

As shown in fig. 11, an opening 1132 is formed in which at least a portion of the soft plug material 230, 630 is exposed. In the portion of the opening 1132 that extends into the base material 112, the gap 1142 between the base material 112 and the residue 238 of the soft plug material 230 remains in the space previously occupied by the sacrificial material 228. In the portion of the opening 1132 that extends into the first deck 108, the bottom surface of the residue 838 of the cork material 630 is exposed, and the residue 838 remains along the depth D.

The remnants 238, 838 of the soft plug material 230, 630 may then be removed prior to or simultaneously with removing portions of the underlying layers (e.g., the lower insulating layer 104) of the first level 108 and the second level 110 in the areas indicated by circles X and Y in fig. 12. Removing these portions may include exposing the structure 1100 (fig. 11) to an etchant (relative to the material of the liners 340, 940) formulated selectively to the soft plug material 230, 630 and the insulating material 105. For example, in embodiments in which the liners 340, 940 comprise polysilicon and the soft plug material 230, 630 and insulating material 105 comprise oxide, the structure 1100 (fig. 11) may be exposed to an etchant comprising hydrofluoric acid (HF).

The etchant removes the residue 238, 838 of the soft plug material 230, 630 (fig. 11), thereby expanding the gap 1242 between the base material 112 and the liner 340 and forming a gap 1244 between the liner 340 and the liner 940 near the interface between the first and second levels 108, 110. Through the gaps 1242, 1244, the material of the lower layers of the respective levels 108, 110 is exposed to an etchant, and the etchant is formulated to also etch (e.g., isotropically etch) the material of the lower layers in these exposed regions. Accordingly, undercut portions 124, 126 are formed in at least the lower layers, as shown in circles X and Y, to form the opening 1232 shown in fig. 12. At the same time, the pads 340, 940 remain in place, providing protection for the other layers 104, 106 of the decks 108, 110. As such, the lower layers of each deck 108, 110 may be selectively etched relative to the other layers 104, 106 in the stack 102.

Because an isotropic etchant may be used to form the undercut portions 124, 126, the undercut portions 124, 126 define curved sidewall portions that extend along their depths.

The height of the gaps 1242, 1244 is due to previous processing stages. The gap 1242 between the base material 112 and the liner 340 extending along the first deck 108 has a depth D equal to (or approximately equal to) the height of the sacrificial material 228 (FIG. 2)_L. As such, the depth at which the region of sacrificial material 228 is formed prior to the stage of fig. 2 may indicate the depth D at which the etchant will wick to etch the material of the lower layer of first deck 108_L. Likewise, the gap 1244 between the pad 940 extending along the second level 110 and the pad 340 extending along the first level 108 has a depth D described above with respect to fig. 6, which is defined by the depth D at which the filler material 536 is recessed and filled with the soft plug material 630. Thus, depths D and D_LCan be adapted in view of the ability of the etchant to act on the exposed material at the top of the gaps 1242, 1244. For example, depths D and D_LMay be adapted to enable an etchant to "wick" up into the gaps 1242, 1244 and remove exposed material (e.g., insulating material 105) of lower layers of the respective levels 108, 110 to form the undercut portions 124, 126.

After forming the undercut portions 124, 126, the material of the liners 340, 940 may be removed to form the opening 1332 of fig. 13. For example, in embodiments where the liners 340, 940 comprise polysilicon, tetramethylammonium hydroxide (TMAH) may be used as an etchant to remove the liners 340, 940. However, any etchant may be used provided that it is selective to the material of the pads 340, 940 relative to the insulating material 105 of the insulating layer 104 and the material 107 of the word line layer 106 exposed by the removal of the pads 340, 940.

The opening 1332 extends through the entire stack 102 to form a channel opening that communicates through the first level 108, the second level 110 to the source region 114 that is at least partially exposed at the base of the opening 1332. The sidewalls 120 defining the opening 1332 are not constantly tapered through the height of the stack 102 or through the height of either of the levels 108, 110 because the undercut portions 124, 126 expand the width of the opening 1332 near the lower layer from which material is removed.

Although fig. 2-13 illustrate the process with two levels (e.g., first level 108 and second level 110) in stack 102, in other embodiments, stack 102 may have only one level (e.g., first level 108) or more than two levels. As each level other than the second level 110 is fabricated, the stages of fig. 7-10 may be repeated, and the formed structures of the multiple levels then undergo the stages of fig. 11-13 (e.g., the sacrificial material (e.g., the residue 238, 838 of the sacrificial material 228 and the soft plug material 230, 630) is then removed to define gaps 1242, 1244 that enable selective etching of the material of the lower layers of each level-accordingly, each of the lower layers of the respective levels 108, 110 of the stack 102 may be etched in the same stage to form the undercut portions 124, 126 at approximately the same point in the fabrication process.

With the described method embodiments, vertical scaling is achieved even as the depth of the channel opening (e.g., opening 1332 of fig. 13) increases, as the undercut portions 124, 126 provide wider access to the region at lower depths in the channel opening.

Although fig. 12 shows that only the lower layers (e.g., the lowest insulating layer 104) of each of the levels 108, 110 are exposed to and etched to form the undercut portions 124, 126, in other embodiments, the etch may be configured to remove material from more than the lower layers, for example, by etching for a longer period of time and/or etching with different etchant chemistries. Regardless, the undercut portions 124, 126 are defined by removing regions X, Y of material that would otherwise be occupied by the material of the layers 104, 106.

Cell material 122 described above with respect to fig. 1 may then be formed in opening 1332 defining undercut portions 124, 126, and, as shown in fig. 14, leaving an opening 1443 lined by cell material 122. Cell material 122 may be formed by a conformal deposition process known in the art and therefore not described in detail herein. As such, cell material 122 may be formed to initially cover source regions 114.

As shown in fig. 15, a liner 1540 may be conformally formed over cell material 122, leaving an opening 1543 lined by liner 1540. The liner 1540 includes a material formulated to protect the cell material 122 during subsequent processing. In some embodiments, liner 1540 may include any of the materials described above for liners 340 and 940. Pad 1540 may have the same composition and thickness as either or both pads 340, 940, or a different composition and/or thickness.

Referring to fig. 16, a portion of each of the liner 1540 and the cell material 122 may be removed (e.g., anisotropically etched) to expose the portion 118 of the source region 114 in the base of the opening 1640. Due to the earlier formation of the undercut portions 124, 126, a greater width of the source region 114 may be exposed for the height of the opening 1640 than is achievable by a conventional channel opening process that does not include forming the undercut portions 124, 126. The liner 1540 may or may not be subsequently removed, and fabrication of the semiconductor device is then completed to include the channel material within the channel opening 1640.

Accordingly, a method of forming a semiconductor device is disclosed. The method includes forming a stack of vertically alternating layers of insulating material and other materials over a base material, a sacrificial material disposed in the base material, and a soft plug material disposed in the sacrificial material. An opening is formed extending through the stack and through the cork material, leaving a residue of the cork material along sidewalls of the opening. A liner is formed in the opening. A portion of the sacrificial material is exposed through the liner. The remnants of the sacrificial material and the soft plug material are removed without removing the liner to define a gap between the liner and the sidewalls of the base material. The gap exposes a portion of the lower layers of the stack. The portion of the lower layer of the stack is etched to define an undercut portion in the lower layer of the stack. The liner is removed to form a channel opening extending through the stack and into the substrate material. The channel opening exposes a source region of the base material at a base of the channel opening. The channel opening is defined by a sidewall that includes an undercut portion.

Referring to fig. 17 through 22, another embodiment of forming the structure 100 of fig. 1 is shown. The stage in forming structure 1700 shown in figure 17 follows the stage in the process shown in figure 4 of the method described above. According to this embodiment, the fill material 1736 formed to fill the opening 432 of fig. 4 is formulated as an etch stop material. The filler material 1736 is not recessed and does not form a cork material (e.g., cork material 630).

Referring to fig. 18, the second level 110 is formed in the same manner as described with respect to fig. 7, except that a lower layer of the second level 110 is formed over the first level 108, the liner 340, and the fill material 1736. Thereby forming structure 1800.

Referring to fig. 19, the second level 110 is then etched down to the upper surface of the fill material 1736 to expose a portion 1934 of the fill material 1736 at the base of the opening 1932. The etching process may be the same process as described above with respect to fig. 8.

Referring to fig. 20, then pads 940 may be formed in the same manner as described above with respect to fig. 9, except that pads 940 completely cover the sidewalls of layers 104, 106 of second level 110 and do not extend into the elevation of first level 108.

Referring to fig. 21, the liner 940 may be partially removed to expose a portion 2134 of the fill material 1736 at the base of the opening 2132 in the same manner as described above with respect to fig. 10, except that the exposed portion 2134 of the fill material 1736 is coplanar with the lower surface of the lower layer of the second layer 110.

The fill material 1736 and sacrificial material 228 may then be removed (e.g., excavated) in a manner similar to the removal of the fill material 536 and sacrificial material 228 in the stage of fig. 11 described above. The residue 238 of the soft plug material 230 may then be removed in the same manner as described above with respect to fig. 11. This exposes at least portions (in circles X 'and Y' of fig. 22) of the material of the lower layer (e.g., the insulating material 105 of the lower layer) of each of the levels 108, 110, which can then be isotropically etched in the same manner as in fig. 12 to define the undercut portions 124, 126 of fig. 1.

However, according to the embodiment of fig. 17-22, the lower layers of the second layer 110 are directly exposed into the openings 2232 without an intervening gap (e.g., gap 1244 of fig. 12). However, at least a portion of the lower layer is etched to define the undercut portion 126 of fig. 13. Fig. 13 follows the stage of fig. 22, and the process may continue as previously described to form the structure 100 of fig. 1. Although the undercut portion 126 formed by the embodiment including fig. 17-22 may have a different size or shape than the undercut portion 126 formed by the embodiment including fig. 2-16, the undercut portion 126 widens the portion that would otherwise be the narrower bottleneck point of the opening 1332 (fig. 13) and the final opening 1640 (fig. 16) and subsequently formed channel pillars.

As with the embodiments described above, the stages of fig. 17-21 may be repeated a variable number of times to form additional levels of layers 104, 106 to vertically enlarge the structure, followed by removal of each level of fill material 1736 and sacrificial material 228 in base material 112 to expose portions of the lower layers of each level.

In some embodiments, a region may also have been formed in the base material 112 below the first layer face 108 using the fill material 1736, such as the region occupied by the sacrificial material 228 and the soft plug material 230 according to the embodiments described above. In such alternative embodiments, the opening 232 of fig. 2 would have a lower surface that is coplanar with the lower surface of the first deck 108 and exposes a portion of the fill material, such as the fill material 1736 (if used in place of the sacrificial material 228 and the soft plug material 230). The pads (e.g., pads 340) that pass through the first deck 108 will extend to a lower elevation that is coplanar with the lower surface of the first deck 108, and later removal of the fill material 1736 will thus expose a portion of the lower layers of the first deck 108 in a manner similar to the second deck 110 described with respect to fig. 22. However, the subsequent isotropic etch will selectively etch into the lower layers of each level 108, 110, while the other layers of levels 108, 110 are protected by the liners 340, 940. Also, the undercut portions 124, 126 will form and make wider access to expose the source region 114 at the bottom of the channel opening.

In other embodiments, the process of forming the soft plug material 230, 630, the residue 238, 838, and the subsequent gap 1242, 1244 to expose portions of the underlying layer material may be used with some layers of the stack 102, while the process of fig. 17-22 may be used with some other layers of the stack 102.

Accordingly, a method of forming a semiconductor device is disclosed. The method includes forming a first level of vertically alternating layers of insulating and other materials over a base material and a sacrificial material disposed in the base material. An opening is formed through the first level and into the sacrificial material. A liner and a fill material are formed within the opening. A second level of vertically alternating layers of insulating and other materials is formed over the first level, the liner, and the fill material. Another opening is formed extending through the second level to the fill material within the other opening. Another liner is formed within the other opening, and a portion of the fill material is exposed through the other liner. The filler material and the sacrificial material are removed to form an extended opening exposing at least a portion of the lower layer of each of the first level and the second level without removing the liner or another liner. The portion of the lower layer of each of the first and second levels is isotropically etched to define an undercut portion. The liner and another liner are removed to form a channel opening defined by a sidewall that includes an undercut portion.

Referring to fig. 23, a structure 2300 of a semiconductor device is shown in which a channel pillar 2348 has been formed by forming a channel material 2350 within the space of the opening 116 (fig. 1). The channel material 2350 of the channel post 2348 extends through all levels of the stack 102 (e.g., through the first level 108 and the second level 110) into the base material 112 to contact the exposed portion 118 at the bottom of the channel opening 116 (fig. 1).

Because the dopants providing the source regions 114 (fig. 1) of the structure 100 (fig. 1) may alternatively be included along more regions of the base material 112, source regions 2314, such as shown in fig. 23, may be included, the source regions 2314 extending horizontally a greater distance than the discrete regions of the source regions 114 in the base material 112 of fig. 1.

The trench posts 2348 define shoulders along the undercut portions 124, 126. The shoulders are formed by filling the undercut portions 124, 126 with channel material 2350. As such, the channel pillar 2348 has a sidewall 2320 along the cell material 122, and the sidewall 2320 tapers inward through the second level 110, expands outward through the undercut portion 126, tapers inward again through the first level 108, expands outward again through the undercut portion 124, and then tapers inward again toward the source region 2314, in accordance with embodiments of the present disclosure. Because the undercut portions 124, 126 may be formed by isotropic etching, corresponding shoulder portions of the channel posts 2348 may define curved portions of the sidewalls 2320.

In some embodiments, the structure 2300 including the channel post 2348 may further include CMOS (complementary metal oxide semiconductor) circuitry 2360 below the channel post 2348 (e.g., the source region 2314). This structure 2300 can be characterized as having "array-below CMOS" ("CuA") components. The area comprising CMOS circuitry 2360 may be spaced apart from source regions 2314 by one or more intermediate materials, such as additional regions 2370 of base material 112.

In embodiments having CMOS components under the array, the base material 112 may comprise polysilicon. In embodiments without underlying CMOS components of the array, the base material 112 may comprise polycrystalline silicon or monocrystalline silicon.

Referring to FIG. 24, an enlarged view of block A of FIG. 23 is shown, according to an alternative embodiment. In embodiments such as this embodiment, the channel material 2350 may not completely fill the width of the channel pillar 2348 (fig. 23), but may be formed to line the sidewalls 2320 of the channel pillar 2348. Another material or void space (collectively 2448) may fill the central portion of the channel pillar 2348.

Fig. 24 also shows example material 107 for word line layer 106. Such material 107 can include conductive material 2452 (e.g., of gates (e.g., control gates, floating gates), charge traps, and/or storage devices) in addition to access lines (word lines); insulating material 2454 (e.g., of inter-gate dielectric regions), and other materials 2456. In some embodiments, conductive material 2452 may be present in word line layer 106 prior to, for example, the stage of fig. 2. In other embodiments, the conductive material 2452 may be formed by replacing selective portions of the material 107 of the word line layer 106 after forming the undercut portions 124, 126, such as after the stage of fig. 13 but before forming the cell material 122.

Accordingly, a semiconductor device is disclosed that includes a stack of vertically alternating layers over a base material and over CMOS circuit components. The vertically alternating layers include layers comprising insulating material vertically interleaved with layers comprising word lines. The channel pillar extends through the stack and into the base material to a source region at the base of the channel pillar. The sidewalls of the channel posts define shoulder portions laterally adjacent to at least a lower layer of the stack of vertically alternating layers.

Referring to fig. 25, a simplified block diagram of a semiconductor device 2500 implemented in accordance with one or more embodiments described herein is shown. The semiconductor device 2500 includes a memory array 2502 having a 3D NAND architecture and a control logic component 2504. The memory array 2502 may include a plurality of structures 100 (fig. 1), 2300 (fig. 23) including any of a stack of vertically alternating layers that may have been formed according to the methods described above that define undercut portions 124, 126 along at least a lower layer of each level of the stack discussed above. Control logic component 2504 may be configured to operatively interact with memory array 2502 to read from or write to any or all memory cells within memory array 2502, e.g., devices having structure 100 (fig. 1) or 2300 (fig. 23).

Referring to fig. 26, a processor-based system 2600 is depicted. The processor-based system 2600 may include various electronic devices manufactured in accordance with embodiments of the present disclosure. The processor-based system 2600 may be any of a number of types, such as a computer, pager, cellular telephone, personal assistant, control circuit, or other electronic device. The processor-based system 2600 may include one or more processors 2602, such as microprocessors, to control processing of system functions and requests in the processor-based system 2600. The processor 2602 and other subcomponents of the processor-based system 2600 may include semiconductor devices (e.g., 3D NAND memory devices) manufactured in accordance with embodiments of the present disclosure.

The processor-based system 2600 may include a power supply 2604 in operable communication with the processor 2602. For example, if the processor-based system 2600 is a portable system, the power supply 2604 may include one or more of a fuel cell, a power harvesting device (power harvesting device), a permanent battery, a replaceable battery, and a rechargeable battery. For example, power supply 2604 may also include an AC adapter; thus, the processor-based system 2600 may be plugged into a wall outlet. For example, the power supply 2604 may also include a DC adapter such that the processor-based system 2600 may be plugged into a vehicle cigarette lighter or a vehicle power port.

Various other devices may be coupled to the processor 2602 depending on the functions performed by the processor-based system 2600. For example, a user interface 2606 may be coupled to the processor 2602. The user interface 2606 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touch screens, voice recognition systems, microphones, or combinations thereof. A display 2608 may also be coupled to the processor 2602. The display 2608 may include an LCD display screen, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a three-dimensional projection, an audio display, or a combination thereof. Further, an RF sub-system/baseband processor 2610 may also be coupled to the processor 2602. The RF subsystem/baseband processor 2610 may include an antenna (not shown) coupled to an RF receiver and an RF transmitter. A communication port 2612 or more than one communication port 2612 may also be coupled to the processor 2602. For example, the communication port 2612 may be adapted to couple to one or more peripheral devices 2614, such as a modem, printer, computer, scanner, or camera; or to a network such as a local area network, remote area network, intranet, or the internet.

The processor 2602 may control the processor-based system 2600 by implementing software programs stored in the memory. For example, the software program may include an operating system, database software, drawing software, word processing software, media editing software, or media playing software. The memory is operatively coupled to the processor 2602 to store and facilitate execution of various programs. For example, the processor 2602 may be coupled to a system memory 2616, which may include memory having a 3D NAND architecture, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), racetrack memory, and other known memory types. The system memory 2616 can include volatile memory, non-volatile memory, or combinations thereof. The system memory 2616 is typically large so that it can dynamically store loaded applications and data. In some embodiments, the system memory 2616 may include a semiconductor device, such as the semiconductor device 2500 of fig. 25, a semiconductor device including the structures 100 (fig. 1), 2300 (fig. 23) described above, or a combination thereof.

The processor 2602 may also be coupled to non-volatile memory 2618, which does not suggest that the system memory 2616 be necessarily volatile. The non-volatile memory 2618 can include one or more of NAND (e.g., 3D NAND) memory, Read Only Memory (ROM) such as EPROM, Resistive Read Only Memory (RROM), and other flash memory to be used in connection with the system memory 2616. The size of non-volatile memory 2618 is typically selected to be just large enough to store any necessary operating system, application programs, and fixed data. Further, the non-volatile memory 2618 may include high capacity memory such as disk drive memory, for example, a hybrid drive including resistive memory or other types of non-volatile solid state memory. The non-volatile memory 2618 may include a semiconductor device, such as a semiconductor device including the structure 100 of figure 1 or 2300 of figure 23 described above, or a combination thereof.

Accordingly, a system is disclosed that includes a three-dimensional array of memory devices that includes a stack of insulating layers interleaved with word line layers and includes channel pillars extending through the stack to source regions. The channel strut has a sidewall defining a curved surface along at least a portion of the sidewall. At least one processor is coupled to a three-dimensional array of memory devices. At least one peripheral device is in operable communication with the at least one processor.

While the disclosure may be susceptible to various modifications and alternative forms in its implementation, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the invention is not intended to be limited to the particular forms disclosed. Rather, the disclosure covers all modifications, combinations, equivalents, variations, and alternatives falling within the scope of the disclosure as defined by the appended claims and their legal equivalents.