阅读说明：本技术 跨时钟域同步电路以及方法 (Clock domain crossing synchronization circuit and method ) 是由 白玉晶 于 2019-03-26 设计创作，主要内容包括：本申请实施例公开了一种跨时钟域同步电路,本申请跨时钟域同步电路包括时钟域通道电路、写地址产生电路、读地址产生电路和数据缓存电路,写地址产生电路用于根据写使能信号得到写地址,写地址用于控制数据缓存电路接收输入数据,输入数据处于写时钟域；时钟域通道电路用于对写使能信号进行采样以得到多个采样结果,并根据时钟相位差从多个采样结果中选择一个采样结果作为读使能信号,时钟相位差为处于写时钟域的写时钟信号和处于读时钟域的读时钟信号的相位差；读地址产生电路用于根据读使能信号得到读地址,读地址用于控制数据缓存电路产生输出数据,输出数据处于读时钟域；数据缓存电路用于根据写地址和读地址,将输入数据缓存并产生输出数据。(The embodiment of the application discloses a clock domain crossing synchronization circuit, which comprises a clock domain channel circuit, a write address generating circuit, a read address generating circuit and a data cache circuit, wherein the write address generating circuit is used for obtaining a write address according to a write enable signal, the write address is used for controlling the data cache circuit to receive input data, and the input data is in a write clock domain; the clock domain channel circuit is used for sampling the write enable signal to obtain a plurality of sampling results, selecting one sampling result from the plurality of sampling results as a read enable signal according to a clock phase difference, wherein the clock phase difference is the phase difference between the write clock signal in the write clock domain and the read clock signal in the read clock domain; the read address generating circuit is used for obtaining a read address according to the read enable signal, the read address is used for controlling the data cache circuit to generate output data, and the output data is in a read clock domain; the data buffer circuit is used for buffering input data and generating output data according to the write address and the read address.)