阅读说明：本技术 感测两个存储器单元以确定一个数据值 (Sensing two memory cells to determine a data value ) 是由 F·佩里兹 于 2021-05-06 设计创作，主要内容包括：本公开包含用于感测两个存储器单元以确定一个数据值的设备、方法及系统。实施例包含具有多个存储器单元的存储器及经配置以感测两个存储器单元中的每一个的存储器状态以确定一个数据值的电路系统。通过以下操作来确定一个数据值：在对应于第一存储器状态的第一阈值电压分布与对应于第二存储器状态的第二阈值电压分布之间的感测窗中使用第一感测电压来感测所述两个存储器单元中的第一个的所述存储器状态,且在所述感测窗中使用第二感测电压来感测所述两个存储器单元中的第二个的所述存储器状态。所述第一感测电压及所述第二感测电压在所述感测窗中选择性地更靠近于所述第一阈值电压分布或所述第二阈值电压分布。(The present disclosure includes apparatus, methods, and systems for sensing two memory cells to determine one data value. Embodiments include a memory having a plurality of memory cells and circuitry configured to sense a memory state of each of two memory cells to determine one data value. Determining a data value by: the memory state of a first one of the two memory cells is sensed using a first sensing voltage in a sensing window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state, and the memory state of a second one of the two memory cells is sensed using a second sensing voltage in the sensing window. The first and second sensing voltages are selectively closer to the first or second threshold voltage distributions in the sensing window.)

1. An apparatus having two memory cells to determine a data value, comprising:

a memory (100, 306) having a plurality of memory cells (125); and

circuitry (305, 324) configured to sense a memory state of each of two memory cells (201-1, 204-1) of the plurality of memory cells (125) to determine one data value by:

sensing a memory state (202-1) of a first (201-1) of the two memory cells (201-1, 204-1) using a first sense voltage (211-1) in a sense window (212-1) between a first threshold voltage distribution (208-1) corresponding to a first memory state (202-1) and a second threshold voltage distribution (208-2) corresponding to a second memory state (202-2); and

sensing the memory state (202-2) of a second (204-1) of the two memory cells (201-1, 204-1) using a second sensing voltage (210-1) in the sensing window (212-1);

wherein the first sensing voltage (211-1) and the second sensing voltage (210-1) are selectively closer to the first threshold voltage distribution (208-1, 209-1) or the second threshold voltage distribution (208-2, 209-2) in the sensing window (212-1).

2. The apparatus of claim 1, wherein the circuitry (305, 324) is further configured to program the one data value by:

applying a first voltage pulse to the first memory cell (201-1), wherein the first memory cell (201-1) stores its memory state (202-1) as an expected data value corresponding to the one data value; and is

Applying a second voltage pulse to the second memory cell (204-1), wherein the second memory cell (204-1) stores its memory state (202-2) as a reference data value corresponding to the expected data value.

3. The apparatus of claim 1, wherein the first sensing voltage (211-1) and the second sensing voltage (210-1) are selectively closer to different ones of the first threshold voltage distribution (208-1, 209-1) and the second sensing voltage (210-1) in the sensing window (212-1).

4. The apparatus of any of claims 1-3, wherein the circuitry (305, 324) is configured to further determine the one data value by:

comparing the sensed memory state of each of the two memory cells (201-1, 204-1);

verifying that the memory state (202-1) of the first memory cell (201-1) is the expected data value corresponding to the one data value by determining that the sensed memory state is a complementary binary memory state; and

determining a switching of the memory states of the two memory cells (201-1, 204-1) by determining that the sensed memory state matches a binary memory state.

5. The apparatus of any of claims 1-3, wherein the sensed memory states include a memory state of a first subset of the plurality of memory cells (125) associated with the first threshold voltage distribution (208-1), a relative magnitude of the memory states being greater for a particular polarity than a different one of the two memory states of a second subset of the plurality of memory cells (125) associated with the second threshold voltage distribution (208-2).

6. The apparatus of any of claims 1-3, wherein the circuitry (305, 324) is further configured to:

storing the memory state (202-1) of the first memory cell (201-1) in association with a particular end of the sensing window (212-1) having a particular magnitude of polarity; and

storing the memory state (202-2) of the second memory cell (204-1) in association with opposite ends of the sensing window (212-1) having different magnitudes of the polarity;

wherein the polarity may be selected from a positive polarity and a negative polarity.

7. The apparatus of claim 1, wherein each of the two memory cells (201-1, 204-1) is a self-selected memory cell in which a single material is used as a select element and a storage element, and wherein the single material is a chalcogenide material.

8. An apparatus having two memory cells to determine a data value, comprising:

circuitry (305, 324) in a memory device (302), the circuitry (305, 324) configured to:

sensing a memory state of each of two memory cells (201-1, 204-1) of a plurality of memory cells (125) to determine a data value by:

sensing the memory state of a first (201-1) of the two memory cells (201-1, 204-1) using a first sensing voltage (211-1) in a sensing window (212-1) between a first threshold voltage distribution (208-1) corresponding to a first memory state (202-1) and a second threshold voltage distribution (208-2) corresponding to a second memory state (202-2);

sensing the memory state of a second (204-1) of the two memory cells (201-1, 204-1) using a second sensing voltage (210-1) in the sensing window (212-1); and

determining which of the two memory cells (201-1, 204-1) switches its memory state due to a shift in the sense window (212-1) of the magnitude of the first threshold voltage distribution (208-1) relative to the first sense voltage (211-1);

wherein the magnitude of the first sensing voltage (211-1) is selectively closer to the first threshold voltage distribution (208-1, 209-1) than to the second threshold voltage distribution (208-2, 209-2) in the sensing window (212-1).

9. The apparatus of claim 8, wherein the switching of the memory state is due to a shift in magnitude of the second threshold voltage distribution (208-2) relative to the second sense voltage (210-1) in the sense window (212-1).

10. The apparatus of any of claims 8 to 9, wherein:

one end of the sensing window (212-1) corresponds to a programmed memory state of a first memory cell, and the other end of the polarity of the sensing window (212-1) corresponds to a complementary reprogrammed memory state of the first memory cell (201-1); and is

Which end of the sensing window (212-1) corresponds to the programmed memory state, and which other end of the sensing window (212-1) corresponds to the complementary reprogrammed memory state is determined by:

a first number of voltage pulses applied to the first memory cell (201-1) to program the first memory cell (201-1) to a magnitude less than the first sense voltage (211-1) in the sense window (212-1); and

a second number of voltage pulses, different from the first number, applied to the first memory cell (201-1) to program the first memory cell (201-1) to a magnitude greater than the second sensing voltage (210-1) in the sensing window (212-1).

11. The apparatus of any of claims 8 to 9, wherein:

one end of the sensing window (212-1) corresponds to a programmed memory state (202-1) of a first memory cell (201-1), and the other end of the polarity of the sensing window (212-1) corresponds to a complementary reprogrammed memory state of a second memory cell (204-1); and is

Which end of the sensing window (212-1) corresponds to the programmed memory state, and which other end of the sensing window (212-1) corresponds to the complementary reprogrammed memory state is determined by:

a first number of voltage pulses applied to the first memory cell (201-1) to program the first memory cell (201-1) to a magnitude less than the first sense voltage (211-1) in the sense window (212-1); and

a second number of voltage pulses, different from the first number, applied to the second memory cell (204-1) to program the second memory cell (204-1) to a magnitude greater than the second sensing voltage (210-1) in the sensing window (212-1).

12. The apparatus of claim 8, wherein:

the circuitry (305, 324) is associated with a truth table (213) for implementing:

comparing the sensed memory state (202-1) of the first memory cell (201-1) with the sensed memory state (202-2) of the second memory cell (204-1) in a binary memory state;

determining the switching of the memory state due to the shifting by determining that the sensed memory states match; and

determining which of the two memory cells (201-1, 204-1) has switched from one memory state to another, and in response to the determination, the circuitry (305, 324) is configured to reprogram the memory cell having switched back to the one memory state to enable the one data value to be determined as expected from the memory states of the two memory cells (201-1, 204-1).

13. A method of operating a memory having two memory cells to determine a data value, the method comprising:

sensing a memory state of each of two memory cells (201-1, 204-1) of the plurality of memory cells (125) to determine a data value by:

sensing the memory state of a first (201-1) of the two memory cells (201-1, 204-1) using a first sensing voltage (211-1) in a sensing window (212-1) between a first threshold voltage distribution (208-1) corresponding to a first memory state (202-1) and a second threshold voltage distribution (208-2) corresponding to a second memory state (202-2);

sensing the memory state of a second (204-1) of the two memory cells (201-1, 204-1) using a second sensing voltage (210-1) in the sensing window (212-1); and

the first sensing voltage (211-1) and the second sensing voltage (210-1) are selectively positioned closer to the first threshold voltage distribution (208-1, 209-1) or the second threshold voltage distribution (208-2, 209-2) in the sensing window (212-1).

14. The method of claim 13, further comprising:

selecting the first sensing voltage (211-1) and the second sensing voltage (210-1) to both have a negative polarity or a positive polarity; and

the first sense voltage (211-1) is positioned closer to the first threshold voltage distribution (208-1) than the second threshold voltage distribution (208-2), and the second sense voltage (210-1) is positioned closer to the second threshold voltage distribution (208-2) than the first threshold voltage distribution (208-1), or vice versa.

15. The method of claim 13, further comprising:

selecting the first sensing voltage (211-1) and the second sensing voltage (210-1) to both have the same magnitude; and

both the first sensing voltage (211-1) and the second sensing voltage (210-1) are positioned closer to the second threshold voltage distribution (208-2) than the first threshold voltage distribution (208-1), or vice versa.

16. A method of operating a memory having two memory cells to determine a data value, the method comprising:

sensing a memory state of each of two memory cells (201-1, 204-1) to determine a data value by:

sensing the memory state of a first (201-1) of the two memory cells (201-1, 204-1) using a first sensing voltage (211-1) in a sensing window (212-1) between a first threshold voltage distribution (208-1) corresponding to a first memory state (202-1) and a second threshold voltage distribution (208-2) corresponding to a second memory state (202-2);

sensing the memory state of a second (204-1) of the two memory cells (201-1, 204-1) using a second sensing voltage (210-1) in the sensing window (212-1);

selecting a magnitude of the first sense voltage (211-1) in the sensing window (212-1) to be closer to a first magnitude determined to correspond to a first margin of the first threshold voltage distribution (208-1, 209-1) than a second magnitude determined to correspond to a second margin of the second threshold voltage distribution (208-2, 209-2); and

determining which of the two memory cells (201-1, 204-1) switches its data state due to a shift of the first threshold voltage distribution (208-1, 209-1) relative to the first magnitude by:

comparing an inverse of a pair of memory states determined to be reliable for the first memory cell and the second memory cell to the sensed memory states of the first memory cell and the second memory cell; and

determining which of the two memory cells (201-1, 204-1) has switched its memory state based on which memory cell has a sensed memory state that is different from the inverse of the pair of memory states of the first and second memory cells.

17. The method of claim 16, further comprising:

in response to determining which of the two memory cells (201-1, 204-1) has switched its memory state, reprogramming the memory cell that has switched its memory state back to its complementary memory state; and

the one data value is determined as expected from complementary memory states of the two memory cells (201-1, 204-1).

18. The method of any one of claims 16-17, further comprising:

programming the two memory cells (201-1, 204-1) at negative polarity with one of a pair of complementary memory states for the first memory cell (201-1) and the other of the pair for the second memory cell (204-1) to obtain a negative read;

designating the first memory cell (201-1) to store a reference memory state;

designating the second memory cell (204-1) to store an expected memory state to be compared to the reference memory state of the first memory cell (201-1);

determining a difference between the first memory state (202-1) and the second memory state (202-2) based on a difference in magnitude of an absolute value of a voltage stored by each of the two memory cells (201-1, 204-1), wherein memory cells having voltage values in a threshold voltage distribution with a smaller magnitude are in the first memory state (202-1) and memory cells having voltage values in a threshold voltage distribution with a larger magnitude are in the second memory state (202-2);

selectively positioning the first sensing voltage (211-1) in the sensing window (212-1) at a magnitude greater than and at an edge of the threshold voltage distribution having the smaller magnitude; and

selectively positioning a second sensing voltage (210-1) in the sensing window (212-1) at a magnitude smaller than and at an edge of the threshold voltage distribution having the larger magnitude.

19. The method of any one of claims 16-17, further comprising:

programming the two memory cells (201-1, 204-1) at positive polarity for a positive read using one of a pair of complementary memory states for the first memory cell (201-1) and the other of the pair for the second memory cell (204-1);

designating the first memory cell (201-1) to store an expected memory state;

designating the second memory cell (204-1) to store a reference memory state to be compared to the expected memory state of the first memory cell (201-1);

determining a difference between the first memory state (202-1) and the second memory state (202-2) based on a difference in magnitude of an absolute value of a voltage stored by each of the two memory cells (201-1, 204-1), wherein memory cells having voltage values in a threshold voltage distribution with a larger magnitude are in the first memory state (202-1) and memory cells having voltage values in a threshold voltage distribution with a smaller magnitude are in the second memory state (202-2);

selectively positioning the first sensing voltage (211-1) in the sensing window (212-1) at a magnitude greater than and at an edge of the threshold voltage distribution having the smaller magnitude; and

selectively positioning a second sensing voltage (210-1) in the sensing window (212-1) at a magnitude smaller than and at an edge of the threshold voltage distribution having the larger magnitude.

20. The method of any one of claims 16-17, further comprising:

programming the two memory cells (201-1, 204-1) at negative polarity to obtain a negative read using one of a pair of complementary memory states for the first memory cell (201-1) and the same one of the pair for the second memory cell (204-1);

designating the first memory cell (201-1) to store an expected memory state;

designating the second memory cell (204-1) to store a reference memory state to be compared to the expected memory state of the first memory cell (201-1);

determining a difference between the first memory state (202-1) and the second memory state (202-2) based on a difference in magnitude of an absolute value of a voltage that may be stored by each of the two memory cells (201-1, 204-1), wherein memory cells having voltage values in a threshold voltage distribution with a smaller magnitude are in the first memory state (202-1) and memory cells having voltage values in a threshold voltage distribution with a larger magnitude are in the second memory state (202-2); and

selectively positioning the first sense voltage at a magnitude smaller than and at an edge of the threshold voltage distribution having the larger magnitude for the first memory cell (201-1) and the second memory cell (204-1).

21. The method of any one of claims 16-17, further comprising:

programming the two memory cells (201-1, 204-1) at positive polarity for a positive read using one of a pair of complementary memory states for the first memory cell (201-1) and the same one of the pair for the second memory cell (204-1);

designating the first memory cell (201-1) to store an expected memory state;

designating the second memory cell (204-1) to store a reference memory state to be compared to the expected memory state of the first memory cell (201-1);

determining a difference between the first memory state (202-1) and the second memory state (202-2) based on a difference in magnitude of an absolute value of a voltage that may be stored by each of the two memory cells (201-1, 204-1);

wherein memory cells having voltage values in a threshold voltage distribution with a greater magnitude are in the first memory state and memory cells having voltage values in a threshold voltage distribution with a lesser magnitude are in the second memory state; and

the first sense voltage (211-1) is selectively positioned at a magnitude greater than and at an edge of the threshold voltage distribution having the lesser magnitude for the first memory cell (201-1) and the second memory cell.

Technical Field

The present disclosure relates generally to semiconductor memories and methods, and more particularly, to sensing two memory cells to determine one data value.

Background

Memory devices are typically provided as internal semiconductor integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and may include Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when power is not supplied, and can include nand flash memory, nor flash memory, Read Only Memory (ROM), and resistance variable memory, such as Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Magnetic Random Access Memory (MRAM), and programmable conductive memory, among others.

Memory devices may be used as volatile and non-volatile memory in a wide range of electronic applications requiring high memory density, high reliability, and/or low power consumption. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, Solid State Drives (SSDs), digital cameras, cellular telephones, portable music players such as MP3 players, and movie players, among other electronic devices.

Variable resistance memory devices may include resistance variable memory cells that may store data based on the resistance state of a storage element (e.g., a memory element having a variable resistance). As such, a resistance variable memory cell can be programmed to store data corresponding to a target memory state by varying the resistance level of the memory element. A resistance variable memory cell can be programmed to a target memory state (e.g., corresponding to a particular resistance state) by applying an electric field or energy source, such as a positive or negative electrical pulse (e.g., a positive or negative voltage or current pulse) to the memory cell (e.g., to a memory element of the memory cell) for a particular duration of time. The state of a resistance variable memory cell can be determined by sensing the current through the memory cell in response to an applied interrogation voltage. The sense current, which varies based on the resistance level of the memory cell, may indicate the state of the memory cell.

Various memory arrays may be organized in a cross-point architecture, where memory cells (e.g., resistance variable memory cells) are located at an intersection of a first signal line and a second signal line (e.g., a cross-point of a word line and a bit line) for accessing the memory cells. Some resistance variable memory cells may include a selection element (e.g., a diode, transistor, or other switching device) in series with a storage element (e.g., a phase change material, a metal oxide material, and/or some other material programmable to a different level). Some resistance variable memory cells, which may be referred to as self-selected memory cells, may comprise a single material that may be used as both a selection element and a storage element of the memory cell.

Disclosure of Invention

Aspects of the present disclosure are directed to an apparatus having two memory cells to determine a data value, the apparatus comprising: a memory having a plurality of memory cells; and circuitry configured to sense a memory state of each of two of the plurality of memory cells to determine one data value by: sensing the memory state of a first one of the two memory cells using a first sensing voltage in a sensing window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state; and sensing the memory state of a second of the two memory cells using a second sensing voltage in the sensing window; wherein the first sensing voltage and the second sensing voltage are selectively closer to the first threshold voltage distribution or the second threshold voltage distribution in the sensing window.

Another aspect of the disclosure is directed to an apparatus having two memory cells to determine a data value, comprising: circuitry in a memory device, the circuitry configured to: sensing a memory state of each of two of the plurality of memory cells to determine a data value by: sensing the memory state of a first one of the two memory cells using a first sensing voltage in a sensing window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state; sensing the memory state of a second of the two memory cells using a second sensing voltage in the sensing window; and determining which of the two memory cells switched its memory state due to a shift in the sensing window of the magnitude of the first threshold voltage distribution relative to the first sensing voltage; wherein the magnitude of the first sensing voltage is selectively closer to the first threshold voltage distribution than to the second threshold voltage distribution in the sensing window.

Another aspect of the present disclosure is directed to a method of operating a memory having two memory cells to determine a data value, the method comprising: sensing a memory state of each of two memory cells of the plurality of memory cells to determine a data value by: sensing the memory state of a first one of the two memory cells using a first sensing voltage in a sensing window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state; sensing the memory state of a second of the two memory cells using a second sensing voltage in the sensing window; and selectively positioning the first sensing voltage and the second sensing voltage closer to the first threshold voltage distribution or the second threshold voltage distribution in the sensing window.

Yet another aspect of the present disclosure is directed to a method of operating a memory having two memory cells to determine one data value, the method comprising: sensing a memory state of each of two memory cells to determine a data value by: sensing the memory state of a first one of the two memory cells using a first sensing voltage in a sensing window between a first threshold voltage distribution corresponding to a first memory state 202-1 and a second threshold voltage distribution corresponding to a second memory state; selecting a magnitude of the first sense voltage in the sense window to be closer to a first magnitude determined to correspond to a first margin of the first threshold voltage distribution than a second magnitude determined to correspond to a second margin of the second threshold voltage distribution; and determining which of the two memory cells switched its data state due to the shift in the first threshold voltage distribution relative to the first magnitude by: comparing an inverse of a pair of memory states determined to be reliable for the first memory cell and the second memory cell to the sensed memory states of the first memory cell and the second memory cell; and determining which of the two memory cells has switched its memory state based on which memory cell has a sensed memory state that is different from the inverse of the pair of memory states of the first memory cell and the second memory cell.

Drawings

Figure 1 is a three-dimensional view of an example of a memory array according to an embodiment of the present disclosure.

FIG. 2A illustrates an example of a sensing threshold voltage distribution associated with a memory state of a memory cell of two memory cells sensed to determine a plurality of data values, according to an embodiment of the disclosure.

FIG. 2B is an example of a current versus voltage curve for a memory state corresponding to the threshold voltage distribution shown in FIG. 2A, according to an embodiment of the present disclosure.

FIG. 2C is an example of a current versus voltage curve for another memory state corresponding to the threshold voltage distribution shown in FIG. 2A, according to an embodiment of the present disclosure.

FIG. 2D is another example of a sensing threshold voltage distribution associated with memory states of memory cells of two memory cells being sensed to determine one data value according to another embodiment of the present disclosure.

Fig. 2E is another such example in accordance with another embodiment of the present disclosure.

Fig. 2F is another such example in accordance with another embodiment of the present disclosure.

Fig. 2G is other such examples according to other embodiments of the present disclosure.

Fig. 3 is a block diagram illustration of an example apparatus in accordance with an embodiment of the disclosure.

Detailed Description

The present disclosure includes apparatus, methods, and systems for sensing two memory cells to determine one data value. Embodiments include a memory having a plurality of memory cells and circuitry configured to sense a memory state of each of two of the plurality of memory cells to determine one data value. Determining a data value by: a memory state of a first one of the two memory cells is sensed using a first sensing voltage in a sensing window between a first threshold voltage distribution corresponding to the first memory state and a second threshold voltage distribution corresponding to the second memory state, and a memory state of a second one of the two memory cells is sensed using a second sensing voltage in the sensing window. The first and second sensing voltages are selectively closer to the first or second threshold voltage distributions in the sensing window.

Embodiments of the present disclosure may provide benefits over previous memory devices, such as increasing the reliability and accuracy of data sensing and/or increasing the speed and reducing the complexity of data correction operations. For example, previous methods for programming resistance variable memory cells, such as a self-selected memory cell, may generate one of two different states such that each of the memory cells may be programmed to one of two possible memory states (e.g., state 0 or state 1). In such approaches, a single sensing voltage may be substantially at a median voltage separation in a sensing (e.g., read) window between a first threshold voltage distribution corresponding to a first memory state (e.g., state 0) and a second threshold voltage distribution (e.g., storage voltage distribution of a second number of memory cells) corresponding to a second memory state (e.g., state 1). Each of the first and second threshold voltage distributions may represent separate distributions of storage voltages for a plurality of memory cells and/or statistical distributions of potential storage voltages for a first memory cell and a paired second memory cell.

However, multiple data storage and/or programming considerations for various types of memory cells (e.g., resistance variable memory cells, etc.) may cause the storage voltages of multiple (e.g., a subset or all) memory cells in the first and/or second threshold voltage distributions to shift and overlap with a single sensing voltage at the median value of the sensing window, such that the sensed voltage related to the sensing voltage (e.g., data value) becomes unreliable and/or inaccurate during a read operation. For example, such displacement may be facilitated by (e.g., caused by) at least one of: widening (e.g., over time) the first and/or second threshold voltage distributions to overlap at least with the single sensing voltage, shifting (e.g., over time) the first and/or second threshold voltage distributions to a larger median voltage to overlap at least with the single sensing voltage, and/or disturbing memory states of a subset of the memory cells in the first and/or second threshold voltage distributions to overlap at least with the single sensing voltage as a result of performing read/write operations on at least some of the memory cells, among other possible data storage and/or programming considerations.

Embodiments described herein for sensing two memory cells to determine one data value by using first and second sense voltages that are selectively closer to either a first or second threshold voltage distribution in a sensing window aim to reduce the potential of some of the stored voltages that overlap with the sense voltage of the respective threshold voltage distribution. As such, such embodiments may improve the reliability and accuracy of data accessed from memory cells. Moreover, as described herein, embodiments may increase the speed and/or reduce the complexity of data correction operations for potential data errors that may be caused, for example, by such shifts of the first and/or second threshold voltage distributions, as compared to previous memory devices, to further increase the reliability and accuracy of data accessed from memory cells. A memory device may include multiple arrays of memory cells, where all or a subset (less than all) of the arrays may be configured to store, read, write, and/or perform data verification and correction as described herein.

As used herein, "a", "an" or "a plurality" may refer to one or more of something, while "a plurality" may refer to two or more of such something. For example, a memory device may refer to one or more memory devices, and a plurality of memory devices may refer to two or more memory devices. Additionally, as used herein, the designators "N" and "M" (particularly with respect to the reference numbers in the drawings) indicate that the various embodiments of the disclosure may include a number of the particular features so designated. Moreover, numerals separated from particular reference numbers by hyphens (e.g., 212-1, 212-2, in fig. 2A and 2D-2G, 212-6 with respect to the sensing window) are intended to represent similar features, although the location, magnitude, width, height, and/or shape, etc., of such features may vary within and/or between particular embodiments. The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits.

Fig. 1 is a three-dimensional view of an example of a memory array 100 (e.g., a cross-point memory array) according to an embodiment of the present disclosure. The memory array 100 may include a plurality of first signal lines (e.g., first access lines), which may be referred to as word lines 110-0 to 110-N, and a plurality of second signal lines (e.g., second access lines), which may be referred to as bit lines 120-0 to 120-M that cross each other (e.g., intersect in different planes). For example, one of word lines 110-0 through 110-N may intersect bit lines 120-0 through 120-M. Memory cell 125 may be between a bit line and a word line (e.g., at each bit line/word line intersection).

For example, memory cell 125 may be a resistance variable memory cell. Memory cells 125 may include materials that are programmable to different memory states. In some examples, each of the memory cells 125 may include a single material that can be used as a select element (e.g., a switching material) and a storage element, such that each memory cell 125 can function as both a selector device and a memory element. Such memory cells may be referred to herein as self-selecting memory cells. For example, each memory cell may include a chalcogenide material, which may be formed from various doped or undoped materials, may or may not be a phase change material, and/or may not undergo a phase change during reading and/or writing of the memory cell. In some examples, each memory cell 125 may include a ternary composition that may include selenium (Se), arsenic (As), and germanium (Ge), and/or may include a quaternary composition of elements selected from tellurium (Te), sulfur (S), carbon (C), nitrogen (N), silicon (Si), Se, As, and Ge, and other elements selected from corresponding groups of the periodic table.

In various embodiments, at a threshold voltage, memory cell 125 may snap back in response to the magnitude of the voltage difference applied across it exceeding its threshold voltage. Such memory cells may be referred to as snapback memory cells. For example, in response to the applied voltage difference exceeding a threshold voltage, memory cell 125 may change (e.g., snap back) from a non-conductive (e.g., high impedance) state to a conductive (e.g., low impedance) state. For example, memory cell snapback may refer to a memory cell transitioning from a high impedance state to a lower impedance state in response to a voltage difference applied across the memory cell being greater than a threshold voltage of the memory cell. For example, the threshold voltage at which a memory cell snaps back may be referred to as a snap back event.

The example shown in fig. 1 may include a driver (e.g., a word line driver — not shown) coupled to the word line 110. The word line driver may supply bipolar (e.g., positive and negative) current and/or voltage signals to the word line 110. A sense amplifier (e.g., in the sensing circuitry 305 shown in fig. 3), which may comprise cross-coupled latches, may be coupled to the word line drivers and may detect positive and negative currents and/or positive and negative voltages on the word line 110. In some examples, the sense amplifier may be part of (e.g., included within) a word line driver. For example, the word line drivers may include the sensing functionality of the sense amplifiers. In some examples, the sense amplifier may be (e.g., included in) part of sensing circuitry coupled to the memory cell 125 (e.g., in a memory cell array, as shown at 306 in fig. 3). A bit line driver (not shown) may be coupled to the bit line 120 to supply positive and/or negative current and/or voltage signals to the bit line 120.

The sense amplifier may detect a current and/or voltage associated with one or more memory cells 125 relative to a particular sense voltage (e.g., a threshold), and may output a signal to indicate a particular memory state of each memory cell 125 based on a magnitude of the voltage stored by the particular memory cell relative to the particular sense voltage. As expressed in a truth table (e.g., as shown at 213 and described in connection with fig. 2A and 2D-2G), the sensed memory state of each memory cell 125 can be sent to and/or stored by a particular latch (not shown), and the sensed memory state value can represent a desired particular determination of a verification of the validity of the sensed memory state and/or a correction of an invalid sensed memory state (e.g., associated with a read operation).

FIG. 2A illustrates an example of a sensing threshold voltage distribution associated with a memory state of a memory cell of two memory cells sensed to determine a plurality of data values, according to an embodiment of the disclosure. FIG. 2A illustrates threshold voltage distributions and truth tables associated with various memory states of a memory cell, such as memory cell 125 illustrated in FIG. 1.

The example shown in FIG. 2A illustrates threshold voltage distributions 208-1 and 208-2 and 209-1 and 209-2, respectively, associated with the memory states of two memory cells 201-1 and 204-1, respectively, which may be operated as a pair of memory cells to each store a voltage magnitude that, when sensed and compared, enables determination of one (single) data value. Each of the shown memory cells 201-1, 204-1 represents one of a plurality of such memory cells, where each of the memory cells is configured to selectively store a voltage magnitude (e.g., relative to zero volts (0V)) corresponding to one of two memory states as determined by reference to a determined (e.g., predetermined) sense voltage in sensing window 212-1 between two threshold voltage distributions that each correspond to one of the two memory states when not shifted (e.g., at least overlapped) relative to one or both of their determined sense voltages.

The first memory cell 201-1 may have a first memory state 202-1 (e.g., memory state 0) and a second memory state 202-2 (e.g., memory state 1) in the negative polarity 206. Similarly, the second memory cell 204-1 can also have a first memory state 205-1 (e.g., memory state 0) and a second memory state 205-2 (e.g., memory state 1) in the negative polarity 206. For example, second memory cell 204-1 may store its memory state as an expected data value corresponding to one data value, and second memory cell 204-1 may be programmed by applying a first number of voltage pulses to the memory cell. The first memory cell 201-1 may store its memory state as a reference data value corresponding to an expected data value, and the first memory cell 201-1 may be programmed by applying a second voltage pulse to the memory cell. For example, when the second memory cell 204-1 stores the expected memory state 205-2 of 1 and the first memory cell 201-1 stores the complementary reference memory state 202-1 of 0 (e.g., in a binary memory state), the resulting one data value is determined to be 1. Alternatively, when the second memory cell 204-1 stores the expected memory state 205-1 of 0 and the first memory cell 201-1 stores the complementary reference memory state 202-2 of 1, the resulting one data value is determined to be 0. As further described herein, the memory cells 201-1, 204-1 may alternatively be programmed to a positive polarity 207.

The terms "reference" and "expected" are used herein to more easily distinguish pairs of memory cells (e.g., first memory cell 201-1 and second memory cell 204-1), associated memory states, and corresponding data values from one another. However, it is an object of the present disclosure to output one data value as a "reliable state" from sensing two memory cells, without having to designate one memory cell, an associated memory state, and/or a corresponding data value as "reference" and the other as "expected".

The magnitude and/or number of voltage pulses may be different in the programming of the intended data value and the reference data value. For example, as shown in FIG. 2A, when second memory cell 204-1 is programmed to an expected data value of 1 (corresponding to threshold voltage distribution 209-2) in memory state 205-2, first memory cell 201-1 is programmed to a complementary reference data value of 0 (corresponding to threshold voltage distribution 208-1) in memory state 202-1. As shown in the negative polarity 206, memory state 202-2 of reference memory cell 201-1 and memory state 205-2 of intended memory cell 204-1 (e.g., corresponding to memory state 1) are programmed to be at a larger voltage magnitude (absolute value) in the negative polarity 206 relative to a smaller voltage magnitude (e.g., corresponding to memory state 0) of memory state 202-1 of reference memory cell 201-1 and memory state 205-1 of intended memory cell 204-1.

Alternatively, when second memory cell 204-1 is programmed to an expected data value of 0 (corresponding to threshold voltage distribution 209-1) in memory state 205-1, first memory cell 201-1 is programmed to a complementary reference data value of 1 (corresponding to threshold voltage distribution 208-2) in memory state 202-2. Memory state 202-1 of reference memory cell 201-1 and memory state 205-1 of intended memory cell 204-1 (e.g., corresponding to memory state 0) are programmed to be at a smaller voltage magnitude in negative polarity 206 relative to a larger voltage magnitude of memory state 202-2 of reference memory cell 201-1 and memory state 205-2 of intended memory cell 204-1 (e.g., corresponding to memory state 1). As such, the sensed memory states can include memory states associated with a first threshold voltage distribution of a first subset of the plurality of memory cells that are greater in relative magnitude (e.g., for a particular polarity) than a different one of two memory states associated with a second threshold voltage distribution of a second subset of the plurality of memory cells. The magnitude of the voltage magnitude can depend on the magnitude and/or number of voltage pulses used to program complementary memory states.

In fig. 2A, the Voltage (VCELL) applied to a particular memory cell to program an appropriate storage voltage for a particular memory state may correspond to a voltage difference applied to (e.g., across) the memory cell, such as the difference between a bit line Voltage (VBL) and a word line Voltage (VWL) (e.g., VCELL ═ VBL-VWL), as shown and described in connection with fig. 2B and 2C. Threshold voltage distributions (e.g., ranges) 208-1, 208-2, 209-1, and 209-2 can represent statistical variations in threshold voltages of memory cells programmed to particular memory states. The threshold voltage distributions illustrated in fig. 2A and 2D-2G are illustrated by way of example, and the relative sizes, shapes, spacings, locations, etc., may differ from the actual programming and/or sensing of the respective memory states.

The reliability and/or accuracy of determining a data value may depend on the ability to: memory state 205-2 (corresponding to threshold voltage distribution 209-2) of intended memory cell 204-1 is distinguished from memory state 205-1 (corresponding to threshold voltage distribution 209-1) of intended memory cell 204-1, for example. Reliability and/or accuracy may further depend on the following capabilities: memory state 202-1 (corresponding to threshold voltage distribution 208-1) is distinguished from memory state 202-2 (corresponding to threshold voltage distribution 208-2) of reference memory cell 201-1.

Thus, as shown in the embodiment illustrated in fig. 2A, circuitry (e.g., sensing circuitry 305 and/or control circuitry 324) may be configured to determine one data value. A data value may be determined by: a memory state (e.g., memory state 202-1 or memory state 202-2) of a first of the two memory cells (e.g., memory cell 201-1) is sensed using a first sensing voltage (e.g., 211-1) in a sensing window 212-1 between a first threshold voltage distribution (e.g., 208-1 and/or 209-1) corresponding to a first memory state (e.g., 202-1 and/or 205-1) and a second threshold voltage distribution (e.g., 208-2 or 209-2) corresponding to a second memory state (e.g., 202-2 and/or 205-2), and a second of the two memory cells is sensed using a second sensing voltage (e.g., 210-1) in the sensing window 212-1 (e.g., memory cell 204-1) (e.g., memory state 205-1 or memory state 205-2). In various embodiments illustrated and described in connection with fig. 2A and 2D-2G, the first and second sensing voltages may be selectively closer to the first or second threshold voltage distributions in the sensing window. As presented herein, two sense voltages having reference numerals 210 and 211 can be used to determine the memory states of a corresponding pair of memory cells (e.g., distinguish the memory states as part of a read operation).

In the embodiment shown in FIG. 2A, the first and second sensing voltages may be selectively closer to different ones of the first threshold voltage distribution and the second sensing voltage in the sensing window 212-1. Thus, sense voltage 210-1 is shown to be closer to (e.g., while also having a statistically appropriate separation margin) first threshold voltage distribution 208-1 and/or 209-1, and sense voltage 211-1 is shown to be closer to (e.g., while also having a statistically appropriate separation margin) second threshold voltage distribution 208-2 and/or 209-2.

In various embodiments, the circuitry can be further configured to store the memory state of one memory cell in association with a particular end of the sensing window 212-1 having a particular magnitude of polarity, and to store the memory state of another memory cell in association with an opposite end of the sensing window having a different magnitude of polarity (e.g., the polarity can be selected from the negative polarity 206 and the positive polarity 207, as shown and described in connection with fig. 2A and 2D-2G). For example, as shown in FIG. 2A, memory states 202-1 and 205-1 (corresponding to data value 0 and a smaller voltage magnitude in the negative polarity of threshold voltage distributions 208-1 and/or 209-1) are stored at an end edge of sensing window 212-1 determined by sensing voltage 210-1. In contrast, memory states 202-2 and 205-2 (corresponding to data value 1 and the larger voltage magnitude in the negative polarity of threshold voltage distributions 208-2 and/or 209-2) are stored at the other end edge of sensing window 212-1 as determined by sensing voltage 211-1.

Thus, one end of the sensing window 212-1 can correspond to the programmed memory state 202-1 of the first memory cell 201-1 (e.g., having a data value of 0), and the other end of the polarity of the sensing window can correspond to the complementary reprogrammed memory state 202-2 of the first memory cell 201-1 (e.g., having a data value of 1). Which end of the sensing window 212-1 corresponds to the programmed memory state 202-1 and which other end of the sensing window corresponds to the complementary reprogrammed memory state 202-2 can be determined by: a first number of voltage pulses applied to the first memory cell 201-1 to program the first memory cell to a magnitude less than the first sensing voltage 210-1 in the sensing window, and a second number of voltage pulses different from the first number applied to the first memory cell 201-1 to reprogram the first memory cell to a magnitude greater than the second sensing voltage 211-1 in the sensing window.

Additionally, one end of the sensing window 212-1 can correspond to the programmed memory state 202-1 of the first memory cell 201-1 and the other end of the polarity of the sensing window can correspond to the complementary reprogrammed memory state 205-2 of the second memory cell 204-1. Which end of the sensing window 212-1 corresponds to the programmed memory state 202-1 and which other end of the sensing window corresponds to the complementary reprogrammed memory state 205-2 can be determined by: a first number of voltage pulses applied to first memory cell 201-1 to program the first memory cell to a magnitude less than a first sense voltage 210-1 in the sense window, and a second number of voltage pulses different from the first number applied to second memory cell 204-1 to reprogram the second memory cell to a magnitude greater than a second sense voltage 211-1 in the sense window.

The circuitry may be further configured to determine one data value by: the method includes comparing the sensed memory states of each of the two memory cells, verifying that the memory state of memory cell 204-1 is the expected data value corresponding to the one data value by determining that the sensed memory states are complementary binary memory states (e.g., one memory state is 0 and the other memory state is 1), and determining the switching of the memory states of the two memory cells (e.g., one of memory cells 201-1 or 204-1) by determining that the sensed memory states match the binary memory states (e.g., both memory states are 0 or both memory states are 1). Determining which of the two memory cells has been switched from one memory state to the other memory state (e.g., from 0 to 1 or from 1 to 0) may be based at least in part on one combination of two memory states that are complementary in a binary memory state that is more reliable in readability than the other complementary combination of the two memory states. Reliability is attributable to at least one sense voltage being separated from the threshold voltage distributions of the first or second memory states by a greater magnitude than the separation between at least one sense voltage and the threshold voltage distributions of the other memory states.

For example, as shown in FIG. 2A, sense voltage 210-1 is selectively positioned at the edges of threshold voltage distributions 208-1 and 209-1, corresponding to memory states 202-1 and 205-1 having a data value of 0, and sense voltage 211-1 is selectively positioned at the edges of threshold voltage distributions 208-2 and 209-2, corresponding to memory states 202-2 and 205-2 having a data value of 1. A more reliable determination of one combination readability of sensed memory states may be based on the magnitude of the larger separation, so that there is less likelihood of having a correspondingly larger shift to reach the sense voltage than shifts caused by smaller separations in other combinations of sensed memory states. Thus, as shown in FIG. 2A, the sense voltage 210-1 is used for the reference memory cell 201-1 and is at a greater separation from the threshold voltage distribution 208-2 of the memory state 202-2 (having a data value of 1) than the separation of the sense voltage 210-1 from the threshold voltage distribution 208-1 of the memory state 202-1 (having a data value of 0). Additionally, sense voltage 211-1 is used for reference memory cell 204-1 and is at a greater separation from threshold voltage distribution 209-1 in memory state 205-1 (having a data value of 0) than sense voltage 211-1 is from threshold voltage distribution 209-2 in memory state 205-2 (having a data value of 1).

Thus, where sense voltages 210-1 and 211-1 are so positioned relative to possible threshold voltage distributions in reference memory cell 201-1 and intended memory cell 204-1, a larger separation and corresponding larger shift of at least a portion of the threshold voltage distributions to reach the respective sense voltages may cause (e.g., cause) sensing of memory state 202-2 (having data value 1) of reference memory cell 201-1 and sensing of memory cell 205-1 (having data value 0) of intended memory cell 204-1 with reliable readability. As used herein, readability is intended to mean that the sensed memory state is more reliable than if: for example, as shown in FIG. 2A, a sense voltage 210-1 is used to sense a memory state 202-1 (having a data value of 0) with reference to memory cell 201-1, and a sense voltage 211-1 is used to sense a memory state 205-2 (having a data value of 1) with intended memory cell 204-1.

As used herein, less reliability is intended to mean that the readability of other combinations of the two memory states is less reliable due to the first magnitude of separation of the first sensing voltage from the first distribution of the first memory state and the second magnitude of separation of the second sensing voltage from the second distribution of the first memory state being less than the separation of the sensing voltages from the respective distributions of the first and second memory states in one combination where readability is more reliable. For example, as shown in FIG. 2A, a lesser reliability of data value 0 of reference memory cell 201-1 and data value 1 of intended memory cell 204-1 may result from (e.g., be caused by) a lesser separation and corresponding lesser shift at least a portion of the threshold voltage distribution to reach the respective sense voltages.

The present disclosure describes determining which of two memory cells (e.g., memory cell 201-1 or 204-1) has switched its memory state due to a shift in magnitude in the distribution of at least some of the stored voltage magnitudes of the memory cells (e.g., shifts in the distribution) of at least a portion of the threshold voltage distribution relative to the sense voltage (e.g., sense voltages 210-1 and 211-1) in the sense window 212-1. As shown in FIG. 2A, in the sensing window 212-1, the magnitude of the first sensing voltage (e.g., 210-1) may be selectively closer to the first threshold voltage distribution (e.g., 208-1) than the second threshold voltage distribution (e.g., 208-2). The switching of the memory state may be due, for example, to a shift in the second threshold voltage distribution (e.g., 208-2) relative to the magnitude of the second sensing voltage (e.g., 211-1) in the sensing window 212-1 rather than the magnitude of the first sensing voltage (e.g., 210-1) because of the lesser separation of the second sensing voltage (e.g., 211-1) relative to the first sensing voltage (e.g., 210-1). Because the likelihood of two paired memory cells switching memory states is low due to a shift at the same point in time, determining which of the two memory cells has switched its memory state at that point in time may enable rapid correction of switching storage states back to complementary memory states (e.g., before other memory cells potentially switch memory states) to improve the reliability and/or accuracy of the stored data.

Due to the shifting of at least a portion of the threshold voltage distribution, various factors can contribute to the switching of the memory state. For example, the shifting may be facilitated by at least one of: widening a first threshold voltage distribution (e.g., 208-1, 209-1) of the first subset of memory cells to overlap at least a first sensing voltage (e.g., 210-1); widening a second threshold voltage distribution (e.g., 208-2, 209-2) of a second subset of memory cells to at least overlap with a second sensing voltage (e.g., 211-1); the first threshold voltage distributions of the first subset of memory cells drift to a first greater median magnitude of polarity to overlap at least the first sense voltage; a second threshold voltage distribution of a second subset of memory cells shifts to a second greater median magnitude of polarity to at least overlap with a second sense voltage; performing a first disturb on memory states of a first subset of memories by performing a read or write operation on at least some of the memory cells in the first subset; and/or second disturbing memory states of the second subset of memory by performing a read or write operation on at least some of the memory cells in the second subset such that the second threshold voltage distribution at least overlaps with the second sensing voltage; and other possible contributing factors to shifting the threshold voltage distribution.

The probability that the same factor will affect the reliability of both memory states of both memory cells at the same time is low, which results in a low probability that two paired memory cells switch memory states at the same point in time. For example, a drift of the first threshold voltage distribution 208-1 to a first larger median magnitude may cause at least one memory cell to overlap with the closer first sense voltage 210-1 because the drift will be toward the closer first sense voltage 210-1. Conversely, a drift of second threshold voltage distribution 209-2 to a second larger median magnitude will not cause any memory cells to overlap with closer second sense voltage 211-1, as the drift will be further away from closer second sense voltage 211-1.

In various embodiments, the example described in connection with FIG. 2A may be associated with truth table 213-1. Truth table 213-1 may be configured to enable a comparison of a sensed memory state of a first memory cell (e.g., reference memory cell 201-1) with a sensed memory state of a second memory cell (e.g., intended memory cell 204-1), determine a switching of memory states due to a shift by determining that the sensed memory states match (e.g., both memory states are 0 or both memory states are 1), and determine which of the two memory cells has switched from one memory state to the other memory state. Switching from one memory state to another is intended to mean that both memory cells originally stored complementary memory states (e.g., a data value of 0 in one memory cell and a data value of 1 in the other memory cell), and that one of the memory cells switches (changes) its memory state so that the memory states of the two memory cells then match. In response to using truth table 213-1 to determine which of the two memory cells has switched from one memory state to the other memory state, the circuitry is configured to reprogram the memory cells that have switched back to their complementary memory states to enable one data value from the memory states of the two memory cells to be determined as expected (e.g., to verify the memory state of the intended memory cell 204-1).

Determining which of the two memory cells has been switched from one memory state to the other memory state is based, at least in part, on one combination of the two memory states being complementary being more reliable in readability than the other combination of the two memory states. As indicated herein, the reference to memory state 202-2 of memory cell 201-1 having a data value of 1 and the expected memory state 205-1 of memory cell 204-1 having a data value of 0 are more readability-reliable. Reliability is attributed to the sense voltage 210-1 being separated from the threshold voltage distribution 208-2 of the memory state 202-2 by a greater magnitude than the sense voltage 210-1 being separated from the threshold voltage distribution 208-1 of the memory cell 202-1. Reliability is further attributed to the fact that sense voltage 211-1 is separated from threshold voltage distribution 209-1 of memory state 205-1 by a greater magnitude than sense voltage 211-1 is separated from threshold voltage distribution 209-2 of memory cell 205-2.

Determining which of the two memory cells has switched is further based at least in part on the circuitry being configured to use truth table 213-1 in response to determining that the two memory states match, using as a stable combination one of the two memory cells that is more reliable in readability of the two memory states of the first and second memory cells based on being less likely to switch. As described herein, the combination of the memory state 202-2 of the first memory cell (1 st MC)201-1 having a data value of 1 and the memory state 205-1 of the second memory cell (2 nd MC)204-1 having a data value of 0 is a more reliable combination of readability (e.g., based on being stable and less likely to switch), as shown in row 215 in truth table 213-1. As a "result" of the two data values being complementary, the data value 0 of the second memory cell 204-1 is verified based on a determination that no "switching" has occurred in any of the memory cells, as indicated by N/A in truth table 213-1.

The combination of the memory state 202-1 of the first memory cell 201-1 having a data value of 0 and the memory state 205-2 of the second memory cell 204-1 having a data value of 1 is a combination (e.g., based on being more likely to switch) for which readability is less reliable, as shown in row 214 in truth table 213-1. As a "result" of the two data values being complementary, the data value 1 of the second memory cell 204-1 is verified based on a determination that no "switching" has occurred in any of the memory cells, as indicated by N/A in truth table 213-1.

Truth table 213-1 may indicate complementary other combinations of the two memory states of the first and second memory cells shown in row 214 that are less reliable for readability as switching based on a more likely switching combination. Truth table 213-1 may further be used to compare the matching memory states sensed from the first and second memory cells to the complementary other combinations of the two memory states of the first and second memory cells shown in row 214 that are less reliable.

Truth table 213-1 may be used to enable a determination that a first memory state has been switched from one memory state to another memory state based on the sensed memory state of the matching memory state from the first memory cell being different from the memory states of the first memory cells in complementary other combinations. For example, as shown in FIG. 2A, the less reliable combination shown in row 214 is compared to the sensed match data values 0 and 0 in row 216 for first memory cell 201-1 and second memory cell 204-1. Because the data value of the first memory cell 201-1 in the combination shown in row 214 is 0 and the sensed data value of the second memory cell in row 216 is also 0, it can be determined that the first memory cell has not switched to another memory state. However, because the data value of the second memory cell 204-1 in the combination shown in row 214 is 1 and the sensed data value of the second memory cell in row 216 is different than 1, because it is 0, it can be determined 218 that the second memory cell did switch to another memory state, as indicated in the "switch" column of row 216 of truth table 213-1.

Additionally, truth table 213-1 can be used to enable a determination that a second memory state has been switched from one memory state to another memory state based on a sensed memory state from the second memory cell that matches the memory state of the second memory cell in other combinations that are complementary. For example, as shown in FIG. 2A, the less reliable combination shown in row 214 is compared to the sensed match data values 1 and 1 in row 217 for first memory cell 201-1 and second memory cell 204-1. Because the data value of the second memory cell 201-1 in the combination shown in row 214 is 1, and the sensed data value of the second memory cell in row 217 is also 1, it can be determined that the second memory cell has not switched to another memory state. However, because the data value of the second memory cell 204-1 in the combination shown in row 214 is 0 and the sensed data value of the first memory cell in row 217 is different from 0, because it is a 1, it can be determined 219 that the first memory cell did switch to another memory state, as indicated in the "switch" column of row 217 of truth table 213-1.

Thus, truth table 213-1 may be used to enable a determination of which of two memory cells has switched its memory state due to a shift in its threshold voltage distribution relative to the magnitude of the corresponding sense voltage. The determination may be based on comparing an inverse of a pair of memory states determined to be reliable for the first and second memory cells (e.g., the memory state shown in row 214 of truth table 213-1 is the inverse of the reliable memory state shown in row 215) to the sensed memory states of the first and second memory states. The determination may be further based on: determining which of the two memory cells has switched its memory state based on which memory cell has a sensed memory state that is different from the inverse of the pair of memory states of the first and second memory cells.

Further, truth table 213-1 may be used to reprogram memory cells that have switched their memory state back to their complementary memory state in response to determining which of the two memory cells has switched their memory state. For example, as shown in FIG. 2A, it is determined 218 that the data value of the second memory cell shown in row 214 has switched to the data value of 0 of the second memory cell shown in row 216, so that the second memory cell can be reprogrammed back to its original memory state of 1. In addition, it is determined 219 that the data value 0 of the first memory cell shown in row 214 has switched to the data value 1 of the first memory cell shown in row 217, so that the first memory cell can be reprogrammed back to its original memory state of 0. Reprogramming the switched memory state of the first memory cell or the second memory cell back to its original complementary memory state may enable one data value to be determined as expected from the complementary memory states of the two memory cells, as indicated in the "result" column of truth table 213-1.

Thus, FIG. 2A illustrates programming two memory cells at negative polarity for a negative read using one of a pair of complementary memory states for a first memory cell and the other of the pair for a second memory cell. The first memory cell 201-1 may store a reference memory state and the second memory cell 204-1 may store an expected memory state to be compared to the reference memory state of the first memory cell. Determining the difference between the first memory state and the second memory state may be based on a difference in magnitude of the absolute value of the voltage stored by each of the two memory cells. Memory cells having voltage values in threshold voltage distributions 208-1, 209-1 with smaller magnitudes are in a first memory state 202-1, 205-1 and memory cells having voltage values in threshold voltage distributions 208-2, 209-2 with larger magnitudes are in a second memory state 202-2, 205-2. The first sensing voltage 210-1 is selectively positionable in the sensing window 212-1 at a magnitude greater than and at an edge of the threshold voltage distributions 208-1, 209-1 having a lesser magnitude, and the second sensing voltage 211-1 in the sensing window 212-1 is selectively positionable at a magnitude less than and at an edge of the threshold voltage distributions 208-2, 209-2 having a greater magnitude.

The first sense voltage 210-1 can be used to determine whether the first memory cell 201-1 is in the first memory state 202-1 or the second memory state 202-2, and the second sense voltage 211-1 can be used to determine whether the first memory cell 204-1 is in the first memory state 205-1 or the second memory state 205-2. As shown in row 215 of truth table 213-1, the first memory cells that store the reference memory state as the second memory state at a larger magnitude and the second memory cells that store the expected memory state as the first memory state at a smaller magnitude are readability reliable. The greater reliability is based on the threshold voltage distribution 208-2 of the first memory cell 201-1 having a greater magnitude in the second memory state being more separated from the first sense voltage 210-1 than the threshold voltage distribution 208-1 of the first memory state having a lesser magnitude, and the threshold voltage distribution 209-1 of the second memory cell 204-1 having a lesser magnitude in the first memory state being more separated from the second sense voltage 211-1 than the threshold voltage distribution 209-2 of the second memory state having a greater magnitude.

Based on the greater reliability of the combination shown in row 215, the inverse of the complementary memory states that are reliable for readability may be determined, with the first memory cell storing the reference memory state as a first memory state at a smaller magnitude and the second memory cell storing the expected memory state as a second memory state at a larger magnitude, as shown in row 214 of truth table 213-1, being less reliable for readability because the memory cells are more likely to switch memory states due to the threshold voltage distribution shifting to at least partially overlap with the edge first sensing voltage and/or the edge second sensing voltage. The first memory state of the first memory cell and the second memory state of the second memory cell shown in row 214 for which readability is less reliable may be compared to the sensed memory state of the first memory cell storing the reference memory state and the sensed memory state of the second memory cell storing the expected memory state.

The comparison may result in a determination that the second memory cell stores the reference memory state (having a data value of 0) and is the second memory cell that has been switched from one memory state to another memory state based on a difference between the first memory state (having a data value of 1) for which the readability of the second memory cell is less reliable and the sensed memory state of the second memory cell. Alternatively, the comparison may result in determining that the first memory cell storing the expected memory state (having a data value of 1) is the first memory cell that has switched from one memory state to another memory state based on a difference between the less reliable second memory state (having a data value of 0) of the readability of the first memory cell and the sensed memory state of the first memory state.

Fig. 2B and 2C are examples of current versus voltage curves for memory states corresponding to the threshold voltage distributions shown in fig. 2A and 2D-2G, according to an embodiment of the present disclosure. In this example, the curves in fig. 2B and 2C correspond to memory cells where memory state 1 is designated as the higher threshold voltage state in a particular polarity (positive polarity direction in this example), and where memory state 0 is designated as the higher threshold voltage state in the opposite polarity (negative polarity direction in this example). In various embodiments, the memory state designations may be interchanged such that memory state 0 may correspond to the higher threshold voltage state in the positive polarity direction, with memory state 1 corresponding to the higher threshold voltage state in the negative polarity direction. The examples of current versus voltage curves corresponding to the memory states described in connection with fig. 2B and 2C also apply to embodiments in which both of a pair of memory cells are at the same polarity (e.g., both are at negative polarity 206 or both are at positive polarity 207), as illustrated and described in connection with fig. 2A and 2D-2G.

Fig. 2B and 2C illustrate memory cell snapback as described herein. VCELL may represent an applied voltage across a memory cell. For example, VCELL may be the voltage applied to the top electrode corresponding to a memory cell minus the voltage applied to the bottom electrode corresponding to a memory cell (e.g., via the respective word line and bit line). As shown in fig. 2B, in response to an applied positive polarity Voltage (VCELL), memory cells programmed to memory state 1 (e.g., in a threshold voltage distribution) are in a non-conductive state until VCELL reaches a voltage Vtst02, at which time the memory cells transition to a conductive (e.g., lower resistance) state. This transition may be referred to as a snapback event, which occurs when a voltage (in a particular polarity) applied across the memory cell exceeds a threshold voltage of the memory cell. Therefore, voltage Vtst02 may be referred to as a snapback voltage. In FIG. 2B, voltage Vtst01 corresponds to a snapback voltage of a memory cell programmed to memory state 1 (e.g., in another threshold voltage distribution). That is, as shown in FIG. 2B, when VCELL exceeds Vtst01 in the negative polarity direction, the memory cell transitions (e.g., switches) to a conductive state.

Similarly, as shown in FIG. 2C, in response to an applied negative polarity Voltage (VCELL), memory cells programmed to memory state 0 (e.g., at a threshold voltage distribution) are in a non-conductive state until VCELL reaches a voltage Vtst11, at which time the memory cells snap back to a conductive (e.g., lower resistance) state. In FIG. 2C, voltage Vtst12 corresponds to a snapback voltage for a memory cell programmed to memory state 0 (e.g., at another threshold voltage distribution). That is, as shown in fig. 2C, when VCELL exceeds Vtst12 in the positive polarity direction, the memory cell snaps back from the high-impedance non-conductive state to the low-impedance conductive state.

In various cases, a snapback event may cause a memory cell to switch memory states. For example, if VCELL exceeding Vtst02 is applied to a memory cell that is in memory state 1, the generated snapback event may reduce the threshold voltage of the memory cell to a level below the respective sensing voltage, which, as described herein, will result in the memory cell being sensed (read) as memory state 0 instead of memory state 1. As such, in various embodiments, as described in connection with fig. 2A and 2D-2G, the snapback event may switch the memory cell to the opposite state (e.g., from memory state 1 to memory state 0, and vice versa).

FIG. 2D illustrates another example of sensing threshold voltage distributions associated with memory states of memory cells of two memory cells being sensed to determine one data value, according to another embodiment of the present disclosure. To reduce repetition of the description, the details of the memory states, threshold voltage distributions, and truth tables described in connection with fig. 2A should be considered incorporated into the description of fig. 2D-2G, where appropriate.

FIG. 2D illustrates an alternative embodiment consistent with FIG. 2A, except that the positioning of sensing voltages 210-2 and 211-2 of sensing window 212-2 in FIG. 2D has been changed (e.g., reversed) relative to FIG. 2A. Thus, FIG. 2D also illustrates that two memory cells 201-2 and 204-2 at negative polarity 206 are programmed for a negative read using one of a pair of complementary memory states for a first memory cell and the other of the pair for a second memory cell. The first memory cell 201-2 may store a reference memory state and the second memory cell 204-2 may store an expected memory state to be compared to the reference memory state of the first memory cell.

In contrast to FIG. 2A, FIG. 2D illustrates using the first sense voltage 211-2 to determine whether the second memory cell 204-2 is in the first memory state 205-1 or the second memory state 205-2, and using the second sense voltage 210-2 to determine whether the first memory cell 201-2 is in the first memory state 202-1 or the second memory state 202-2. It may be determined that the first memory cell 201-2 storing the reference memory state as the first memory state 202-1 at a smaller magnitude and the second memory cell 204-2 storing the expected memory state as the second memory state 205-2 at a larger magnitude are readability reliable. The determination of reliability may be based on: the threshold voltage distribution 208-1 of the reference memory cell 201-2 in the first memory state 202-1 having a smaller magnitude is more separated from the second sense voltage 210-2 than the threshold voltage distribution 208-2 in the second memory state 202-2 having a larger magnitude, and the threshold voltage distribution 209-2 of the memory cell 204-2 in the second memory state 205-2 having a larger magnitude is expected to be more separated from the first sense voltage 211-2 than the threshold voltage distribution 209-1 in the first memory state 205-1 having a smaller magnitude.

The determination may be based on comparing an inverse of a pair of memory states determined to be reliable for the first and second memory cells (e.g., the memory state shown in row 215 of truth table 213-2 is the inverse of the reliable memory state shown in row 214) to the sensed memory states of the first and second memory states. The determination may be further based on: determining which of the two memory cells has switched its memory state based on which memory cell has a sensed memory state that is different from the inverse of the pair of memory states of the first and second memory cells. Determining the inverse of the complementary memory states that may be reliable based on the readability, where the first memory cell 201-2 stores the reference memory state as the second memory state 208-2 at a larger magnitude and the second memory cell 204-2 stores the intended memory state as the first memory state 209-1 at a smaller magnitude, is less reliable for readability because the memory cells are more likely to switch memory states due to the threshold voltage distribution shifting to at least partially overlap with the edge first sensing voltage 211-2 and/or the edge second sensing voltage 210-2.

In various embodiments, the example described in connection with FIG. 2D may be associated with truth table 213-2. Truth table 213-2 may be used to enable comparing the second memory state 202-2 of the first memory cell 201-2 and the second memory state of the second memory cell 204-2 having less reliable readability with the sensed memory state of the first memory cell storing the reference memory state and the sensed memory state of the second memory cell storing the intended memory state.

The comparison may result in determining 219 that the first memory cell (1 st MC)201-2 storing the reference memory state is a memory cell that has switched from one memory state to another memory state based on a difference between the less reliable first memory state (e.g., data value 1) of the first memory cell's readability and the sensed memory state (e.g., data value 0) of the first memory state, as shown in row 216 of truth table 213-2. Alternatively, the comparison may result in determining 218 the second memory cell (2 nd MC)204-2 storing the intended memory state as a memory cell that has switched from one memory state to another memory state based on a difference between the sensed memory state (e.g., data value 1) of the first memory cell's less reliable first memory state (e.g., data value 0) and the second memory state, as shown in row 217 of truth table 213-2.

Further, truth table 213-2 may be used to reprogram memory cells that have switched their memory state back to their complementary memory state in response to determining which of the two memory cells has switched their memory state. For example, as shown in fig. 2D, it is determined 218 that data value 0 of the second memory cell shown in row 215 has switched to data value 1 of the second memory cell shown in row 217, so that the second memory cell can be reprogrammed back to its original memory state of 0. In addition, it is determined 219 that the data value 1 of the first memory cell shown in row 215 has switched to the data value 0 of the first memory cell shown in row 216, enabling the first memory cell to be reprogrammed back to its original memory state 1. Reprogramming the switched memory state of the first memory cell or the second memory cell back to its original complementary memory state may enable one data value to be determined as expected from the complementary memory states of the two memory cells, as indicated in the "result" column of truth table 213-2.

FIG. 2E illustrates another example of sensing threshold voltage distributions associated with memory states of memory cells of two memory cells being sensed to determine one data value in accordance with another embodiment of the present disclosure. FIG. 2E illustrates an alternative embodiment consistent with FIG. 2A, except that the positioning (e.g., polarity) of the sense voltages 210-3 and 211-3 of the sense window 212-3 in FIG. 2E has been changed relative to FIG. 2A. FIG. 2E also differs from FIGS. 2A and 2D in that FIG. 2E illustrates the programming of two memory cells 201-3, 204-3 at positive polarity 207 for a positive read using one of a pair of complementary memory states for the first memory cell and the other of the pair for the second memory cell. Also different from fig. 2A and 2D, in fig. 2E, a first memory cell 201-3 may store an expected memory state and a second memory cell 204-3 may store a reference memory state to be compared to the expected memory state of the first memory cell, and not vice versa.

The difference between the first memory state 202-1, 205-1 and the second memory state 202-2, 205-2 may be determined based on the difference in magnitude of the absolute value of the voltage stored by each of the two memory cells. Thus, memory cells having voltage values in threshold voltage distributions 208-1, 209-1 with larger magnitudes are in a first memory state (having a data value of 0) and memory cells having voltage values in threshold voltage distributions 208-2, 209-2 with smaller magnitudes are in a second memory state (having a data value of 1). The first sensing voltage 210-3 may be selectively positioned in the sensing window 212-3 at a magnitude greater than and at an edge of the threshold voltage distributions 208-2, 209-2 having smaller magnitudes. The second sensing voltage 211-3 may be selectively positioned in the sensing window 212-3 at a magnitude smaller and at an edge than the threshold voltage distributions 208-1, 209-1 having a larger magnitude.

FIG. 2E illustrates whether the first sense voltage 210-3 is used to determine whether the second memory cell 204-3 storing the reference memory state is in the first memory state 205-1 or the second memory state 205-2, and the second sense voltage 211-3 is used to determine whether the first memory cell 201-3 storing the intended memory state is in the first memory state 202-1 or the second memory state 202-2. It may be determined that the first memory cell 201-3 storing the expected memory state as the second memory state 202-2 (having a data value of 1) at a smaller magnitude and the second memory cell 204-3 storing the reference memory state as the first memory state 205-1 (having a data value of 0) at a larger magnitude are readability reliable.

The determination of reliability may be based on: the threshold voltage distribution 209-1 of the reference memory cell 204-3 in the first memory state 205-1 having a larger magnitude is more separated from the first sense voltage 210-3 than the threshold voltage distribution 209-2 of the second memory state 205-2 having a smaller magnitude, and the threshold voltage distribution 208-2 of the memory cell 201-3 in the second memory state 202-2 having a smaller magnitude is expected to be more separated from the second sense voltage 211-3 than the threshold voltage distribution 208-1 of the first memory state 202-1 having a larger magnitude.

The determination may be based on comparing an inverse of a pair of memory states determined to be reliable for the first and second memory cells (e.g., the memory state shown in row 215 of truth table 213-3 is the inverse of the reliable memory state shown in row 214) to the sensed memory states of the first and second memory states. The determination may be further based on: determining which of the two memory cells has switched its memory state based on which memory cell has a sensed memory state that is different from the inverse of the pair of memory states of the first and second memory cells. The determination may be based on an inverse of the complementary memory states that are reliable for readability, with the first memory cell 201-3 storing the intended memory state as the first memory state 202-1 at a larger magnitude and the second memory cell 204-3 storing the reference memory state as the second memory state 205-2 at a smaller magnitude, being less reliable for readability because the memory cells are more likely to switch memory states due to threshold voltage distribution shifting to at least partially overlap with the edge first sensing voltage 210-3 and/or the edge second sensing voltage 211-3.

In various embodiments, the example described in connection with FIG. 2E may be associated with truth table 213-3. The truth table 213-3 may be used to enable comparing the first memory state 202-1 of the first memory cell 201-3 and the second memory state 205-2 of the second memory cell 204-3 having less reliable readability with the sensed memory state of the first memory cell storing the intended memory state and the sensed memory state of the second memory cell storing the reference memory state.

The comparison may result in determining 219 that the second memory cell (2 nd MC)204-3 storing the reference memory state is a memory cell that has switched from one memory state to another memory state based on a difference between the less reliable second memory state (e.g., data value 1) of the second memory cell's readability and the sensed memory state (e.g., data value 0) of the second memory cell, as shown in row 216 of truth table 213-3. Alternatively, the comparison may result in determining 218 the first memory cell (1 st MC)201-3 storing the intended memory state as a memory cell that has switched from one memory state to another memory state based on a difference between the less reliable first memory state (e.g., data value 0) of the first memory cell's readability and the sensed memory state (e.g., data value 1) of the first memory state, as shown in row 217 of truth table 213-3.

Further, truth table 213-3 may be used to reprogram memory cells that have switched their memory state back to their complementary memory state in response to determining which of the two memory cells has switched their memory state. For example, as shown in FIG. 2E, it is determined 218 that data value 0 of the first memory cell shown in row 215 has switched to data value 1 of the first memory cell shown in row 217, so that the first memory cell can be reprogrammed back to its original memory state of 0. In addition, it is determined 219 that the data value 1 of the second memory cell shown in row 215 has switched to the data value 0 of the second memory cell shown in row 216, enabling the second memory cell to be reprogrammed back to its original memory state 1. Reprogramming the switched memory state of the second memory cell or the first memory cell back to its original complementary memory state may enable one data value to be determined as expected from the complementary memory states of the two memory cells, as indicated in the "result" column of truth table 213-3.

FIG. 2F illustrates another example of a sensing threshold voltage distribution associated with memory states of memory cells of two memory cells being sensed to determine one data value in accordance with another embodiment of the present disclosure. FIG. 2F illustrates an alternative embodiment consistent with FIG. 2E, except that the positioning of sense voltages 210-4 and 211-4 of sense window 212-4 in FIG. 2F has been changed (e.g., reversed) relative to FIG. 2E. Thus, FIG. 2F also illustrates that two memory cells 201-4 and 204-4 at negative polarity 207 are programmed for a positive read using one of a pair of complementary memory states for the first memory cell and the other of the pair for the second memory cell. The first memory cell 201-4 may store an expected memory state and the second memory cell 204-4 may store a reference memory state to be compared to the expected memory state of the first memory cell.

The difference between the first memory state 202-1, 205-1 and the second memory state 202-2, 205-2 may be determined based on the difference in magnitude of the absolute value of the voltage stored by each of the two memory cells. Thus, memory cells having voltage values in threshold voltage distributions 208-1, 209-1 with larger magnitudes are in a first memory state (having a data value of 0) and memory cells having voltage values in threshold voltage distributions 208-2, 209-2 with smaller magnitudes are in a second memory state (having a data value of 1). The first sensing voltage 210-4 may be selectively positioned in the sensing window 212-4 at a magnitude smaller and at an edge than the threshold voltage distributions 208-1, 209-1 having a larger magnitude. The second sensing voltage 211-4 may be selectively positioned in the sensing window 212-4 at a magnitude greater than and at an edge of the threshold voltage distributions 208-2, 209-2 having smaller magnitudes.

FIG. 2F illustrates using the first sense voltage 210-4 to determine whether the second memory cell 204-4 is in the first memory state 205-1 or the second memory state 205-2, and using the second sense voltage 211-4 to determine whether the first memory cell 201-4 is in the first memory state 202-1 or the second memory state 202-2. It may be determined that a first memory cell 201-4 storing the expected memory state as a first memory state 202-1 (having a data value of 0) at a larger magnitude and a second memory cell 204-4 storing the reference memory state as a second memory state 205-2 (having a data value of 1) at a smaller magnitude are readability reliable.

The determination of reliability may be based on: the threshold voltage distribution 209-2 of the reference memory cell 204-2 in the second memory state 205-2 having a smaller magnitude is more separated from the first sense voltage 210-4 than the threshold voltage distribution 209-1 in the first memory state 205-1 having a larger magnitude, and the threshold voltage distribution 208-1 of the memory cell 201-4 in the first memory state 202-1 having a larger magnitude is expected to be more separated from the second sense voltage 211-4 than the threshold voltage distribution 208-2 in the first memory state 202-2 having a larger magnitude.

The determination may be based on comparing an inverse of a pair of memory states determined to be reliable for the first and second memory cells (e.g., the memory state shown in row 214 of truth table 213-4 is the inverse of the reliable memory state shown in row 215) to the sensed memory states of the first and second memory states. The determination may be further based on: determining which of the two memory cells has switched its memory state based on which memory cell has a sensed memory state that is different from the inverse of the pair of memory states of the first and second memory cells. The determination may be based on an inverse of the complementary memory states that are reliable for readability, with the first memory cell 201-4 storing the intended memory state as the second memory state 202-2 at a smaller magnitude and the second memory cell 204-4 storing the reference memory state as the first memory state 205-1 at a larger magnitude, being less reliable for readability because the memory cells are more likely to switch memory states due to threshold voltage distribution shifting to at least partially overlap with the marginal first sensing voltage 210-4 and/or the marginal second sensing voltage 211-4.

In various embodiments, the example described in connection with FIG. 2F may be associated with truth table 213-4. The truth table 213-4 may be used to enable comparing the second memory state 202-2 of the first memory cell 201-4 and the second memory state 205-1 of the second memory cell 204-4 having less reliable readability with the sensed memory state of the first memory cell storing the intended memory state and the sensed memory state of the second memory cell storing the reference memory state.

The comparison may result in determining 219 that the second memory cell (2 nd MC)204-4 storing the reference memory state is a memory cell that has switched from one memory state to another memory state based on a difference between the less reliable first memory state (e.g., data value 0) of the readability of the second memory cell and the sensed memory state (e.g., data value 1) of the second memory cell, as shown in row 217 of truth table 213-4. Alternatively, the comparison may result in determining 218 the first memory cell (1 st MC)201-4 storing the intended memory state as a memory cell that has switched from one memory state to another memory state based on a difference between the less reliable first memory state (e.g., data value 1) of the first memory cell's readability and the sensed memory state (e.g., data value 0) of the first memory state, as shown in row 216 of truth table 213-4.

Further, truth table 213-4 may be used to reprogram memory cells that have switched their memory state back to their complementary memory state in response to determining which of the two memory cells has switched their memory state. For example, as shown in FIG. 2F, it is determined 218 that the data value of the first memory cell shown in row 214 has switched to the data value of 0 of the first memory cell shown in row 216, so that the first memory cell can be reprogrammed back to its original memory state 1. In addition, it is determined 219 that data value 0 of the second memory cell shown in row 214 has switched to data value 1 of the second memory cell shown in row 217, so that the second memory cell can be reprogrammed back to its original memory state of 0. Reprogramming the switched memory state of the second memory cell or the first memory cell back to its original complementary memory state may enable one data value to be determined as expected from the complementary memory states of the two memory cells, as indicated in the "result" column of truth table 213-4.

FIG. 2G illustrates another example of a sensing threshold voltage distribution associated with memory states of memory cells of two memory cells being sensed to determine one data value in accordance with another embodiment of the present disclosure. FIG. 2G illustrates an alternative embodiment consistent with FIGS. 2A and 2D-2F, except that FIG. 2G illustrates a first pair of memory cells 201-5 and 204-5 in negative polarity 206, and associated threshold voltage distributions 208-1, 208-2, 209-1 and 209-2 for the first memory cell 201-5 whose memory state can be stored as an expected data value corresponding to one data value and the second memory cell 204-5 whose memory state can be stored as an expected data value (e.g., as a reference). FIG. 2G also illustrates associated threshold voltage distributions 208-1, 208-2, 209-1, and 209-2 for the second pair of memory cells 201-6 and 204-6 and the memory states 202-1 and 202-2 of the first memory cell 201-6 and the second memory cell 204-6 in the positive polarity 207. In various embodiments, memory cells 201-6 and 204-6 may be different memory cells in different polarity implementations, or may be the same as memory cells 201-5 and 204-5 in which positive polarity 207 is applied instead of negative polarity 206.

Thus, the left side of FIG. 2G illustrates programming both memory cells 201-5 and 204-5 in negative polarity 206 for a negative read using one of a pair of complementary memory states 202-1 and 202-2 for a first (intended) memory cell 201-5 and the same one of the pair of complementary memory states 202-1 and 202-2 for a second memory cell (reference) memory cell 204-5. As such, a first memory cell 201-5 may store an expected memory state, and a second memory cell 204-5 may store a reference memory state to be compared to the expected memory state of the first memory cell to determine whether it properly stores the same memory state (e.g., a match data value of 0 or a match data value of 1 for two of the paired memory cells).

The difference between the first memory state and the second memory state may be determined based on a difference in magnitude of an absolute value of a voltage that may be stored by each of the two memory cells. For example, memory cells 201-5, 204-5 having voltage values in threshold voltage distributions 208-1, 209-1 with smaller magnitudes are in a first memory state 202-1, and memory cells having voltage values in threshold voltage distributions 208-2, 209-2 with larger magnitudes are in a second memory state 202-2. For the first and second memory cells, the first sensing voltage 210-5 may be selectively positioned at a magnitude smaller than and at an edge of a threshold voltage distribution having a larger magnitude. The first sensing voltage 210-5 may be the only sensing voltage used in this embodiment, or the second sensing voltage 211-5 may be selectively positioned at substantially the same amount level as the first sensing voltage 210-5 or at a different amount level therefrom. For consistency, the first sensing voltage 210-5 and/or the second sensing voltage 211-5 may be referred to as forming ends of or in the sensing window.

The left (negative polarity 206) side of FIG. 2G illustrates whether the first sense voltage 210-5 is used to determine whether the first memory cell 201-5 storing the expected data value is in the first memory state 202-1 or the second memory state 202-2, and also uses the first sense voltage 210-5 to determine whether the second memory cell 204-5 storing the reference data value is in the first memory state or the second memory state. When the memory state of either first memory cell 201-5 or second memory cell 204-5 has been shifted such that at least a portion of threshold voltage distributions 208-1, 208-2, 209-1, and 209-2 overlap with first sensing voltage 210-5, it may be determined that first memory cell 201-5 and second memory cell 204-5 are in different memory states.

As shown in row 215 of truth table 213-5, the first memory cell 201-5 storing the intended memory state as the first memory state 202-1 at a larger magnitude and the second memory cell 204-5 storing the reference memory state as the first memory state 202-1 at a smaller magnitude are readability reliable. Greater reliability is based on the threshold voltage distributions 208-1, 209-1 of the first memory cell (1 st MC)201-5 and the second memory cell (2 nd MC)201-5 having a smaller magnitude in the first memory state 202-1 being more separated from the first sensing voltage 210-5 than the threshold voltage distributions 208-2, 209-2 of the second memory state 202-2 having a larger magnitude. Based on the greater reliability of the combination shown in row 215, the inverse of the memory state that is reliable for readability may be determined, with first memory cell 201-5 storing the intended memory state as the first memory state (with data value 1) and second memory cell 204-5 also storing the reference memory state as the second memory state at a greater magnitude, as shown in row 214 of truth table 213-5, being less reliable for readability because memory cells are more likely to switch memory states due to the threshold voltage distribution shifting to at least partially overlap with the edge first sensing voltage 210-5.

Truth table 213-5 may be used to enable comparing the second memory state 202-2 of the first and second memory cells 201-5 and 204-5, which have less reliable readability, to the sensed memory state of the first memory cell storing the expected memory state and the sensed memory state of the second memory cell storing the reference memory state. The comparison may result in determining 218 the first memory cell 201-5 storing the expected memory state based on the difference between the readability of the first memory cell less reliable second memory state (e.g., data value 1) and the sensed memory state (e.g., data value 0) of the first memory state, as shown in row 216 of truth table 213-5, as a memory cell that has been switched from one memory state to another memory state. Alternatively, the comparison may result in determining 219 that the second memory cell 204-5 storing the reference memory state is a memory cell that has switched from one memory state to another memory state based on a difference between the less reliable second memory state (e.g., data value 1) of the second memory cell's readability and the sensed memory state (e.g., data value 0) of the second memory cell, as shown in row 217 of truth table 213-5.

Further, truth table 213-5 may be used to reprogram memory cells that have switched their memory state back to their complementary memory state in response to determining which of the two memory cells has switched their memory state. For example, as shown in FIG. 2G, it is determined 218 that the data value of the first memory cell shown in row 214 has switched to the data value of 0 of the first memory cell shown in row 216, so that the first memory cell can be reprogrammed back to its original memory state 1. In addition, it is determined 219 that the data value 1 of the second memory cell shown in row 214 has switched to the data value 0 of the second memory cell shown in row 217, so that the second memory cell can be reprogrammed back to its original memory state of 1. Reprogramming the switched memory state of the second memory cell or the first memory cell back to its original complementary memory state may enable one data value to be determined as expected for the same memory state of both memory cells, as indicated in the "result" column of truth table 213-5.

The right side of FIG. 2G illustrates programming two memory cells 201-6 and 204-6 in positive polarity 207 for a positive read using one of a pair of complementary memory states 202-1 and 202-2 for a first (intended) memory cell 201-6 and the same one of the pair of complementary memory states 202-1 and 202-2 for a second memory cell (reference) memory cell 204-6. As such, a first memory cell 201-6 may store an expected memory state, and a second memory cell 204-6 may store a reference memory state to be compared to the expected memory state of the first memory cell to determine whether it properly stores the same memory state (e.g., a match data value of 0 or a match data value of 1 for two of the paired memory cells).

The difference between the first memory state and the second memory state may be determined based on a difference in magnitude of an absolute value of a voltage that may be stored by each of the two memory cells. For example, memory cells 201-6, 204-6 having voltage values in threshold voltage distributions 208-1, 209-1 with larger magnitudes are in a first memory state 202-1, and memory cells having voltage values in threshold voltage distributions 208-2, 209-2 with smaller magnitudes are in a second memory state 202-2. For the first and second memory cells, the first sensing voltage 210-6 may be selectively positioned at a magnitude greater than and at an edge of a threshold voltage distribution having a smaller magnitude. The first sensing voltage 210-6 may be the only sensing voltage used in this embodiment, or the second sensing voltage 211-6 may be selectively positioned at substantially the same amount of level as the first sensing voltage 210-6 or at a different amount of level than the first sensing voltage 210-6.

The right (positive polarity 207) side of FIG. 2G illustrates whether the first sense voltage 210-6 is used to determine whether the first memory cell 201-6 storing the expected data value is in the first memory state 202-1 or the second memory state 202-2, and also uses the first sense voltage 210-6 to determine whether the second memory cell 204-6 storing the reference data value is in the first memory state or the second memory state. When the memory state of either first memory cell 201-6 or second memory cell 204-6 has been shifted such that at least a portion of threshold voltage distributions 208-1, 208-2, 209-1, and 209-2 overlap with first sensing voltage 210-6, it may be determined that first memory cell 201-6 and second memory cell 204-6 are in different memory states.

As shown in row 215 of truth table 213-6, the first memory cell 201-6 storing the intended memory state as the first memory state 202-1 at the larger magnitude and the second memory cell 204-6 storing the reference memory state as the first memory state 202-1 at the larger magnitude are readability reliable. The greater reliability is based on the threshold voltage distributions 208-1, 209-1 of the first memory cell 201-6 and the second memory cell 204-6 having a greater magnitude being more separated from the first sensing voltage 210-6 than the threshold voltage distributions 208-2, 209-2 of the second memory state 202-2 having a lesser magnitude. Based on the greater reliability of the combination shown in row 215, the inverse of the memory state that is reliable for readability may be determined, with the first memory cell 201-6 storing the expected memory state as the first memory state (with data value 1) and the second memory cell 204-6 also storing the reference memory state as the second memory state at a smaller magnitude, as shown in row 214 of truth table 213-6, being less reliable for readability because the memory cells are more likely to switch memory states due to the threshold voltage distribution shifting to at least partially overlap with the edge first sensing voltage 210-6.

The truth table 213-6 may be configured to compare the second memory state 202-2 of the first memory cell 201-6 and the second memory cell 204-6 having less reliable readability with the sensed memory state of the first memory cell storing the expected memory state and the sensed memory state of the second memory cell storing the reference memory state. The comparison may result in determining 218 the first memory cell 201-6 storing the expected memory state based on the difference between the readability of the first memory cell less reliable second memory state (e.g., data value 1) and the sensed memory state (e.g., data value 0) of the first memory state, as shown in row 216 of truth table 213-6, as a memory cell that has been switched from one memory state to another memory state. Alternatively, the comparison may result in determining 219 that the second memory cell 204-6 storing the reference memory state is a memory cell that has switched from one memory state to another memory state based on a difference between the less reliable second memory state (e.g., data value 1) of the second memory cell's readability and the sensed memory state (e.g., data value 0) of the second memory cell, as shown in row 217 of truth table 213-6.

Further, truth tables 213-6 may be used to reprogram memory cells that have switched their memory state back to their complementary memory state in response to determining which of the two memory cells has switched their memory state. For example, it is determined 218 that the data value of 1 for the first memory cell shown in row 214 has switched to the data value of 0 for the first memory cell shown in row 216, enabling the first memory cell to be reprogrammed back to its original memory. The state is 1. In addition, it is determined 219 that the data value 1 of the second memory cell shown in row 214 has switched to the data value 0 of the second memory cell shown in row 217, so that the second memory cell can be reprogrammed back to its original memory state of 1. Reprogramming the switched memory state of the second memory cell or the first memory cell back to its original complementary memory state may enable one data value to be determined as expected for the same memory state of both memory cells, as indicated in the "result" column of truth tables 213-6.

In the various embodiments presented above, the present disclosure describes sensing a memory state of each of two memory cells of a plurality of memory cells to determine one data value. A data value may be determined by: a memory state of a first of the two memory cells is sensed using a first sensing voltage in a sensing window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state. Some embodiments may include sensing a memory state of a second of the two memory cells using a second sensing voltage (e.g., at substantially the same or different magnitude) in the sensing window. The first sensing voltage and/or the second sensing voltage may be selectively positioned closer to the first threshold voltage distribution or the second threshold voltage distribution in the sensing window.

For example, as shown and described in connection with fig. 2A and 2D, sensing a memory state may include selecting a first sense voltage and a second sense voltage to have a negative polarity. The first sensing voltage may be located closer to the first threshold voltage distribution than the second threshold voltage distribution, and the second sensing voltage may be located closer to the second threshold voltage distribution than the first threshold voltage distribution, or vice versa. As shown and described in connection with fig. 2E and 2F, sensing a memory state may include selecting a first sensing voltage and a second sensing voltage to have a positive polarity. The first sensing voltage may be located closer to the first threshold voltage distribution than the second threshold voltage distribution, and the second sensing voltage may be located closer to the second threshold voltage distribution than the first threshold voltage distribution, or vice versa. As shown and described in connection with fig. 2G, sensing a memory state can include selecting the first sensing voltage and the second sensing voltage to both have a negative polarity or a positive polarity of the same magnitude. Both the first sensing voltage and the second sensing voltage may be positioned closer to the first threshold voltage distribution than the second threshold voltage distribution, or vice versa.

FIG. 3 is a block diagram illustration of an example apparatus (e.g., electronic memory system 300) in accordance with an embodiment of the disclosure. Memory system 300 can include an apparatus such as a memory device 302 and a controller 304 such as a memory controller (e.g., a host controller). For example, the controller 304 may include a processor. The controller 304 may, for example, be coupled to a host, and may receive command signals (or commands), address signals (or addresses), and data signals (or data) from the host, and may output data to the host.

The memory device 302 includes a memory array 306 of memory cells. For example, the memory array 306 may include one or more of the memory arrays of memory cells disclosed herein, such as a cross-point array. Memory device 302 may include address circuitry 308 to latch address signals provided over I/O connections 310 through/O circuitry 312. Address signals may be received and decoded by a row decoder 314 and a column decoder 316 to access the memory array 306. For example, row decoder 314 and/or column decoder 316 may include drivers.

The memory device 302 can sense (e.g., read) data in the memory array 306 by sensing voltage and/or current changes in the memory array columns using sense/buffer circuitry, which in some examples can be read/latch circuitry 320. The read/latch circuitry 320 can read and latch data from the memory array 306. The sensing circuitry 305 can include a plurality of sense amplifiers coupled to the memory cells of the memory array 306, which can operate in conjunction with read/latch circuitry 320 to sense (read) a memory state from a target memory cell. I/O circuitry 312 may be included for bi-directional data communication over the I/O connections 310 with the controller 304. Write circuitry 322 may be included to write data to the memory array 306.

Control circuitry 324 may decode signals provided from controller 304 by control connections 326. These signals may include chip signals, write enable signals, and address latch signals to control operations on the memory array 306, including data read and data write operations.

For example, the control circuitry 324 may be included in the controller 304. The controller 304 may include other circuitry, firmware, software, etc., alone or in combination. The controller 304 can be an external controller (e.g., in a separate die from the memory array 306, whether in whole or in part) or an internal controller (e.g., included in the same die as the memory array 306). For example, the internal controller may be a state machine or a memory sequencer.

In some examples, the controller 304 may be configured to cause the memory device 302 to perform at least the methods disclosed herein, such as sensing two memory cells to determine one data value. In some examples, memory device 302 may include the circuitry previously described in connection with fig. 1 and 2A-2G. For example, memory device 302 may include circuitry such as sense amplifiers, latches, truth tables, word and bit lines, and/or pairs of memory cells, as well as other circuitry disclosed herein.

As used herein, the term "coupled" may include not electrically coupled, directly coupled, and/or directly connected (e.g., by direct physical contact) to intermediate elements or indirectly coupled and/or connected to intermediate elements. The term "coupled" may further include two or more elements that cooperate or interact with each other (e.g., as a cause and effect relationship).

It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory system 300 of FIG. 3 has been simplified. It should be recognized that the functionality of the various block components described with reference to fig. 3 may not necessarily need to be isolated to distinguish the components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform the functionality of more than one block component of fig. 3. Alternatively, one or more components or component portions of an integrated circuit device may be combined to perform the functionality of a single block component of fig. 3.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that an arrangement that is calculated to achieve the same result may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of ordinary skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. The scope of various embodiments of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

In the foregoing detailed description, certain features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.