阅读说明：本技术 确定以经优化读取电压为中心的信号和噪声特性 (Determining signal and noise characteristics centered on optimized read voltage ) 是由 P·R·哈亚特 S·帕塔萨拉蒂 J·菲兹帕特里克 于 2021-05-07 设计创作，主要内容包括：本申请涉及确定以经优化读取电压为中心的信号和噪声特性。一种存储器装置响应于识别存储器单元群组的命令而估计所述存储器单元群组的信号和噪声特性。例如,所述存储器装置基于第一测试电压测量所述存储器单元群组的第一信号和噪声特性,使用所述第一信号和噪声特性计算所述存储器单元群组的经优化读取电压,并使用所述第一信号和噪声特性估计所述存储器单元群组的第二信号和噪声特性,其中所述第二信号和噪声特性是基于以所述存储器单元群组的所述经优化读取电压为中心的第二测试电压。(The application relates to determining signal and noise characteristics centered around an optimized read voltage. A memory device estimates signal and noise characteristics of a group of memory cells in response to a command identifying the group of memory cells. For example, the memory device measures a first signal and noise characteristic of the group of memory cells based on a first test voltage, calculates an optimized read voltage for the group of memory cells using the first signal and noise characteristic, and estimates a second signal and noise characteristic for the group of memory cells using the first signal and noise characteristic, wherein the second signal and noise characteristic is based on a second test voltage centered on the optimized read voltage for the group of memory cells.)

1. A memory device, comprising:

an integrated circuit package enclosing the memory device; and

a plurality of groups of memory cells formed on at least one integrated circuit die;

wherein in response to a command identifying a group of memory cells within the plurality of groups, the memory device is configured to:

measuring a first signal and noise characteristic of the group of memory cells based on a first test voltage;

calculating an optimized read voltage for the group of memory cells as a function of the first signal and noise characteristics; and

estimating, from the first signal and noise characteristics, a second signal and noise characteristic of the group of memory cells based on a second test voltage centered on the optimized read voltage of the group of memory cells.

2. The memory device of claim 1, wherein the first test voltages are equally spaced by a predetermined voltage gap.

3. The memory device of claim 2, wherein to measure the first signal and noise characteristic, the memory device is configured to:

reading the group of memory cells at the plurality of first test voltages;

determining a bit count at the first test voltage, respectively, wherein each bit count at a test voltage identifies a number of memory cells in the group that provide a predetermined bit value when read at the test voltage; and

calculating a count difference of the bit counts of pairs of adjacent voltages in the first test voltage, wherein each count difference of a voltage interval between a pair of adjacent voltages in the first test voltage is a difference between bit counts of the pair of adjacent voltages.

4. The memory device of claim 3, wherein the memory device is configured to estimate the second signal and noise characteristics from the first signal and noise characteristics without reading the group of memory cells at the second test voltage.

5. The memory device of claim 4, wherein at least two of the second test voltages are not coincident with any of the first test voltages.

6. The memory device of claim 5, wherein none of the second test voltages are coincident with any of the first test voltages.

7. The memory device of claim 4, wherein the second test voltage includes:

a first voltage that is one-half the predetermined voltage gap higher than the optimized read voltage, and

a second voltage that is one-half of the predetermined voltage gap lower than the optimized read voltage.

8. The memory device of claim 7, wherein the second signal and noise characteristic includes a count difference between a bit count at the first voltage and a bit count at the second voltage.

9. The memory device of claim 8, wherein the second test voltage further comprises:

a third voltage higher than the optimized read voltage by the predetermined voltage gap, and

a fourth voltage lower than the optimized read voltage by the predetermined voltage gap.

10. The memory device of claim 9, wherein the second signal and noise characteristic includes a count difference between a bit count at the third voltage and a bit count at the fourth voltage.

11. The memory device of claim 10, wherein when it is determined that the optimized read voltage is in a voltage interval of a first count difference, the first count difference is not greater than two second count differences having a voltage interval that encloses the voltage interval of the first count difference, the memory device configured to estimate the second signal and noise characteristic based on an increase from the first count difference and a ratio between the two second count differences.

12. The memory device of claim 11, wherein the memory device is configured to estimate the second signal and noise characteristics based on a comparison of the ratio to 1/8, 1/4, 4, and 8.

13. The memory device of claim 10, wherein when it is determined that the optimized read voltage is in a voltage interval of a first count difference that is not enclosed within two count differences of the bit counts of the adjacent voltage pairs in the first test voltage, the memory device is configured to estimate the second signal and noise characteristic based on a ratio between the first count difference and a second count difference whose voltage interval is closest in the count differences of the bit counts of the adjacent voltage pairs in the first test voltage to the voltage interval of the first count difference.

14. The memory device of claim 13, wherein the memory device is configured to estimate the second signal and noise characteristics based on a comparison of the ratio to 3/4, 1/2, 1/4, 1/8, 1/16, and 1/32.

15. A method, comprising:

receiving a command identifying a group of memory cells within a memory device; and

in response to the command, the computer program product,

measuring a first signal and noise characteristic of the group of memory cells based on a first test voltage;

calculating an optimized read voltage for the group of memory cells as a function of the first signal and noise characteristics; and

estimating, from the first signal and noise characteristics, a second signal and noise characteristic of the group of memory cells based on a second test voltage centered on the optimized read voltage of the group of memory cells.

16. The method of claim 15, wherein the first test voltages are separated from each other by a predetermined voltage gap; and measuring the first signal and noise characteristics comprises:

reading the group of memory cells at the plurality of first test voltages;

determining a bit count at the first test voltage, respectively, wherein each bit count at a test voltage identifies a number of memory cells in the group that provide a predetermined bit value when read at the test voltage; and

calculating a count difference of the bit counts of pairs of adjacent voltages in the first test voltage, wherein each count difference of a voltage interval between a pair of adjacent voltages in the first test voltage is a difference between bit counts of the pair of adjacent voltages.

17. The method of claim 16, wherein the second test voltage comprises:

a first voltage that is one-half of the predetermined voltage gap higher than the optimized read voltage;

a second voltage that is one-half the predetermined voltage gap lower than the optimized read voltage;

a third voltage higher than the optimized read voltage by the predetermined voltage gap; and

a fourth voltage that is lower than the optimized read voltage by the predetermined voltage gap;

wherein the second signal and noise characteristics include:

a count difference between a bit count at the first voltage and a bit count at the second voltage; and

a count difference between a bit count at the third voltage and a bit count at the fourth voltage.

18. A memory subsystem, comprising:

a processing device; and

at least one memory device having a group of memory cells formed on an integrated circuit die;

wherein the processing device is configured to transmit a command to the memory device having an address identifying the group of memory cells; and

wherein in response to the command, the memory device is configured to:

measuring a first signal and noise characteristic of the group of memory cells based on a first test voltage;

calculating an optimized read voltage for the group of memory cells as a function of the first signal and noise characteristics; and

estimating, from the first signal and noise characteristics, a second signal and noise characteristic of the group of memory cells based on a second test voltage centered on the optimized read voltage of the group of memory cells.

19. The memory subsystem of claim 18, wherein adjacent pairs of the first test voltages are separated from each other by a predetermined voltage gap; and to measure the first signal and noise characteristics, the memory device is configured to:

reading the group of memory cells at the plurality of first test voltages;

determining a bit count at the first test voltage, respectively, wherein each bit count at a test voltage identifies a number of memory cells in the group that provide a predetermined bit value when read at the test voltage; and

calculating a count difference of the bit counts of pairs of adjacent voltages in the first test voltage, wherein each count difference of a voltage interval between a pair of adjacent voltages in the first test voltage is a difference between bit counts of the pair of adjacent voltages.

20. The memory subsystem of claim 19, wherein the second test voltage includes:

a first voltage that is one-half of the predetermined voltage gap higher than the optimized read voltage;

a second voltage that is one-half the predetermined voltage gap lower than the optimized read voltage;

a third voltage higher than the optimized read voltage by the predetermined voltage gap; and

a fourth voltage that is lower than the optimized read voltage by the predetermined voltage gap; and

wherein the second test voltages are all not equal to any of the first test voltages; and is

Wherein the second signal and noise characteristics include:

a count difference between a bit count at the first voltage and a bit count at the second voltage; and

a count difference between a bit count at the third voltage and a bit count at the fourth voltage.

Technical Field

At least some embodiments disclosed herein relate generally to memory systems and, more particularly, are not limited to memory systems configured to estimate signal and noise characteristics centered on an optimized voltage for reading data from a memory cell.

Background

The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, a host system may utilize a memory subsystem, storing data at and retrieving data from a memory device.

Disclosure of Invention

An aspect of the present disclosure provides a memory device, wherein the memory device includes: an integrated circuit package enclosing the memory device; and a plurality of groups of memory cells formed on at least one integrated circuit die; wherein in response to a command identifying a group of memory cells within the plurality of groups, the memory device is configured to: measuring a first signal and noise characteristic of the group of memory cells based on a first test voltage; calculating an optimized read voltage for the group of memory cells according to the first signal and noise characteristics; and estimating, from the first signal and noise characteristics, a second signal and noise characteristic of the group of memory cells based on a second test voltage centered on the optimized read voltage of the group of memory cells.

Another aspect of the present disclosure provides a method, wherein the method comprises: receiving a command identifying a group of memory cells within a memory device; and measuring a first signal and noise characteristic of the group of memory cells based on a first test voltage in response to the command; calculating an optimized read voltage for the group of memory cells as a function of the first signal and noise characteristics; and estimating, from the first signal and noise characteristics, second signal and noise characteristics of the group of memory cells based on a second test voltage centered on the optimized read voltage of the group of memory cells.

Another aspect of the present disclosure provides a memory subsystem, wherein the memory subsystem comprises: a processing device; and at least one memory device having a group of memory cells formed on an integrated circuit die; wherein the processing device is configured to transmit a command to the memory device having an address identifying the group of memory cells; wherein in response to the command, the memory device is configured to: measuring a first signal and noise characteristic of the group of memory cells based on a first test voltage; calculating an optimized read voltage for the group of memory cells as a function of the first signal and noise characteristics; and estimating, from the first signal and noise characteristics, a second signal and noise characteristic of the group of memory cells based on a second test voltage centered on the optimized read voltage of the group of memory cells.

Drawings

Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

FIG. 1 illustrates an example computing system having a memory subsystem in accordance with some embodiments of the present disclosure.

FIG. 2 illustrates an integrated circuit memory device having a calibration circuit configured to measure signal and noise characteristics, according to one embodiment.

FIG. 3 illustrates an example of measuring signal and noise characteristics to improve memory operation according to one embodiment.

4-6 illustrate a technique to calculate an optimized read voltage from a count difference according to one embodiment.

7-10 illustrate a technique for estimating signal and noise characteristics centered on an optimized read voltage according to one embodiment.

FIG. 11 illustrates a method of calculating signal and noise characteristics centered on an optimized read voltage for reading a group of memory cells, according to one embodiment.

FIG. 12 is a block diagram of an example computer system in which embodiments of the present disclosure may operate.

Detailed Description

At least some aspects of the present disclosure relate to a memory subsystem configured to measure signal and noise characteristics of a group of memory cells to calculate an optimized voltage for reading the group of memory cells and to estimate signal and noise characteristics centered around the optimized read voltage based on the measured signal and noise characteristics. Examples of memory devices and memory modules are described below in conjunction with FIG. 1. In general, a host system may utilize a memory subsystem that includes one or more components (e.g., memory devices) that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

Integrated circuit memory cells (e.g., flash memory cells) can be programmed at a threshold voltage to store data by virtue of their state. For example, if a memory cell is configured/programmed to be in a state that allows a large amount of current to pass through the memory cell at a threshold voltage, then the memory cell is storing a bit one; otherwise the memory cell is storing bit zero. Furthermore, a memory cell may store multiple bits of data by being configured/programmed differently at multiple threshold voltages. For example, a memory cell may store multiple bits of data by having combinations of states at multiple threshold voltages; and different combinations of states of the memory cells at the threshold voltages can be interpreted as representing different states of a data bit stored in the memory cell.

However, after configuring/programming the state of an integrated circuit memory cell using a write operation to store data in the memory cell, the optimized threshold voltage for reading the memory cell may shift due to several factors such as charge loss, read disturb, cross temperature effects (e.g., write and read at different operating temperatures), particularly when the memory cell is programmed to store multiple bits of data.

The data may be encoded with redundant information to facilitate error detection and recovery. When data encoded with redundant information is stored in the memory subsystem, the memory subsystem may detect errors in the original encoded data retrieved from the memory subsystem and/or recover the original uncoded data used to generate the encoded data for storage in the memory subsystem. The recovery operation may succeed (or have a high probability of success) when the original encoded data retrieved from the memory subsystem contains less than a threshold amount of errors or the bit error rate in the encoded data is below a threshold. For example, error detection and data recovery may be performed using techniques such as Error Correction Codes (ECC), Low Density Parity Check (LDPC) codes, and the like.

When the encoded data retrieved from the memory cells of the memory subsystem is too many errors to be successfully decoded, the memory subsystem may retry executing the read command using the adjustment parameters for reading the memory cells. However, searching for a parameter set by multiple read retries with multiple rounds of calibration, reads, decode failures, and retries until the encoded data retrieved from the memory cell can be decoded as error-free data is very inefficient. For example, blindly searching for an optimized read voltage is inefficient. For example, one or more commands introduced between retries of a read may result in a long latency to recover data from the error.

Conventional calibration circuitry has been used to self-calibrate the memory region in applying a read level signal in view of the shifting of the threshold voltages of the memory cells within the memory region. During calibration, the calibration circuitry is configured to apply different test signals to the memory regions to count the number of memory cells outputting a specified data state of the test signal. Based on the count, the calibration circuitry determines a read level offset value as a response to the calibration command.

At least some aspects of the present disclosure address the above and other deficiencies by calculating voltages optimized to read a group of memory cells from signal and noise characteristics of the group of memory cells using an efficient method that may be implemented in a memory device. After the optimized read voltage is calculated from the measured signal and noise characteristics, the signal and noise characteristics centered on the optimized read voltage may be estimated from the measured signal and noise characteristics (e.g., to estimate the bit error rate).

For example, in response to a command from a controller of the memory subsystem, the memory device may automatically calibrate voltages used to read groups of memory cells based on measured signal and noise characteristics for the memory cells. When applying a test voltage to read a memory cell, the signal and noise characteristics measured for the memory cell may be based on the bit count of the memory cells in the group having the predetermined state. Different test voltages that are separated from each other by a predetermined voltage interval or gap may have different bit counts. The difference in the bit counts of two adjacent test voltages provides a count difference in the voltage spacing or gap between the adjacent test voltages. The optimized read voltage may be obtained at a voltage where the distribution of the count difference over the voltages reaches a minimum.

When one of the count differences is less than its two adjacent neighbors, the minimum may be determined to be in the voltage interval or gap of the smallest count difference. As discussed further below in connection with FIG. 5, an improved location of an optimized read voltage within a gap may be calculated based on a ratio of adjacent neighbors.

When there is no count difference between two higher adjacent neighbors, the optimized read voltage may be identified as being in a voltage interval or gap corresponding to a count difference that is less than two of the next two count differences. As discussed further below in connection with FIG. 6, the improved position of the optimized read voltage within the gap may be calculated based on the ratio of the bit counts at the test voltage across the gap.

After the optimized read voltage is calculated (e.g., using the techniques illustrated in fig. 3-6), the memory device may read the memory cells and obtain hard bit data using the optimized read voltage, and optionally modulate the applied read voltage to an adjacent voltage to further read the memory cells for soft bit data.

Preferably, the operations of reading the hard bit data and reading the soft bit data are scheduled together during execution of the read command to minimize the time required to obtain the soft bit data and/or to avoid delays that may be caused by processing a separate read command or by intermediate operations on the memory cells.

Optionally, the signal and noise characteristics measured for the memory cell are further used to evaluate the quality of the hard bit data retrieved using the calibrated read voltage. The evaluation may be performed at least partially concurrently with the reading of the hard bit data. Based on the evaluated quality of the hard bit data, the memory device may selectively read and/or transmit the soft bit data.

Hard bit data retrieved from a group of memory cells using a calibrated/optimized read voltage may be decoded using error detection and data recovery techniques, such as Error Correction Codes (ECC), Low Density Parity Check (LDPC) codes, and so forth. When the error rate in the hard bit data is high, the soft bit data retrieved from memory cells using read voltages having predetermined offsets relative to the calibrated/optimized read voltages can be used to assist in decoding the hard bit data. When soft bit data is used, error resilience in decoding hard bit data is improved.

Optionally, a controller of the memory subsystem may first send a command to the memory device to read the hard bit data with the calibrated read voltage; and in response to a failure to decode the hard bit data, the controller may further send a command to the memory device to read the corresponding soft bit data. Such an implementation is effective when the probability of a hard bit data decoding failure without soft bit data is below a threshold. However, when the probability is higher than the threshold, the overhead of sending a separate command becomes disadvantageous.

When the probability of using soft bit data is above a threshold, it is advantageous to transmit a single command to the memory device to cause the memory device to read the soft bit data and hard bit data together. In addition, the memory device may use the signal and noise characteristics of the memory cells to predict whether soft bit data is likely to be used by the controller. If the probability of using the soft bit data is less than the threshold, the memory device may skip the operation of reading the soft bit data.

For example, during a calibration operation, the memory device may measure signal and noise characteristics of the memory cells and use the measurements to calculate an optimized/calibrated read voltage for reading the memory cells. Once the optimized/calibrated read voltage is obtained, the memory device reads the memory cells to obtain the hard bit data. Subsequently, the memory device adjusts the optimized/calibrated read voltage that has been applied (e.g., by boost modulation) to be lower than the optimized/calibrated read voltage by a predetermined offset (e.g., 50mV) to retrieve the data set, and further adjusts the currently applied voltage (e.g., by boost modulation) to be higher than the optimized/calibrated read voltage by a predetermined offset to retrieve another data set. An XOR (exclusive or) logical operation of the two sets of data at both sides of the offset (e.g., 50mV) relative to the optimized/calibrated read voltage provides an indication of whether the memory cell is doing the same read at the offset location around the optimized/calibrated read voltage. The result of the XOR operation may be used as soft bit data for decoding hard bit data read using the optimized/calibrated read voltage. In some implementations, another set of soft bit data can be read using a larger offset (e.g., 90mV), thereby indicating whether the memory cell is reading the same at a location consistent with a larger offset (e.g., 90mV) around the optimized/calibrated read voltage.

For example, in response to a read command from a controller of the memory subsystem, a memory device of the memory subsystem performs an operation to calibrate a read voltage of the memory cell. Calibration is performed by reading memory cell measurement signals and noise characteristics at multiple voltage levels near the estimated location of the optimized read voltage. The optimized read voltage may be calculated based on statistics of results produced by reading the memory cell at the voltage level. For example, the statistical data may include and/or may be based on counts measured by the calibration circuitry at the voltage level. Optionally, such signal and noise characteristics may be measured in parallel for the sub-regions to shorten the total time for measuring the signal and noise characteristics. Statistics of the results produced by reading a memory cell at a voltage level can be used to predict whether decoding of hard bit data retrieved using an optimized read voltage is likely to require successful decoding using soft bit data. Accordingly, transmission of soft bit data may be selectively performed based on the prediction.

For example, a predictive model may be generated by machine learning to estimate or evaluate the quality of data that may be retrieved from a set of memory cells using calibrated/optimized read voltages. The prediction model may use features calculated from measured signal and noise characteristics of the memory cells as inputs to generate the prediction. Reading and/or transmission of soft bit data may be selectively skipped based on the prediction.

The data quality (e.g., error rate of hard bit data) read using the optimized read voltage may be estimated using the signal and noise characteristics of the group of memory cells. Preferably, the signal and noise characteristics used to estimate the error rate of the hard bit data are based on a test voltage centered on the optimized read voltage. For example, the count difference between the bit counts centered at two test voltages of the optimized read voltage can be used to classify the error rate of hard bit data read using the optimized read voltage. In general, the test voltages used to measure the signal and noise characteristics to calculate the optimized read voltage are not centered on the calculated optimized read voltage. However, simplified techniques may be used to estimate the signal and noise characteristics that will be measured at test voltages arranged according to the optimized read voltages, as discussed further in connection with FIGS. 7-11.

FIG. 1 illustrates an example computing system 100 that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

Memory subsystem 110 may be a memory device, a memory module, or a mixture of memory devices and memory modules. Examples of storage devices include Solid State Drives (SSDs), flash drives, Universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and Hard Disk Drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an aircraft, drone, train, automobile, or other vehicle), an internet of things (IoT) -enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or networked business device), or such computing device including memory and processing devices.

The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. FIG. 1 shows one example of a host system 120 coupled to one memory subsystem 110. As used herein, "coupled to" or "coupled with … …" generally refers to a connection between components that may be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including electrical, optical, magnetic, etc. connections.

Host system 120 may include a processor chipset (e.g., processing device 118) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., controller 116) (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The memory subsystem 110 is used by the host system 120, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a Universal Serial Bus (USB) interface, a fibre channel, a serial attached SCSI (sas), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), a Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further utilize an NVM express (NVMe) interface to access components (e.g., the memory device 130) when the memory subsystem 110 is coupled with the host system 120 over a PCIe interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. By way of example, FIG. 1 illustrates a memory subsystem 110. In general, the host system 120 may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and/or a combination of communication connections.

The processing device 118 of the host system 120 may be, for example, a microprocessor, a Central Processing Unit (CPU), a processing core of a processor, an execution unit, or the like. In some cases, the controller 116 may be referred to as a memory controller, a memory management unit, and/or an initiator. In one example, the controller 116 controls communication over a bus coupled between the host system 120 and the memory subsystem 110. In general, the controller 116 may send commands or requests to the memory subsystem 110 that desire access to the memory devices 130, 140. The controller 116 may further include interface circuitry for communicating with the memory subsystem 110. The interface circuitry may convert responses received from the memory subsystem 110 into information for the host system 120.

The controller 116 of the host system 120 may communicate with the controller 115 of the memory subsystem 110 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, 140, among other such operations. In some cases, the controller 116 is integrated within the same package as the processing device 118. In other cases, the controller 116 is separate from the packaging of the processing device 118. The controller 116 and/or the processing device 118 may include hardware, such as one or more Integrated Circuits (ICs) and/or discrete components, cache memory, or a combination thereof. The controller 116 and/or the processing device 118 may be a microcontroller, special purpose logic circuitry (e.g., a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), etc.), or another suitable processor.

Memory devices 130, 140 may include any combination of different types of non-volatile memory components and/or volatile memory components. Volatile memory devices, such as memory device 140, may be, but are not limited to, Random Access Memory (RAM), such as Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM).

Some examples of non-volatile memory components include NAND (or NOT AND) (NAND) type flash memory AND write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. The non-volatile memory cross-grid array may perform bit storage based on changes in body resistance in conjunction with the stackable cross-gridded data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memories can perform in-place write operations in which a non-volatile memory cell can be programmed if it has been previously erased. The NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

Each of memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a Single Level Cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, as well as an MLC portion, a TLC portion, or a QLC portion of a memory cell. The memory cells of memory device 130 may be grouped into pages, which may refer to logical units of the memory device for storing data. In some types of memory (e.g., NAND), pages may be grouped to form blocks.

Although non-volatile memory devices are described, such as 3D cross-point and NAND type memories (e.g., 2D NAND, 3D NAND), memory device 130 may be based on any other type of non-volatile memory, such as Read Only Memory (ROM), Phase Change Memory (PCM), self-selection memory, other chalcogenide based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), Magnetic Random Access Memory (MRAM), Spin Transfer Torque (STT) -MRAM, conductive bridge ram (cbram), Resistive Random Access Memory (RRAM), oxide based RRAM (oxram), NOR (NOR) flash memory, and Electrically Erasable Programmable Read Only Memory (EEPROM).

Memory subsystem controller 115 (or controller 115 for simplicity) may communicate with memory device 130 to perform operations, such as reading data, writing data, or erasing data at memory device 130 and other such operations (e.g., in response to commands scheduled by controller 116 on a command bus). The controller 115 may include hardware such as one or more Integrated Circuits (ICs) and/or discrete components, cache memory, or a combination thereof. The hardware may comprise digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller 115 may be a microcontroller, special purpose logic circuitry (e.g., a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), etc.), or another suitable processor.

The controller 115 may include a processing device 117 (processor) configured to execute instructions stored in the local memory 119. In the example shown, the local memory 119 of the controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, and so forth. Local memory 119 may also include Read Only Memory (ROM) for storing microcode. Although the embodiment memory subsystem 110 in fig. 1 is shown as including a controller 115, in another embodiment of the present disclosure, the memory subsystem 110 does not include a controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and Error Correction Code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., Logical Block Addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The controller 115 may further include host interface circuitry for communicating with the host system 120 via a physical host interface. Host interface circuitry may convert commands received from the host system into command instructions to access memory device 130 and convert responses associated with memory device 130 into information for host system 120.

Memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, memory subsystem 110 may include cache or buffers (e.g., DRAM) and address circuitry (e.g., row and column decoders) that may receive addresses from controller 115 and decode the addresses to access memory devices 130.

In some embodiments, memory device 130 includes a local media controller 150 used in conjunction with memory subsystem controller 115 to perform operations on one or more memory units of memory device 130. An external controller (e.g., memory subsystem controller 115) may manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is an original memory device combined with a local controller (e.g., local controller 150) for media management within the same memory device package. An example of a managed memory device is a managed nand (mnand) device.

Controller 115 and/or memory device 130 may include a read manager 113 configured to calculate voltages optimized to read a group of memory cells based on signal and noise characteristics of the group of memory cells and then re-estimate signal and noise characteristics of the group of memory cells centered on the optimized voltages. In some embodiments, controller 115 in memory subsystem 110 includes at least a portion of read manager 113. In other embodiments, or in combination, the controller 116 and/or the processing device 118 in the host system 120 include at least part of the read manager 113. For example, controller 115, controller 116, and/or processing device 118 may include logic circuitry that implements read manager 113. For example, the controller 115 or processing device 118 (processor) of the host system 120 may be configured to execute instructions stored in memory for performing the operations of the read manager 113 described herein. In some embodiments, read manager 113 is implemented in an integrated circuit chip disposed in memory subsystem 110. In other embodiments, read manager 113 may be part of the firmware of memory subsystem 110, the operating system of host system 120, a device driver or application, or any combination thereof.

For example, a read manager 113 implemented in the controller 115 may transmit a read command or a calibration command to the memory device 130. In response to such commands, the read manager 113 implemented in the memory device 130 is configured to measure the signal and noise characteristics of the group of memory cells by reading the group of memory cells at a plurality of test voltages configured to approximate the estimated location of the optimized read voltage for the group of memory cells. The test voltages may be configured to be equally spaced by the same amount of voltage gap. Based on the results of reading a group of memory cells at a test voltage, when the group is read at the test voltage, a bit count of the memory cells in the group is determined to store or report a predetermined bit (e.g., a 0 or 1 corresponding to a memory cell that is conductive or non-conductive at the test voltage). The count difference may be calculated from the bit count for each pair of adjacent test voltages. The read manager 113 compares the count differences to identify the voltage interval containing the optimized read voltage, and then estimates the position in the voltage interval for the optimized read voltage based on comparing the bit count or count difference closest to the voltage interval. The estimated position may be used as an optimized read voltage to read hard bit data; and a voltage having a predetermined offset relative to the optimized read voltage may be used to read the soft bit data. As part of the process of calculating the estimated position, signal and noise characteristics of a group of memory cells defined based on a test voltage centered at the estimated position may be calculated without reading the group of memory cells at a test voltage configured to be centered at the estimated position.

FIG. 2 illustrates an integrated circuit memory device 130 having a calibration circuit 145 configured to measure signal and noise characteristics, according to one embodiment. For example, memory device 130 in memory subsystem 110 of FIG. 1 may be implemented using integrated circuit memory device 130 of FIG. 2.

The integrated circuit memory device 130 may be enclosed in a single integrated circuit package. The integrated circuit memory device 130 includes a plurality of groups 131, … …, 133 of memory cells that may be formed in one or more integrated circuit dies. Typical memory cells in a group 131, … …, 133 can be programmed to store one or more bits of data.

Some memory cells in the integrated circuit memory device 130 may be configured to be used together for a particular type of operation. For example, memory cells on an integrated circuit die may be organized into planes, blocks, and pages. One plane contains a plurality of blocks; one block contains a plurality of pages; and one page may have a plurality of memory cell strings. For example, an integrated circuit die may be the smallest unit that can independently execute a command or report status; the same concurrent operation may be performed in parallel on multiple planes in an integrated circuit die; the block may be a minimum unit for performing an erase operation; and a page may be the smallest unit for performing a data programming operation (writing data into the memory cells). The memory cells of each string are connected to a common bit line; and the control gates of memory cells at the same location in the strings in a block or page are connected to a common word line. Control signals may be applied to the word lines and bit lines to address the individual memory cells.

The integrated circuit memory device 130 has a communication interface 147 to receive commands having an address 135 from the controller 115 of the memory subsystem 110, retrieve both hard bit data 177 and soft bit data 173 from the memory address 135, and provide at least the hard bit data 177 as a response to the commands. The address decoder 141 of the integrated circuit memory device 130 converts the address 135 into control signals to select a group of memory cells in the integrated circuit memory device 130; and read/write circuits 143 of integrated circuit memory device 130 perform operations to determine hard bit data 177 and soft bit data 173 of the memory cells at address 135.

The integrated circuit memory device 130 has a calibration circuit 145 configured to determine measurements of signal and noise characteristics 139 of memory cells in a group (e.g., 131, … …, or 133). For example, statistics of memory cells in a group or region having a particular state at one or more test voltages may be measured to determine signal and noise characteristics 139. Optionally, the signal and noise characteristics 139 may be provided by the memory device 130 to the controller 115 of the memory subsystem 110 via the communication interface 147.

In at least some embodiments, the calibration circuit 145 determines an optimized read voltage for a group of memory cells based on the signal and noise characteristics 139. In some embodiments, the signal and noise characteristics 139 are further used in the calibration circuit 145 to determine whether the error rate in the hard bit data 177 is high enough such that the combination of hard bit data 177 and soft bit data 173 is preferably decoded using a sophisticated decoder. When predicting use of the soft bit data 173 based on the prediction/classification of the error rate in the hard bit data 177, the read manager 113 may transmit both the soft bit data 173 and the hard bit data 177 to the controller 115 of the memory subsystem 110.

For example, the calibration circuit 145 may measure the signal and noise characteristics 139 by reading different responses from the memory cells in a group (e.g., 131, … …, 133) by changing an operating parameter used to read the memory cells (e.g., a voltage applied during an operation to read data from the memory cells).

For example, calibration circuit 145 may measure signal and noise characteristics 139 on the fly when executing commands to read hard bit data 177 and soft bit data 173 from address 135. Since signal and noise characteristics 139 are measured as part of the operation of reading hard bit data 177 from address 135, signal and noise characteristics 139 may be used in read manager 113 where the latency lost in executing a command to read hard bit data 177 from address 135 is reduced or zero.

Read manager 113 of memory device 130 is configured to use signal and noise characteristics 139 to determine a voltage for reading memory cells identified by address 135 for both hard bit data and soft bit data and to determine whether to transmit soft bit data to memory subsystem controller 113.

For example, the read manager 113 may use a predictive model trained via machine learning to predict the probability that hard bit data 177 retrieved from a group of memory cells (e.g., 131 or 133) fails a data integrity test. The prediction may be based on the signal and noise characteristics 139. The read manager 113 uses the signal and noise characteristics 139 to predict the results of the test before testing using Error Correction Codes (ECC) and/or Low Density Parity Check (LDPC) codes, even before transmitting the hard bit data 177 to the decoder. Based on the predicted test results, read manager 113 determines whether to transmit soft bit data to memory subsystem controller 113 in response to the command.

For example, if the hard bit data 177 is predicted to be decoded using a low power decoder that utilizes the hard bit data 177 without utilizing the soft bit data 173, the read manager 113 may skip transmitting the soft bit data 173 to the memory subsystem controller 115; and the read manager 113 provides the hard bit data 177 read from the memory cells using the optimized read voltage calculated from the signal and noise characteristics 139 for decoding by the low power decoder. For example, the low power decoder may be implemented in memory subsystem controller 115. Alternatively, the low power decoder may be implemented in the memory device 130; and read manager 113 may provide the results of the low power decoder to memory subsystem controller 115 as a response to the received command.

For example, if it is predicted that hard bit data 177 fails to decode in a low power decoder, but can be decoded using a high power decoder that utilizes both hard bit data and soft bit data, read manager 113 may decide to provide both hard bit data 177 and soft bit data 173 for decoding by the high power decoder. For example, a high power decoder may be implemented in the controller 115. Alternatively, a high power decoder may be implemented in the memory device 130.

Optionally, if the hard bit data 137 is predicted to fail decoding in a decoder available in the memory subsystem 110, the read manager 113 may decide to skip transmitting the hard bit data 173 to the memory subsystem controller 115 and immediately initiate a read retry, such that when the memory subsystem controller 115 requests a read retry, at least a portion of the read retry operation is performed to reduce the time to respond to requests from the memory subsystem controller 115 for a read retry. For example, during a read retry, the read manager 133 instructs the calibration circuit 145 to perform a modified calibration to obtain a new set of signal and noise characteristics 139 that can be further used to determine an improved read voltage.

Data from the memory cell identified by address (135) may include hard bit data 177 and soft bit data 173. The hard bit data 177 is retrieved using the optimized read voltage. Hard bit data 177 identifies the state of memory cells that are programmed to store data and are subsequently detected in view of changes caused by factors such as charge loss, read disturb, cross-temperature effects (e.g., write and read at different operating temperatures), and the like. The soft bit data 173 is obtained by reading the memory cells using a read voltage centered at each optimized read voltage and having a predetermined offset relative to the center optimized read voltage. The XOR of the read results at the read voltages with the offset indicates whether the memory cell provides a different read result at the read voltages with the offset. Soft bit data 173 may include XOR results. In some cases, a set of XOR results is obtained based on a smaller offset; while another set of XOR results is obtained based on a larger offset. In general, multiple sets of XOR results may be obtained for multiple offsets, with each respective offset used to determine a lower read voltage and a higher read voltage, such that both the lower and higher read voltages have the same respective offset relative to an optimized read voltage, determining the XOR results.

FIG. 3 illustrates an example of measuring signal and noise characteristics 139 to improve memory operation, according to one embodiment.

In FIG. 3, the calibration circuit 145 applies different read voltages V_A、V_B、V_C、V_DAnd V_ETo read the state of the memory cells in a group (e.g., 131, … …, or 133). In general, more or less read voltages may be used to generate the signal and noise characteristics 139.

Because the voltages applied during a read operation are different, the same memory cell in a group (e.g., 131, … …, or 133) may show different states. Thus, in general, at different read voltages V_A、V_B、V_C、V_DAnd V_ECount of memory cells having a predetermined state C_A、C_B、C_C、C_DAnd C_EMay be different. The predetermined state may be a state in which a large amount of current passes through the memory cell, or a state in which a large amount of current does not pass through the memory cell. Count C_A、C_B、C_C、C_DAnd C_EMay be referred to as a bit count.

Calibration circuit 145 may be implemented by applying read voltage V, one at a time, across a group of memory cells (e.g., 131, … …, or 133)_A、V_B、V_C、V_DAnd V_ETo measure the bit count.

Alternatively, a group of memory cells (e.g., 131, … …, or 133) may be configured as multiple subgroups; and the calibration circuit 145 may be enabled by applying the read voltage V_A、V_B、V_C、V_DAnd V_EThe bit counts of the quantum groups are measured in parallel. The bit count of a subgroup is considered to represent the bit count in the entire group (e.g., 131, … …, or 133). Thus, a count C is obtained_A、C_B、C_C、C_DAnd C_EThe duration of time can be shortened.

In some embodiments, the mapping from execution to one or more stores in a group (e.g., 131, … …, or 133) is performedMeasuring a bit count C during a command to read data 137 from an address 135 of a memory cell_A、C_B、C_C、C_DAnd C_E. Thus, the controller 115 need not send a separate command to request bit count based C_A、C_B、C_C、C_DAnd C_ESignal and noise characteristics 139.

The difference between the bit counts of adjacent voltages indicates an error in the state of the memory cells in the read group (e.g., 133, … …, or 133).

For example, according to C_A-C_BCalculating a count difference D_ABy applying a read voltage from V_AChange to V_BBut an indication of an introduced read threshold error.

Similarly, D_B＝C_B-C_C；D_C＝C_C-C_D(ii) a And D_D＝C_D-C_E。

Based on the counting difference D_A、D_B、D_CAnd D_DThe resulting curve 157 represents a prediction of the read threshold error E as a function of read voltage. From curve 157 (and/or the count difference), the optimized read voltage V_OCan be calculated to provide the lowest read threshold error D on curve 157_MINPoint 153 of (a).

In one embodiment, the calibration circuit 145 calculates the optimized read voltage V_OAnd having the read/write circuit 143 use the optimized read voltage V_OData 137 is read from address 135.

Alternatively, calibration circuitry 145 may provide count difference D to controller 115 of memory subsystem 110 via communication interface 147_A、D_B、D_CAnd D_DAnd/or an optimized read voltage V calculated by the calibration circuit 145_O。

FIG. 3 illustrates generating a set of statistical data (e.g., bit counts and/or count differences) for use in optimized read voltages V_OThe following example of reading is made. In general, a group of memory cells may be configured to store more than one bit in the memory cells; and read access using multiple read voltagesData stored in the memory cells. The statistical data sets can be similarly measured for each of the read voltages to identify a corresponding optimized read voltage, where the test voltage in each statistical data set is configured near an expected location of the corresponding optimized read voltage. Thus, the measured signal and noise characteristics 139 for a group of memory cells (e.g., 131 or 133) may include multiple sets of statistical data measured for multiple threshold voltages, respectively.

For example, controller 115 may instruct memory device 130 to perform a read operation by providing address 135 and at least one read control parameter. For example, the read control parameter may be a suggested read voltage.

Memory device 130 may perform a read operation by determining the state of the memory cell at address 135 at a read voltage and provide data 137 according to the determined state.

During a read operation, calibration circuitry 145 of memory device 130 generates signal and noise characteristics 139. Data 137 and signal and noise characteristics 139 are provided in response from memory device 130 to controller 115. Alternatively, the processing of the signal and noise characteristics 139 may be performed at least in part using logic circuitry configured in the memory device 130. For example, processing of the signal and noise characteristics 139 may be partially or fully implemented using processing logic configured in the memory device 130. For example, processing logic may be implemented using Complementary Metal Oxide Semiconductor (CMOS) circuitry formed below an array of memory cells on an integrated circuit die of memory device 130. For example, the processing logic may be formed within an integrated circuit package of the memory device 130 on a separate integrated circuit die that is connected to the integrated circuit die having the memory cells using Through Silicon Vias (TSVs) and/or other connection techniques.

The signal and noise characteristics 139 may be determined based at least in part on the read control parameters. For example, when the read control parameter is a suggested read voltage for reading the memory cell at address 135, calibration circuit 145 may calculate a read voltage V near the suggested read voltage_A、V_B、V_C、V_DAnd V_E。

The signal and noise characteristics 139 may include a bit count C_A、C_B、C_C、C_DAnd C_E. Alternatively or in combination, the signal and noise characteristics 139 may include a count difference D_A、D_B、D_CAnd D_D。

Optionally, the calibration circuit 145 uses a method to count the difference D based on the difference_A、D_B、D_CAnd D_DCalculating an optimized read voltage V_O(ii) a And the controller 115 calculates the optimized read voltage V from the signal and noise characteristics 139 and optionally other data not available to the calibration circuit 145 using another different method_O。

When the calibration circuit 145 can be based on the count difference D generated during the read operation_A、D_B、D_CAnd D_DCalculating an optimized read voltage V_OOptionally, the signal and noise characteristics may include an optimized read voltage V_O. Further, the memory device 130 may use the optimized read voltage V when determining hard bit data in the data 137 from the memory cells at the address 135_O. Can be obtained by using a read voltage V optimized with respect to_OThe read voltage at which the predetermined offset occurs reads the memory cells to obtain the soft bit data in data 137. Alternatively, memory device 130 uses a controller-specified read voltage provided in the read control parameters when reading data 137.

Controller 115 may be configured with more processing power than calibration circuitry 145 of integrated circuit memory device 130. Moreover, the controller 115 may have other signal and noise characteristics suitable for memory cells in a group (e.g., 133, … …, or 133). Thus, in general, the controller 115 may calculate an optimized read voltage V_OFor example, for a subsequent read operation, or for a retry of the read operation.

In general, the calibration circuit 145 need not be in the form of a distribution of bit counts over a set of read voltages or in the form of a difference in counts over a set of read voltagesThe form of the closed distribution provides signal and noise characteristics 139. For example, the calibration circuit 145 may provide an optimized read voltage V calculated by the calibration circuit 145_OAs signal and noise characteristics 139.

The calibration circuit 145 may be configured to generate signal and noise characteristics 139 (e.g., a bit count or bit count difference) as a byproduct of a read operation. The generation of the signal and noise characteristics 139 may be implemented in the integrated circuit memory device 130 with little or no impact on the latency of the read operation compared to a typical read that does not generate the signal and noise characteristics 139. Thus, the calibration circuitry 145 may effectively determine the signal and noise characteristics 139 as a byproduct of performing a read operation according to commands from the controller 115 of the memory subsystem 110.

In general, the optimized read voltage V_OMay be performed within memory device 130 or by controller 115 of memory subsystem 111 receiving signal and noise characteristics 139 as part of a rich state response from memory device 130.

Can be obtained by applying an optimized read voltage V across a group of memory cells_OAnd subjected to an optimized read voltage V at the memory cell_OThe state of the memory cell is determined to obtain hard bit data 177.

Can be obtained by applying and comparing an optimized read voltage V_OThe read voltages 181 and 182 are shifted by a predetermined amount to obtain soft bit data 173. For example, the read voltage 181 is at a lower than the optimized read voltage V_OA low predetermined amount of offset 183; and the read voltage 182 is at a lower than the optimized read voltage V_OAt an offset 184 that is the same predetermined amount higher. The memory cell subjected to read voltage 181 may have a different state than the memory cell subjected to read voltage 182. Soft bit data 173 may include or indicate the XOR result of data read from memory cells using read voltages 181 and 182. The XOR result shows whether the memory cell subjected to the read voltage 181 has the same state as the read voltage 182.

4-6 illustrate a technique to calculate an optimized read voltage from a count difference according to one embodiment. The technique of FIGS. 4-6Simplification for calculating optimized read voltage V_OSuch that the operations may be implemented using reduced computing power and/or circuitry.

May be based on the test voltage V in fig. 3_A、V_B、V_C、V_DAnd V_EThe bit count and count difference are shown to perform the operations shown in fig. 4-6.

In FIG. 4, operation 201 is performed to compare two center count differences D_BAnd D_C。

If D is_BGreater than D_CThen it can be assumed that V can be_CTo V_EThe minimum is obtained on the upper half of the test voltage region in between. Thus, operation 203 is performed to count the lower of the two center bits by the difference D_CAnd another adjacent one D_DA comparison is made.

If D is_CNot greater than its other neighbor D_DThen D_CNot greater than its neighbor D_BAnd D_D. Therefore, can be deduced out, can be at the test voltage V_CAnd V_DGet the minimum value in between. Based on D_CAdjacent thereto D_BAnd D_DMay be determined using techniques similar to those shown in fig. 5_OIs estimated.

If D is_CGreater than another neighbor thereof D_DThen it can be assumed that the minimum may be at V_DAnd V_EIn the highest test voltage interval in between. Therefore, based on the closest test voltage V_DAnd V_ED of (A)_DAnd D_CMay determine the optimized read voltage V using a technique similar to that shown in FIG. 6_OIs estimated.

Similarly, if D_BNot more than D_CThen it can be assumed that V can be_ATo V_CThe minimum is obtained on the lower half of the test voltage region in between. Thus, operation 205 is performed to count the lower of the two center bits by the difference D_BAnd another adjacent one D_ARatio of performanceThen the obtained product is obtained.

If D is_BSmaller than another neighbor thereof D_AThen D_BNot greater than its neighbor D_AAnd D_C. Thus, it can be concluded that at the test voltage V_BAnd V_CGet the minimum value in between. Based on D_BAdjacent thereto D_AAnd D_CMay be determined using techniques similar to those shown in fig. 5_OIs estimated.

If D is_BNot less than another neighbor thereof D_AThen it can be assumed that the minimum may be at V_AAnd V_BIn the lowest test voltage interval in between. Therefore, based on the closest test voltage V_AAnd V_BD of (A)_AAnd D_BCan be determined using a technique similar to that shown in FIG. 6_OIs estimated.

FIG. 5 shows the center count difference D_BNot greater than its neighbor D_AAnd D_CTime-estimated optimized read voltage V_OThe location of (a).

Due to the counting difference D_BIs at a test voltage V_BAnd V_CLower bit count C_BAnd C_CIs estimated, thus estimating the optimized read voltage V_OIs located at V_BAnd V_CIn the voltage interval or gap between.

When counting the difference D from the center_BTo its neighbor D_AAnd D_CAre substantially equal to each other, the optimized read voltage V is estimated_OAt V_BAnd V_CAt the midpoint therebetween.

Counting the difference D from the center_BTo its neighbor D_AAnd D_CMay be mapped to the test voltage V in logarithmic scale_BAnd V_CThe scale grid lines in between.

For example, a ratio (D) of 1_A-D_B)/(D_C-D_B) Mapping to a test voltage V_BAnd V_CIn betweenThe location of the optimized read voltage at the midpoint.

Is a ratio (D) of 1/2_A-D_B)/(D_C-D_B) Mapping to a test voltage V_BAnd V_CThe position of the optimized read voltage at the midpoint therebetween, wherein towards V_BThe offset is a fixed increment. For example, the increment may be V_BAnd V_COne tenth of the voltage gap in between.

A ratio (D) of 1/4, 1/8 or 1/16_A-D_B)/(D_C-D_B) Mapping to a test voltage V_BAnd V_CThe position of the optimized read voltage at the midpoint therebetween, wherein towards V_BOffset by two, three or four increments. Ratio (D) less than 1/16_A-D_B)/(D_C-D_B) Is mappable to V_BThe location of the optimized read voltage.

Similarly, a ratio (D) of 1/2, 1/4, 1/8 or 1/16_C-D_B)/(D_A-D_B) Mapping to a test voltage V_BAnd V_CThe position of the optimized read voltage at the midpoint therebetween, wherein towards V_COffset by one, two, three, or four increments. Ratio (D) less than 1/16_C-D_B)/(D_A-D_B) Is mappable to V_CThe location of the optimized read voltage.

The technique of FIG. 5 may be via setting a coarse estimate of the optimized read voltage at V_B(or V)_C) And by counting the difference D_BTo the difference of counts D_AIncrease of (D)_A-D_B) And difference of count D_BTo the difference of counts D_CIncrease of (D)_C-D_B) A fraction or multiple of (a) to apply an increment to adjust the coarse estimate. Increase in logarithmic scale (D)_C-D_B) The fraction or multiple of (d) may be calculated by iteratively dividing by two or multiplying by two, which may be effectively implemented by a bitwise left or right shift operation.

For example, the optimum voltage V may be set_OIs set at a test voltage V_BTo (3). Can increase the amount (D)_A-D_B) And can be made by reacting (D)_C-D_B) Is calculated by (D)_C-D_B) A comparison was made of/16. If (D)_A-D_B) Greater than (D)_C-D_B) /16, then V_BAnd V_CAn increment of one tenth of the gap between can be added to the optimized voltage V_OAn estimate of (d). Subsequently, the (D)_A-D_B) And can be made by reacting (D)_C-D_B) Bit shift computation of/16 (D)_C-D_B) Comparison was performed at 8. If (D)_A-D_B) Greater than (D)_C-D_B) 8, then V_BAnd V_CThe same increment of one tenth of the gap therebetween is further added to the optimized voltage V_OAn estimate of (d). Similarly, will (D)_A-D_B) In sequence with (D)_C-D_B)/4、(D_C-D_B)/2、(D_C-D_B)、(D_C-D_B)*2、 (D_C-D_B)*4、(D_C-D_B) 8 and (D)_C-D_B) 16 to compare. If (D)_A-D_B) Greater than (D) in the comparison_C-D_B) Any of these scaled versions of (a), then the same increment is added to the estimate. After a series of comparisons, the resulting estimate can be used as the optimum voltage V_O。

FIG. 6 shows the count difference D when one side counts_ALess than the following two count differences D_BAnd D_CBut one of its neighbors has not yet been measured (e.g., test voltage V)_AAnd is less than V_AThe count difference between the other test voltages) is estimated_OThe location of (a).

Due to the counting difference D_AAt the difference of counts D_A、D_BAnd D_CMedium minimum, so the optimum voltage V is estimated_OAt a value corresponding to the count difference D_AIn the gap. Due to the counting difference D_AIs at a test voltage V_AAnd V_BLower bit count C_AAnd C_BIs estimated, thus estimating the optimized read voltage V_OIs located at V_AAnd V_BIn the voltage interval or gap between。

In FIG. 6, at V_AAnd V_BIn the voltage interval or gap between them_OBased on the count difference D_AAnd D_BThe ratio of (a) to (b). Ratio on logarithmic scale D_A/D_BMapping to V_AAnd V_BOptimized read voltage V between_OIs linearly distributed.

For example, V_AAnd V_BThe voltage interval or gap between may be divided into five equal increments. Can optimize the voltage V_OIs set at a test voltage V_BTo (3). The difference D can be counted in sequence_AAnd difference of count D_BScaled versions of (e.g. D)_B、D_B[ 2 ] and D_BAnd/4) comparison. If the difference D is counted in the comparison_ALess than the count difference D_BIs used to scale any of the versions, then the estimate reduction is used towards the test voltage V_AAn increment of movement.

Curve 157 in fig. 3 shows the change in the count difference as a function of the center of the test voltage interval. For example, count the difference D_AAt V_AAnd V_BAt the center of the test voltage interval in between; count difference D_BAt V_BAnd V_CAt the center of the test voltage interval in between; count difference D_CAt V_CAnd V_DAt the center of the test voltage interval in between; and the difference in count D_DAt V_DAnd V_EAt the center of the test voltage interval in between.

Lowest point D on curve 157_MINIs represented by an optimized read voltage V_OThe count difference between the centered test voltage intervals. Lowest point D_MINCan be calculated using the techniques shown in fig. 7 and 10.

Fig. 7 and 10 illustrate techniques for estimating signal and noise characteristics centered on an optimized read voltage, according to one embodiment.

When the optimized read voltage V is determined_OTesting voltage intervals (e.g. V) at the center_BTo V_CAnd V_CTo V_D) In (e.g. such asBy comparison 201-205 shown in fig. 4), optimized read voltage V_OAt two neighbors thereof (e.g. D)_AAnd D_C) Difference in count between (e.g., D)_B) In the test voltage interval of (c). Such optimized read voltage V_OLowest point D of_MINMay be determined using the technique of fig. 7.

In FIG. 7, based on D_BAdjacent thereto D_AAnd D_COf (D) a ratio of_MINMapping D_BA certain fraction of (a). When ratio (D)_A-D_B)/(D_C-D_B) Less than 1/4 or greater than 4, estimate D_MINIs D_B*3/4. When ratio (D)_A-D_B)/(D_C-D_B) Between 1/4 and 4, estimate D_MINIs D_B。

Count difference D_MINCorresponding to an optimized read voltage V_OLow test voltage gap V_B-V_CMeasured at half the test voltage and the ratio optimized read voltage V_OHigh test voltage gap V_B-V_CHalf of the test voltage. Count difference D_MINRepresenting having a bit below the optimized read voltage V in the group_OTest voltage gap V of_B-V_CIs higher than the optimized read voltage V_OTest voltage gap V of_B-V_CA count of memory cells of threshold voltage between half.

In some embodiments, the difference in counts D_MIN2Is at a ratio-optimized read voltage V_OLow integrity test voltage gap V_B-V_CMeasured at a test voltage of and above an optimized read voltage V_OComplete test voltage gap V of_B-V_CThe difference between the measured bit counts at the test voltage of (a). Such a count difference D_MIN2Can also be used to determine the use of an optimized read voltage V_OThe quality of the data read (e.g., error rate of hard bit data).

FIG. 8 shows a given ratio (D)_A-D_B)/(D_C-D_B) Lower estimate D_MIN2Examples of (3). When the ratio is between 1/4 and 4, estimate D_MIN2Is D_B+(D_A+D_C)/4. When the ratio is less than 1/4, estimate D_MIN2Is D_B+D_A(ii) a And when the ratio is greater than 4, estimate D_MIN2Is D_B+D_C. Other estimation schemes may also be used in order to simplify the calculations while maintaining a desired level of accuracy.

The mapping schemes of FIGS. 7 and 8 may be compared to the calculated optimized read voltage V shown in FIG. 5_OThe techniques of (1) are combined. In FIG. 5, the ratio (D)_A-D_B)/(D_C-D_B) Compared to 1/16, 1/8, 1/4, 1/2, 1, 2, 4, 8, and 16 to determine an optimized read voltage V_O. Based on the comparison, D can be estimated from the mapping of FIG. 7_MINIs D_BOr D_B3/4; and from the mapping of fig. 8, D can be estimated_MIN2Is D_B+D_A、D_B+(D_A+D_C) /4 or D_B+D_C。

When the optimized read voltage V is determined_OTesting voltage intervals (e.g., V) on the sides_ATo V_BOr V_DTo V_E) Inner (e.g., by comparisons 201-205 shown in FIG. 4), the optimized read voltage V may be_OEstimated as the difference in counts with two bits on the voltage axis (e.g., D)_A) The most recent count difference on the same side of (e.g., D)_AAnd D_B) Difference in counts of (e.g., D)_A) In the test voltage interval (e.g., using the technique shown in fig. 6). Such optimized read voltage V_OLowest point D of_MINMay be determined using the technique of fig. 10.

Alternatively, the optimized read voltage V_OCan be estimated as being at a test voltage (e.g., V) shared by the two count differences_B) To (3). When the read voltage V is optimized_OEstimated at the test voltage V_BWhile in time, such optimized read voltage V_OLowest point D of_MINMay be determined using the technique of fig. 9.

Optimized read voltage V similar to that in FIG. 6_ODetermination of (D) in FIG. 9 or FIG. 10_MINIs based on the side count difference D_AAnd its neighbor D_BThe ratio of (a) to (b).

In the example of FIG. 9, the ratio D_A/D_BCompared to ratios 1, 3/4, 1/2, 1/4, 1/8, 1/16, 1/32, respectively. When the ratio D is_A/D_BBetween 1 and 3/4, D_MINEstimated as AND D_AThe same is true. When the ratio D is_A/D_BReduced to 1/2, 1/4, 1/8, 1/16, 1/32, respectively, D_MINRespectively reduced to D_A*5/4、D_A*6/4、D_A*2、D_A*11/4、 D_A*4、D_A*6. Other estimation schemes may also be used in order to simplify the calculations while maintaining a desired level of accuracy.

In FIG. 10, the ratio D_A/D_BCompared to the ratio 1/4. When the ratio D is_A/D_BBetween 1 and 1/4, D_MINEstimated as AND D_AThe same is true. When the ratio D is_A/D_BUntil it is reduced to 1/4 or less, D_MINIs reduced to D_A*3/4。

In one embodiment, when the optimized read voltage V is determined_OTesting voltage intervals (e.g., V) on the sides_ATo V_B) Internal time, optimized read voltage V_OD of (A)_MIN2Is the sum of the count differences closest to the test interval (e.g., D)_A+D_B)。

The techniques of FIGS. 7-10 are greatly simplified to optimize the read voltage V_OCentered signal and noise characteristics (e.g., D)_MINAnd D_MIN2) And (4) calculating.

FIG. 11 illustrates a method of calculating signal and noise characteristics centered on an optimized read voltage for reading a group of memory cells, according to one embodiment. The method of fig. 11 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of the device, integrated circuits, etc.), software/firmware (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method of fig. 11 is performed at least in part by processing logic in controller 115 of fig. 1 or memory device 130 of fig. 2. In some implementations, the computations involved in the method of fig. 11 are greatly simplified so that the method can be performed in the memory device 130 of fig. 2. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Thus, the illustrated embodiments are to be understood as examples only, and the processes shown may be performed in a different order, and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Thus, not all processes are required in every embodiment. Other process flows are possible.

For example, the method of fig. 11 may be implemented in the computing system of fig. 1 having the memory device of fig. 2 and the signal noise characteristics shown in fig. 3 using some of the operations shown in fig. 4-10.

At block 301, memory device 130 receives a command identifying a group of memory cells (e.g., 131 or 133) within memory device 130. Operations at blocks 303 through 307 may be performed in response to the command.

At block 303, memory device 130 is based on a first test voltage (e.g., V)_A、V_B、V_C、V_DAnd V_E) A first signal and noise characteristic 139 of a group of memory cells (e.g., 131 or 133) is measured.

For example, a first test voltage (e.g., V)_A、V_B、V_C、V_DAnd V_E) Separated from each other by a predetermined voltage gap (e.g., G ═ V)_B-V_A＝V_C-V_B＝V_D-V_C＝V_E-V_D). Thus, each adjacent pair of the first test voltages has the same predetermined voltage gap; and the first test voltages are equally spaced by a predetermined voltage gap.

For example, calibration circuitry 145 of memory device 130 may be configured to pass at a plurality of first test voltages (e.g., V)_A、V_B、V_C、V_DAnd V_E) A group of memory cells (e.g., 131 or 133) is read down to measure a first signal and noise characteristic 139. At a first test voltage (e.g., V)_A、V_B、V_C、V_DAnd V_E) Lower count bit count (e.g., C)_A、C_B、C_C、C_DAnd C_E) Thereafter, a first test voltage (e.g., V) is calculated_A、V_B、V_C、V_DAnd V_E) A count difference of bit counts of adjacent voltage pairs (e.g., D)_A、D_B、D_CAnd D_D). Test voltage (e.g. V)_A) Count per bit of (e.g., D)_A) When in a test voltage (e.g., V) in an identification group (e.g., 131 or 133)_A) The number of memory cells providing a predetermined bit value (e.g., 0 or 1) at the time of the lower read; and a first test voltage (e.g., V)_A、V_B、V_C、 V_DAnd V_E) Of a pair of adjacent voltages (e.g., V)_AAnd V_B) Each count difference of voltage intervals therebetween (e.g., D)_A) Is the pair of adjacent voltages (e.g., V)_AAnd V_B) Bit count of (e.g., C)_AAnd C_B) The difference between them.

At block 305, the read manager 133 calculates an optimized read voltage V for a group of memory cells (e.g., 131 or 133) as a function of the first signal and noise characteristics 139_O。

For example, an optimized read voltage V_OThe technique of fig. 5 can be used based on D_A-D_BAnd D_C-D_BBased on D using the technique of FIG. 6_AAnd D_BIs calculated from the ratio between.

At block 307, the read manager 133 estimates what is believed to be based on the optimized read voltage V for the group of memory cells (e.g., 131 or 133) from the first signal and noise characteristics 139_OSecond signal and noise characteristics (e.g., D) of the centered second test voltage_MINAnd D_MIN2). The evaluation is performed without actually reading the group of memory cells (e.g., 131 or 133) at the second test voltage.

For example, the second test voltage may include: ratio optimized read voltage V_OA first voltage higher by half of a predetermined voltage gap G; ratio optimized read voltage V_OA second voltage lower by half of the predetermined voltage gap G; ratio optimized read voltage V_OA third voltage higher than the predetermined voltage gap G; and a ratio-optimized read voltage V_OA fourth voltage lower than the predetermined voltage gap G. For example, the second signal and noise characteristic may include a first voltage (e.g., V)_OBit count at + G/2) and a second voltage (e.g., V)_O-a count difference estimate between bit counts at G/2). The second signal and noise characteristic may further include a third voltage (e.g., V)_OBit count at + G) and a fourth voltage (e.g., V)_O-a count difference estimate between bit counts at G).

Typically, at least two of the second test voltages are not the same as the first test voltage (e.g., V)_A、V_B、V_C、V_DAnd V_E) Are consistent with each other. In some cases, none of the second test voltages is the same as the first test voltage (e.g., V)_A、 V_B、V_C、V_DAnd V_E) Are consistent with each other.

Second signal and noise characteristics (e.g. V)_MINAnd V_MIN2) The evaluation may be performed without reading the group of memory cells at the second test voltage.

For example, the second signal and noise characteristics (e.g., D)_MINAnd D_MIN2) The techniques of fig. 7 and 8 may be used based on D_A-D_BAnd D_C-D_BOr based on D using the technique of FIG. 9 or FIG. 10_AAnd D_BThe ratio between them.

In one example, when determining the optimized read voltage V_OAt no more than two second count differences (e.g., D)_AAnd D_C) First count difference of (e.g., D)_B) Electricity (D) fromPressure gap (e.g. V)_BTo V_C) (the voltage interval of the two second count differences (e.g., V)_ATo V_BAnd V_CTo V_D) Enclosing a first count difference (e.g., D)_B) Voltage interval (e.g. V)_BTo V_C) Memory device 130 is configured to be based on a first count difference (e.g., D)_B) Increase (e.g., D)_A-D_BAnd D_C-D_B) And the two second count differences (e.g. D)_AAnd D_C) To estimate a second signal and noise characteristic (e.g., D)_MINAnd D_MIN2). For example, memory device 130 is configured to be based on a ratio (D)_A-D_B)/(D_C-D_B) Comparison with 1/8, 1/4, 4, and 8 to estimate a second signal and noise characteristic (e.g., D_MINAnd D_MIN2) As shown in fig. 7 and 8. The comparison may be performed via comparing scaled versions of the increment, e.g., comparing (D)_A-D_B) And (D)_C-D_B) /8, or comparison (D)_A-D_B) 2 and (D)_C-D_B)/4。

In another example, when determining the optimized read voltage V_OIs not enclosed at a first test voltage (e.g., V)_A、 V_B、V_C、V_D、V_E) A first count difference (e.g., D) within two count differences of bit counts of adjacent voltage pairs in_A) Voltage interval (e.g. V)_ATo V_B) Memory device 130 is configured to be based on a first count difference (e.g., D)_A) And a second count difference (e.g., D)_B) To estimate a second signal and noise characteristic (e.g., D)_MINAnd D_MIN2) A voltage interval of the second count difference being closest to the first count difference in count differences of bit counts of adjacent voltage pairs in the first test voltage (e.g., D)_A) Voltage interval of (c). For example, the memory device is configured to be based on the ratio D_A/D_BComparison with 3/4, 1/2, 1/4, 1/8, 1/16, and 1/32 to estimate a second signal and noise characteristic (e.g., D_MINAnd D_MIN2) As shown in fig. 10 and 11. The comparison may be performed via comparing scaled versions of the count difference, e.g., comparing D_AAnd D_B3/4, or comparison D_A4 and D_B*3。

The scaled version may be efficiently generated by a bitwise shift operation corresponding to multiplying a factor of 2 by a power of a number and/or by addition/accumulation.

A non-transitory computer storage medium may be used to store instructions of firmware (e.g., 113) of a memory subsystem. When executed by the controller 115 and/or the processing device 117, the instructions cause the controller 115, the processing device 117, and/or the separate hardware module to perform the methods discussed above.

Fig. 12 illustrates an example machine of a computer system 400 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In some embodiments, computer system 400 may correspond to a host system (e.g., host system 120 of fig. 1) that includes, is coupled to, or utilizes a memory subsystem (e.g., memory subsystem 110 of fig. 1), or may be used to perform operations of read manager 113 (e.g., to execute instructions to perform operations corresponding to read manager 113 described with reference to fig. 1-11). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Additionally, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

Example computer system 400 includes a processing device 402, a main memory 404 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM), such as synchronous DRAM (sdram) or Rambus DRAM (RDRAM), Static Random Access Memory (SRAM), etc.), and a data storage system 418, which communicate with each other via a bus 430 (which may include multiple buses).

Processing device 402 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 402 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), network processor, or the like. The processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. The computer system 400 may further include a network interface device 408 that communicates over a network 420.

The data storage system 418 may include a machine-readable storage medium 424 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 426 or software embodying any one or more of the methodologies or functions described herein. The instructions 426 may also reside, completely or at least partially, within the main memory 404 and/or within the processing device 402 during execution thereof by the computer system 400, the main memory 404, and the processing device 402 also constituting machine-readable storage media. The machine-readable storage media 424, data storage system 418, and/or main memory 404 may correspond to memory subsystem 110 of fig. 1.

In one embodiment, instructions 426 include instructions to implement functionality corresponding to read manager 113 (e.g., read manager 113 described with reference to FIGS. 1-11). While the machine-readable storage medium 424 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the most effective means used by those skilled in the data processing arts to convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear from the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, and so forth.

In this specification, various functions and operations are described as being performed by or caused by computer instructions for simplicity of description. However, those skilled in the art will recognize that the intent of such expressions is that the functions result from execution of computer instructions by one or more controllers or processors (e.g., microprocessors). Alternatively or in combination, the functions and operations may be implemented using special purpose circuitry, with or without software instructions, such as an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA). Embodiments may be implemented using hardwired circuitry without software instructions or in combination with software instructions. Thus, the techniques are not limited to any specific combination of hardware circuitry and software nor to any particular source for the instructions executed by the data processing system.

In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.