阅读说明：本技术 基于延时的数字测试码型生成方法 (Digital test pattern generation method based on time delay ) 是由 戴志坚 杨万渝 惠佳成 于 2021-07-30 设计创作，主要内容包括：本发明公开了基于延时的数字测试码型生成方法,包括以下步骤：一：测试向量抽象,将原始信号A的测试波形进行向量抽象,获得具有若干个周期波形原始信号A；二：测试码型合成,对原始信号A进行延迟处理,分别获得第一延迟信号B和第二延迟信号C,并对第一延迟信号B和第二延迟信号C进行逻辑处理生成脉冲信号D。本发明能满足数字IC的工作频率要求,同时可以提高在数字IC支持的范围内测试码型的生成速度,节约了测试时间,可产生最高200Mbps,边沿定位分辨率最高39ps的数字测试码型,为精确控制发送的测试向量提供了保证,有利于更为合理地指定测试方案、编写测试向量。(The invention discloses a digital test pattern generation method based on time delay, which comprises the following steps: firstly, the method comprises the following steps: test vector abstraction, wherein a test waveform of an original signal A is subjected to vector abstraction to obtain the original signal A with a plurality of periodic waveforms; II, secondly: and synthesizing a test pattern, namely performing delay processing on the original signal A to respectively obtain a first delay signal B and a second delay signal C, and performing logic processing on the first delay signal B and the second delay signal C to generate a pulse signal D. The invention can meet the requirement of the working frequency of the digital IC, can improve the generation speed of the test pattern in the range supported by the digital IC, saves the test time, can generate the digital test pattern with the highest 200Mbps and the highest edge positioning resolution of 39ps, provides guarantee for accurately controlling the sent test vector, and is beneficial to more reasonably appointing a test scheme and compiling the test vector.)

1. The digital test pattern generation method based on time delay is characterized by comprising the following steps of:

the method comprises the following steps: test vector abstraction, wherein a test waveform of an original signal A is subjected to vector abstraction to obtain the original signal A with a plurality of periodic waveforms;

step two: and synthesizing a test pattern, namely performing delay processing on the original signal A to respectively obtain a first delay signal B and a second delay signal C, and performing logic operation on the first delay signal B and the second delay signal C to generate a pulse signal D with time sequence edge information.

2. The delay-based digital test pattern generation method according to claim 1, wherein the second step specifically comprises: in the FPGA, in a unit period T, an original signal A is input into an input-output delay unit, delay processing is carried out according to delay time lengths T0 and T1 respectively, a first delay signal B corresponding to the delay time length T0 and a second delay signal C corresponding to the delay time length T1 are obtained, and exclusive OR processing is carried out on the first delay signal B and the second delay signal C to obtain a pulse signal D with the pulse width being a delay value; the delay value is t1-t 0.

3. The method of claim 2, wherein the second step further comprises a test pattern synthesizing process for two consecutive periods T1 and T2: in the FPGA, a signal E which is opposite to the logic generation principle of an original signal A is generated firstly, when the signal A is at the rising edge of a second period T2, the signal E is output as the original signal instead of the signal A, the signal E is delayed by the same delay time lengths T0 and T1 respectively, a third delay signal F corresponding to the delay time length T0 and a fourth delay signal G corresponding to the delay time length T1 are obtained, and the third delay signal F and the fourth delay signal G are subjected to XOR processing to obtain a pulse signal D with the pulse width being a delay value.

4. The method for generating digital test patterns based on time delay of claim 2, wherein the second step further comprises: the operation information and the test vectors are stored in the DDR, and the timing edge information is stored in the RAM inside the FPGA.

5. The method for generating digital test patterns based on time delay as claimed in claim 1, wherein the pulse signal D having timing edge information in the second step is specifically a waveform of four timing edge information of D0, D1, D2, D3; wherein D0 is the signal-on edge, D1 is the data start edge, D2 is the data return edge, and D3 is the signal-off edge.

6. The method for generating digital test patterns based on time delay of claim 5, wherein the second step further comprises: the signal on edge D0 and the signal off edge D3 are used as a signal switch combination and are controlled by switch signals; the data start edge D1 and the data return edge D2 are combined as one data output, implemented with a waveform signal; when the switch is in an open state, a data logic state is output, the output level is a preset high-low level value, and the edges of the output waveform are the edges of the switch signal and the waveform signal respectively.

Technical Field

The invention relates to the field of data field test, in particular to a method for realizing edge-adjustable digital test code pattern by using a hardware method in integrated circuit test.

Background

Integrated Circuit (IC) testing is one of the key means to ensure the performance and quality of an integrated circuit, and is mainly implemented by a special integrated circuit testing system and other auxiliary equipment. The test system is controlled by computer software, and each hardware module operates in a proper state according to instructions. In the digital IC testing process, a computer issues a testing instruction and related information, and in the testing process, a digital channel module generates a testing code pattern, and compares an acquired result with a preset expectation to judge pass or fail.

With the continuous development of the digital IC testing industry, the requirements for the speed and resolution of the test pattern are also increasing, and both requirements are required. On one hand, as the working frequency of the digital IC is gradually increased, the test pattern needs to meet the working frequency requirement of the digital IC, and on the other hand, the speed of testing the pattern in the range supported by the digital IC can greatly influence the speed of the whole test, thereby saving the test time. The edge positioning resolution of the test code determines the control precision of the edge of the test code, smaller edge positioning resolution and higher edge positioning precision, provides guarantee for accurately controlling the sent test vector, and is beneficial to more reasonably appointing a test scheme and compiling the test vector.

For example, patent application No. CN201711299365.9 discloses a pulse pattern generator, which includes a switching power supply, a timing circuit, a control circuit, a delay circuit and an output circuit; the switching power supply is used for providing power supply for other circuits; the control circuit is used for controlling the work of other circuit modules and completing parameter setting through peripheral equipment; the timing circuit is used for generating a pulse signal and timing control, and the delay circuit is used for finely adjusting the delay width of the pulse signal generated by the timing circuit; the output circuit is used for carrying out edge adjustment, gain control and output amplification on the pulse signal. However, the scheme cannot control the generation of the switching signal and the waveform signal respectively, and the edge positioning resolution and the edge positioning accuracy are still to be further improved.

For example, patent application No. CN201711299365.9 discloses a pulse pattern generator, which includes a switching power supply, a timing circuit, a control circuit, a delay circuit and an output circuit; the switching power supply is used for providing power supply for other circuits; the control circuit is used for controlling the work of other circuit modules and completing parameter setting through peripheral equipment; the timing circuit is used for generating a pulse signal and timing control, and the delay circuit is used for finely adjusting the delay width of the pulse signal generated by the timing circuit; the output circuit is used for carrying out edge adjustment, gain control and output amplification on the pulse signal. Although the scheme can also carry out edge adjustment on the pulse signal, the adjustment process is not carried out in a test waveform abstraction mode, and the resolution of the obtained test pattern still needs to be further improved.

Disclosure of Invention

The invention aims to overcome the defects of the prior art, provides a digital test pattern generation method based on time delay, realizes high-resolution digital test pattern generation by utilizing time delay resources and logic resources inside an FPGA, and can generate a digital test pattern with the highest 200Mbps and the highest edge positioning resolution of 39ps based on the method.

The purpose of the invention is realized by the following technical scheme:

the digital test pattern generation method based on time delay comprises the following steps:

the method comprises the following steps: test vector abstraction, wherein a test waveform of an original signal A is subjected to vector abstraction to obtain the original signal A with a plurality of periodic waveforms;

step two: and synthesizing a test pattern, namely performing delay processing on the original signal A to respectively obtain a first delay signal B and a second delay signal C, and performing logic operation on the first delay signal B and the second delay signal C to generate a pulse signal D with time sequence edge information.

Specifically, the second step specifically comprises: in the FPGA, in a unit period T, an original signal A is input into an input-output delay unit, delay processing is carried out according to delay time lengths T0 and T1 respectively, a first delay signal B corresponding to the delay time length T0 and a second delay signal C corresponding to the delay time length T1 are obtained, and exclusive OR processing is carried out on the first delay signal B and the second delay signal C to obtain a pulse signal D with the pulse width being a delay value; the delay value is t1-t 0.

Specifically, the second step further includes a test pattern synthesizing process for two consecutive periods T1 and T2: in the FPGA, a signal E which is opposite to the logic generation principle of an original signal A is generated firstly, when the signal A is at the rising edge of a second period T2, the signal E is output as the original signal instead of the signal A, the signal E is delayed by the same delay time lengths T0 and T1 respectively, a third delay signal F corresponding to the delay time length T0 and a fourth delay signal G corresponding to the delay time length T1 are obtained, and the third delay signal F and the fourth delay signal G are subjected to XOR processing to obtain a pulse signal D with the pulse width being a delay value.

Further, the operation information and the test vectors are stored in the DDR, and the timing edge information is stored in the RAM inside the FPGA.

Specifically, the pulse signal D having the timing edge information in the second step is specifically a waveform of four timing edge information of D0, D1, D2, and D3; wherein D0 is the signal-on edge, D1 is the data start edge, D2 is the data return edge, and D3 is the signal-off edge.

Furthermore, the signal on edge D0 and the signal off edge D3 are used as a signal switch combination and are controlled by switch signals; the data start edge D1 and the data return edge D2 are combined as one data output, implemented with a waveform signal; when the switch is in an open state, a data logic state is output, the output level is a preset high-low level value, and the edges of the output waveform are the edges of the switch signal and the waveform signal respectively.

The invention has the beneficial effects that:

1. the method of the invention can meet the requirement of the working frequency of the digital IC, and simultaneously can improve the generation speed of the test code pattern in the range supported by the digital IC, thereby saving the test time.

2. The method can generate the digital test code pattern with the highest 200Mbps and the highest edge positioning resolution of 39ps, provides guarantee for accurately controlling the transmitted test vector, and is favorable for more reasonably appointing a test scheme and compiling the test vector.

Drawings

FIG. 1 is a flow chart of the method of the present invention.

FIG. 2 is a test vector abstraction diagram of the present invention.

Fig. 3 is a schematic diagram of the pulse signal generation of the present invention.

FIG. 4 is a schematic diagram of the generation of digital patterns in a unit period according to the present invention.

FIG. 5 is a first schematic diagram illustrating the generation of digital patterns in successive periods according to the present invention.

FIG. 6 is a second schematic diagram of the generation of digital patterns in successive cycles according to the present invention.

FIG. 7 is a diagram of an example of waveform synthesis according to the present invention.

FIG. 8 is a second example of waveform synthesis according to the present invention.

Detailed Description

In order to clearly understand the technical features, objects and effects of the present invention, the following detailed description of the embodiments of the present invention is provided in conjunction with the drawings, and only some embodiments but not all embodiments of the present invention are described in detail in the embodiments, and other embodiments obtained by innovative modifications by other persons in the field are within the scope of the present invention.

The first embodiment is as follows:

in this embodiment, as shown in fig. 1, the method for generating a digital test pattern based on a delay includes the following steps:

the method comprises the following steps: test vector abstraction, wherein a test waveform of an original signal A is subjected to vector abstraction to obtain the original signal A with a plurality of periodic waveforms;

step two: and synthesizing a test pattern, namely performing delay processing on the original signal A to respectively obtain a first delay signal B and a second delay signal C, and performing logic operation on the first delay signal B and the second delay signal C to generate a pulse signal D with time sequence edge information.

Specifically, the second step specifically comprises: in the FPGA, in a unit period T, an original signal A is input into an input-output delay unit, delay processing is carried out according to delay time lengths T0 and T1 respectively, a first delay signal B corresponding to the delay time length T0 and a second delay signal C corresponding to the delay time length T1 are obtained, and exclusive OR processing is carried out on the first delay signal B and the second delay signal C to obtain a pulse signal D with the pulse width being a delay value.

In this embodiment, the delay value is a difference between the delay time duration t1 and the delay time duration t0, that is, the delay value = t1-t 0.

In this embodiment, the test waveforms are synthesized in a vector manner according to the requirements of the digital IC test. And test vector abstraction, namely performing vector abstraction on the test waveform of the original signal A to obtain the original signal A with a plurality of periodic waveforms, wherein the waveforms in each period are different, and the pulse signal D after code pattern synthesis has waveforms of four time sequence edge information of D0, D1, D2 and D3. As shown in FIG. 2, D0 is the signal-on edge, D1 is the data start edge, D2 is the data return edge, and D3 is the signal-off edge.

In this embodiment, the signal on edge D0 and the signal off edge D3 are used as a signal switch combination, and are controlled by switch signals; the data start edge D1 and the data return edge D2 are combined as one data output, implemented with a waveform signal; when the switch is in an open state, a data logic state is output, the output level is a preset high-low level value, and the edges of the output waveform are the edges of the switch signal and the waveform signal respectively.

As shown in fig. 3, if there are two signals with rising edges (or falling edges), one of the signals (B) is the delay (a) of the other signal, after the two signals are subjected to the exclusive or operation, a pulse signal C with a pulse width of a delay value is obtained.

Based on the method, the pulse signal with the edge related to the delay value can be generated by adjusting the delay value and carrying out exclusive OR operation on the two signals.

In practical engineering applications, the logic state of the a signal can be changed at the rising edge (or the falling edge) in fig. 3, and the logic state at this time is usually determined by the vector file. When the working clock of the FPGA is 200Mhz, the maximum frequency of the generated A signal is 100 Mhz. In the testing process, the computer can send the information required by the current test to the FPGA at one time, the FPGA completes the processes of processing, storing and the like, and finally the information is output to the driver to generate the test vector, so that the large-capacity information required by the one-time test is stored in the FPGA. Limited by FPGA on-chip resources, DDR memory is needed to temporarily store vector information. The data information required for generating the digital code pattern can be divided into two parts, one part is operation information and test vector data, and the other part is timing edge information. The operation information and the test vector have large storage capacity requirements and are stored in the DDR, and the time sequence edge information has small storage capacity requirements and is stored in the RAM inside the FPGA.

In this embodiment, the generation of the digital code pattern in one period is described in detail by taking the unit period T as an example. As shown in fig. 4, the time T0 is a clock rising edge, and according to the current vector file, the signal between T0 and T1 is logic "1", at this time, the a signal changes from 0 to 1, and the B, C signal is a signal obtained by delaying the a signal by T0 and T1, respectively. The D signal is obtained by XOR operation of the B signal and the C signal, and the D signal is a code pattern signal. Only a single cycle of pattern synthesis is considered when the generation of the desired digital pattern has been completed.

The embodiment can achieve the following technical effects:

1. the method of the embodiment can meet the requirement of the working frequency of the digital IC, can improve the generation speed of the test code pattern in the range supported by the digital IC, and saves the test time.

Example two:

in this embodiment, based on the digital test pattern generation method provided in the first embodiment, the digital test pattern generation process is more complicated in practice, and when the vector file is set to send logic "1" for two consecutive cycles (e.g., T0 to T1 and T1 to T2), as shown in fig. 4, the signal a will always keep logic "1" state during the period from T1 to T2, which will cause the signal B and the signal C to always be in logic "1" state, and the signal D and the desired output signal to be inconsistent. The reason for the error is that the a signal will not produce a "0 to 1" or "1 to 0" changing edge when a logic "1" is sent for two consecutive cycles. Therefore, there is a need for further improvement of the method provided in the first embodiment, where the improved method flow is as follows:

the method comprises the following steps: test vector abstraction, wherein a test waveform of an original signal A is subjected to vector abstraction to obtain the original signal A with a plurality of periodic waveforms;

step two: and test code pattern synthesis, namely firstly generating a signal E which is opposite to the logic generation principle of the original signal A in the FPGA, replacing the signal A with the signal E to serve as the original signal to be output when the signal A is at the rising edge of a second period T2, respectively carrying out delay processing on the signal E by the same delay time length T0 and T1 to obtain a third delay signal F corresponding to the delay time length T0 and a fourth delay signal G corresponding to the delay time length T1, and carrying out exclusive OR processing on the third delay signal F and the fourth delay signal G to obtain a pulse signal D with the pulse width being a delay value.

As shown in fig. 5, to solve the problem of the method of the first embodiment, the present embodiment adds another signal E to solve the problem. The signal and the signal A have the same logic generation principle, when the signal A is at the rising edge of the time T1, the signal A is set to be logic '0', the signal E is changed according to the vector file at the time, the signal A and the signal E are alternated, the original signal is the signal A from T0 to T1, the original signal is the signal E from T1 to T2, the signal A and the signal E are alternated to be used as the output original signal, and at the time, the output value D is the same as the expected generated digital code pattern.

According to the vector file, if a logic "1" is expected to be sent in the period T0-T1 and a logic "0" is expected to be sent in the period T1-T2, as shown in FIG. 6, the D signal will generate two "pulse" signals due to the two data transition edges of the A signal, which do not match the expected values.

Thus, the operation of D signal generation should be modified from exclusive-or operation to inverting the B signal with the C signal, i.e., D = B & |.c.

The embodiment can achieve the following technical effects:

1. the method of the embodiment can meet the requirement of the working frequency of the digital IC, can improve the generation speed of the test code pattern in the range supported by the digital IC, and saves the test time.

2. The method based on the embodiment can generate the digital test pattern with the highest 200Mbps and the highest edge positioning resolution of 39ps, provides guarantee for accurately controlling the sent test vector, and is beneficial to more reasonably appointing a test scheme and compiling the test vector.

3. In the embodiment, by adding the signal with the logic opposite to that of the original signal and alternately performing code pattern synthesis by using the original signal and the added signal, the test code pattern generated by the embodiment can better meet the test requirement, the requirement of a test code pattern synthesis scene of a plurality of continuous periods is met, and the finally output test code pattern resolution is improved.

Example three:

in this embodiment, on the basis of the first embodiment and the second embodiment, the digital test pattern with variable edges and adjustable period can be generated by using the methods of the two embodiments. The output rate is set to be 200Mbps, the switching edges are 0ns and 5ns, the data start edges are 0.78ns and 1.56ns, the output code patterns are sequentially '1', '0', '1', and the output waveform is shown in FIG. 7.

The same is true. By using the method, the part of the signals are inverted, and the normalization code pattern can be generated. The output rate is set to be 200Mbps, the switching edges are 0ns and 5ns, the data start edges are 0.78ns and 2.34ns, the output code patterns are sequentially '1', '0', and the output waveform is shown in FIG. 8. It can also be seen from the comparison that the pulse widths generated in fig. 7 and 8 are the same as the set values.

In this embodiment, since the test pattern synthesis is completed in the FPGA, it is proposed to use the FPGA having a delay unit or full adder resource to support the DDR. Such as XILINX corporation FPGA, which has IODELAY delay resources and full adder resources, or ALTERA corporation FPGA, which has LCELL delay resources and full adder resources.

For a small-scale FPGA which does not support delay line and full adder resources, the method of the present embodiment can also be used to implement code pattern synthesis by adding a delay chip outside the FPGA.

DDR is used for expanding storage capacity, and besides part of small-scale FPGAs, the DDR is supported. Whether DDR is supported or not does not affect the realization of the code pattern generation method designed by the patent, and only affects the storage capacity.

The first embodiment and the second embodiment describe a digital code pattern synthesis method based on time delay, and various methods for realizing time delay in an FPGA (field programmable gate array) are available, such as a full adder method and an IODELAY method. The IODELAY resource is rich and convenient to use. The SELECTIO of XILINX FPGA has ILOGIC and OLOGIC resources, and can realize IDDR/ODDR, IDELAY and ODELAY functions. Meanwhile, the delay precision and the delay time of IDELAY can be adjusted within a certain range. The delay tray of IDELAY becomes green determined by the input clock, and the resolution of the tap coefficients is 78ps for the 200M reference clock. At a reference clock of 300M, the resolution is 52 ps. When the reference clock is 400M, the resolution is 39 ps. The delay TAP can be adjusted in the range of 0 to 31, and a plurality of IDELAYs can be cascaded under the condition of needing high precision and large delay. For a small-scale FPGA, the FPGA may not have a delay or full adder resource, and the scheme can also be realized by externally realizing delay by a method of adding a delay chip outside the FPGA.

The embodiment can achieve the following technical effects:

1. the method of the embodiment can meet the requirement of the working frequency of the digital IC, can improve the generation speed of the test code pattern in the range supported by the digital IC, and saves the test time.

2. The method based on the embodiment can generate the digital test pattern with the highest 200Mbps and the highest edge positioning resolution of 39ps, provides guarantee for accurately controlling the sent test vector, and is beneficial to more reasonably appointing a test scheme and compiling the test vector.

3. In the embodiment, by adding the signal with the logic opposite to that of the original signal and alternately performing code pattern synthesis by using the original signal and the added signal, the test code pattern generated by the embodiment can better meet the test requirement, the requirement of a test code pattern synthesis scene of a plurality of continuous periods is met, and the finally output test code pattern resolution is improved.

The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.