阅读说明：本技术 带有高磷掺杂物浓度的源极或漏极结构 (Source or drain structures with high phosphorus dopant concentration ) 是由 R·埃莱特 T·耶恩 A·巴梅埃夫 S·黑格德 S·查鲁厄-巴克 于 2020-12-23 设计创作，主要内容包括：本发明的主题是“带有高磷掺杂物浓度的源极或漏极结构”。描述了具有高磷掺杂物浓度的集成电路结构。在示例中,集成电路结构包括具有下部鳍部分和上部鳍部分的鳍。栅极叠层在鳍的上部鳍部分的上方,栅极叠层具有与第二侧相对的第一侧。第一源极或漏极结构包括在栅极叠层的第一侧处嵌入鳍中的外延结构。第二源极或漏极结构包括在栅极叠层的第二侧处嵌入鳍中的外延结构。第一源极或漏极结构和第二源极或漏极结构的外延结构中的每一个包括硅和磷,磷在硅的核心区域中具有的原子浓度大于磷在硅的外围区域中具有的原子浓度。(The subject of the invention is a "source or drain structure with high phosphorus dopant concentration". Integrated circuit structures having high phosphorus dopant concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. The first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. The second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first source or drain structure and the second source or drain structure includes silicon and phosphorus having an atomic concentration in a core region of the silicon that is greater than an atomic concentration of phosphorus in a peripheral region of the silicon.)

1. An integrated circuit structure, the integrated circuit structure comprising:

a fin having a lower fin portion and an upper fin portion;

a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;

a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack; and

a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, each of the epitaxial structures of the first and second source or drain structures comprising silicon and phosphorus having an atomic concentration in a core region of the silicon that is greater than an atomic concentration of the phosphorus in a peripheral region of the silicon, wherein the core region of the silicon is laterally within and over the peripheral region of the silicon, and wherein the core region of the silicon is exposed at a top of each of the epitaxial structures of the first and second source or drain structures.

2. The integrated circuit structure of claim 1 wherein the atomic concentration of phosphorus in the core region of the silicon is greater than 5E21 atoms/cm³。

3. The integrated circuit structure of claim 1 or 2, wherein the atomic concentration of phosphorus in the peripheral region of the silicon is less than 4E21 atoms/cm³。

4. According to claim 1The integrated circuit structure of or 2, wherein the atomic concentration of phosphorus of the core region at the top of each of the epitaxial structures is greater than 6E21 atoms/cm³And graded to less than 2E21 atoms/cm in the peripheral region at the bottom of each of the epitaxial structures³。

5. The integrated circuit structure of claim 1 or 2, wherein the first source or drain structure and the second source or drain structure have a resistivity of less than about 0.4 mOhm-cm.

6. The integrated circuit structure of claim 1 or 2, wherein the lower fin portion comprises a portion of an underlying bulk monocrystalline silicon substrate.

7. The integrated circuit structure of claim 1 or 2, further comprising:

first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

8. The integrated circuit structure of claim 1 or 2, further comprising:

a first conductive contact on the epitaxial structure of the first source or drain structure; and

a second conductive contact on the epitaxial structure of the second source or drain structure.

9. The integrated circuit structure of claim 8, wherein the first and second conductive contacts are in partial recesses in the epitaxial structures of the first and second source or drain structures, respectively.

10. An integrated circuit structure, the integrated circuit structure comprising:

a fin having a lower fin portion and an upper fin portion;

a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;

a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and an overlying semiconductor layer on the lower semiconductor layer; and

a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, the epitaxial structure includes a lower semiconductor layer and an overlying semiconductor layer on the lower semiconductor layer, wherein the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises silicon and phosphorus, the phosphorus has an atomic concentration in the core region of the silicon that is greater than an atomic concentration of the phosphorus in the peripheral region of the silicon, wherein the core region of the silicon is laterally within and above the peripheral region of the silicon, and wherein the core region of the silicon is exposed at a top of the semiconductor layer of each of the epitaxial structures of the first and second source or drain structures.

11. The integrated circuit structure of claim 10 wherein the atomic concentration of phosphorus in the core region of the silicon is greater than 5E21 atoms/cm³。

12. The integrated circuit structure of claim 10 or 11, wherein the atomic concentration of phosphorus in the peripheral region of the silicon is less than 4E21 atoms/cm³。

13. The integrated circuit structure of claim 10 or 11, wherein in the epitaxial structureThe atomic concentration of phosphorus of the core region at the top of each epitaxial structure in (a) is greater than 6E21 atoms/cm³And graded to less than 2E21 atoms/cm in the peripheral region at the bottom of each of the epitaxial structures³。

14. The integrated circuit structure of claim 10 or 11, wherein the first source or drain structure and the second source or drain structure have a resistivity of less than about 0.4 mOhm-cm.

15. The integrated circuit structure of claim 10 or 11, wherein the lower fin portion comprises a portion of an underlying bulk monocrystalline silicon substrate.

16. The integrated circuit structure of claim 10 or 11, further comprising:

first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

17. The integrated circuit structure of claim 10 or 11, further comprising:

a first conductive contact on the blanket semiconductor layer of the first source or drain structure; and

a second conductive contact on the blanket semiconductor layer of the second source or drain structure.

18. The integrated circuit structure of claim 17, wherein the first and second conductive contacts are in partial recesses in the overlying semiconductor layer of the first and second source or drain structures, respectively.

19. A computing device, the computing device comprising:

a plate; and

a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising:

a fin having a lower fin portion and an upper fin portion;

a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;

a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack; and

a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, each of the epitaxial structures of the first and second source or drain structures comprising silicon and phosphorus having an atomic concentration in a core region of the silicon that is greater than an atomic concentration of the phosphorus in a peripheral region of the silicon, wherein the core region of the silicon is laterally within and over the peripheral region of the silicon, and wherein the core region of the silicon is exposed at a top of each of the epitaxial structures of the first and second source or drain structures.

20. The computing device of claim 19, further comprising:

a memory coupled to the board.

21. The computing device of claim 19 or 20, further comprising:

a communication chip coupled to the board.

22. The computing device of claim 19 or 20, further comprising:

a camera coupled to the board.

23. The computing device of claim 19 or 20, further comprising:

a battery coupled to the plate.

24. The computing device of claim 19 or 20, further comprising:

an antenna coupled to the board.

25. The computing device of claim 19 or 20, wherein the component is a packaged integrated circuit die.

Technical Field

Embodiments of the present disclosure are within the field of advanced integrated circuit structure fabrication, and in particular, are integrated circuit structures having source or drain structures with high phosphorus dopant concentrations.

Background

Scaling of features in integrated circuits has been a driving force behind the growing semiconductor industry for the past decades. Scaling to smaller and smaller features enables increased density of functional units on the limited real estate (real estate) of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, resulting in the fabrication of products with increased capacity. However, driving for more and more capacities is not without problems. The necessity to optimize the performance of each device becomes increasingly important.

Variability in conventional and currently known manufacturing processes may limit the possibility of extending them further into the 10 nanometer node or sub-10 nanometer node range. Therefore, the manufacture of functional components required by future technology nodes may require the introduction of new methods or integration of new technologies in or in place of the current manufacturing process.

Drawings

Fig. 1A illustrates an angled cross-sectional view representative of various examples of integrated circuit structures having a source or drain structure in a semiconductor fin, in accordance with an embodiment of the present disclosure.

Fig. 1B includes phosphorus concentration (atoms/cm) as a function of depth (nanometers) in accordance with embodiments of the present disclosure³) A graph of (a).

Fig. 1C illustrates a cross-sectional view of an integrated circuit structure, in accordance with an embodiment of the present disclosure.

FIG. 1D includes phosphorus concentration (atoms/cm) as a function of distance from the surface along the direction of the arrows of FIG. 1C according to embodiments of the present disclosure³) A graph of (a).

Fig. 1E includes a graphical representation of relative contact resistance as a function of gas flow chemistry in accordance with an embodiment of the disclosure.

Fig. 2A-2G illustrate cross-sectional views representative of various operations in a method of fabricating an integrated circuit structure having a source or drain structure with a high phosphorus dopant concentration, in accordance with an embodiment of the present disclosure.

Figure 2G' illustrates a cross-sectional view of another integrated circuit structure having a source or drain structure with a high phosphorus dopant concentration, in accordance with another embodiment of the present disclosure.

Figure 2G "illustrates a cross-sectional view of another integrated circuit structure having a source or drain structure with a high phosphorus dopant concentration, in accordance with another embodiment of the present disclosure.

Fig. 3A illustrates a plan view of a plurality of gate lines over a pair of semiconductor fins in accordance with another embodiment of the present disclosure.

FIG. 3B illustrates a cross-sectional view taken along the a-a' axis of FIG. 3A, in accordance with an embodiment of the present disclosure.

Figure 4 illustrates a cross-sectional view of an integrated circuit structure having trench contacts for NMOS devices, according to another embodiment of the present disclosure.

Figure 5 illustrates a cross-sectional view of an integrated circuit structure having a conductive contact on a raised source or drain region, in accordance with an embodiment of the present disclosure.

Fig. 6A and 6B illustrate cross-sectional views of various integrated circuit structures each having a trench contact including an overlying insulating cap layer and having a gate stack including an overlying insulating cap layer, in accordance with embodiments of the present disclosure.

FIG. 7 illustrates a computing device in accordance with one implementation of the present disclosure.

Fig. 8 illustrates an interposer (interposer) including one or more embodiments of the present disclosure.

Fig. 9 is an isometric view of a mobile computing platform employing an IC manufactured according to one or more processes described herein or including one or more features described herein, according to an embodiment of the disclosure.

Fig. 10 illustrates a cross-sectional view of a flip-chip mounted die according to an embodiment of the disclosure.

Detailed Description

An integrated circuit structure having a source or drain structure with a high phosphorus dopant concentration and a method of fabricating a source or drain structure with a high phosphorus dopant concentration are described. In the following description, numerous specific details are set forth, such as specific integration and material systems, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration. Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.

This specification includes references to "one embodiment" or "an embodiment". The appearances of the phrase "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

Terminology. The following paragraphs provide definitions or contexts for terms found in this disclosure (including the appended claims):

"include". This term is open ended. As used in the appended claims, this term does not exclude additional structures or operations.

"configured to". Various units or components may be described or claimed as being "configured to" perform one or more tasks. In such a context, "configured to" is used to connote structure by indicating that a unit or component includes structure to perform those one or more tasks during operation. As such, a unit or component may be said to be configured to perform a task even when the specified unit or component is not currently operating (e.g., not on or active). It is stated that a unit or circuit or component being "configured to" perform one or more tasks is specifically not intended to invoke the american law 35, section 112, sixth (35 u.s.c. § 112, six para) for that unit or component.

"first", "second", etc. As used herein, these terms are used as labels before nouns and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

"coupled". The following description refers to elements or nodes or features being "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element or node or feature is directly or indirectly joined to (or directly or indirectly communicates with) another element or node or feature, and not necessarily mechanically.

In addition, certain terminology may also be used in the following description for the purpose of reference only and is not intended to be limiting. For example, terms such as "upper," "lower," "above … …," and "below … …" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," "side," "outboard," and "inboard" describe the orientation or position or both of portions of the component within a consistent but arbitrary frame of reference as would be apparent by reference to the text and associated drawings describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

"inhibit". As used herein, suppression is used to describe a reducing or minimizing effect. When a component or feature is described as inhibiting an action, motion, or condition, it may completely prevent the result or outcome or future state. Additionally, "inhibit" may also refer to a reduction or alleviation of an achievement, performance, or effect that may otherwise occur. Thus, when a component, element, or feature is referred to as inhibiting a result or state, it need not completely prevent or eliminate the result or state.

Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of Integrated Circuit (IC) fabrication in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically covers everything up to (but not including) the deposition of the metal interconnect layer. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any conductive lines).

Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. The BEOL is the second part of IC fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. The BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for chip-to-package connections. In the BEOL portion of the fabrication stage, contacts (pads), interconnect lines, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

The embodiments described below may be applicable to FEOL processes and structures, BEOL processes and structures, or both FEOL and BEOL processes and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such an approach may also be applicable to BEOL processing. Likewise, although the exemplary processing scheme may be illustrated using a BEOL processing scenario, such an approach may also be applicable to FEOL processing.

In accordance with one or more embodiments of the present disclosure, an in-situ high phosphorus doped epitaxial source or drain structure for highly scaled transistors is described.

To provide context, Chemical Vapor Deposition (CVD) epitaxy at low temperatures and high growth rates is challenging. The inventors have discovered that the use of nitrogen as a carrier gas instead of hydrogen can provide lower temperatures, higher growth rates, and extremely high doping levels (e.g., greater than 5E 21/cm) for use that have not been previously reported³) The way to obtain high quality membrane. In the case of deposition of silicon (Si: P) selectively doped with phosphorus for nMOS source or drain (S/D), the use of a nitrogen flow, rather than a hydrogen flow, can be achieved to enable reduced contact resistance and allow FinFET scaling below the 10nm node. In addition, the external resistance and short channel effects of modern transistors are major limiters in device performance and efficiency. Reducing body and contact resistance may improve drive characteristics, but this must be achieved while maintaining an abrupt epitaxial interface at the source or drain tip for proper leakage and short channel characteristics.

Previous solutions to address the above considerations have included the use of low temperature deposition processes, or implantation after epitaxial deposition, or amorphization and annealing processes. Disadvantages of such approaches include the inability of the implanted source/drain tips to achieve abrupt doping profiles that may have doped epitaxial source/drains and also to be unsuitable for the observation of deep gate undercut layers (which may be useful in highly scaled devices).

According to embodiments of the present disclosure, the use of a selective, epitaxially doped phosphorus silicon (Si) source or drain layer is described. Embodiments may include the use of nitrogen (N)₂) Carrier gas instead of hydrogen (H)₂) To epitaxially grow a selective low temperature chemistry of abrupt, highly conductive, epitaxially doped source/drain contacts at a high growth rate. Implementing advantages of embodiments described herein may include overcoming such as having been largely comprised ofThe external resistance of the source/drain epitaxial contacts limits previous obstacles to early observations of device performance on highly scaled transistors. The external resistance (Rext) decreases rapidly as a result of contact area reduction (which can be linked to transistor scaling) and as a result of three-dimensional (3D) device structures (e.g., finfets) where the contact width is typically smaller than the channel width. Reducing this resistance may play an increasingly important role in advanced CMOS technology development. For example, in-situ doping can effectively reduce Rext by introducing more dopant during epitaxy. In one embodiment, implementations of the embodiments described herein may provide for a reduced defect concentration to limit the driving force for dopant diffusion while achieving a highly conductive epitaxial source or drain structure. In one such embodiment, the result is an abrupt, highly conductive tip and S/D region with improved device performance due to increased short channel control.

To provide further context, in modern transistor technology, with gate length (L)_G) Scaling, a small portion of the total device resistance due to the channel continues to scale. Therefore, the external resistance Rext has become a major source of device resistance and plays a major role in limiting device performance. Addressing such needs in the embodiments described herein may address and/or may benefit from the effectiveness of using a nitrogen gas stream instead of a hydrogen gas stream while forming a phosphorus doped epitaxial S/D film.

As an exemplary comparative process flow, fig. 1A illustrates angled cross-sectional views representative of various examples of integrated circuit structures having source or drain structures in a semiconductor fin, in accordance with embodiments of the present disclosure. In particular, fig. 1A is a schematic diagram depicting the difference in dopant diffusion in Si source and drain regions that are in-situ P-doped using a nitrogen flow versus a hydrogen flow.

Referring to fig. 1A, during growth of an epitaxial source or drain structure 106, the structure 100 includes a fin 102, a gate structure 104.

The structure 110 includes a fin 112, a gate structure 114, and an in-situ P-doped source or drain structure 116 formed using a hydrogen gas flow. As indicated by curve 152 of the correlation plot 150 of fig. 1B, described below, the structure 110 is a completed version of the structure 100 in which P diffusion occurs into the channel region.

The structure 120 includes a fin 122, a gate structure 124, and an in-situ P-doped source or drain structure 126 formed using a nitrogen gas flow. As indicated by curve 154 of the associated graph 150 of fig. 1B, described below, structure 120 is a completed version of structure 100 in which negligible P diffusion occurs into the channel region.

The embodiments described herein may be detectable as a final structural feature in an integrated circuit structure. For example, gate-cut (multi-cut) TEM images may reveal epitaxial growth of phosphorus doped S/D that is conformal and grows with perfect or substantially perfect epitaxy in the fin region. Also, a standard epitaxial source/drain process flow may be used for phosphorus-doped film growth, where a nitrogen-flowing doping operation replaces a hydrogen-flowing doping operation. A phosphorus doped silicon film or layer such as described herein can be grown on or within a planar, tri-gate, FinFET, nanowire or nanoribbon structure with minimal modification to the baseline process flow. In an embodiment, the entire epitaxial structure of the source or drain structure is doped with phosphorus, an example of which is described below in connection with fig. 2G'. It is to be appreciated, however, that depending on the desired dopant profile in the resulting source or drain structure, a phosphorus-doped material may alternatively be used only in the tip or only at the lower structure portions, with an epitaxial fill and/or cap formed thereon, examples of which are described below in connection with fig. 2G and 2G ".

With respect to the embodiments described herein, elemental analysis in cross-sectional Transmission Electron Microscopy (TEM) can reveal high chemical phosphorus (P) concentrations. Moreover, in-situ doping can effectively reduce the epitaxial (Epi) resistance (Rext) and can be implemented to introduce relatively more dopant during epitaxy as the primary driving force for Rext improvement. Fig. 1B includes phosphorus concentration (atoms/cm) as a function of depth (nanometers) in accordance with embodiments of the present disclosure³) Curve of (2)Fig. 150. Referring to graph 150 of FIG. 1B, the SIMS distribution 152 of P inside the Si: P S/D of NFET is shown for a current state-of-the-art Si: P S/D process, where hydrogen (H)₂) Is used as the carrier gas. According to an embodiment of the present disclosure, the SIMS profile 154 of P inside Si: P S/D of NFET is shown for a Si: P S/D process, where nitrogen (N)₂) Is used as the carrier gas. In N₂P Epi with an observed approximately 40% increase in-situ doping level, resulting in a dopant concentration and 6E21 atoms/cm³As high for selective NMOS S/D epitaxy on patterned wafers (see, e.g., fig. 1C and 1D described below). This 40% increase in doping level results in a 10+% Rext reduction and a proportional transistor drive gain for nMOS FinFET transistors (see, e.g., fig. 1E described below).

Referring again to FIG. 1B, by the user using H₂Pair of carrier gases N₂The carrier gas indicates the chemical dopant concentration at a similar growth rate with the thickness of the blanket Si: P film of the same nucleation layer process. Can be in N₂A 40% increase in dopant concentration was obtained in the carrier gas process. In one embodiment, the source or drain epitaxial structure is formed by selective Chemical Vapor Deposition (CVD) using a combination of dichlorosilane, phosphine, and nitrogen to provide a phosphorus doped silicon structure. Efficient conversion of the carrier gas from nitrogen to hydrogen was observed to increase the growth rate at higher temperatures.

Fig. 1C illustrates a cross-sectional view of an integrated circuit structure, in accordance with an embodiment of the present disclosure. In particular, fig. 1C illustrates gate cuts of the epitaxial S/D regions, with a dopant concentration shading diagram shown in a schematic diagram of a FinFET transistor structure.

Referring to fig. 1C, an integrated circuit structure 160 includes a fin having a lower fin portion 161 and an upper fin portion 162. A gate stack 164 is over the upper fin portion 162 of the fin, the gate stack having a first side opposite a second side. The first source or drain structure (left side 166) includes an epitaxial structure (region within the dashed line) embedded in the fin at the first side of the gate stack 164. The second source or drain structure (right side 166) includes an epitaxial structure (region within dashed line 166A) embedded in the fin at the second side of the gate stack 164. In an embodiment, each of the epitaxial structures of the first and second source or drain structures 166 includes silicon and phosphorous. In one embodiment, the phosphorus has a greater atomic concentration in the core region 166C of silicon than in the peripheral region 166B of silicon. The core region 166C of silicon is laterally within and above the peripheral region 166B of silicon. In one embodiment, as depicted, a core region 166C of silicon is exposed at the top of each of the epitaxial structures of the first and second source or drain structures 166.

In one embodiment, the atomic concentration of phosphorus in the silicon core region 166C is greater than 5E21 atoms/cm³. In one embodiment, the atomic concentration of phosphorus in the peripheral region 166B of silicon is less than 4E21 atoms/cm³. In one embodiment, the atomic concentration of phosphorus of the core region 166C at the top of each of the epitaxial structures is greater than 6E21 atoms/cm³And successively to less than 2E21 atoms/cm in a peripheral region at the bottom of each of the epitaxial structures³。

FIG. 1D includes phosphorus concentration (atoms/cm) as a function of distance from the surface along the direction of arrow 168 of FIG. 1C in accordance with an embodiment of the present disclosure³) Graph 170 of (a). Referring to graph 170 of FIG. 1D, a dopant profile as measured by Atom Probe Tomography (APT) along arrow 168 of FIG. 1C shows greater than 5E21 atoms/cm in the core region 166C of the source or drain structure 166 of FIG. 1C³Chemical dopant concentration of (a).

It is to be appreciated that in the case of source/drains composed of highly doped Si: P, one concern is that the device may suffer significant dopant diffusion into the channel region, causing leakage and other short channel effects. However, [ P ] was observed]Diffusion is even in 6E21 cm^-3Is also minimal at chemical doping levels and is controllable during the thermal anneal necessary for dopant activation. Planar, tri-gate, FinFET, nanowire and nanoribbon structures can be fabricated with minimal modification to existing process flowsOn which an epitaxial structure or layer is grown.

Fig. 1E includes a graphical representation 180 of relative contact resistance as a function of gas flow chemistry in accordance with an embodiment of the disclosure. Refer to diagram 180 of FIG. 1E, corresponding to conventional H₂Flow gas method comparison for Using 5+ E21 [ P]Doping Process (N)₂Flowing gas) observed about a 10% or greater reduction in Rext for nMOS FinFET transistors.

One or more embodiments described herein are directed to a structure and fabrication process for a phosphorus doped silicon source or drain structure including a phosphorus doped silicon cap grown thereon, examples of which are described in connection with fig. 2A-2G. One or more embodiments described herein are directed to a structure and fabrication process including a phosphorus doped silicon source or drain structure without an overlying layer, examples of which are described in connection with fig. 1A, 2A-2D, and 2G'. One or more embodiments described herein are directed to a structure and fabrication process for a phosphorus doped silicon source or drain structure including a phosphorus doped silicon cap having grown thereon, the cap being fabricated during a contact opening, examples of which are described in connection with fig. 2A-2D and 2G ″.

As an exemplary process flow, fig. 2A-2G illustrate cross-sectional views representative of various operations in a method of fabricating an integrated circuit structure having a source or drain structure with a high phosphorus dopant concentration, in accordance with an embodiment of the present disclosure. Figure 2G' illustrates a cross-sectional view of another integrated circuit structure having a source or drain structure with a high phosphorus dopant concentration, in accordance with another embodiment of the present disclosure. Figure 2G "illustrates a cross-sectional view of another integrated circuit structure having a source or drain structure with a high phosphorus dopant concentration, in accordance with another embodiment of the present disclosure.

Referring to fig. 2A, optionally, a channel material 204 is grown on a substrate 202, such as a silicon substrate. In an embodiment, the channel material 204 includes silicon. In an embodiment, the channel material 204 includes silicon and germanium. In an embodiment, the channel material 204 includes germanium. In an embodiment, the channel material 204 is a III-V material. In other embodiments, no distinct channel material 204 is formed and the process operations described below are performed on the surface of the substrate 202.

Referring to fig. 2B, the channel material 204 is patterned into a fin 206. As depicted, the patterning may form a groove 208 into the substrate 202.

Referring to fig. 2C, the trenches between the fins 206 are filled with a shallow trench isolation material, which is then polished and recessed to form isolation structures 210. The process may further involve deposition, patterning and recessing of the dielectric isolation barrier. The process continues with the deposition and patterning of gate oxide material and gate electrode material (which may be dummy gate oxide material and dummy gate electrode material) and the formation of gate spacers to form gate stack 212 and gate spacers 214.

Referring to fig. 2D, at location 218, the fin 206 is etched adjacent to both sides of the gate stack 212. The etch leaves channel region 216 under gate stack 212.

Referring to fig. 2E, source or drain structure formation involves growth of underlying source or drain material 220 and overlying semiconductor layer 222 (which may be grown in situ). Alternatively, without growing the blanket semiconductor layer 222, an exemplary resulting structure is described in connection with fig. 2G'. In either case, in an embodiment, the source or drain structures each comprise an epitaxial structure. As illustrated in connection with fig. 1C, each of the epitaxial structures includes silicon and phosphorus. The phosphorus has an atomic concentration in the core region of the silicon that is greater than the atomic concentration of phosphorus in the peripheral region of the silicon. A core region of silicon is laterally within and over the peripheral region of silicon and the core region of silicon is exposed at a top of each of the epitaxial structures of the first and second source or drain structures. In one such embodiment, phosphine and dichlorosilane are used as precursors flowed with nitrogen to provide a phosphorous dopant in an in situ phosphorous doped silicon epitaxial deposition process.

Referring to fig. 2F, an isolation material is formed on the source or drain structure of fig. 2E. The isolation material is then patterned and recessed to expose the source or drain structures and form second spacers 226 and trenches 228. In one embodiment, the recessing of the isolation material is performed using an etching process that stops on the overlying semiconductor layer 222 or partially into the overlying semiconductor layer 222, wherein in the latter case, a patterned source or drain overlying semiconductor layer 222' is formed. In another embodiment, the etching process stops on the source or drain material 220 or partially into the source or drain material 220 without implementing the overlying semiconductor layer 222.

Referring to fig. 2G, source or drain contact material deposition and patterning is performed to form conductive contacts 230. In an embodiment, the conductive contact 230 is on the overlying semiconductor layer 222 or 222' of the first and second source or drain structures. In one such embodiment, the first and second conductive contacts 230 are in partial recesses in the overlying semiconductor layer 222' of the first and second source or drain structures. It is to be appreciated that although not depicted, back-end processing may then be performed on the structure of fig. 2G.

Referring again to fig. 2G, the integrated circuit structure has fins (216 and patterned portions of the substrate 202), according to an embodiment of the disclosure. The fin has a lower fin portion (a portion of 216 below the top surface of the isolation structure 210 and a patterned portion of 202) and an upper fin portion (a portion of 216 above the top surface of the isolation structure 210). A gate stack 212 is over the upper fin portion of the fin, the gate stack 212 having a first side opposite a second side. The first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack (e.g., the left-hand side of gate stack 212). The second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack (e.g., a right-hand side of the gate stack 212). The epitaxial structure of the first and second source or drain structures includes a lower semiconductor layer 220 and an overlying semiconductor layer 222' (or 222 of fig. 2E without a recess) on the lower semiconductor layer 220. In one embodiment, the lower semiconductor layer 220 of each of the epitaxial structures of the first and second source or drain structures comprises silicon and phosphorous. The phosphorus has an atomic concentration in the core region of the silicon that is greater than the atomic concentration of phosphorus in the peripheral region of the silicon. The core region of silicon is laterally within and above the peripheral region of silicon. A core region of silicon is exposed at a top of the semiconductor layer of each of the epitaxial structures of the first and second source or drain structures. In one embodiment, the overlying semiconductor layer 222' or 222 of each of the epitaxial structures of the first and second source or drain structures consists essentially of silicon and phosphorus.

With respect to fig. 2G, in an embodiment, the atomic concentration of phosphorus in the core region of silicon is greater than 5E21 atoms/cm³. In an embodiment, the atomic concentration of phosphorus in the peripheral region of silicon is less than 4E21 atoms/cm³. In an embodiment, the atomic concentration of phosphorus of the core region at the top of each of the epitaxial structures is greater than 6E21 atoms/cm³And graduating to less than 2E21 atoms/cm in a peripheral region at a bottom of each of the epitaxial structures³。

With respect to fig. 2G, in an embodiment, the first and second source or drain structures have a resistivity of less than about 0.4mOhm cm. In an embodiment, the use of the nitrogen gas flow gas substantially limits or completely prevents diffusion of phosphorus from the source or drain structure into the upper fin portion (a portion of 216 above the top surface of the isolation structure 210), i.e., substantially limits or completely prevents diffusion of phosphorus into the channel region of the integrated circuit structure. In one such embodiment, phosphorus diffuses from the source or drain structure into the channel region to an extent of less than 1 nanometer, and in some embodiments between 0 and 0.5 nanometers.

In contrast to fig. 2G, in fig. 2G', an embodiment is depicted in which no overlying semiconductor layer is used. In particular, the source or drain structure includes only a single source or drain material 220'. A conductive contact 230 is on the single source or drain material 220' of the first and second source or drain structures. In one such embodiment, although not depicted, the first and second conductive contacts are in partial recesses in a single source or drain material 220' of the first and second source or drain structures. It is to be appreciated that although not depicted, back-end processing may then be performed on the structure of fig. 2G'.

Referring again to fig. 2G', in accordance with an embodiment of the present disclosure, the integrated circuit structure includes a fin (216 and a patterned portion of the substrate 202) having a lower fin portion (a portion of 216 below the top surface of the isolation structure 210 and a patterned portion of 202) and an upper fin portion (a portion of 216 above the top surface of the isolation structure 210). A gate stack 212 is over the upper fin portion of the fin, the gate stack 212 having a first side opposite a second side. The first source or drain structure includes an epitaxial structure (220' left hand) embedded in the fin at a first side of the gate stack 212. The second source or drain structure includes an epitaxial structure (220' right hand) embedded in the fin at the second side of the gate stack 212. In an embodiment, each of the epitaxial structures includes silicon and phosphorus, as illustrated in connection with fig. 1C described above. The phosphorus has an atomic concentration in the core region of the silicon that is greater than the atomic concentration of phosphorus in the peripheral region of the silicon. The core region of silicon is laterally within and over the peripheral region of silicon and the core region of silicon is exposed at a top of each of the epitaxial structures.

With respect to fig. 2G', in an embodiment, the atomic concentration of phosphorus in the core region of silicon is greater than 5E21 atoms/cm³. In an embodiment, the atomic concentration of phosphorus in the peripheral region of silicon is less than 4E21 atoms/cm³. In an embodiment, the atomic concentration of phosphorus of the core region at the top of each of the epitaxial structures is greater than 6E21 atoms/cm³And graduating to less than 2E21 atoms/cm in a peripheral region at a bottom of each of the epitaxial structures³。

With respect to fig. 2G', in an embodiment, the first and second source or drain structures have a resistivity of less than about 0.4mOhm cm. In an embodiment, the use of the nitrogen gas flow gas substantially limits or completely prevents diffusion of phosphorus from the source or drain structure into the upper fin portion (a portion of 216 above the top surface of the isolation structure 210), i.e., substantially limits or completely prevents diffusion of phosphorus into the channel region of the integrated circuit structure. In one such embodiment, phosphorus diffuses from the source or drain structure into the channel region to an extent of less than 1 nanometer, and in some embodiments between 0 and 0.5 nanometers.

In contrast to fig. 2G and 2G', in fig. 2G ″ an embodiment is depicted wherein a blanket semiconductor layer is formed after forming the second spacers 226. In particular, the epitaxial structures of the first and second source or drain structures each include an overlying semiconductor layer 225 on the lower semiconductor layer 220 ″. A conductive contact 230 is on the overlying semiconductor layer 225 of the first and second source or drain structures. It is to be appreciated that although not depicted, back-end processing may then be performed on the structure of fig. 2G ″.

Referring again to fig. 2G', in accordance with an embodiment of the present disclosure, the integrated circuit structure includes a fin (216 and a patterned portion of the substrate 202) having a lower fin portion (a portion of 216 below the top surface of the isolation structure 210 and a patterned portion of 202) and an upper fin portion (a portion of 216 above the top surface of the isolation structure 210). A gate stack 212 is over the upper fin portion of the fin, the gate stack 212 having a first side opposite a second side. The first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack, the epitaxial structure having a lower semiconductor layer (220 "left hand) and an overlying semiconductor layer (225" left hand). The second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack, the epitaxial structure having a lower semiconductor layer (220 "right hand) and an overlying semiconductor layer (225 right hand). The second source or drain structure includes a lower epitaxial source or drain structure (220 "right hand) embedded in the fin at the second side of the gate stack 212. The first and second source or drain structures include an overlying semiconductor layer 225 confined between dielectric spacers 226 of a conductive contact 230. In an embodiment, the first and second source or drain structures comprise silicon and phosphorus, and in a particular embodiment, the first and second source or drain structures are formed using a nitrogen flow process.

In an embodiment, referring again to fig. 2G ", a first conductive contact (left-hand 230) is on the overlying semiconductor layer (left-hand 225) of the first source or drain structure. A second conductive contact (right hand 230) is on the overlying semiconductor layer (right hand 225) of the second source or drain structure. The first dielectric spacers (left-handed 226) are along sidewalls of the first conductive contact (left-handed 230) and the overlying semiconductor layer (left-handed 225) of the first source or drain structure is confined between the first dielectric spacers (left-handed 226). The second dielectric spacers (right-hand 226) are along sidewalls of the second conductive contact (right-hand 230) and the overlying semiconductor layer (right-hand 225) of the second source or drain structure is confined between the second dielectric spacers (right-hand 226). In one embodiment, not depicted, the cap semiconductor layer 225 is in partial recesses in the first and second lower semiconductor layers 220 ″. In another embodiment, as depicted, the first and second lower semiconductor layers 220 ″ are not recessed.

With respect to fig. 2G ", in an embodiment, an atomic concentration of phosphorus in the core region of silicon is greater than 5E21 atoms/cm³. In an embodiment, the atomic concentration of phosphorus in the peripheral region of silicon is less than 4E21 atoms/cm³. In an embodiment, the atomic concentration of phosphorus of the core region at the top of each of the epitaxial structures is greater than 6E21 atoms/cm³And graduating to less than 2E21 atoms/cm in a peripheral region at a bottom of each of the epitaxial structures³。

With respect to fig. 2G ", in an embodiment, the first and second source or drain structures have a resistivity of less than about 0.4mOhm cm. In an embodiment, the use of the nitrogen gas flow gas substantially limits or completely prevents diffusion of phosphorus from the source or drain structure into the upper fin portion (a portion of 216 above the top surface of the isolation structure 210), i.e., substantially limits or completely prevents diffusion of phosphorus into the channel region of the integrated circuit structure. In one such embodiment, phosphorus diffuses from the source or drain structure into the channel region to an extent of less than 1 nanometer, and in some embodiments between 0 and 0.5 nanometers.

In another aspect, fig. 3A illustrates a plan view of a plurality of gate lines over a pair of semiconductor fins in accordance with another embodiment of the present disclosure.

Referring to fig. 3A, a plurality of active gate lines 304 are formed over the plurality of semiconductor fins 300. The dummy gate line 306 is at an end of the plurality of semiconductor fins 300. Spaces 308 between gate lines 304/306 are locations where trench contacts may be positioned to provide conductive contacts to source or drain regions, such as source or drain regions 351, 352, 353, and 354. In an embodiment, the pattern of the plurality of gate lines 304/306 or the pattern of the plurality of semiconductor fins 300 is described as a grid structure. In one embodiment, the grid-like pattern includes a pattern of multiple semiconductor fins 300 spaced apart at a constant pitch and having a constant width and/or multiple gate lines 304/306, or both.

Fig. 3B illustrates a cross-sectional view taken along the a-a' axis of fig. 3A, in accordance with an embodiment of the present disclosure.

Referring to fig. 3B, a plurality of active gate lines 364 are formed over a semiconductor fin 362 formed over a substrate 360. The dummy gate line 366 is at an end of the semiconductor fin 362. Dielectric layer 370 is outside dummy gate line 366. The trench contact material 397 is between the active gate lines 364 and between the dummy gate lines 366 and the active gate lines 364. Embedded lower source or drain structures 368 and corresponding overlying semiconductor layers 369 are in the semiconductor fin 362 between the active gate lines 364 and between the dummy gate lines 366 and the active gate lines 364. The embedded lower source or drain structure 368 and corresponding source or drain overlying semiconductor layer 369 may be as described in connection with the source or drain structure of fig. 2G. Alternatively, source or drain structures such as those described in connection with fig. 2G' and 2G ″ may be used.

Active gate line 364 includes a gate dielectric structure 398/399, a work function gate electrode portion 374 and a fill gate electrode portion 376, and a dielectric capping layer 378. Dielectric spacers 380 overlay sidewalls of active gate line 364 and dummy gate line 366.

In another aspect, a trench contact structure, for example for a source or drain region, is described. In an example, fig. 4 illustrates a cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device, according to another embodiment of the present disclosure.

Referring to fig. 4, integrated circuit structure 450 includes a fin 452, such as a silicon germanium fin. A gate dielectric layer 454 is over fin 452. A gate electrode 456 is over the gate dielectric layer 454. In an embodiment, gate electrode 456 includes a conformal conductive layer 458 and conductive fill 460. In an embodiment, a dielectric cap 462 is over the gate electrode 456 and over the gate dielectric layer 454. The gate electrode has a first side 456A and a second side 456B opposite the first side 456A. Dielectric spacers 463 are along sidewalls of the gate electrode 456. In one embodiment, as depicted, the gate dielectric layer 454 is further between a first one of the dielectric spacers 463 and the first side 456A of the gate electrode 456 and between a second one of the dielectric spacers 463 and the second side 456B of the gate electrode 456. In an embodiment, although not depicted, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between fin 452 and gate dielectric layer 454.

A first semiconductor source or drain region 464 and a second semiconductor source or drain region 466 are adjacent the first side 456A and the second side 456B, respectively, of the gate electrode 456. In one embodiment, as depicted, first and second semiconductor source or drain regions 464 and 466 include embedded epitaxial lower regions and corresponding source or drain overlying semiconductor layers 495 or 497 and are formed in recesses 465 and 467, respectively, of fin 452. The embedded lower source or drain structure and the corresponding overlying semiconductor layer 495 or 497 may be as described in connection with the source or drain structure of fig. 2G. Alternatively, source or drain structures such as those described in connection with fig. 2G' and 2G ″ may be used.

First and second trench contact structures 468 and 470 are over first and second semiconductor source or drain regions 464 and 466, respectively, adjacent the first and second sides 456A and 456B of the gate electrode 456. Both the first trench contact structure 468 and the second trench contact structure 470 include a U-shaped metal layer 472 and a T-shaped metal layer 474 over and on the entirety of the U-shaped metal layer 472. In one embodiment, the composition of the U-shaped metal layer 472 and the T-shaped metal layer 474 are different. In one such embodiment, the U-shaped metal layer 472 comprises titanium and the T-shaped metal layer 474 comprises cobalt. In one embodiment, both the first trench contact structure 468 and the second trench contact structure 470 further include a third metal layer 476 on the T-shaped metal layer 474. In one such embodiment, third metal layer 476 and U-shaped metal layer 472 have the same composition. In a particular embodiment, the third metal layer 476 and the U-shaped metal layer 472 comprise titanium and the T-shaped metal layer 474 comprises cobalt.

First trench contact via 478 is electrically connected to first trench contact 468. In a particular embodiment, the first trench contact via 478 is on the third metal layer 476 of the first trench contact 468 and is coupled to the third metal layer 476 of the first trench contact 468. The first trench contact via 478 is further over and in contact with a portion of one of the dielectric spacers 463, and over and in contact with a portion of the dielectric cap 462. The second trench contact via 480 is electrically connected to the second trench contact 470. In a particular embodiment, the second trench contact via 480 is on the third metal layer 476 of the second trench contact 470 and is coupled to the third metal layer 476 of the second trench contact 470. The second trench contact via 480 is further over and in contact with a portion of another one of the dielectric spacers 463 and over and in contact with another portion of the dielectric cap 462.

In an embodiment, the metal silicide layer 482 is directly between the first trench contact structure 468 and the first semiconductor source or drain region 464 and between the second trench contact structure 470 and the second semiconductor source or drain region 466, respectively. In one embodiment, metal silicide layer 482 comprises titanium and silicon. In a particular such embodiment, the first and second semiconductor source or drain regions 464, 466 are first and second N-type semiconductor source or drain regions. In one embodiment, metal silicide layer 482 further includes phosphorus or arsenic, or both.

One or more embodiments described herein are directed to the use of metal chemical vapor deposition for wrap-around semiconductor contacts. Embodiments may be adapted for or include one or more of Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), conductive contact fabrication, or thin films. Particular embodiments may include fabricating a titanium or similar metal layer using low temperature (e.g., less than 500 degrees celsius or in the range of 400-500 degrees celsius) chemical vapor deposition of a contact metal to provide conformal source or drain contacts. Implementation of such conformal source or drain contacts may improve three-dimensional (3D) transistor Complementary Metal Oxide Semiconductor (CMOS) performance.

To provide context, sputtering may be used to deposit metal to the semiconductor contact layer. Sputtering is a line-of-sight process and may not be well suited for 3D transistor fabrication. Known sputtering solutions have poor or incomplete metal-semiconductor junctions on device contact surfaces that have an angle to the drop direction of deposition. In accordance with one or more embodiments of the present disclosure, a low temperature chemical vapor deposition process is implemented for fabricating contact metals to provide three-dimensional conformality and maximize metal-semiconductor junction contact area. The resulting larger contact area may reduce the resistance of the junction. Embodiments may include deposition on a semiconductor surface having a non-planar topography, where the topography of the area refers to the surface shape and features themselves, and the non-planar topography includes non-planar surface shapes and features or portions of surface shapes and features, i.e., surface shapes and features that are not completely planar. In an embodiment, the semiconductor surface is deposited on a source or drain structure having a relatively high germanium content.

Embodiments described herein may include fabricating wrap-around contact structures. In one such embodiment, the use of pure metals conformally deposited onto the transistor source-drain contacts by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or plasma enhanced atomic layer deposition is described. Such conformal deposition can be used to increase the available area for metal-semiconductor contacts and reduce resistance, thereby improving the performance of transistor devices. In an embodiment, the relatively low temperature of deposition results in a minimized resistance per unit area of the junction.

It is to be appreciated that a wide variety of integrated circuit structures can be fabricated using an integration scheme involving a metal layer deposition process as described herein. In accordance with an embodiment of the present disclosure, a method of fabricating an integrated circuit structure includes providing a substrate having features thereon in a Chemical Vapor Deposition (CVD) chamber having an RF source. The process further comprises reacting titanium tetrachloride (TiCl)₄) And hydrogen (H)₂) React to form a titanium (Ti) layer on the features of the substrate. In an embodiment, the titanium layer has a total atomic composition including 98% or greater titanium and 0.5-2% chlorine. In an alternative embodiment, a similar process is used to fabricate high purity metal layers of zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), or vanadium (V).

According to an embodiment of the present disclosure, the substrate is characterized by a source or drain contact trench exposing the semiconductor source or drain structure. The titanium layer (or other high purity metal layer) is a conductive contact layer for a semiconductor source or drain structure. An exemplary embodiment of such an implementation is described below in connection with fig. 5.

Figure 5 illustrates a cross-sectional view of an integrated circuit structure having a conductive contact on a raised source or drain region, in accordance with an embodiment of the present disclosure.

Referring to fig. 5, a semiconductor structure 550 includes a gate structure 552 over a substrate 554. The gate structure 552 includes a gate dielectric layer 552A, a work function layer 552B, and a gate fill 552C. Source region 558 and drain region 560 are on opposite sides of gate structure 552. A source or drain contact 562 is electrically connected to the source region 558 and the drain region 560 and the source or drain contact 562 is separated from the gate structure 552 by one or both of an interlayer dielectric layer 564 or a gate dielectric spacer 566. The source region 558 and the drain region 560 include an epitaxial or embedded lower material region formed in the etched out region of the substrate 554 and a corresponding source or drain overlying semiconductor layer 502. The embedded lower source or drain structure and corresponding overlying semiconductor layer 502 may be as described in connection with the source or drain structure of fig. 2G. Alternatively, source or drain structures such as those described in connection with fig. 2G' and 2G "may be used.

In an embodiment, the source or drain contacts 562 comprise a high purity metal layer 562A and a conductive trench fill material 562B such as described above. In one embodiment, high purity metal layer 562A has a total atomic composition including 98% or greater titanium. In one such embodiment, the total atomic composition of high-purity metal layer 562A further includes 0.5-2% chlorine. In an embodiment, the high purity metal layer 562A has a thickness variation of 30% or less. In an embodiment, the conductive trench fill material 562B is comprised of a conductive material such as, but not limited to, Cu, Al, W, Co, or alloys thereof.

In another aspect, an active over active gate (COAG) structure and process are described. One or more embodiments of the present disclosure are directed to semiconductor structures or devices having one or more gate contact structures (e.g., as gate contact vias) disposed over an active portion of a gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure are directed to methods of fabricating a semiconductor structure or device having one or more gate contact structures formed over an active portion of a gate electrode of the semiconductor structure or device. The methods described herein may be used to reduce standard cell area by enabling gate contact formation over an active gate region. In one or more embodiments, the gate contact structure fabricated to contact the gate electrode is a self-aligned via structure.

In an embodiment, the integrated circuit structure, semiconductor structure, or device is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device. In such embodiments, the channel region of the corresponding semiconductor is comprised of or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of gate lines surrounds at least a top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is fabricated as a discrete three-dimensional body such as in a gate-all-around device. In one such embodiment, each gate electrode stack of the plurality of gate lines completely surrounds the channel region.

More generally, one or more embodiments are directed to methods for landing a gate contact via directly on an active transistor gate and structures formed by landing a gate contact via directly on an active transistor gate. Such an approach may eliminate the need to extend the gate lines over the isolation for contact purposes. Such an approach may also eliminate the need for a separate Gate Contact (GCN) layer to conduct signals from the gate lines or structures. In an embodiment, eliminating the above feature is achieved by recessing the contact metal in the Trench Contact (TCN) and introducing additional dielectric material in the process flow (e.g., TILA). Additional dielectric material is included as a trench contact dielectric cap layer having different etch characteristics than a gate dielectric material cap layer that has been used for trench contact alignment in a gate aligned contact process (GAP) processing scheme (e.g., GILA).

In an embodiment, providing an integrated circuit structure involves forming a contact pattern that is substantially perfectly aligned with an existing gate pattern, while eliminating the use of a lithography operation with a very tight registration budget. In one such embodiment, this method enables the use of an inherently highly selective wet etch (as compared, for example, to a dry or plasma etch) to create the contact openings. In an embodiment, the contact pattern is formed by using an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the method enables elimination of the need for otherwise critical lithographic operations to generate contact patterns as used in other methods. In an embodiment, the trench contact grid is not separately patterned, but instead is formed between poly (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

In addition, the gate stack structure may be fabricated by a replacement gate process. In such an approach, the dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being performed according to an earlier process. In an embodiment, the dummy gate is removed by a dry etch or a wet etch process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is formed using a process including SF₆The dummy gate is removed by the dry etching process of (1). In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and utilizes NH including water₄A wet etch process of OH or tetramethylammonium hydroxide removes the dummy gate. In one embodiment, the dummy gate is composed of silicon nitride, and the dummy gate is removed using a wet etch comprising aqueous phosphoric acid.

In an embodiment, one or more of the methods described herein essentially contemplate dummy and replacement gate processes in combination with dummy and replacement contact processes to obtain an integrated circuit structure. In one such embodiment, a replacement contact process is performed after the replacement gate process to allow for a high temperature anneal of at least a portion of the permanent gate stack. For example, in certain such embodiments, the annealing of at least a portion of the permanent gate structure is performed at a temperature greater than about 600 degrees celsius, for example, after the gate dielectric layer is formed. Annealing is performed prior to forming the permanent contact.

It is to be appreciated that different structural relationships between the insulated gate cap layer and the insulated trench contact cap layer may be fabricated. As an example, fig. 6A and 6B illustrate cross-sectional views of various integrated circuit structures each having a trench contact including an overlying insulating cap layer and having a gate stack including an overlying insulating cap layer, in accordance with embodiments of the present disclosure.

Referring to fig. 6A and 6B, integrated circuit structures 600A and 600B, respectively, include a fin 602, such as a silicon germanium fin. Although depicted as a cross-sectional view, it is to be appreciated that fin 602 has a top 602A and sidewalls (into and out of the page of the perspective view shown). A first gate dielectric layer 604 and a second gate dielectric layer 606 are over the top 602A of the fin 602 and laterally adjacent to the sidewalls of the fin 602. A first gate electrode 608 and a second gate electrode 610 are over the first gate dielectric layer 604 and the second gate dielectric layer 606, respectively, over the top 602A of the fin 602 and laterally adjacent to the sidewalls of the fin 602. The first gate electrode 608 and the second gate electrode 610 each include a conformal conductive layer 609A, such as a workfunction setting layer, and a conductive fill material 609B over the conformal conductive layer 609A. Both the first gate electrode 608 and the second gate electrode 610 have a first side 612 and a second side 614 opposite the first side 612. Both the first gate electrode 608 and the second gate electrode 610 also have an insulating cap 616, the insulating cap 616 having a top surface 618.

A first dielectric spacer 620 is adjacent the first side 612 of the first gate electrode 608. A second dielectric spacer 622 is adjacent the second side 614 of the second gate electrode 610. A semiconductor source or drain region 624 is adjacent the first dielectric spacer 620 and the second dielectric spacer 622. A trench contact structure 626 is over the semiconductor source or drain region 624 adjacent the first dielectric spacer 620 and the second dielectric spacer 622. In an embodiment, the semiconductor source or drain region 624 has a structure such as described above in connection with fig. 2G, 2G', 2G ", and other embodiments described herein.

Trench contact structure 626 includes an insulating cap 628 over a conductive structure 630. The insulating cap 628 of the trench contact structure 626 has a top surface 629 that is substantially coplanar with the top surfaces 618 of the insulating caps 616 of the first gate electrode 608 and the second gate electrode 610. In an embodiment, the insulating cap 628 of the trench contact structure 626 extends laterally into the recess 632 in the first dielectric spacer 620 and the second dielectric spacer 622. In such an embodiment, insulative cap 628 of trench contact structure 626 overhangs conductive structure 630 of trench contact structure 626. However, in other embodiments, the insulative cap 628 of the trench contact structure 626 does not extend laterally into the recesses 632 in the first and second dielectric spacers 620, 622, and thus does not overhang the conductive structure 630 of the trench contact structure 626.

It is to be appreciated that the conductive structure 630 of the trench contact structure 626 may not be rectangular, as depicted in fig. 6A and 6B. For example, the conductive structure 630 of the trench contact structure 626 may have a cross-sectional geometry similar or identical to the geometry shown for the conductive structure 630A illustrated in the projection of fig. 6A.

In an embodiment, the insulating cap 628 of the trench contact structure 626 has a composition different from the composition of the insulating caps 616 of the first gate electrode 608 and the second gate electrode 610. In one such embodiment, insulative cap 628 of trench contact structure 626 comprises a carbide material, such as a silicon carbide material. The insulating cap 616 of the first gate electrode 608 and the second gate electrode 610 includes a nitride material such as a silicon nitride material.

In an embodiment, as depicted in fig. 6A, both insulating caps 616 of first gate electrode 608 and second gate electrode 610 have a bottom surface 617A that is lower than a bottom surface 628A of insulating caps 628 of trench contact structures 626. In another embodiment, as depicted in fig. 6B, both the insulating caps 616 of the first and second gate electrodes 608, 610 have bottom surfaces 617B that are substantially coplanar with bottom surfaces 628B of the insulating caps 628 of the trench contact structures 626. In another embodiment, although not depicted, both insulating caps 616 of first gate electrode 608 and second gate electrode 610 have a bottom surface that is higher than a bottom surface of insulating caps 628 of trench contact structure 626.

In an embodiment, the conductive structure 630 of the trench contact structure 626 includes a U-shaped metal layer 634, a T-shaped metal layer 636 over and above the entirety of the U-shaped metal layer 634, and a third metal layer 638 over the T-shaped metal layer 636. An insulating cap 628 of the trench contact structure 626 is on the third metal layer 638. In one such embodiment, the third metal layer 638 and the U-shaped metal layer 634 comprise titanium, and the T-shaped metal layer 636 comprises cobalt. In certain such embodiments, the T-shaped metal layer 636 further comprises carbon.

In an embodiment, the metal silicide layer 640 is directly between the conductive structure 630 of the trench contact structure 626 and the semiconductor source or drain region 624. In one such embodiment, the metal silicide layer 640 comprises titanium and silicon. In a particular such embodiment, the semiconductor source or drain region 624 is an N-type semiconductor source or drain region.

As described throughout this application, the substrate may be composed of a semiconductor material that is resistant to the fabrication process and in which charge can migrate. In embodiments, the substrate described herein is a bulk substrate composed of crystalline silicon, silicon/germanium, or germanium layer doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof, used to form the active region. In one embodiment, the concentration of silicon atoms in such a bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on top of a distinct crystalline substrate, such as a silicon epitaxial layer grown on top of a bulk silicon single crystal substrate doped with boron. The bulk substrate may alternatively be composed of a III-V material. In an embodiment, the bulk substrate is composed of a group III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate is composed of a group III-V material and the charge carrier dopant impurity atoms are charge carrier dopant impurity atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

As described throughout this application, an isolation region, such as a shallow trench isolation region or a sub-fin isolation region, may be comprised of a material suitable to ultimately electrically isolate, or facilitate isolation of, a portion of a permanent gate structure from an underlying bulk substrate or an active region formed within an underlying bulk substrate (such as an isolation fin active region). For example, in one embodiment, the isolation region is composed of one or more layers of dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or combinations thereof.

As described throughout this application, a gate line or gate structure may be comprised of a gate electrode stack including a gate dielectric layer and a gate electrode layer. In an embodiment, the gate electrode of the gate electrode stack is comprised of a metal gate and the gate dielectric layer is comprised of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Further, a portion of the gate dielectric layer may include a native oxide layer formed from the top few layers of the semiconductor substrate. In an embodiment, the gate dielectric layer is comprised of a top high-k portion and a lower portion comprised of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is comprised of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U" shaped structure that includes a bottom portion substantially parallel to a surface of the substrate and two sidewall portions substantially perpendicular to a top surface of the substrate.

In one embodiment, the gate electrode is comprised of a metal layer such as, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a particular embodiment, the gate electrode is comprised of a non-workfunction setting fill material formed above the metal workfunction setting layer. The gate electrode layer may be comprised of a P-type work function metal or an N-type work function metal, depending on whether the transistor is to be a PMOS transistor or an NMOS transistor. In some implementations, the gate electrode layer may be comprised of a stack of two or more metal layers, where one or more of the metal layers is a workfunction metal layer and at least one of the metal layers is a conductive fill layer. For a PMOS transistor, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). The P-type metal layer will enable the formation of a PMOS gate electrode having a workfunction between about 4.9eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode having a workfunction between about 3.9eV and about 4.2 eV. In some implementations, the gate electrode can be comprised of a "U" shaped structure that includes a bottom portion substantially parallel to a surface of the substrate and two sidewall portions substantially perpendicular to a top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the present disclosure, the gate electrode may be comprised of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be comprised of one or more U-shaped metal layers formed atop one or more planar non-U-shaped layers.

As described throughout this application, the spacers associated with the gate line or electrode stack may be comprised of a material suitable for ultimately electrically isolating or helping to isolate the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are comprised of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

In embodiments, the methods described herein may involve forming contact patterns that align very well with existing gate patterns, while precluding the use of lithography operations with very tight registration budgets. In one such embodiment, this method enables the use of an inherently highly selective wet etch (as compared, for example, to a dry or plasma etch) to create the contact openings. In an embodiment, the contact pattern is formed by using an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the method enables elimination of the need for otherwise critical lithographic operations to generate contact patterns as used in other methods. In an embodiment, the trench contact grid is not separately patterned, but instead is formed between poly (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

The pitch division process and patterning scheme may be implemented to enable or may be included as part of the embodiments described herein. Pitch division patterning typically refers to pitch halving, pitch quartering, etc. The pitch division scheme may be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print unidirectional lines (e.g., either strictly unidirectional or predominantly unidirectional) at a predefined pitch. The pitch division process is then implemented as a technique to increase the line density.

In an embodiment, the term "grid structure" as used for fins, gate lines, metal lines, ILD lines, or hardmask lines is used herein to refer to a tight pitch grid structure. In one such embodiment, tight pitch is not directly achievable by selective lithography. For example, a pattern based on selected lithography may be formed first, but the pitch may be bisected by patterning using a spacer mask, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Thus, the grid-like pattern described herein may have metal lines, ILD lines, or hardmask lines spaced apart at substantially uniform intervals and having substantially uniform widths. For example, in some embodiments, the pitch variation will be within ten percent and the width variation will be within ten percent, and in some embodiments, the pitch variation will be within five percent and the width variation will be within five percent. The pattern may be fabricated by pitch halving or pitch quartering or other pitch dividing methods. In embodiments, the grid need not be a single pitch.

In embodiments, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO)₂) Doped oxides of silicon, fluorinated oxides of silicon, siliconCarbon doped oxides, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by techniques such as, for example, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or by other deposition methods.

In embodiments, as also used throughout this specification, the metal line or interconnect line material (and via material) is comprised of one or more metals or other conductive structures. A common example is the use of copper lines and structures that may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of metals. For example, the metal interconnect lines may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, and the like. Thus, the interconnect line may be a single layer of material or may be formed from several layers including a conductive liner layer and a fill layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form the interconnect lines. In an embodiment, the interconnect line is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnect lines are also sometimes referred to in the art as traces, wires, lines, metals, or simply interconnects.

In an embodiment, as also used throughout this specification, the hard mask material is composed of a dielectric material that is different from the interlayer dielectric material. In one embodiment, different hard mask materials may be used in different regions to provide different growth or etch selectivity with respect to each other and with respect to the underlying dielectric and metal layers. In some embodiments, the hard mask layer comprises a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material comprises a metal species (a metal species). For example, the hard mask or other overlying material may include a layer of titanium or another metal nitride (e.g., titanium nitride). Potentially smaller amounts of other materials such as oxygen may be included in one or more of these layers. Alternatively, other hard mask layers known in the art may be used depending on the particular implementation. The hard mask layer may be formed by CVD, PVD, or by other deposition methods.

In an embodiment, as also used throughout this specification, a lithographic operation is performed using 193nm immersion lithography (i 193), Extreme Ultraviolet (EUV) lithography, or Electron Beam Direct Write (EBDW) lithography, among others. Either positive tone or negative tone resists may be used. In one embodiment, the photolithographic mask is a tri-layer mask consisting of a profile masking portion, an anti-reflective coating (ARC) layer and a photoresist layer. In a particular such embodiment, the topography masking portion is a Carbon Hard Mask (CHM) layer and the antireflective coating layer is a silicon ARC layer.

It will be appreciated that not all aspects of the above-described processes need be implemented to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, the dummy gate need not be formed at any time prior to making a gate contact over the active portion of the gate stack. The gate stack described above may actually be a permanent gate stack as originally formed. Also, the processes described herein may be used to fabricate one or more semiconductor devices. The semiconductor device may be a transistor or the like. For example, in an embodiment, the semiconductor device is a Metal Oxide Semiconductor (MOS) transistor or a bipolar transistor for logic or memory. Also, in an embodiment, the semiconductor device has a three-dimensional architecture such as a tri-gate device, an independently accessed dual-gate device, a FIN-FET, a nanowire device, or a nanoribbon device. One or more embodiments may be particularly useful for fabricating semiconductor devices at 10 nanometer (10 nm) technology nodes sub-10 nanometer (10 nm) technology nodes.

Additional or intermediate operations for FEOL layer or structure fabrication may include standard microelectronic fabrication processes such as photolithography, etching, thin film deposition, planarization (such as Chemical Mechanical Polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, or any other action associated with microelectronic component fabrication. Moreover, it is to be appreciated that the process operations described with respect to the previous process flows can be performed in an alternative order, that each operation need not be performed, or that additional process operations can be performed, or both.

It will be appreciated that in the above exemplary FEOL embodiments, 10nm or sub-10 nm node processing is directly implemented into the fabrication scheme and resulting structure as a technology driver in the embodiments. In other embodiments, FEOL considerations may be driven by BEOL 10 nanometer or sub-10 nanometer processing requirements. For example, the material selection and layout for FEOL layers and devices may need to be adapted to BEOL processing. In one such embodiment, the material selection and gate stack architecture are selected to accommodate high density metallization of the BEOL layers, for example to reduce fringe capacitance in transistor structures formed in the FEOL layers but coupled together by the high density metallization of the BEOL layers.

The embodiments disclosed herein may be used to fabricate a wide variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories may be fabricated. Furthermore, integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronic devices, and the like. The integrated circuit may be coupled to buses and other components in the system. For example, the processor may be coupled to the memory, chipset, etc. by one or more buses. Each of the processors, memories, and chipsets can potentially be manufactured using the methods disclosed herein.

FIG. 7 illustrates a computing device 700 in accordance with one implementation of the present disclosure. The computing device 700 houses a board 702. The board 702 may include a number of components, including but not limited to a processor 704 and at least one communication chip 706. The processor 704 is physically and electrically coupled to the board 702. In some implementations, at least one communication chip 706 is also physically and electrically coupled to the board 702. In further implementations, the communication chip 706 is part of the processor 704.

Depending on its applications, the computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a Global Positioning System (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, a Compact Disc (CD), a Digital Versatile Disc (DVD), and so forth).

The communication chip 706 enables wireless communication for data transfer to and from the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 706 may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and above. The computing device 700 may include a plurality of communication chips 706. For example, the first communication chip 706 may be dedicated for shorter range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 706 may be dedicated for longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and so forth.

The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some implementations of embodiments of the present disclosure, the integrated circuit die of the processor includes one or more structures such as integrated circuit structures constructed in accordance with implementations of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers or memory, or both, to transform that electronic data into other electronic data that may be stored in registers or memory, or both.

The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. In accordance with another implementation of the present disclosure, an integrated circuit die of a communication chip is constructed in accordance with an implementation of the present disclosure.

In further implementations, another component housed within the computing device 700 may contain an integrated circuit die constructed in accordance with implementations of embodiments of the present disclosure.

In various embodiments, the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a Personal Digital Assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.

Fig. 8 illustrates an interposer (interposer) 800 including one or more embodiments of the present disclosure. The interposer 800 is an intervening substrate used to bridge a first substrate 802 to a second substrate 804. The first substrate 802 may be, for example, an integrated circuit die. The second substrate 804 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the interposer 800 is to spread connections to a wider pitch or to reroute connections to different connections. For example, the interposer 800 may couple an integrated circuit die to a Ball Grid Array (BGA) 806, which BGA 806 may then be coupled to the second substrate 804. In some embodiments, the first and second substrates 802/804 are attached to opposite sides of the interposer 800. In other embodiments, the first and second substrates 802/804 are attached to the same side of the interposer 800. Also, in further embodiments, three or more substrates are interconnected through interposer 800.

The interposer 800 may be formed of epoxy, fiberglass reinforced epoxy, ceramic material, or polymeric material such as polyimide. In further implementations, the interposer 800 may be formed of alternative rigid or flexible materials that may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials.

Interposer 800 may include metal interconnects 808 and vias 810, including but not limited to Through Silicon Vias (TSVs) 812. The interposer 800 may further include embedded devices 814, the embedded devices 814 including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as Radio Frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 800. In accordance with embodiments of the present disclosure, the devices or processes disclosed herein may be used in the fabrication of the interposer 800 or in the fabrication of components included in the interposer 800.

Fig. 9 is an isometric view of a mobile computing platform 900 employing an Integrated Circuit (IC) fabricated according to one or more processes described herein or including one or more features described herein, according to an embodiment of the disclosure.

The mobile computing platform 900 may be any portable device configured for each of electronic data display, electronic data processing, and wireless electronic data transmission. For example, the mobile computing platform 900 may be any of a tablet computer, a smart phone, a laptop computer, and the like and include a display screen 905, which in an exemplary embodiment is a touch screen (capacitive, inductive, resistive, etc.), a chip-level (SoC) or package-level integrated system 910, and a battery 913. As illustrated, the greater the level of integration in the system 910 enabled by the higher transistor packing density, the greater the portion of the mobile computing platform 900 that may be occupied by the battery 913 or non-volatile storage (such as solid state drives), or the greater the transistor gate count for improved platform functionality. Similarly, the greater the carrier mobility of each transistor in the system 910, the greater the functionality. Likewise, the techniques described herein may enable performance and form factor improvements in mobile computing platform 900.

The integrated system 910 is further illustrated in expanded view 920. In an exemplary embodiment, packaged device 977 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and/or a graphics processor) fabricated according to one or more processes described herein or including one or more features described herein. One or more of the packaged device 977 is further coupled to a board 960 along with a Power Management Integrated Circuit (PMIC) 915, an RF (wireless) integrated circuit (RFIC) 925 including a wideband RF transmitter and/or receiver (e.g., including a digital baseband and an analog front end module further including a power amplifier in a transmit path and a low noise amplifier in a receive path), and a controller 911 therein. Functionally, PMIC 915 performs battery power regulation, DC-to-DC conversion, etc., and thus has an input coupled to battery 913 and an output that provides a current source to all other functional modules. As further illustrated, in the exemplary embodiment, RFIC 925 has an output coupled to an antenna to provide for implementing any one of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and above. In alternative implementations, each of these board-level modules may be integrated onto a separate IC coupled to the package substrate of packaged device 977 or integrated within a single IC (soc) coupled to the package substrate of packaged device 977.

In another aspect, semiconductor packages are used to protect Integrated Circuit (IC) chips or dies, and also to provide electrical interfaces to external circuitry for the dies. With the increasing demand for smaller electronic devices, semiconductor packages are designed to be even more compact and must support greater circuit densities. Furthermore, the demand for higher performance devices has resulted in a need for improved semiconductor packages that enable thin package profiles and low overall warpage compatible with subsequent assembly processes.

In an embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, the die is mounted to a ceramic or organic package substrate using a C4 process. In particular, C4 solder ball connections may be implemented to provide flip-chip interconnects between the semiconductor device and the substrate. Flip chip or controlled collapse chip connection (C4) is a type of mounting for semiconductor devices such as Integrated Circuit (IC) chips, MEMS, or components that utilizes solder bumps rather than wire bonding. Solder bumps are deposited on the C4 pads located on the topside of the substrate package. In order to mount the semiconductor device on the substrate, it is turned upside down with the active side facing down on the mounting area. Solder bumps are used to directly connect a semiconductor device to a substrate.

Fig. 10 illustrates a cross-sectional view of a flip-chip mounted die according to an embodiment of the disclosure.

Referring to fig. 10, in accordance with an embodiment of the present disclosure, an apparatus 1000 includes a die 1002, such as an Integrated Circuit (IC), fabricated in accordance with one or more processes described herein or including one or more features described herein. The die 1002 includes a metallization pad 1004 thereon. A package substrate 1006, such as a ceramic or organic substrate, includes connections 1008 thereon. The die 1002 and the package substrate 1006 are electrically connected by solder balls 1010 coupled to the metallization pads 1004 and connections 1008. The unfilled material 1012 surrounds the solder balls 1010.

Processing the flip chip may be similar to conventional IC fabrication with some additional operations. Towards the end of the manufacturing process, the attachment pads are metallized to make them more receptive to solder. This typically consists of several processes. A small solder joint is then deposited on each metallized pad. The chips are then cut from the wafer as usual. To attach a flip chip to a circuit, the chip is inverted to bring the solder joints down to connectors on the underlying electronic device or circuit board. The solder is then remelted to create an electrical connection, typically using an ultrasonic or alternatively a reflow soldering process. This also leaves a small space between the circuitry of the chip and the underlying mounting. In most cases, the electrically insulating adhesive is then "underfilled" to provide a stronger mechanical connection, provide a thermal bridge, and ensure that the solder joint is not stressed due to differential heating of the chip and the rest of the system.

In other embodiments, newer packaging and die-to-die interconnection methods, such as through-silicon vias (TSVs) and silicon interposers, are implemented to fabricate high performance multi-chip modules (MCMs) and system-in-packages (sips) incorporating Integrated Circuits (ICs) fabricated according to one or more processes described herein or including one or more features described herein, in accordance with embodiments of the present disclosure.

Accordingly, embodiments of the present disclosure include an integrated circuit structure having a source or drain structure with a high phosphorous dopant concentration, and methods of fabricating an integrated circuit structure having a source or drain structure with a high phosphorous dopant concentration are described.

Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the disclosure, even though a single embodiment is described herein with respect to only certain features. Unless otherwise specified, examples of features provided in the present disclosure are intended to be illustrative and not limiting. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to those skilled in the art having the benefit of this disclosure.

The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly) or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Thus, during the prosecution of the present application (or of an application claiming priority thereto), a new claim may be formulated to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.

The following examples pertain to further embodiments. Various features of the different embodiments may be combined in different ways with some features included and others excluded to suit a wide variety of different applications.

Example embodiment 1: an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. The first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. The second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first source or drain structure and the second source or drain structure includes silicon and phosphorus having an atomic concentration in a core region of the silicon that is greater than an atomic concentration of phosphorus in a peripheral region of the silicon. A core region of silicon is laterally within and over the peripheral region of silicon and the core region of silicon is exposed at a top of each of the epitaxial structures of the first source or drain structure and the second source or drain structure.

Example embodiment 2: the integrated circuit structure of example embodiment 1, wherein the atomic concentration of phosphorus in the core region of silicon is greater than 5E21 atoms/cm³。

Example embodiment 3: the integrated circuit structure of example embodiments 1 or 2, wherein an atomic concentration of phosphorus in the peripheral region of the silicon is less than 4E21 atoms/cm³。

Example embodiment 4: the integrated circuit structure according to example embodiments 1, 2, or 3, wherein the phosphorus of the core region at the top of each of the epitaxial structuresThe atomic concentration is more than 6E21 atoms/cm³And graduates to less than 2E21 atoms/cm in the peripheral region at the bottom of each of the epitaxial structures³。

Example embodiment 5: the integrated circuit structure of example embodiments 1, 2, 3, or 4, wherein the first source or drain structure and the second source or drain structure have a resistivity of less than about 0.4mOhm cm.

Example embodiment 6: the integrated circuit structure of example embodiments 1, 2, 3, 4, or 5, wherein the lower fin portion comprises a portion of an underlying bulk monocrystalline silicon substrate.

Example embodiment 7: the integrated circuit structure of example embodiments 1, 2, 3, 4, 5, or 6, further comprising first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

Example embodiment 8: the integrated circuit structure of example embodiments 1, 2, 3, 4, 5, 6, or 7, further comprising a first conductive contact on the epitaxial structure of the first source or drain structure, and a second conductive contact on the epitaxial structure of the second source or drain structure.

Example embodiment 9: the integrated circuit structure of example embodiment 8, wherein the first conductive contact and the second conductive contact are in partial recesses in the epitaxial structures of the first source or drain structure and the second source or drain structure, respectively.

Example embodiment 10: an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. The first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack, the epitaxial structure having a lower semiconductor layer and an overlying semiconductor layer on the lower semiconductor layer. The second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack, the epitaxial structure having a lower semiconductor layer and an overlying semiconductor layer on the lower semiconductor layer. The lower semiconductor layer of each of the epitaxial structures of the first source or drain structure and the second source or drain structure includes silicon and phosphorus. The phosphorus has an atomic concentration in the core region of the silicon that is greater than the atomic concentration of phosphorus in the peripheral region of the silicon. The core region of silicon is laterally within and above the peripheral region of silicon. A core region of silicon is exposed at a top of the semiconductor layer of each of the epitaxial structures of the first source or drain structure and the second source or drain structure.

Example embodiment 11: the integrated circuit structure of example embodiment 10, wherein the atomic concentration of phosphorus in the core region of silicon is greater than 5E21 atoms/cm³。

Example embodiment 12: the integrated circuit structure of example embodiments 10 or 11, wherein an atomic concentration of phosphorus in the peripheral region of silicon is less than 4E21 atoms/cm³。

Example embodiment 13: the integrated circuit structure of example embodiments 10, 11, or 12, wherein an atomic concentration of phosphorus of the core region at a top of each of the epitaxial structures is greater than 6E21 atoms/cm³And graduates to less than 2E21 atoms/cm in the peripheral region at the bottom of each of the epitaxial structures³。

Example embodiment 14: the integrated circuit structure according to example embodiments 10, 11, 12, or 13, wherein the first source or drain structure and the second source or drain structure have a resistivity of less than about 0.4mOhm cm.

Example embodiment 15: the integrated circuit structure of example embodiments 10, 11, 12, 13, or 14, wherein the lower fin portion comprises a portion of an underlying bulk monocrystalline silicon substrate.

Example embodiment 16: the integrated circuit structure of example embodiments 10, 11, 12, 13, 14, or 15, further comprising first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

Example embodiment 17: the integrated circuit structure of example embodiments 10, 11, 12, 13, 14, 15, or 16, further comprising a first conductive contact on the overlying semiconductor layer of the first source or drain structure; and a second conductive contact on the overlying semiconductor layer of the second source or drain structure.

Example embodiment 18: the integrated circuit structure of example embodiment 17, wherein the first and second conductive contacts are in partial recesses in the overlying semiconductor layer of the first and second source or drain structures, respectively.

Example embodiment 19: a computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure. The integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. The first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. The second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first source or drain structure and the second source or drain structure includes silicon and phosphorus having an atomic concentration in a core region of the silicon that is greater than an atomic concentration of phosphorus in a peripheral region of the silicon. A core region of silicon is laterally within and over the peripheral region of silicon and the core region of silicon is exposed at a top of each of the epitaxial structures of the first source or drain structure and the second source or drain structure.

Example embodiment 20: the computing device of example embodiment 19, further comprising a memory coupled to the board.

Example embodiment 21: the computing device of example embodiment 19 or 20, further comprising a communication chip coupled to the board.

Example embodiment 22: the computing device according to example embodiments 19, 20, or 21, further comprising a camera coupled to the board.

Example embodiment 23: the computing device according to example embodiments 19, 20, 21, or 22, further comprising a battery coupled to the board.

Example embodiment 24: the computing device according to example embodiments 19, 20, 21, 22, or 23, further comprising an antenna coupled to the board.

Example embodiment 25: the computing device of example embodiments 19, 20, 21, 22, 23, or 24, wherein the component is a packaged integrated circuit die.