Oxide semiconductor transistor

文档序号：290094 发布日期：2021-11-23 浏览：14次中文

阅读说明：本技术 氧化物半导体晶体管 (Oxide semiconductor transistor ) 是由李光熙金尚昱许镇盛于 2021-03-09 设计创作，主要内容包括：本发明提供一种氧化物半导体晶体管,该氧化物半导体晶体管包括：包括沟槽的绝缘基板；在沟槽中的栅电极；在绝缘基板的表面上的氧化物半导体层,该表面通过沟槽暴露；以及在栅电极和氧化物半导体层之间的铁电层,其中氧化物半导体层可以包括源极区和漏极区,源极区和漏极区在绝缘基板上在沟槽外部并且彼此隔开,其中栅电极在源极区和漏极区之间。(The present invention provides an oxide semiconductor transistor, including: an insulating substrate including a trench; a gate electrode in the trench; an oxide semiconductor layer on a surface of the insulating substrate, the surface being exposed through the trench; and a ferroelectric layer between the gate electrode and the oxide semiconductor layer, wherein the oxide semiconductor layer may include source and drain regions outside the trench and spaced apart from each other on the insulating substrate, wherein the gate electrode is between the source and drain regions.)

1. An oxide semiconductor transistor comprising:

an insulating substrate including a trench;

a gate electrode in the trench;

an oxide semiconductor layer on a surface of the insulating substrate, the surface being exposed through the trench; and

a ferroelectric layer between the gate electrode and the oxide semiconductor layer,

wherein the oxide semiconductor layer includes a source region and a drain region spaced apart from each other outside the trench on the insulating substrate, and the gate electrode is between the source region and the drain region.

2. The oxide semiconductor transistor according to claim 1, wherein the ferroelectric layer extends along both side surfaces and a bottom surface of the gate electrode.

3. The oxide semiconductor transistor of claim 2, wherein the ferroelectric layer further extends onto a top surface of the gate electrode.

4. The oxide semiconductor transistor according to claim 3, wherein the ferroelectric layer completely covers the top surface of the gate electrode.

5. The oxide semiconductor transistor according to claim 1, wherein the ferroelectric layer extends along the oxide semiconductor layer outside the trench and exposes the source region and the drain region.

6. The oxide semiconductor transistor according to claim 1, further comprising a dielectric layer between the oxide semiconductor layer and the ferroelectric layer, wherein the ferroelectric layer and the dielectric layer have negative capacitance characteristics.

7. The oxide semiconductor transistor of claim 6, wherein the ferroelectric layer and the dielectric layer extend along the oxide semiconductor layer outside the trench and expose the source region and the drain region.

8. The oxide semiconductor transistor according to claim 1, further comprising a first diffusion barrier between the oxide semiconductor layer and the insulating substrate,

wherein the first diffusion barrier prevents hydrogen from penetrating into the oxide semiconductor layer.

9. The oxide semiconductor transistor of claim 8, wherein the first diffusion barrier extends between the insulating substrate and the source region and between the insulating substrate and the drain region.

10. The oxide semiconductor transistor according to claim 1, further comprising a second diffusion barrier between the oxide semiconductor layer and the ferroelectric layer,

wherein the second diffusion barrier prevents hydrogen from penetrating into the oxide semiconductor layer.

11. The oxide semiconductor transistor of claim 10, wherein the second diffusion barrier extends along the oxide semiconductor layer outside the trench and exposes the source region and the drain region.

12. The oxide semiconductor transistor according to claim 1, further comprising:

an additional gate electrode on a side of the oxide semiconductor layer, the side being opposite to the gate electrode; and

an additional gate insulating layer between the additional gate electrode and the oxide semiconductor layer.

13. The oxide semiconductor transistor of claim 12, wherein the additional gate electrode and the additional gate insulating layer are along a bottom surface of the gate electrode.

14. The oxide semiconductor transistor according to claim 13, wherein the additional gate electrode and the additional gate insulating layer extend along both side surfaces of the gate electrode.

15. The oxide semiconductor transistor according to claim 14, wherein the additional gate electrode and the additional gate insulating layer separate the oxide semiconductor layer from the surface of the insulating substrate exposed through the trench.

16. The oxide semiconductor transistor according to claim 1, further comprising:

a source electrode on the source region; and

a drain electrode on the drain region,

wherein the source electrode and the drain electrode are electrically connected to the source region and the drain region, respectively.

17. The oxide semiconductor transistor according to claim 16, wherein

The ferroelectric layer extends along the oxide semiconductor layer outside the trench, an

The source electrode and the drain electrode penetrate the ferroelectric layer and are in direct contact with the source region and the drain region, respectively.

18. An oxide semiconductor transistor comprising:

an insulating substrate;

a gate electrode on the insulating substrate;

an oxide semiconductor layer on the insulating substrate to cover the gate electrode; and

a gate insulating layer between the gate electrode and the oxide semiconductor layer,

wherein the oxide semiconductor layer includes a source region and a drain region spaced apart from each other, and the gate electrode is between the source region and the drain region.

19. The oxide semiconductor transistor according to claim 18, wherein the oxide semiconductor layer and the gate insulating layer extend along both side surfaces and a top surface of the gate electrode.

20. The oxide semiconductor transistor according to claim 19, wherein the oxide semiconductor layer is separated from the insulating substrate by the gate insulating layer.

21. The oxide semiconductor transistor according to claim 20, wherein the gate insulating layer overlaps the source region and the drain region in a direction perpendicular to a top surface of the insulating substrate.

22. The oxide semiconductor transistor according to claim 19, further comprising a dielectric layer between the oxide semiconductor layer and the gate insulating layer,

wherein the gate insulating layer comprises a ferroelectric material.

23. The oxide semiconductor transistor according to claim 19, further comprising a first diffusion barrier between the oxide semiconductor layer and the gate insulating layer,

wherein the first diffusion barrier prevents hydrogen from penetrating into the oxide semiconductor layer.

24. The oxide semiconductor transistor according to claim 19, further comprising a second diffusion barrier over the oxide semiconductor layer,

wherein the second diffusion barrier prevents hydrogen from penetrating into the oxide semiconductor layer.

25. The oxide semiconductor transistor of claim 24, wherein the second diffusion barrier extends along the oxide semiconductor layer and exposes the source region and the drain region.

26. The oxide semiconductor transistor according to claim 19, wherein

The gate insulating layer includes a pair of end surfaces opposite to each other in an extending direction of the gate insulating layer, an

The pair of end surfaces of the gate insulating layer is in direct contact with a top surface of the insulating substrate.

27. The oxide semiconductor transistor of claim 26, wherein the source region and the drain region are in direct contact with the top surface of the insulating substrate.

28. The oxide semiconductor transistor according to claim 18, further comprising:

a source electrode on the source region; and

a drain electrode on the drain region,

wherein the source electrode and the drain electrode are electrically connected to the source region and the drain region, respectively.

29. The oxide semiconductor transistor according to claim 28, further comprising an upper insulating layer over the oxide semiconductor layer,

wherein the source electrode and the drain electrode penetrate the upper insulating layer and are electrically connected to the source region and the drain region, respectively.

30. The oxide semiconductor transistor according to claim 18, further comprising:

an additional gate electrode on a side of the oxide semiconductor layer, the side being opposite to the gate electrode; and

an additional gate insulating layer between the additional gate electrode and the oxide semiconductor layer.

31. The oxide semiconductor transistor of claim 30, wherein the additional gate electrode and the additional gate insulating layer are along a top surface of the gate electrode.

32. The oxide semiconductor transistor of claim 30, wherein the additional gate electrode and the additional gate insulating layer are along both side surfaces and a top surface of the gate electrode.

33. The oxide semiconductor transistor of claim 32, wherein the additional gate insulating layer extends along the oxide semiconductor layer and exposes the source region and the drain region.

Technical Field

The present disclosure relates to an oxide semiconductor transistor.

Background

Oxide semiconductor devices have been studied for many years as transparent semiconductor materials having a wide band gap in the range of 3.0eV or more. Oxide semiconductor devices have been mass-produced as driving devices for large-area Organic Light Emitting Diodes (OLED) TVs.

As the integration degree of semiconductor devices increases, smaller semiconductor devices are required. In the case of an oxide semiconductor transistor, the reduction in size may result in a reduction in channel length. This may reduce the charge mobility of the oxide semiconductor transistor and cause a short channel effect that causes a threshold voltage shift. In the case of ferroelectric field effect transistors (fefets), the number of domains in the ferroelectric decreases due to the reduction in gate size, and thus the number of bits that can be stored decreases.

Disclosure of Invention

An oxide semiconductor transistor having improved electrical characteristics is provided.

However, the present disclosure is not limited thereto.

Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the presented example embodiments of the disclosure.

According to an aspect of example embodiments, an oxide semiconductor transistor includes: an insulating substrate including a trench; a gate electrode in the trench; an oxide semiconductor layer on a surface of the insulating substrate, the surface being exposed through the trench; and a ferroelectric layer between the gate electrode and the oxide semiconductor layer, wherein the oxide semiconductor layer includes a source region and a drain region on the insulating substrate outside the trench and spaced apart from each other with the gate electrode therebetween.

The ferroelectric layer may extend along both side surfaces and the bottom surface of the gate electrode.

The ferroelectric layer may further extend onto a top surface of the gate electrode.

The ferroelectric layer may completely cover the top surface of the gate electrode.

The ferroelectric layer may extend along the oxide semiconductor layer outside the trench and expose the source and drain regions.

The oxide semiconductor transistor may further include a dielectric layer between the oxide semiconductor layer and the ferroelectric layer, wherein the ferroelectric layer and the dielectric layer may have negative capacitance characteristics.

The ferroelectric layer and the dielectric layer may extend along the oxide semiconductor layer outside the trench and expose the source and drain regions.

The oxide semiconductor transistor may further include a first diffusion barrier between the oxide semiconductor layer and the insulating substrate, wherein the first diffusion barrier may prevent, for example, hydrogen from penetrating into the oxide semiconductor layer.

The first diffusion barrier may extend between the insulating substrate and the source region and between the insulating substrate and the drain region.

The oxide semiconductor transistor may further include a second diffusion barrier between the oxide semiconductor layer and the ferroelectric layer, wherein the second diffusion barrier may prevent, for example, hydrogen from penetrating into the oxide semiconductor layer.

The second diffusion barrier may extend along the oxide semiconductor layer outside the trench and expose the source and drain regions.

The oxide semiconductor transistor may further include: an additional gate electrode on a side of the oxide semiconductor layer, the side being opposite to the gate electrode; and an additional gate insulating layer between the additional gate electrode and the oxide semiconductor layer.

The additional gate electrode and the additional gate insulating layer may be along a bottom surface of the gate electrode.

The additional gate electrode and the additional gate insulating layer may extend along both side surfaces of the gate electrode.

The additional gate electrode and the additional gate insulating layer may separate the oxide semiconductor layer from a surface of the insulating substrate exposed through the trench.

The oxide semiconductor transistor may further include: a source electrode on the source region; and a drain electrode on the drain region, wherein the source electrode and the drain electrode may be electrically connected to the source region and the drain region, respectively.

The ferroelectric layer may extend along the oxide semiconductor layer outside the trench, and the source and drain electrodes may penetrate the ferroelectric layer and may be in direct contact with the source and drain regions, respectively.

According to an aspect of example embodiments, an oxide semiconductor transistor includes: an insulating substrate; a gate electrode on the insulating substrate; an oxide semiconductor layer on the insulating substrate to cover the gate electrode; and a gate insulating layer between the gate electrode and the oxide semiconductor layer, wherein the oxide semiconductor layer includes a source region and a drain region spaced apart from each other, and the gate electrode is between the source region and the drain region.

The oxide semiconductor layer and the gate insulating layer may extend along both side surfaces and a top surface of the gate electrode.

The oxide semiconductor layer may be separated from the insulating substrate by a gate insulating layer.

The gate insulating layer may overlap the source and drain regions in a direction perpendicular to a top surface of the insulating substrate.

The oxide semiconductor transistor may further include a dielectric layer between the oxide semiconductor layer and the gate insulating layer, wherein the gate insulating layer may include a ferroelectric material.

The oxide semiconductor transistor may further include a first diffusion barrier between the oxide semiconductor layer and the gate insulating layer, wherein the first diffusion barrier may prevent, for example, hydrogen from penetrating into the oxide semiconductor layer.

The oxide semiconductor transistor may further include a second diffusion barrier on the oxide semiconductor layer, wherein the second diffusion barrier may prevent, for example, hydrogen from penetrating into the oxide semiconductor layer.

The second diffusion barrier may extend along the oxide semiconductor layer and expose the source and drain regions.

The gate insulating layer may include a pair of end surfaces opposite to each other in an extending direction of the gate insulating layer, and the pair of end surfaces of the gate insulating layer may be in direct contact with the top surface of the insulating substrate.

The source and drain regions may be in direct contact with the top surface of the insulating substrate.

The oxide semiconductor transistor may further include an upper insulating layer on the oxide semiconductor layer, wherein the source and drain electrodes may penetrate the upper insulating layer and may be electrically connected to the source and drain regions, respectively.

The additional gate electrode and the additional gate insulating layer may be along a top surface of the gate electrode.

The additional gate electrode and the additional gate insulating layer may be along both side surfaces and a top surface of the gate electrode.

The additional gate insulating layer may extend along the oxide semiconductor layer and expose the source and drain regions.

Drawings

The above and other aspects, features and advantages of certain exemplary embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a perspective view of an oxide semiconductor transistor according to an example embodiment;

FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1;

fig. 3 is a cross-sectional view illustrating an oxide semiconductor transistor according to an example embodiment, the cross-sectional view corresponding to a line a-a' of fig. 1;

fig. 4 is a cross-sectional view illustrating an oxide semiconductor transistor according to an example embodiment, the cross-sectional view corresponding to a line a-a' of fig. 1;

fig. 5 is a cross-sectional view illustrating an oxide semiconductor transistor according to an example embodiment, the cross-sectional view corresponding to a line a-a' of fig. 1;

fig. 6 is a cross-sectional view illustrating an oxide semiconductor transistor according to an example embodiment, the cross-sectional view corresponding to a line a-a' of fig. 1;

fig. 7 is a perspective view of an oxide semiconductor transistor according to an example embodiment;

FIG. 8 is a cross-sectional view taken along line B-B' of FIG. 7;

fig. 9 is a cross-sectional view illustrating an oxide semiconductor transistor according to an example embodiment, the cross-sectional view corresponding to line B-B' of fig. 7;

fig. 10 is a cross-sectional view illustrating an oxide semiconductor transistor according to an example embodiment, the cross-sectional view corresponding to line B-B' of fig. 7;

fig. 11 is a cross-sectional view illustrating an oxide semiconductor transistor according to an example embodiment, the cross-sectional view corresponding to line B-B' of fig. 7;

fig. 12 is a cross-sectional view showing an oxide semiconductor transistor according to an example embodiment, the cross-sectional view corresponding to line B-B' of fig. 7;

fig. 13 is a perspective view of an oxide semiconductor transistor according to an example embodiment;

FIG. 14 is a cross-sectional view taken along line C-C' of FIG. 13;

fig. 15 is a cross-sectional view illustrating an oxide semiconductor transistor according to an example embodiment, the cross-sectional view corresponding to line C-C' of fig. 13;

fig. 16 is a cross-sectional view showing an oxide semiconductor transistor according to an example embodiment, the cross-sectional view corresponding to line C-C' of fig. 13;

fig. 17 is a cross-sectional view illustrating an oxide semiconductor transistor according to an example embodiment, the cross-sectional view corresponding to line C-C' of fig. 13; and

fig. 18 is a sectional view illustrating an oxide semiconductor transistor according to an example embodiment, the sectional view corresponding to line C-C' of fig. 13.

Detailed Description

Reference will now be made in detail to example embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. In this regard, the present example embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the exemplary embodiments are described below to explain aspects by referring to the figures only. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of … …," when following a column of elements, modify the entire column of elements without modifying individual elements in the column.

Hereinafter, example embodiments will be described with reference to the accompanying drawings. In the drawings, like reference numerals refer to like elements, and the sizes of the elements may be exaggerated for clarity and convenience of illustration. The example embodiments described herein are for illustrative purposes only and various modifications may be made therein.

In the following description, when an element is referred to as being "over" or "on" another element, it may be directly on the other element while being in contact with the other element or may be over the other element without being in contact with the other element.

Unless otherwise mentioned, terms in the singular may include the plural. It will be further understood that the terms "comprises" and/or "comprising … …," as used herein, specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

Fig. 1 is a perspective view of an oxide semiconductor transistor 1 according to an example embodiment. Fig. 2 is a sectional view taken along line a-a' of fig. 1.

Referring to fig. 1 and 2, the oxide semiconductor transistor 1 may be provided as follows. The oxide semiconductor transistor 1 may include an insulating substrate 100, an oxide semiconductor layer 200, a gate insulating layer 300, a gate electrode 400, a source electrode 510, and/or a drain electrode 520. The insulating substrate 100 may include an electrically insulating material. For example, the insulating substrate 100 may include silicon oxide, silicon nitride, or silicon oxynitride.

The insulating substrate 100 may include a trench 102. The trench 102 may be a region formed by recessing the top surface 100u of the insulating substrate 100. The trench 102 may have a width in a first direction DR1 parallel to the top surface 100u of the insulating substrate 100. The trench 102 may extend in a second direction DR2 crossing the first direction DR1 and parallel to the top surface 100u of the insulating substrate 100.

The oxide semiconductor layer 200 may be provided on the insulating substrate 100. The oxide semiconductor layer 200 may be provided on the surface of the insulating substrate 100 exposed through the trench 102 and on the top surface 100u of the insulating substrate 100. The oxide semiconductor layer 200 may extend along the surface of the insulating substrate 100 exposed through the trench 102 and the top surface 100u of the insulating substrate 100. For example, the oxide semiconductor layer 200 may be conformally extended. The thickness of the oxide semiconductor layer 200 may be determined as needed. The oxide semiconductor layer 200 may include an oxide semiconductor. For example, the oxide semiconductor layer 200 may include an oxide of a material selected from group 12, 13, and 14 metal elements, such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), hafnium (Hf), or a combination thereof. For example, the oxide semiconductor layer 200 may include a material based on a Zn oxide, such as a Zn oxide, an In-Zn oxide, or a Ga-In-Zn oxide. For example, the oxide semiconductor layer 200 may include an In-Ga-Zn-o (igzo) semiconductor In which metals such as indium (In) and gallium (Ga) are contained In ZnO. The oxide semiconductor layer 200 may provide a region in which a channel of the oxide semiconductor transistor 1 is formed.

The oxide semiconductor layer 200 may include a source region 210 and a drain region 220. The source region 210 and the drain region 220 may be spaced apart from each other in the first direction DR1 with the trench 102 therebetween. The source region 210 and the drain region 220 may be formed by implanting n-type or p-type dopants into the oxide semiconductor layer 200 provided on the top surface 100u of the insulating substrate 100. The source region 210 and the drain region 220 may have a conductivity type. For example, the source region 210 and the drain region 220 may have n-type conductivity. The source region 210 and the drain region 220 may be in direct contact with the top surface 100u of the insulating substrate 100.

A gate electrode 400 may be provided in the trench 102. The gate electrode 400 may extend in a third direction DR3 perpendicular to the top surface 100u of the insulating substrate 100. The gate electrode 400 may protrude outside the trench 102. The top surface 404 of the gate electrode 400 may be higher than the top surface 100u of the insulating substrate 100. The gate electrode 400 may extend in the second direction DR 2. The first side surface 401, the second side surface 402, and the bottom surface 403 of the gate electrode 400 may face the oxide semiconductor layer 200. The gate electrode 400 may be electrically disconnected from the oxide semiconductor layer 200. The gate electrode 400 may be separated from the oxide semiconductor layer 200. The gate electrode 400 may include a conductive material. For example, the gate electrode 400 may include a metal or a metal compound.

In the trench 102, the gate insulating layer 300 may be between the gate electrode 400 and the oxide semiconductor layer 200. Outside the trench 102, a gate insulating layer 300 may be provided on the oxide semiconductor layer 200 and the gate electrode 400. The gate insulating layer 300 may surround the top surface 404, the first side surface 401, the second side surface 402, and the bottom surface 403 of the gate electrode 400. The gate insulating layer 300 may extend along the top surface of the oxide semiconductor layer 200. In the following description, the top surface of the oxide semiconductor layer 200 may refer to a surface of the oxide semiconductor layer 200 opposite to a surface of the oxide semiconductor layer 200 facing the insulating substrate 100. In the following description, a surface of the oxide semiconductor layer 200 facing the insulating substrate 100 may be referred to as a bottom surface of the oxide semiconductor layer 200. The gate insulating layer 300 may expose the source region 210 and the drain region 220. In other words, the gate insulating layer 300 may include openings through which the source region 210 and the drain region 220 are exposed, respectively. The gate insulating layer 300 may separate the gate electrode 400 and the oxide semiconductor layer 200 from each other. The gate insulating layer 300 may electrically disconnect the gate electrode 400 and the oxide semiconductor layer 200 from each other. The thickness of the gate insulating layer 300 may be determined as needed.

In an example, the gate insulating layer 300 may include a ferroelectric material. Ferroelectric materials refer to non-conductors or dielectrics that exhibit spontaneous polarization and are distinguished from multiferroic materials that exhibit two or more ferroic properties, such as ferroelectricity, ferroelasticity, ferromagnetism, antiferromagnetism, and the like. For example, the ferroelectric material may include a material selected from the group consisting of an oxide ferroelectric material, a polymer ferroelectric material, such as (BMF) BaMgF₄At least one of the group consisting of fluoride ferroelectric material and ferroelectric material semiconductor. Examples of the oxide ferroelectric material may include: perovskite ferroelectrics, such as (PZT) PbZr_xTi_1-xO₃、BaTiO₃And PbTiO₃(ii) a Pseudo-ilmenite (pseudo-ilmenite) ferroelectrics, such as LiNbO₃And LiTaO₃(ii) a Tungsten Bronze (TB) ferroelectrics, such as PbNb₃O₆And Ba₂NaNb₅O₁₅(ii) a Bismuth layer structured ferroelectrics, such as SBT (SrBi)₂Ta₂O₉)、BLT((Bi,La)₄Ti₃O₁₂) And Bi₄Ti₃O₁₂(ii) a Pyrochlore (pyrochlore) ferroelectrics, such as La₂Ti₂O₇(ii) a Solid solutions of these ferroelectrics; RMnO including rare earth elements (R) such as yttrium (Y), erbium (Er), holmium (Ho), thulium (Tm), ytterbium (Yb) and lutetium (Lu)₃；PGO(Pb₅Ge₃O₁₁). For example, the polymeric ferroelectric material may include at least one selected from the group consisting of polyvinylidene fluoride (PVDF), PVDF-containing polymers, PVDF-containing copolymers, PVDF-containing terpolymers, cyano-based polymers, and polymers and/or copolymers thereof. Examples of the ferroelectric material semiconductor may include group 2-6 compounds such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe, and CdFeSe. For example, the ferroelectric material may include HfO, Hf_xZr_1-xO, ZrO or a ferroelectric having a fluorite structure and doped with silicon (Si), aluminum (Al), zirconium (Zr), yttrium (Y), lanthanum (La), gadolinium (Gd), strontium (Sr), or hafnium (Hf).

In an example, the gate insulation layer 300 may include a high-k dielectric material. A high-k dielectric material may refer to a material having a dielectric constant greater than that of silicon oxide. For example, the gate insulating layer 300 may include ZrO₂、HfO₂、La₂O₃、Ta₂O₅BaO or TiO₂。

In an example, the gate insulation layer 300 may include a dielectric material that is not a high-k dielectric material. For example, the gate insulating layer 300 may include SiO₂SiN, AlO, or a combination thereof.

A source electrode 510 and a drain electrode 520 may be provided on the source region 210 and the drain region 220, respectively. The source electrode 510 and the drain electrode 520 may be electrically connected to the source region 210 and the drain region 220, respectively. The source electrode 510 and the drain electrode 520 may penetrate the gate insulating layer 300 and may be in direct contact with the source region 210 and the drain region 220, respectively. The source electrode 510 and the drain electrode 520 may include a conductive material. For example, the source electrode 510 and the drain electrode 520 may include a metal or a metal compound.

The channel length of the oxide semiconductor transistor 1 may be the same as or substantially the same as the length of the oxide semiconductor layer 200 between the source region 210 and the drain region 220. When the gate electrode 400 is disposed on the top surface 100u of the insulating substrate 100 without the trench 102, the channel length may be the same or substantially the same as the distance between the source region 210 and the drain region 220 in the first direction DR 1. Since the oxide semiconductor layer 200 of the present example embodiment extends along the surface of the insulating substrate 100 exposed through the trench 102, the channel length may be greater than the distance between the source region 210 and the drain region 220 in the first direction DR 1. The oxide semiconductor transistor 1 of the present exemplary embodiment can have a large channel length. Accordingly, the oxide semiconductor transistor 1 can have improved electrical characteristics.

Fig. 3 is a cross-sectional view illustrating the oxide semiconductor transistor 2 according to an example embodiment, the cross-sectional view corresponding to a line a-a' of fig. 1. For clarity of illustration, structures that are the same or substantially the same as those described with reference to fig. 1 and 2 may not be described herein.

Referring to fig. 3, the oxide semiconductor transistor 2 may be provided as follows. The oxide semiconductor transistor 2 may include an insulating substrate 100, an oxide semiconductor layer 200, a dielectric layer 600, a gate insulating layer 300, a gate electrode 400, a source electrode 510, and/or a drain electrode 520. The insulating substrate 100, the oxide semiconductor layer 200, the gate electrode 400, the source electrode 510, and the drain electrode 520 may be the same or substantially the same as the insulating substrate 100, the oxide semiconductor layer 200, the gate electrode 400, the source electrode 510, and the drain electrode 520 described with reference to fig. 1 and 2.

Unlike in the description given with reference to fig. 1 and 2, the gate insulating layer 300 may be a ferroelectric layer. In other words, the gate insulating layer 300 may not include a dielectric material or a high-k dielectric material.

The dielectric layer 600 may be provided between the oxide semiconductor layer 200 and the gate insulating layer 300. The dielectric layer 600 may extend along the top surface of the oxide semiconductor layer 200. Dielectric layer 600 may expose source region 210 and drain region 220. The source electrode 510 and the drain electrode 520 may penetrate the dielectric layer 600, andand may be in direct contact with the source region 210 and the drain region 220, respectively. The thickness of the dielectric layer 600 may be determined as desired. Dielectric layer 600 may include a material for obtaining a desired capacitance. As a material included in the dielectric layer 600, a dielectric having a high dielectric constant may be used to cope with high integration of the integrated circuit device. The dielectric layer 600 may include a material having a high dielectric constant. A high dielectric constant may refer to a dielectric constant that is greater than the dielectric constant of silicon oxide. In example embodiments, the dielectric layer 600 may include a metal oxide including at least one metal selected from the group consisting of calcium (Ca), strontium (Sr), barium (Ba), scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tantalum (Ta), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd), dysprosium (Dy), ytterbium (Yb), and lutetium (Lu). For example, dielectric layer 600 may include HfO₂、ZrO₂、CeO₂、La₂O₃、Ta₂O₃Or TiO₂。

The gate insulating layer 300 (i.e., the ferroelectric layer) may have a negative capacitance characteristic due to the dielectric layer 600. According to the present example embodiment, the oxide semiconductor transistor 2 may have a large channel length and may use a negative capacitance characteristic. Accordingly, the oxide semiconductor transistor 2 can have improved electrical characteristics.

Fig. 4 is a cross-sectional view showing the oxide semiconductor transistor 3 according to an example embodiment, the cross-sectional view corresponding to the line a-a' of fig. 1. For clarity of illustration, structures that are the same or substantially the same as those described with reference to fig. 1 and 2 may not be described herein.

Referring to fig. 4, the oxide semiconductor transistor 3 may be provided as follows. The oxide semiconductor transistor 3 may include an insulating substrate 100, a lower diffusion barrier 710, an oxide semiconductor layer 200, an upper diffusion barrier 720, a gate insulating layer 300, a gate electrode 400, and a source electrode 510 and/or a drain electrode 520. The insulating substrate 100, the oxide semiconductor layer 200, the gate electrode 400, the source electrode 510, and the drain electrode 520 may be the same or substantially the same as the insulating substrate 100, the oxide semiconductor layer 200, the gate electrode 400, the source electrode 510, and the drain electrode 520 described with reference to fig. 1 and 2.

The lower diffusion barrier 710 may be provided between the insulating substrate 100 and the oxide semiconductor layer 200. The lower diffusion barrier 710 may extend along the bottom surface of the oxide semiconductor layer 200. The lower diffusion barrier 710 may extend between the source region 210 and the insulating substrate 100. The lower diffusion barrier 710 may separate the source region 210 and the insulating substrate 100 from each other. The lower diffusion barrier 710 may be in direct contact with the source region 210. The lower diffusion barrier 710 may extend between the drain region 220 and the insulating substrate 100. The lower diffusion barrier 710 may separate the drain region 220 and the insulating substrate 100 from each other. The lower diffusion barrier 710 may be in direct contact with the drain region 220. The lower diffusion barrier 710 may prevent, for example, hydrogen from penetrating into a lower portion of the oxide semiconductor layer 200. For example, the lower diffusion barrier 710 may include Al₂O₃SiN, SiON or combinations thereof. The thickness of the lower diffusion barrier 710 may be determined as desired.

The upper diffusion barrier 720 may be provided between the oxide semiconductor layer 200 and the gate insulating layer 300. The upper diffusion barrier 720 may extend along the top surface of the oxide semiconductor layer 200. The upper diffusion barrier 720 may expose the source region 210 and the drain region 220. The source electrode 510 and the drain electrode 520 may penetrate the upper diffusion barrier 720 and may be in direct contact with the source region 210 and the drain region 220, respectively. The upper diffusion barrier 720 may prevent, for example, hydrogen from penetrating into an upper portion of the oxide semiconductor layer 200. For example, the upper diffusion barrier 720 may include Al₂O₃SiN, SiON or combinations thereof. The thickness of the upper diffusion barrier 720 may be determined as desired. In other examples, only one of the lower diffusion barrier 710 and the upper diffusion barrier 720 may be provided. In the present example embodiment, the lower diffusion barrier 710 and the upper diffusion barrier 720 may prevent, for example, hydrogen from penetrating into the oxide semiconductor layer 200, and the oxide semiconductor transistor 3 may have a large channel length. Therefore, the oxide semiconductor transistor 3 can have improved electrical characteristics.

Fig. 5 is a cross-sectional view illustrating the oxide semiconductor transistor 4 according to an example embodiment, the cross-sectional view corresponding to a line a-a' of fig. 1. For clarity of illustration, structures that are the same or substantially the same as those described with reference to fig. 1 and 2 may not be described herein.

Referring to fig. 5, the oxide semiconductor transistor 4 may be provided as follows. The oxide semiconductor transistor 4 may include an insulating substrate 100, an oxide semiconductor layer 200, a gate insulating layer 300, a gate electrode 400, a source electrode 510, a drain electrode 520, a first additional gate electrode 410, and/or a first additional gate insulating layer 310.

The insulating substrate 100, the oxide semiconductor layer 200, the gate insulating layer 300, the gate electrode 400, the source electrode 510, and the drain electrode 520 may be the same or substantially the same as the insulating substrate 100, the oxide semiconductor layer 200, the gate insulating layer 300, the gate electrode 400, the source electrode 510, and the drain electrode 520 described with reference to fig. 1 and 2.

The first additional gate electrode 410 may be provided on a surface of the insulating substrate 100 exposed through the trench 102. The first additional gate electrode 410 may extend along the surface of the insulating substrate 100 exposed through the trench 102. End surfaces of the first additional gate electrodes 410 opposite to each other in the extending direction of the first additional gate electrodes 410 may be coplanar with the top surface 100u of the insulating substrate 100. End surfaces of the first additional gate electrodes 410 opposite to each other in the extending direction of the first additional gate electrodes 410 may be substantially located at the same level as the top surface 100u of the insulating substrate 100. The first additional gate electrode 410 may be electrically disconnected from the oxide semiconductor layer 200. The first additional gate electrode 410 may be spaced apart from the oxide semiconductor layer 200. The first additional gate electrode 410 may include a conductive material. For example, the first additional gate electrode 410 may include a metal or a metal compound.

The first additional gate insulating layer 310 may be provided between the first additional gate electrode 410 and the oxide semiconductor layer 200 and between the insulating substrate 100 and the oxide semiconductor layer 200. The first additional gate insulating layer 310 may extend along the bottom surface of the oxide semiconductor layer 200. The first additional gate insulating layer 310 may electrically disconnect the first additional gate electrode 410 and the oxide semiconductor layer 200 from each other. The first additional gate insulating layer 310 may separate the first additional gate electrode 410 and the oxide semiconductor layer 200 from each other. The first additional gate insulating layer 310 may extend between the source region 210 and the insulating substrate 100 to separate the source region 210 and the insulating substrate 100 from each other. The first additional gate insulating layer 310 may extend between the drain region 220 and the insulating substrate 100 to separate the drain region 220 and the insulating substrate 100 from each other. The thickness of the first additional gate insulating layer 310 may be determined as needed. The first additional gate insulation layer 310 may include a ferroelectric material, a dielectric material, or a high-k dielectric material. The ferroelectric material, dielectric material, and high-k dielectric material may be the same or substantially the same as those described with reference to fig. 1 and 2. In an example, the first additional gate insulating layer 310 may have the same or substantially the same thickness and material as the gate insulating layer 300.

The gate electrode 400 and the first additional gate electrode 410 may be gate electrodes of a double gate structure. The oxide semiconductor transistor 4 of the present example embodiment may have a double gate structure and a large channel length. Accordingly, the oxide semiconductor transistor 4 can have improved electrical characteristics.

Fig. 6 is a cross-sectional view illustrating the oxide semiconductor transistor 5 according to an example embodiment, the cross-sectional view corresponding to a line a-a' of fig. 1. For clarity of illustration, structures that are the same or substantially the same as those described with reference to fig. 1 and 2 may not be described herein.

Referring to fig. 6, the oxide semiconductor transistor 5 may be provided as follows. The oxide semiconductor transistor 5 may include an insulating substrate 100, an oxide semiconductor layer 200, a gate insulating layer 300, a gate electrode 400, a source electrode 510, a drain electrode 520, a second additional gate insulating layer 320, and/or a second additional gate electrode 420.

Unlike in the description given with reference to fig. 1 and 2, the lower portion of the trench 102 may not be filled with the oxide semiconductor layer 200, the gate insulating layer 300, and the gate electrode 400. A second additional gate electrode 420 and a second additional gate insulating layer 320 may be provided in a lower portion of the trench 102. The trench 102 may be completely filled with the second additional gate electrode 420, the second additional gate insulating layer 320, the oxide semiconductor layer 200, the gate insulating layer 300, and the gate electrode 400.

The second additional gate electrode 420 may be provided at a side of the oxide semiconductor layer 200 opposite to the gate electrode 400. The second additional gate electrode 420 and the gate electrode 400 may be spaced apart from each other in the third direction DR 3. The second additional gate electrode 420 may include a conductive material. For example, the second additional gate electrode 420 may include a metal or a metal compound.

A second additional gate insulating layer 320 may be provided between the second additional gate electrode 420 and the oxide semiconductor layer 200. The second additional gate insulating layer 320 may be disposed on the opposite side of the oxide semiconductor layer 200 from the gate insulating layer 300. The second additional gate insulating layer 320 may electrically isolate the second additional gate electrode 420 and the oxide semiconductor layer 200 from each other. The second additional gate insulating layer 320 may separate the second additional gate electrode 420 and the oxide semiconductor layer 200 from each other. The second additional gate insulating layer 320 may include a ferroelectric material, a dielectric material, or a high-k dielectric material. The ferroelectric material, dielectric material, and high-k dielectric material may be the same or substantially the same as those described with reference to fig. 1 and 2. In an example, the second additional gate insulating layer 320 may have the same or substantially the same thickness and material as the gate insulating layer 300.

The gate electrode 400 and the second additional gate electrode 420 may be gate electrodes of a double gate structure. The oxide semiconductor transistor 5 of the present example embodiment may have a double gate structure and a large channel length. Accordingly, the oxide semiconductor transistor 5 can have improved electrical characteristics.

Fig. 7 is a perspective view of the oxide semiconductor transistor 6 according to an example embodiment. Fig. 8 is a sectional view taken along line B-B' of fig. 7. For clarity of illustration, structures that are the same or substantially the same as those described with reference to fig. 1 and 2 may not be described herein.

Referring to fig. 7 and 8, the oxide semiconductor transistor 6 may be provided as follows. The oxide semiconductor transistor 6 may include an insulating substrate 1100, a gate electrode 1200, a gate insulating layer 1300, an oxide semiconductor layer 1400, a source electrode 1610, and/or a drain electrode 1620. The insulating substrate 1100 may include an electrically insulating material. For example, the insulating substrate 1100 may include silicon oxide, silicon nitride, or silicon oxynitride.

The gate electrode 1200 may be provided on the insulating substrate 1100. The first side surface 1201, the second side surface 1202, and the top surface 1204 of the gate electrode 1200 may be exposed over the insulating substrate 1100. The first side surface 1201 and the second side surface 1202 of the gate electrode 1200 may be opposite to each other in the first direction DR 1. In an example, the bottom surface 1203 of the gate electrode 1200 may be in direct contact with the top surface 1100u of the insulating substrate 1100. The gate electrode 1200 may include a conductive material. For example, the gate electrode 1200 may include a metal or a metal compound.

A gate insulating layer 1300 may be provided on the insulating substrate 1100 and the gate electrode 1200. The gate insulating layer 1300 may cover the insulating substrate 1100 and the gate electrode 1200. The gate insulating layer 1300 may extend along the top surface 1100u of the insulating substrate 1100 and the first side surface 1201, the second side surface 1202, and the top surface 1204 of the gate electrode 1200. For example, the gate insulating layer 1300 may conformally extend along the top surface 1100u of the insulating substrate 1100 and the first side surface 1201, the second side surface 1202, and the top surface 1204 of the gate electrode 1200. The thickness of the gate insulating layer 1300 may be determined as needed. The gate insulation layer 1300 may include a ferroelectric material, a dielectric material, or a high-k dielectric material. The ferroelectric material, dielectric material, and high-k dielectric material may be the same or substantially the same as those described with reference to fig. 1 and 2.

The oxide semiconductor layer 1400 may be provided on the gate insulating layer 1300. The oxide semiconductor layer 1400 may extend along the gate insulating layer 1300. For example, the oxide semiconductor layer 1400 may conformally extend along the top surface of the gate insulating layer 1300. A top surface of the gate insulating layer 1300 may be opposite to a bottom surface of the gate insulating layer 1300 facing the insulating substrate 1100. The oxide semiconductor layer 1400 may be separated from the gate electrode 1200 and the insulating substrate 1100 due to the gate insulating layer 1300. The oxide semiconductor layer 1400 may be electrically disconnected from the gate electrode 1200 due to the gate insulating layer 1300. The thickness of the oxide semiconductor layer 1400 may be determined as needed. The oxide semiconductor layer 1400 may include an oxide semiconductor. The oxide semiconductor may be the same or substantially the same as described with reference to fig. 1 and 2.

The oxide semiconductor layer 1400 may include a source region 1410 and a drain region 1420. The source region 1410 and the drain region 1420 may be spaced apart from each other in the first direction DR1 with the gate electrode 1200 therebetween. The source and drain regions 1410 and 1420 may be formed by implanting n-type or p-type dopants into the oxide semiconductor layer 1400 provided over the top surface 1100u of the insulating substrate 1100. The source region 1410 and the drain region 1420 may have a conductivity type. For example, the source region 1410 and the drain region 1420 may have n-type conductivity. The source region 1410 and the drain region 1420 may be in direct contact with the top surface of the gate insulating layer 1300.

The upper insulating layer 1500 may be provided on the oxide semiconductor layer 1400. The upper insulating layer 1500 may cover the oxide semiconductor layer 1400. The upper insulating layer 1500 may include an electrically insulating material. For example, the upper insulating layer 1500 may include silicon oxide, silicon nitride, or silicon oxynitride.

A source electrode 1610 and a drain electrode 1620 may be provided on the source region 1410 and the drain region 1420, respectively. The source electrode 1610 and the drain electrode 1620 may be electrically connected to the source region 1410 and the drain region 1420, respectively. The source and drain electrodes 1610 and 1620 may penetrate the upper insulating layer 1500, and may be in direct contact with the source and drain regions 1410 and 1420, respectively. The source electrode 1610 and the drain electrode 1620 may include a conductive material. For example, the source electrode 1610 and the drain electrode 1620 may include a metal or a metal compound.

The channel length of the oxide semiconductor transistor 6 may be the same as or substantially the same as the length of the oxide semiconductor layer 1400 between the source region 1410 and the drain region 1420. When the oxide semiconductor layer 1400 is provided between the gate electrode 1200 and the insulating substrate 1100, the channel length of the oxide semiconductor transistor 6 depends on the distance between the source region 1410 and the drain region 1420 in the first direction DR 1.

Since the oxide semiconductor layer 1400 of the present example embodiment extends along the first side surface 1201, the second side surface 1202, and the top surface 1204 of the gate electrode 1200, the channel length may be greater than the distance between the source region 1410 and the drain region 1420 in the first direction DR 1. Therefore, the oxide semiconductor transistor 6 of the present exemplary embodiment can have a large channel length. As a result, the oxide semiconductor transistor 6 can have improved electrical characteristics.

Fig. 9 is a sectional view showing the oxide semiconductor transistor 7 according to an example embodiment, the sectional view corresponding to a line B-B' of fig. 7. For clarity of illustration, the same or substantially the same structure as that described with reference to fig. 7 and 8 may not be described herein.

Referring to fig. 9, the oxide semiconductor transistor 7 may be provided as follows. The oxide semiconductor transistor 7 may include an insulating substrate 1100, a gate electrode 1200, a gate insulating layer 1300, a dielectric layer 1700, an oxide semiconductor layer 1400, a source electrode 1610, and/or a drain electrode 1620. The insulating substrate 1100, the gate electrode 1200, the oxide semiconductor layer 1400, the source electrode 1610, and the drain electrode 1620 may be the same or substantially the same as the insulating substrate 1100, the gate electrode 1200, the oxide semiconductor layer 1400, the source electrode 1610, and the drain electrode 1620 described with reference to fig. 7 and 8.

Unlike in the description given with reference to fig. 7 and 8, the gate insulating layer 1300 may be a ferroelectric layer. In other words, the gate insulation layer 1300 may not include a dielectric material or a high-k dielectric material.

A dielectric layer 1700 may be provided between the gate insulating layer 1300 and the oxide semiconductor layer 1400. The dielectric layer 1700 may extend along the top surface of the gate insulating layer 1300. A dielectric layer 1700 may extend between the source region 1410 and the gate insulation layer 1300. The dielectric layer 1700 may separate the source region 1410 and the gate insulating layer 1300 from each other. Dielectric layer 1700 may be in direct contact with source regions 1410. A dielectric layer 1700 may extend between the drain region 1420 and the gate insulating layer 1300. The dielectric layer 1700 may separate the drain region 1420 and the gate insulating layer 1300 from each other. The dielectric layer 1700 may be in direct contact with the drain region 1420. The thickness of the dielectric layer 1700 may be determined as desired. Electric powerDielectric layer 1700 may include a material having a high dielectric constant. A high dielectric constant may refer to a dielectric constant that is greater than the dielectric constant of silicon oxide. In some example embodiments, dielectric layer 1700 may include a metal oxide including at least one metal selected from the group consisting of calcium (Ca), strontium (Sr), barium (Ba), scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tantalum (Ta), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd), dysprosium (Dy), ytterbium (Yb), and lutetium (Lu). For example, dielectric layer 1700 may include HfO₂、ZrO₂、CeO₂、La₂O₃、Ta₂O₃Or TiO₂。

The gate insulating layer 1300 (i.e., the ferroelectric layer) may have a negative capacitance characteristic due to the dielectric layer 1700. According to the present exemplary embodiment, the oxide semiconductor transistor 7 can have a large channel length and can use a negative capacitance characteristic. Therefore, the oxide semiconductor transistor 7 can have improved electrical characteristics.

Fig. 10 is a sectional view showing the oxide semiconductor transistor 8 according to an example embodiment, the sectional view corresponding to the line B-B' of fig. 7. For clarity of illustration, the same or substantially the same structure as that described with reference to fig. 7 and 8 may not be described herein.

Referring to fig. 10, the oxide semiconductor transistor 8 may be provided as follows. The oxide semiconductor transistor 8 may include an insulating substrate 1100, a gate electrode 1200, a gate insulating layer 1300, a lower diffusion barrier 1810, an oxide semiconductor layer 1400, an upper diffusion barrier 1820, and a source electrode 1610 and/or a drain electrode 1620. The insulating substrate 1100, the gate electrode 1200, the gate insulating layer 1300, the oxide semiconductor layer 1400, the source electrode 1610, and the drain electrode 1620 may be the same as or substantially the same as the insulating substrate 1100, the gate electrode 1200, the gate insulating layer 1300, the oxide semiconductor layer 1400, the source electrode 1610, and the drain electrode 1620 described with reference to fig. 7 and 8.

The lower diffusion barrier 1810 may be provided between the gate insulating layer 1300 and the oxide semiconductor layer 1400. The lower diffusion barrier 1810 may extend along the top surface of the gate insulating layer 1300. Lower diffusion barrierThe stopper 1810 may extend between the source region 1410 and the gate insulation layer 1300. The lower diffusion barrier 1810 may separate the source region 1410 and the gate insulating layer 1300 from each other. The lower diffusion barrier 1810 may extend between the drain region 1420 and the gate insulating layer 1300. The lower diffusion barrier 1810 may separate the drain region 1420 and the gate insulating layer 1300 from each other. The lower diffusion barrier 1810 may prevent, for example, hydrogen from penetrating into a lower portion of the oxide semiconductor layer 1400. For example, the lower diffusion barrier 1810 may include Al₂O₃SiN, SiON or combinations thereof.

An upper diffusion barrier 1820 may be provided between the oxide semiconductor layer 1400 and the upper insulating layer 1500. The upper diffusion barrier 1820 may extend along a top surface of the oxide semiconductor layer 1400. The upper diffusion barrier 1820 may expose the source region 1410 and the drain region 1420. The source and drain electrodes 1610 and 1620 may penetrate the upper diffusion barrier 1820. The source and drain electrodes 1610 and 1620 may be electrically connected to the source and drain regions 1410 and 1420, respectively, through the upper diffusion barrier 1820. The upper diffusion barrier 1820 may prevent, for example, hydrogen from penetrating into an upper portion of the oxide semiconductor layer 1400. For example, the upper diffusion barrier 1820 may comprise Al₂O₃SiN, SiON or combinations thereof. In other examples, only one of the upper and lower diffusion barriers 1820, 1810 may be provided.

In the present example embodiment, the lower diffusion barrier 1810 and the upper diffusion barrier 1820 may prevent, for example, hydrogen from penetrating into the oxide semiconductor layer 1400, and the oxide semiconductor transistor 8 may have a large channel length. Accordingly, the oxide semiconductor transistor 8 can have improved electrical characteristics.

Fig. 11 is a sectional view showing the oxide semiconductor transistor 9 according to an example embodiment, the sectional view corresponding to a line B-B' of fig. 7. For clarity of illustration, the same or substantially the same structure as that described with reference to fig. 7 and 8 may not be described herein.

Referring to fig. 11, the oxide semiconductor transistor 9 may be provided as follows. The oxide semiconductor transistor 9 may include an insulating substrate 1100, a gate electrode 1200, a gate insulating layer 1300, an oxide semiconductor layer 1400, a third additional gate insulating layer 1310, a third additional gate electrode 1210, an upper insulating layer 1500, a source electrode 1610, and/or a drain electrode 1620. The insulating substrate 1100, the gate electrode 1200, the gate insulating layer 1300, the oxide semiconductor layer 1400, the upper insulating layer 1500, the source electrode 1610, and the drain electrode 1620 may be the same as or substantially the same as the insulating substrate 1100, the gate electrode 1200, the gate insulating layer 1300, the oxide semiconductor layer 1400, the upper insulating layer 1500, the source electrode 1610, and the drain electrode 1620 described with reference to fig. 7 and 8.

A third additional gate insulating layer 1310 may be provided between the oxide semiconductor layer 1400 and the upper insulating layer 1500. The third additional gate insulating layer 1310 may extend along the top surface of the oxide semiconductor layer 1400. For example, the third additional gate insulating layer 1310 may conformally extend along the top surface of the oxide semiconductor layer 1400. The third additional gate insulating layer 1310 may expose the source region 1410 and the drain region 1420. The source electrode 1610 and the drain electrode 1620 may penetrate the third additional gate insulating layer 1310. The source and drain electrodes 1610 and 1620 may be electrically connected to the source and drain regions 1410 and 1420 through the third additional gate insulating layer 1310, respectively. The thickness of the third additional gate insulating layer 1310 may be determined as needed. The third additional gate insulating layer 1310 may include a ferroelectric material, a dielectric material, or a high-k dielectric material. The ferroelectric material, dielectric material, and high-k dielectric material may be the same or substantially the same as those described with reference to fig. 7 and 8. In an example, the third additional gate insulating layer 1310 may have the same or substantially the same thickness and material as the gate insulating layer 1300.

A third additional gate electrode 1210 may be provided on the third additional gate insulating layer 1310. The third additional gate electrode 1210 may be disposed on a side of the oxide semiconductor layer 1400 opposite to the gate electrode 1200 and on a side of the third additional gate insulating layer 1310 opposite to the oxide semiconductor layer 1400. The third additional gate electrode 1210 may face the first side surface 1201, the second side surface 1202, and the top surface 1204 of the gate electrode 1200. The third additional gate electrode 1210 may be electrically disconnected from the oxide semiconductor layer 1400. The third additional gate electrode 1210 may be separated from the oxide semiconductor layer 1400 by the third additional gate insulating layer 1310. The third additional gate electrode 1210 may include a conductive material. For example, the third additional gate electrode 1210 may include a metal or a metal compound.

The gate electrode 1200 and the third additional gate electrode 1210 may be gate electrodes of a double gate structure. The oxide semiconductor transistor 9 of this example embodiment may have a double gate structure and a large channel length. Therefore, the oxide semiconductor transistor 9 can have improved electrical characteristics.

Fig. 12 is a cross-sectional view illustrating the oxide semiconductor transistor 10 according to an example embodiment, the cross-sectional view corresponding to a line B-B' of fig. 7. For clarity of illustration, the same or substantially the same structure as that described with reference to fig. 7 and 8 may not be described herein.

Referring to fig. 12, the oxide semiconductor transistor 10 may be provided as follows. The oxide semiconductor transistor 10 may include an insulating substrate 1100, a gate electrode 1200, a gate insulating layer 1300, an oxide semiconductor layer 1400, a fourth additional gate insulating layer 1320, a fourth additional gate electrode 1220, an upper insulating layer 1500, a source electrode 1610, and/or a drain electrode 1620. The insulating substrate 1100, the gate electrode 1200, the gate insulating layer 1300, the oxide semiconductor layer 1400, the upper insulating layer 1500, the source electrode 1610, and the drain electrode 1620 may be the same as or substantially the same as the insulating substrate 1100, the gate electrode 1200, the gate insulating layer 1300, the oxide semiconductor layer 1400, the upper insulating layer 1500, the source electrode 1610, and the drain electrode 1620 described with reference to fig. 7 and 8.

A fourth additional gate insulating layer 1320 may be provided over the top surface 1204 of the gate electrode 1200. A fourth additional gate insulating layer 1320 may be provided over the top surface 1204 of the gate electrode 1200 on the opposite side of the oxide semiconductor layer 1400 from the gate insulating layer 1300. The fourth additional gate insulating layer 1320 may extend along the top surface of the oxide semiconductor layer 1400. A top surface of the oxide semiconductor layer 1400 may be opposite to a bottom surface of the oxide semiconductor layer 1400 facing the gate insulating layer 1300. The thickness of the fourth additional gate insulating layer 1320 may be determined as needed. The fourth additional gate insulating layer 1320 may include a ferroelectric material, a dielectric material, or a high-k dielectric material. The ferroelectric material, dielectric material, and high-k dielectric material may be the same or substantially the same as those described with reference to fig. 7 and 8. In an example, the fourth additional gate insulating layer 1320 may have the same or substantially the same thickness and material as the gate insulating layer 1300.

A fourth additional gate electrode 1220 may be provided on the fourth additional gate insulating layer 1320. The fourth additional gate electrode 1220 may be provided at a side of the fourth additional gate insulating layer 1320 opposite to the oxide semiconductor layer 1400. The fourth additional gate electrode 1220 may be electrically disconnected from the oxide semiconductor layer 1400. The fourth additional gate electrode 1220 may be separated from the oxide semiconductor layer 1400 by a fourth additional gate insulating layer 1320. The fourth additional gate electrode 1220 may include a conductive material. For example, the fourth additional gate electrode 1220 may include a metal or a metal compound.

The gate electrode 1200 and the fourth additional gate electrode 1220 may be gate electrodes of a double gate structure. The oxide semiconductor transistor 10 of the present example embodiment may have a double gate structure and a large channel length. Accordingly, the oxide semiconductor transistor 10 can have improved electrical characteristics.

Fig. 13 is a perspective view of the oxide semiconductor transistor 11 according to an example embodiment. Fig. 14 is a sectional view taken along line C-C' of fig. 13. For clarity of illustration, the same or substantially the same structure as that described with reference to fig. 7 and 8 may not be described herein.

Referring to fig. 13 and 14, the oxide semiconductor transistor 11 may be provided as follows. The oxide semiconductor transistor 11 may include an insulating substrate 2100, a gate electrode 2200, a gate insulating layer 2300, an oxide semiconductor layer 2400, an upper insulating layer 2500, a source electrode 2610, and/or a drain electrode 2620. The insulating substrate 2100, the gate electrode 2200, the oxide semiconductor layer 2400, the upper insulating layer 2500, the source electrode 2610, and the drain electrode 2620 may be the same or substantially the same as the insulating substrate 1100, the gate electrode 1200, the oxide semiconductor layer 1400, the upper insulating layer 1500, the source electrode 1610, and the drain electrode 1620 described above with reference to fig. 7 and 8.

Unlike in the description given with reference to fig. 7 and 8, the gate insulating layer 2300 may not be provided between the top surface 2100u of the insulating substrate 2100 and the bottom surface of the oxide semiconductor layer 2400. Two end surfaces of the gate insulating layer 2300 opposite to each other in the extending direction of the gate insulating layer 2300 may be in direct contact with the top surface 2100u of the insulating substrate 2100. A bottom surface of the oxide semiconductor layer 2400 may be in direct contact with the top surface 2100u of the insulating substrate 2100. The source region 2410 and the drain region 2420 may be in direct contact with the insulating substrate 2100.

Since the oxide semiconductor layer 2400 of the present example embodiment extends along the first side surface 2201, the second side surface 2202, and the top surface 2204 of the gate electrode 2200, the channel length of the oxide semiconductor transistor 11 may be greater than the distance between the source region 2410 and the drain region 2420 in the first direction DR 1. Therefore, the oxide semiconductor transistor 11 of the present exemplary embodiment can have a large channel length. As a result, the oxide semiconductor transistor 11 can have improved electrical characteristics.

Fig. 15 is a sectional view showing the oxide semiconductor transistor 12 according to an example embodiment, the sectional view corresponding to the line C-C' of fig. 13. For clarity of illustration, the same or substantially the same structure as that described with reference to fig. 13 and 14 may not be described herein.

Referring to fig. 15, the oxide semiconductor transistor 12 may be provided as follows. The oxide semiconductor transistor 12 may include an insulating substrate 2100, a gate electrode 2200, a gate insulating layer 2300, a dielectric layer 2700, an oxide semiconductor layer 2400, an upper insulating layer 2500, a source electrode 2610, and/or a drain electrode 2620. The insulating substrate 2100, the gate electrode 2200, the gate insulating layer 2300, the oxide semiconductor layer 2400, the upper insulating layer 2500, the source electrode 2610, and the drain electrode 2620 may be the same as or substantially the same as the insulating substrate 2100, the gate electrode 2200, the gate insulating layer 2300, the oxide semiconductor layer 2400, the upper insulating layer 2500, the source electrode 2610, and the drain electrode 2620 described with reference to fig. 13 and 14.

The gate insulating layer 2300 may be a ferroelectric layer. In other words, the gate insulating layer 2300 may not include a dielectric material or a high-k dielectric material.

The dielectric layer 2700 may extend along a bottom surface of the oxide semiconductor layer 2400. Dielectric mediumThe layer 2700 may be provided between the gate insulating layer 2300 and the oxide semiconductor layer 2400 over the first side surface 2201, the second side surface 2202, and the top surface 2204 of the gate electrode 2200. The dielectric layer 2700 may be provided between the oxide semiconductor layer 2400 and the insulating substrate 2100 over the top surface 2100u of the insulating substrate 2100. Dielectric layer 2700 can extend between source region 2410 and insulating substrate 2100. The dielectric layer 2700 may separate the source region 2410 and the insulating substrate 2100 from each other. Dielectric layer 2700 can extend between drain region 2420 and insulating substrate 2100. The dielectric layer 2700 may separate the drain region 2420 and the insulating substrate 2100 from each other. Dielectric layer 2700 may be in direct contact with drain region 2420. The thickness of the dielectric layer 2700 may be determined as desired. For example, dielectric layer 2700 may include a material having a high dielectric constant. A high dielectric constant may refer to a dielectric constant that is greater than the dielectric constant of silicon oxide. In some example embodiments, the dielectric layer 2700 may include a metal oxide including at least one metal selected from the group consisting of calcium (Ca), strontium (Sr), barium (Ba), scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tantalum (Ta), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd), dysprosium (Dy), ytterbium (Yb), and lutetium (Lu). For example, dielectric layer 2700 may include HfO₂、ZrO₂、CeO₂、La₂O₃、Ta₂O₃Or TiO₂。

Due to the dielectric layer 2700, the gate insulating layer 2300 (i.e., the ferroelectric layer) may have a negative capacitance characteristic. According to the present example embodiment, the oxide semiconductor transistor 12 may have a large channel length and may use negative capacitance characteristics. Accordingly, the oxide semiconductor transistor 12 can have improved electrical characteristics.

Fig. 16 is a sectional view illustrating the oxide semiconductor transistor 13 according to an example embodiment, the sectional view corresponding to a line C-C' of fig. 13. For clarity of illustration, the same or substantially the same structure as that described with reference to fig. 13 and 14 may not be described herein.

Referring to fig. 16, the oxide semiconductor transistor 13 may be provided as follows. The oxide semiconductor transistor 13 may include an insulating substrate 2100, a gate electrode 2200, a gate insulating layer 2300, a lower diffusion barrier 2810, an oxide semiconductor layer 2400, an upper diffusion barrier 2820, an upper insulating layer 2500, a source electrode 2610, and/or a drain electrode 2620. The insulating substrate 2100, the gate electrode 2200, the gate insulating layer 2300, the oxide semiconductor layer 2400, the source electrode 2610, and the drain electrode 2620 may be the same as or substantially the same as the insulating substrate 2100, the gate electrode 2200, the gate insulating layer 2300, the oxide semiconductor layer 2400, the source electrode 2610, and the drain electrode 2620 described with reference to fig. 13 and 14.

The lower diffusion barrier 2810 may extend along the bottom surface of the oxide semiconductor layer 2400. The lower diffusion barrier 2810 may be provided between the gate insulating layer 2300 and the oxide semiconductor layer 2400 over the first side surface 2201, the second side surface 2202, and the top surface 2204 of the gate electrode 2200. The lower diffusion barrier 2810 may be provided between the oxide semiconductor layer 2400 and the insulating substrate 2100 over the top surface 2100u of the insulating substrate 2100. The lower diffusion barrier 2810 may extend between the source region 2410 and the insulating substrate 2100. The lower diffusion barrier 2810 can prevent, for example, hydrogen from penetrating into a lower portion of the oxide semiconductor layer 2400. For example, the lower diffusion barrier 2810 may include Al₂O₃SiN, SiON or combinations thereof.

The upper diffusion barrier 2820 may be provided between the oxide semiconductor layer 2400 and the upper insulating layer 2500. The upper diffusion barrier 2820 may extend along the top surface of the oxide semiconductor layer 2400. The upper diffusion barrier 2820 may expose the source region 2410 and the drain region 2420. The source electrode 2610 and the drain electrode 2620 may penetrate the upper diffusion barrier 2820. The source and drain electrodes 2610 and 2620 may be electrically connected to the source and drain regions 2410 and 2420, respectively, through the upper diffusion barrier 2820. The upper diffusion barrier 2820 may prevent, for example, hydrogen from penetrating into an upper portion of the oxide semiconductor layer 2400. For example, the upper diffusion barrier 2820 may comprise Al₂O₃SiN, SiON or combinations thereof.

In the present example embodiment, the lower diffusion barrier 2810 and the upper diffusion barrier 2820 may prevent, for example, hydrogen from penetrating into the oxide semiconductor layer 2400, and the oxide semiconductor transistor 13 may have a large channel length. Accordingly, the oxide semiconductor transistor 13 can have improved electrical characteristics.

Fig. 17 is a sectional view showing the oxide semiconductor transistor 14 according to an example embodiment, the sectional view corresponding to the line C-C' of fig. 13. For clarity of illustration, the same or substantially the same structure as that described with reference to fig. 11 and fig. 13 and 14 may not be described herein.

Referring to fig. 17, the oxide semiconductor transistor 14 may be provided as follows. The oxide semiconductor transistor 14 may include an insulating substrate 2100, a gate electrode 2200, a gate insulating layer 2300, an oxide semiconductor layer 2400, a fifth additional gate insulating layer 2310, a fifth additional gate electrode 2210, an upper insulating layer 2500, a source electrode 2610, and/or a drain electrode 2620. The insulating substrate 2100, the gate electrode 2200, the gate insulating layer 2300, the oxide semiconductor layer 2400, the upper insulating layer 2500, the source electrode 2610, and the drain electrode 2620 may be the same as or substantially the same as the insulating substrate 2100, the gate electrode 2200, the gate insulating layer 2300, the oxide semiconductor layer 2400, the upper insulating layer 2500, the source electrode 2610, and the drain electrode 2620 described with reference to fig. 13 and 14.

The fifth additional gate insulating layer 2310 and the fifth additional gate electrode 2210 may be the same as or substantially the same as the third additional gate insulating layer 1310 and the third additional gate electrode 1210 described with reference to fig. 11.

The gate electrode 2200 and the fifth additional gate electrode 2210 may be gate electrodes of a double gate structure. The oxide semiconductor transistor 14 of the present example embodiment may have a double gate structure and a large channel length. Accordingly, the oxide semiconductor transistor 14 can have improved electrical characteristics.

Fig. 18 is a sectional view showing the oxide semiconductor transistor 15 according to an example embodiment, the sectional view corresponding to the line C-C' of fig. 13. For clarity of illustration, the same or substantially the same structure as that described with reference to fig. 12 and fig. 13 and 14 may not be described herein.

Referring to fig. 18, the oxide semiconductor transistor 15 may be provided as follows. The oxide semiconductor transistor 15 may include an insulating substrate 2100, a gate electrode 2200, a gate insulating layer 2300, an oxide semiconductor layer 2400, a sixth additional gate insulating layer 2320, a sixth additional gate electrode 2220, an upper insulating layer 2500, a source electrode 2610, and/or a drain electrode 2620. The insulating substrate 2100, the gate electrode 2200, the gate insulating layer 2300, the oxide semiconductor layer 2400, the upper insulating layer 2500, the source electrode 2610, and the drain electrode 2620 may be the same as or substantially the same as the insulating substrate 2100, the gate electrode 2200, the gate insulating layer 2300, the oxide semiconductor layer 2400, the upper insulating layer 2500, the source electrode 2610, and the drain electrode 2620 described with reference to fig. 13 and 14.

The sixth additional gate insulating layer 2320 and the sixth additional gate electrode 2220 may be the same as or substantially the same as the fourth additional gate insulating layer 1320 and the fourth additional gate electrode 1220 described with reference to fig. 12.

The gate electrode 2200 and the sixth additional gate electrode 2220 may be gate electrodes of a double gate structure. The oxide semiconductor transistor 15 of this example embodiment may have a double gate structure and a large channel length. Accordingly, the oxide semiconductor transistor 15 can have improved electrical characteristics.

As described above, the present disclosure provides an oxide semiconductor transistor having improved electrical characteristics.

However, the effect of the present disclosure is not limited thereto.

It should be understood that the example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within example embodiments should generally be considered as available for other similar features or aspects in other embodiments. Although one or more example embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope defined by the following claims.

This application claims the benefit of korean patent application No. 10-2020-0059968, filed in the korean intellectual property office on year 2020, 5, 19, the disclosure of which is incorporated herein by reference in its entirety.

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Oxide semiconductor transistor

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