阅读说明：本技术 可动态调整的时钟路径电路 (Dynamically adjustable clock path circuit ) 是由 赖振安 陈俊晟 于 2021-08-31 设计创作，主要内容包括：本发明公开了一种可动态调整的时钟路径电路包括：由n级时钟延迟单元串联而成的时钟延迟链。第1级时钟延迟单元的输入端连接时钟输入信号。第k级时钟延迟单元的输入端连接第(k-1)级时钟延迟单元的输出端。时钟输入信号连接到第一多路选择器的输入端。各级时钟延迟单元的输出端通过对应的选择开关连接到第一多路选择器的输入端；从时钟输入信号和各级延迟信号中选择一个信号作为时钟输出信号。各选择开关的控制信号以及第一多路选择器的选择信号通过延迟链控制电路控制,以实现对时钟输出信号的相位的动态调整。本发明能对时钟输出信号的相位进行动态调整,能应用于双端口静态存储器的可测试设计电路中并实现对双端口静态存储器进行有效且快速的测试和特性分析。(The invention discloses a clock path circuit capable of being dynamically adjusted, which comprises: the clock delay chain is formed by connecting n stages of clock delay units in series. The input end of the 1 st stage clock delay unit is connected with a clock input signal. The input end of the kth stage clock delay unit is connected with the output end of the (k-1) th stage clock delay unit. The clock input signal is connected to the input of the first multiplexer. The output end of each level of clock delay unit is connected to the input end of the first multiplexer through a corresponding selection switch; one signal is selected from the clock input signal and the delayed signals of each stage as a clock output signal. The control signal of each selection switch and the selection signal of the first multiplexer are controlled by a delay chain control circuit to realize the dynamic adjustment of the phase of the clock output signal. The invention can dynamically adjust the phase of the clock output signal, can be applied to a testable design circuit of the dual-port static memory and realizes effective and rapid test and characteristic analysis of the dual-port static memory.)

1. A dynamically adjustable clock path circuit, comprising:

the clock delay chain is formed by connecting n stages of clock delay units in series, wherein n is greater than 1;

the input end of the 1 st-stage clock delay unit is connected with a clock input signal;

the input end of the kth-stage clock delay unit is connected with the output end of the (k-1) th-stage clock delay unit, and k is more than or equal to 2 and less than or equal to n;

the clock input signal is connected to the input end of the first multiplexer;

the output end of each clock delay unit is connected to the input end of the first multiplexer through a corresponding selection switch; the output end of each clock delay unit outputs each level delay signal of the clock input signal, and the first multiplexer selects one signal from the clock input signal and each level delay signal of the clock input signal as a clock output signal;

and the control signal of each selection switch and the selection signal of the first multiplexer are controlled by a delay chain control circuit so as to realize the dynamic adjustment of the phase of the clock output signal.

2. The dynamically adjustable clock path circuit of claim 1, wherein: the number of the selection switches is (n-1), and one selection switch is connected between the input end and the output end of the kth-stage clock delay unit;

the first multiplexer comprises two input ends, the first input end of the first multiplexer is connected with the clock input signal, and the second input end of the first multiplexer is connected with the output end of the nth-stage clock delay unit.

3. The dynamically adjustable clock path circuit of claim 2, wherein: the clock delay units of all levels have the same structure and the same time delay.

4. The dynamically adjustable clock path circuit of claim 3, wherein: each stage of the clock delay unit is formed by connecting an even number of inverters in series.

5. The dynamically adjustable clock path circuit of claim 4, wherein: each stage of the clock delay unit is formed by connecting 2 inverters in series.

6. The dynamically adjustable clock path circuit of claim 2, wherein: the clock path circuit is applied to a testable design circuit of the dual-port static memory;

the testable design circuit comprises two clock path circuits, wherein the two clock path circuits are respectively a first clock path circuit and a second clock path circuit, a clock output signal of the first clock path circuit is a first clock output signal, a clock output signal of the second clock path circuit is a second clock output signal, a clock input signal of the first clock path circuit is a first clock input signal, and a clock input signal of the second clock path circuit is a second clock input signal;

when the dual-port static memory is tested, the clock input end of the first port of the dual-port static memory is connected with the first clock output signal, the clock input end of the second port of the dual-port static memory is connected with the second clock output signal, and the time delay of the port clock signal between the first port and the second port of the dual-port static memory is adjusted by dynamically adjusting the phase of the first clock output signal and the phase of the second clock output signal in the test.

7. The dynamically adjustable clock path circuit of claim 6, wherein: the testing of the dual-port static memory comprises finding out the lowest operating voltage under the worst condition, wherein the worst condition corresponds to the condition that the first port and the second port of the dual-port static memory simultaneously access the same address, and the phase of the first clock output signal and the phase of the second clock output signal are continuously adjusted to ensure that the phases of the port clock signals of the first port and the second port of the dual-port static memory are the same, so that the first port and the second port of the dual-port static memory simultaneously access the same address.

8. The dynamically adjustable clock path circuit of claim 6 or 7, wherein: the design for test circuit further comprises two second multiplexers, two input ends of the first second multiplexer are respectively connected with the first clock signal and the second clock signal, and two input ends of the second multiplexer are respectively connected with the second clock signal and the ground;

the output end of the first multiplexer is connected with the input end of the first clock path circuit and provides the first clock input signal;

a second one of the second multiplexers has an output coupled to the input of the second clock path circuit and provides the second clock input signal.

9. The dynamically adjustable clock path circuit of claim 8, wherein: when the dual-port static memory works normally, the first multiplexer selects a first clock signal as the first clock input signal, the second multiplexer selects a second clock signal as the second clock input signal, the first multiplexer of the first clock path circuit selects the first clock input signal as the first clock output signal, and the first multiplexer of the second clock path circuit selects the second clock input signal as the second clock output signal.

10. The dynamically adjustable clock path circuit of claim 9, wherein: when the dual-port static memory is tested, the first multiplexer selects a second clock signal as the first clock input signal, the second multiplexer selects a second clock signal as the second clock input signal, the first multiplexer of the first clock path circuit selects a delay signal of a corresponding stage of the first clock input signal as the first clock output signal, and the first multiplexer of the second clock path circuit selects the second clock input signal as the second clock output signal.

11. The dynamically adjustable clock path circuit of claim 2, wherein: the delay chain control circuit controls (n-1) of the selection switches by a digital signal of (n-1) bits.

12. The dynamically adjustable clock path circuit of claim 2, wherein: the selection signal of each of the first multiplexers is provided by a 1-bit digital signal provided by the delay chain control circuit.

13. The dynamically adjustable clock path circuit of claim 8, wherein: the selection signal of each of the second multiplexers is provided by a 1-bit digital signal provided by the delay chain control circuit.

14. The dynamically adjustable clock path circuit of claim 10, wherein: the design-for-test circuit is implanted inside the dual-port static memory; alternatively, the design for test circuit is placed in a built-in self-test circuit of the dual-port static memory.

15. The dynamically adjustable clock path circuit of claim 6, wherein: and two clock path circuits in the testable design circuit are completely symmetrical and identical on the layout.

Technical Field

The present invention relates to semiconductor integrated circuits, and more particularly to a dynamically adjustable clock path circuit.

Background

Dual Port (DP) static memory (SRAM) is widely used in integrated circuits for parallel computing and data exchange in different frequency domains. Fig. 1 is a circuit diagram of a memory cell structure of a conventional dual-port SRAM; the storage node comprises a first phase inverter consisting of a pull-up tube PU1 and a pull-down tube PD1 and a second phase inverter consisting of a pull-up tube PU2 and a pull-down tube PD2, wherein the output end of the first phase inverter is connected with the input end of the second phase inverter, the connection point of the output end of the first phase inverter and the input end of the second phase inverter forms a storage node Q, and the input end of the first phase inverter and the output end of the second phase inverter are connected, and the connection point of the input end of the first phase inverter and the output end of the second phase inverter forms a storage node QB. The first port comprises selection tubes PG1 and PG3, and the second port comprises selection tubes PG2 and PG 4; a pair of bit lines of the first port are BLA and/BLA, and word lines are WLA; the second port has a pair of bit lines BLB and/BLB and word lines WLB. The first port is also commonly referred to as an a-port and the second port is commonly referred to as a B-port.

The dual-port static memory is mainly provided with one more port on the basis of a single-port static memory, and is essentially the same as the single-port static memory, so that the read-write limit is similar.

Because the dual-port static memory supports reading or writing an address through different ports at the same time, the operation mode causes the alpha ratio and the beta ratio of writing to be more deteriorated than that of the static memory with a single port. alpha ratio is Idsat between the pull-up tube and the pull-down tube, namely the ratio of saturated leakage current; beta ratio is the ratio of Idsat, the saturation leakage current, between the pull-down tube and the select tube.

FIG. 2 is a signal curve of the circuit shown in FIG. 1 when the ground bounce phenomenon occurs at the node Q; taking the read operation through one port as an example, when the data storage value is 0, i.e. when the storage node Q is 0, when the word line WL is turned on, i.e. when one of WLA and WLB in fig. 1 is turned on, the storage node Q which is originally 0 will be subjected to a phenomenon of similar bounce (ground bounce) due to the voltage division principle. The bit line pair of BL and BLB in FIG. 2 is one of a BLA and/BLA bit line pair and a BLB and/BLB bit line pair.

The phenomenon of ground bounce occurs when one port reads, and is worsened when two ports read the same address at the same time.

The ground bounce phenomenon can not reduce the operation voltage VCC all the time, and how to effectively obtain the lowest operation voltage VCC in the real sense during the characteristic analysis_MINIt is the most important task.

As shown in fig. 3, it is a structural diagram of a conventional dual-port SRAM; dual port SRAM, DP SRAM201, includes a memory array 202, a write circuit 203, a read circuit 204, a control circuit (controller)205, and an Address Decoder (Address Decoder) 206.

The memory array 202 includes a plurality of memory cells 2021, and the structure of the memory cells 2021 is shown in fig. 1.

The write circuit 203 includes a plurality of column-corresponding sub-write circuits 2031. The read circuit 204 includes a plurality of column-corresponding sub-read circuits 2041.

In FIG. 3, columns of storage array 202 are represented by Col.1, Col.2. Col.L, respectively; BL is used for a pair of bit lines of the first port_1AAnd BL_1A’、BL_2AAnd BL_2A’···BL_LAAnd BL_LA’Indicating that word lines are represented by WL1A and WL 2A. WLMA; BL is used for a pair of bit lines of the second port_1BAnd BL_1B’、BL_2BAnd BL_2B’···BL_LBAnd BL_LB’The word lines are denoted by WL1B and WL 2B. WLMB respectively; the memory cells 2021 are respectively denoted by subscripts consisting of C plus columns and rows, and as shown in fig. 3, for example, the memory cell 2021 corresponding to the first column and the first row is C_1,1。

The address of the A port is ADDR_AThe address of the B port is ADDR_B.

RWB for read/write control signal of A port_ARWB for read/write control signal indicating B-port_BAnd (4) showing.

WData for L-bit write signal of A-port_A[1:L]Indicating that WData is used for L-bit write signal of B-port_B[1:L]And (4) showing.

RData for L-bit read signal of A port_A[1:L]The L-bit read signal at the B-port is represented by RData_B[1:L]And (4) showing.

Because the ports a and B have respective clock signals and input/output signals, the same address is accessed at the same time, and the transmission delay of the two clock signals of the ports a and B must be considered in the SoC chip, which is only the synchronization of the test signals and not the real time. Whereas in the existing test methods only the synchronization of the test signals is considered.

As shown in fig. 4, it is a two-dimensional SHMOO diagram of the lowest operating voltage under the Worst Case (Worst Case) most found in the test method of the conventional dual-port SRAM; the current practice in the industry is to find the lowest operating voltage of Worst Case by using two-dimensional SHMOO. In fig. 4, a broken line 103 corresponds to the Best Case (Best Case) and a broken line 104 corresponds to Worst Case. Actual test data shows that the lowest operating voltage of a double-port word case may be 100mV higher than that of a single-port read-write word case.

However, this is time consuming, and the testing range must be enlarged due to the different delays between signals caused by the tester, and the testing range is enlarged due to the large brackets corresponding to 104 in fig. 4. And the time delay difference estimated by the length of the signal line on the layout has no reference function.

Disclosure of Invention

The invention aims to provide a clock path circuit capable of being dynamically adjusted, which can dynamically adjust the phase of a clock output signal, can be applied to a design for test (DFT) circuit of a dual-port static memory and realizes effective and rapid test and characteristic analysis of the dual-port static memory.

To solve the above technical problem, the dynamically adjustable clock path circuit provided by the present invention comprises:

the clock delay chain is formed by connecting n stages of clock delay units in series, and n is larger than 1.

The input end of the 1 st stage clock delay unit is connected with a clock input signal.

The input end of the kth-stage clock delay unit is connected with the output end of the (k-1) th-stage clock delay unit, and k is more than or equal to 2 and less than or equal to n.

The clock input signal is connected to an input of a first multiplexer.

The output end of each clock delay unit is connected to the input end of the first multiplexer through a corresponding selection switch; the output end of each stage of the clock delay unit outputs each stage of delay signals of the clock input signals, and the first multiplexer selects one signal from the clock input signals and each stage of delay signals of the clock input signals as clock output signals.

And the control signal of each selection switch and the selection signal of the first multiplexer are controlled by a delay chain control circuit so as to realize the dynamic adjustment of the phase of the clock output signal.

In a further improvement, the number of the selection switches is (n-1), and one selection switch is connected between the input end and the output end of the kth stage clock delay unit.

The first multiplexer comprises two input ends, the first input end of the first multiplexer is connected with the clock input signal, and the second input end of the first multiplexer is connected with the output end of the nth-stage clock delay unit.

The further improvement is that the clock delay units of each stage have the same structure and the same time delay.

The further improvement is that each stage of the clock delay unit is formed by connecting an even number of inverters in series.

In a further improvement, each stage of the clock delay unit is formed by connecting 2 inverters in series.

In a further improvement, the clock path circuit is applied to a testable design circuit of the dual-port static memory.

The testable design circuit comprises two clock path circuits, wherein the two clock path circuits are respectively a first clock path circuit and a second clock path circuit, a clock output signal of the first clock path circuit is a first clock output signal, a clock output signal of the second clock path circuit is a second clock output signal, a clock input signal of the first clock path circuit is a first clock input signal, and a clock input signal of the second clock path circuit is a second clock input signal.

When the dual-port static memory is tested, the clock input end of the first port of the dual-port static memory is connected with the first clock output signal, the clock input end of the second port of the dual-port static memory is connected with the second clock output signal, and the time delay of the port clock signal between the first port and the second port of the dual-port static memory is adjusted by dynamically adjusting the phase of the first clock output signal and the phase of the second clock output signal in the test.

In a further improvement, testing the dual-port static memory includes finding a lowest operating voltage in a worst case scenario, the worst case scenario corresponding to a same address being accessed by both the first port and the second port of the dual-port static memory, and adjusting the phase of the first clock output signal and the phase of the second clock output signal continuously to make the phases of the port clock signals of the first port and the second port of the dual-port static memory the same and thereby achieve the same address being accessed by both the first port and the second port of the dual-port static memory.

In a further improvement, the design for test circuit further includes two second multiplexers, two input terminals of a first one of the second multiplexers are respectively connected to the first clock signal and the second clock signal, and two input terminals of a second one of the second multiplexers are respectively connected to the second clock signal and ground.

An output of a first one of the second multiplexers is coupled to an input of the first clock path circuit and provides the first clock input signal.

A second one of the second multiplexers has an output coupled to the input of the second clock path circuit and provides the second clock input signal.

In a further improvement, when the dual port static memory operates normally, a first one of the second multiplexers selects a first clock signal as the first clock input signal, a second one of the second multiplexers selects a second clock signal as the second clock input signal, the first multiplexer of the first clock path circuit selects the first clock input signal as the first clock output signal, and the first multiplexer of the second clock path circuit selects the second clock input signal as the second clock output signal.

In a further improvement, during testing of the dual port static memory, a first one of the second multiplexers selects a second clock signal as the first clock input signal, a second one of the second multiplexers selects a second clock signal as the second clock input signal, the first multiplexer of the first clock path circuit selects a delayed signal of a stage corresponding to the first clock input signal as the first clock output signal, and the first multiplexer of the second clock path circuit selects the second clock input signal as the second clock output signal.

In a further improvement, the delay chain control circuit controls (n-1) of the selection switches by a digital signal of (n-1) bits.

In a further improvement, the selection signal of each of the first multiplexers is provided by a 1-bit digital signal provided by the delay chain control circuit.

In a further improvement, the selection signal of each of the second multiplexers is provided by a 1-bit digital signal provided by the delay chain control circuit.

In a further improvement, the design for test circuit is implanted inside the dual-port static memory; alternatively, the design for test circuit is placed in a built-in self-test circuit of the dual-port static memory.

In a further improvement, two of the clock path circuits in the design for test circuit are completely symmetrical and identical on the layout.

The clock path circuit can dynamically adjust the phase of the clock output signal, is beneficial to controlling the phase of the clock wave among multiple ports in the multiple ports and enables the phases of the clock waves among different ports to be quickly identical.

The dynamically adjustable clock path circuit can be applied to a testable design circuit of the dual-port static memory, and the clock waves of the two ports of the dual-port static memory can have no time delay as far as possible through the arrangement of the clock path circuit, such as the arrangement of the two clock path circuits, so that the effective and rapid test and characteristic analysis of the dual-port static memory can be realized, and the test time for finding the lowest operating voltage under the worst condition can be effectively reduced.

The invention can make two clock path circuits in the testable design circuit completely symmetrical and the same on the layout, and forcibly uses one clock wave as input to reduce the time delay caused by external winding when starting DFT to test the design circuit, so that the time delay of two ports of the dual-port static memory for simultaneously accessing the same address is greatly reduced, the length of a delay chain can be effectively reduced, and the speed of characteristic analysis test can be further improved.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1 is a circuit diagram of a memory cell structure of a conventional dual port SRAM;

FIG. 2 is a signal curve of the circuit of FIG. 1 showing the occurrence of a ground bounce at node Q;

FIG. 3 is a block diagram of a conventional dual port SRAM;

FIG. 4 is a two-dimensional SHOO diagram of the worst-case lowest operating voltage in a conventional test method for a dual-port SRAM;

FIG. 5 is a circuit diagram of a dynamically adjustable clock path circuit according to an embodiment of the present invention;

FIG. 6 is a circuit diagram of a testable design circuit of a dual port static memory with a dynamically adjustable clock path circuit according to an embodiment of the present invention;

FIG. 7 is a signal curve for one port of the dual-port SRAM of FIG. 6 under test;

FIG. 8 is a circuit diagram of the design for test circuit of FIG. 6;

FIG. 9 is a two-dimensional SHOO diagram of the worst-case lowest operating voltage best found by testing the testable design circuit of the dual-port SRAM of the present invention.

Detailed Description

FIG. 5 is a circuit diagram of a dynamically adjustable clock path circuit 301 according to an embodiment of the present invention; the dynamically adjustable clock path circuit 301 according to the embodiment of the present invention includes:

the clock delay chain is formed by connecting n stages of clock delay units 302 in series, wherein n is larger than 1.

The input of the stage 1 clock delay unit 302 is connected to the clock input signal CLKIN.

The input end of the kth-stage clock delay unit 302 is connected with the output end of the (k-1) -stage clock delay unit 302, and k is more than or equal to 2 and less than or equal to n.

The clock input signal CLKIN is connected to an input of the first multiplexer 303.

The output end of each stage of the clock delay unit 302 is connected to the input end of the first multiplexer 303 through a corresponding selection switch 304; the output end of each stage of the clock delay unit 302 outputs each stage of the delayed signals of the clock input signal CLKIN, and the first multiplexer 303 selects one signal from each stage of the delayed signals of the clock input signal CLKIN and the clock input signal CLKIN as a clock output signal CLKOUT.

The control signal of each of the selection switches 304 and the selection signal SEL1 of the first multiplexer 303 are controlled by a delay chain control circuit to achieve dynamic adjustment of the phase of the clock output signal CLKOUT.

The number of the selection switches 304 is (n-1), and one selection switch 304 is connected between the input end and the output end of the kth stage clock delay unit 302. I.e. the selection switch 304 comprises (n-1). The delay chain control circuit controls (n-1) of the selection switches 304 by the (n-1) -bit digital signal. In fig. 5, the control signals of the selection switch 304, i.e., S0, S1, and S2, are shown at 3 bits.

The first multiplexer 303 includes two input terminals, a first input terminal of the first multiplexer 303 is connected to the clock input signal CLKIN, and a second input terminal of the first multiplexer 303 is connected to the output terminal of the nth stage clock delay unit 302.

The selection signal SEL1 of the first multiplexer 303 is supplied by a 1-bit digital signal supplied from the delay chain control circuit.

In the embodiment of the present invention, the clock delay units 302 at different levels have the same structure and the same delay.

Each stage of the clock delay unit 302 is formed by connecting an even number of inverters in series. Preferably, each stage of the clock delay unit 302 is formed by connecting 2 inverters in series.

Fig. 6 is a circuit diagram of a testable design circuit 305 of a dual-port static memory, in which a dynamically adjustable clock path circuit according to an embodiment of the present invention is applied; the clock path circuit 301 is applied to the testable design circuit 305 of the dual-port static memory.

The testable design circuit 305 includes two clock path circuits 301, where the two clock path circuits 301 are a first clock path circuit 301a and a second clock path circuit 301b, respectively, and the clock output signal CLKOUT of the first clock path circuit 301a is a first clock output signal CLKOUT1, the clock output signal CLKOUT of the second clock path circuit 301b is a second clock output signal CLKOUT2, the clock input signal CLKIN of the first clock path circuit 301a is a first clock input signal CLKIN1, and the clock input signal CLKIN of the second clock path circuit 301b is a second clock input signal CLKIN 2.

When the dual-port static memory is tested, the clock input end of the first port of the dual-port static memory is connected with the first clock output signal CLKOUT1, the clock input end of the second port of the dual-port static memory is connected with the second clock output signal CLKOUT2, and the delay of the port clock signals ACLK and BCLK between the first port and the second port of the dual-port static memory is adjusted by dynamically adjusting the phase of the first clock output signal CLKOUT1 and the phase of the second clock output signal CLKOUT2 during the test. ACLK represents the port clock signal of the first port and BCLK represents the port clock signal of the second port.

Testing the dual port static memory includes finding a lowest operating voltage for a worst case scenario, the worst case scenario corresponding to the first port and the second port of the dual port static memory accessing the same address at the same time, and making the phases of the port clock signals of the first port and the second port of the dual port static memory the same by continuously adjusting the phase of the first clock output signal CLKOUT1 and the phase of the second clock output signal CLKOUT2, thereby achieving the first port and the second port of the dual port static memory accessing the same address at the same time.

FIG. 8 is a circuit diagram of the design for test circuit of FIG. 6; preferably, the design for test circuit 305 further includes two second multiplexers, a first one of the second multiplexers 306a has two inputs respectively connected to the first clock signal CLK1 and the second clock signal CLK2, and a second one of the second multiplexers 306b has two inputs respectively connected to the second clock signal CLK2 and ground.

An output terminal of a first one of the second multiplexers 306a is coupled to an input terminal of the first clock path circuit 301a and provides the first clock input signal CLKIN 1.

The output of a second one of the second multiplexers 306b is connected to the input of the second clock path circuit 301b and provides the second clock input signal CLKIN 2.

The selection signal of each of the second multiplexers is provided by a 1-bit digital signal provided by the delay chain control circuit. The selection signal of the first multiplexer 306a is the signal SEL2, and the selection signal of the second multiplexer 306b is the signal SEL 3.

When the dual port static memory normally operates, a first one of the second multiplexers 306a selects a first clock signal CLK1 as the first clock input signal CLKIN1, a second one of the second multiplexers 306b selects a second clock signal CLK2 as the second clock input signal CLKIN2, the first multiplexer 303 of the first clock path circuit 301a selects the first clock input signal CLKIN1 as the first clock output signal CLKOUT1, and the first multiplexer 303 of the second clock path circuit 301b selects the second clock input signal CLKIN2 as the second clock output signal CLKOUT 2.

During the test of the dual port static memory, the first second multiplexer 306a selects the second clock signal CLK2 as the first clock input signal CLKIN1, the second multiplexer 306b selects the second clock signal CLK2 as the second clock input signal CLKIN2, the first multiplexer 303 of the first clock path circuit 301a selects the delayed signal of the corresponding stage of the first clock input signal CLKIN1 as the first clock output signal CLKOUT1, and the first multiplexer 303 of the second clock path circuit 301b selects the second clock input signal CLKIN2 as the second clock output signal CLKOUT 2.

In FIG. 8, the signals Ctr1 include the (n-1) bits of the first clock path circuit 301a, namely, the control signals S0, S1 through S (n-1), of the selection switch 304, and the selection signal SEL1 of the first clock path circuit 301 a; the signal Ctr2 includes control signals S0, S1 through S (n-1) of the (n-1) bit selection switch 304 of the second clock path circuit 301b and a selection signal SEL1 of the second clock path circuit 301 b.

In the signals of fig. 8, SEL3 remains at 1; the SEL2 is 1 when the dual-port static memory works normally, and the SEL2 is 0 when the dual-port static memory is tested.

In the signal Ctr1, the (n-1) bits of the first clock path circuit 301a control signals S0, S1 through S (n-1) of the selection switch 304 are adjusted as needed; the SEL1 of the first clock path circuit 301a is 1 when the dual port static memory is operating normally, and the SEL1 of the first clock path circuit 301a is 0 when testing.

In the signal Ctr2, the SEL1 of the second clock path circuit 301b remains at 1, and the (n-1) bits of the second clock path circuit 301b do not need to be considered as the values of the control signals S0, S1 through S (n-1) of the selection switch 304. Thus, BCLK always takes the second signal CLK 2; ACLK takes the first signal CLK1 during operation and the delayed signal of the second signal CLK2 during testing, so that the delay between BCLK and ACKL is determined by the delayed signals of the second signal CLK2 and the second signal CLK 2. The circuit can also be arranged symmetrically so that ACLK always takes the first signal CLK1, BCLK takes the second signal CLK2 in operation and takes the delayed version of the first signal CLK1 in test.

The design for test circuit 305 is implanted inside the dual-port static memory; alternatively, the design for test circuit 305 is placed in a built-in self-test circuit of the dual port static memory.

The two clock path circuits 301 in the testable design circuit 305 are completely symmetrical and identical in layout.

As shown in fig. 9, it is a two-dimensional SHMOO diagram of the worst lowest operating voltage for the test by using the testable design circuit of the dual-port SRAM according to the embodiment of the present invention, and since the embodiment of the present invention can realize the same phase as ACLK and BCLK at the same time, it only needs to test the range corresponding to the mark 501; the test range is much smaller and the test rate is increased compared to fig. 4.

Fig. 6 is a circuit structure diagram of a testable design circuit of a dual-port static memory, in which a dynamically adjustable clock path circuit according to an embodiment of the present invention is applied; the Address signals a/B Address of the a port and the B port are input into an Address Buffer (Address Buffer)406, and two port clock signals ACLK and BCLK are respectively generated by the testable design circuit 305 with a first clock signal CLK1 and a second clock signal CLK 2.

The address buffer 406 inputs addresses to a Column Decoder (Column Decoder)402 and a Row Decoder (Row Decoder)403 for decoding, respectively, for selecting Memory cells in the Memory Array (Memory Array) 401.

The Read-Write Control signal Read/Write Control controls the Read-Write; a Driver circuit (Driver)405 is required for writing, and a sense Amplifier (sense Amplifier)404 is required for signal amplification for reading.

FIG. 7 is a signal curve of the dual-port SRAM of FIG. 6 during one-port test; taking port B as an example:

the clock signal CLK in FIG. 7 corresponds to BCLK, TBPWH being the high pulse width of CLK and TBPWL being the low pulse width of CLK;

signal ADRR represents an Address signal such as B Address in fig. 6, and TBACK represents a time interval between a start position of signal ADRR and a rising edge of CLK;

signal DIN represents the input data signal, TBDCK represents the time interval between the start position of signal DIN and the rising edge of CLK;

signal DOUT represents the output data signal, TBCKO represents the time interval between the rising edge of CLK and the start position of signal DOUT;

the signal WE is a READ-WRITE control signal including a WRITE control signal and a READ control signal, and TBWCK indicates a time interval between a start position of the WRITE control signal of the signal WE and a rising edge of CLK.

As shown in fig. 7, each signal during reading and writing needs to be controlled by the clock signal CLK.

The clock path circuit 301 of the embodiment of the present invention can dynamically adjust the phase of the clock output signal CLKOUT, which is beneficial to control the phase of the clock wave between multiple ports in multiple ports and make the phase of the clock wave between different ports quickly identical.

The dynamically adjustable clock path circuit 301 in the embodiment of the present invention can be applied to the testable design circuit 305 of the dual port static memory, and the clock waves of the two ports of the dual port static memory can have no time delay as much as possible through the setting of the clock path circuit 301, for example, through the setting of the two clock path circuits 301, thereby realizing effective and rapid test and characteristic analysis of the dual port static memory, and effectively reducing the test time for finding the lowest operating voltage under the worst condition.

The embodiment of the invention can make two clock path circuits 301 in the testable design circuit 305 completely symmetrical and identical on the layout, and force one clock wave to be used as input when starting the DFT testable design circuit 305 to reduce the time delay caused by external winding, so that the time delay of two ports of the dual-port static memory accessing the same address simultaneously is greatly reduced, the length of a delay chain can be effectively reduced, and the speed of characteristic analysis test can be further improved.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.