阅读说明：本技术 在读取一次性可编程存储器时提高性能的方法和装置 (Method and apparatus for improving performance when reading otp memory ) 是由 S·巴利苏布兰马尼安 S·W·斯普里格斯 G·B·贾米森 于 2020-02-14 设计创作，主要内容包括：公开了在读取一次性可编程存储器时提高性能的方法、装置、系统和制品。示例装置包括：升压电路(236),其包括第一输出(215a)、第二输出(215b)、被配置为耦合到控制器(234)的第一输入(213)、耦合到解码器(246)的第一输出的第二输入(221)、耦合到解码器(246)的第二输出的第三输入(223)；以及多路复用器(206),其包括耦合到升压电路(236)的第一输出(215a)的第一输入、耦合到升压电路(236)的第二输出(215b)的第二输入、耦合到存储器阵列(202/204)的第三输入,以及耦合到感测电路(208)的输出。(Methods, apparatus, systems, and articles of manufacture to improve performance when reading one-time programmable memory are disclosed. An example apparatus includes: a boost circuit (236) comprising a first output (215a), a second output (215b), a first input (213) configured to be coupled to the controller (234), a second input (221) coupled to the first output of the decoder (246), a third input (223) coupled to the second output of the decoder (246); and a multiplexer (206) including a first input coupled to the first output (215a) of the boost circuit (236), a second input coupled to the second output (215b) of the boost circuit (236), a third input coupled to the memory array (202/204), and an output coupled to the sense circuit (208).)

1. An apparatus, comprising:

a boost circuit comprising a first output, a second output, a first input configured to be coupled to a controller, a second input coupled to a first output of a decoder, a third input coupled to a second output of the decoder; and

a multiplexer comprising a first input coupled to the first output of the boost circuit, a second input coupled to the second output of the boost circuit, a third input coupled to a memory array, and an output coupled to a sense circuit.

2. The apparatus of claim 1, wherein the boost circuit comprises:

a boost network comprising an output, a first input configured to be coupled to the output of the controller, and a second input coupled to an input voltage node;

a first level shifter comprising a first input coupled to the second output of the decoder, a second input coupled to the first output of the decoder, a third input coupled to the output of the boost network, and an output coupled to the first input of the multiplexer; and

a second level shifter comprising a first input coupled to the first output of the decoder, a second input coupled to the second output of the decoder, a third input coupled to the output of the boost network, and an output coupled to the second input of the multiplexer.

3. The apparatus of claim 2, wherein the boost network is configured to:

transmitting a signal comprising a voltage level; and is

Raising the voltage level of a signal at an output of the controller in response to a rising edge on the signal; and wherein

At least one of the first level shifter or the second level shifter is configured to transmit the signal to the first input of the multiplexer or the second input of the multiplexer based on a first logical value at the first output of the decoder and a second logical value at the second output of the decoder.

4. The apparatus of claim 1, further comprising an inverter comprising an output coupled to a fourth input of the multiplexer, and an input coupled to the first output of the decoder.

5. The apparatus of claim 4, wherein:

the memory array is a first memory array; and is

The multiplexer includes:

a first n-channel transistor including a control terminal coupled to the first output of the boost circuit, a first current terminal coupled to a first p-channel transistor and a first current terminal of the first memory array, and a second current terminal coupled to the first p-channel transistor and a second current terminal of the sense circuit; and

a second n-channel transistor including a control terminal coupled to the second output of the boost circuit, a first current terminal coupled to a first current terminal of a second memory array and a second p-channel transistor, and a second current terminal coupled to a second current terminal of the second p-channel transistor and a second current terminal of the sense circuit.

6. The device of claim 5, wherein the multiplexer comprises:

the first p-channel transistor comprising a control terminal coupled to the first output of the decoder, the first current terminal coupled to the first memory array and the first current terminal of the first n-channel transistor, and a second current terminal coupled to the sensing circuit and the second current terminal of the first n-channel transistor; and

a second p-channel transistor comprising a control terminal coupled to the output of the inverter, the first current terminal coupled to the first current terminals of the second memory array and the second n-channel transistor, and the second current terminal coupled to the sensing circuit and the second current terminal of the second n-channel transistor.

7. The device of claim 1, wherein the memory array comprises a one-time programmable memory array.

8. An apparatus, comprising:

a boost network configured to:

transmitting a signal comprising a voltage level; and is

Raising the voltage level of a signal at an output of a controller in response to a rising edge on the signal; and

a level shifter configured to transmit the signal to an input of the multiplexer based on a first logic value of the first selection signal and a second logic value of the second selection signal.

9. The apparatus of claim 8, wherein the boost network comprises a first input configured to be coupled to the output of the controller, a second input coupled to an input voltage node, and an output coupled to an input of the level shifter.

10. The apparatus of claim 8, wherein the multiplexer comprises an n-channel transistor coupled to a memory array, and wherein the level shifter comprises a first input coupled to the first select signal, a second input coupled to the second select signal, a third input coupled to the output of the boost network, and an output coupled to a control terminal of the n-channel transistor.

11. The apparatus of claim 10, wherein the level shifter is configured to transmit the signal to the control terminal of the n-channel transistor in response to the first logic value of the first select signal being a logic high value and the second logic value of the second select signal being a logic low value.

12. The apparatus of claim 8, wherein the multiplexer comprises an n-channel transistor coupled to a memory array, and wherein the level shifter comprises a first input coupled to the second select signal, a second input coupled to the first select signal, a third input coupled to the output of the boost network, and an output coupled to a control terminal of the n-channel transistor.

13. The apparatus of claim 12, wherein the level shifter is configured to transmit the signal to the control terminal of the n-channel transistor in response to the first logic value of the first select signal being a logic low value and the second logic value of the second select signal being a logic high value.

14. The device of claim 8, wherein the multiplexer is operable to select a one-time programmable memory array.

15. A method, comprising:

transmitting a signal comprising a voltage level;

raising the voltage level of a signal at an output of a controller in response to a rising edge on the signal; and

the signal is transmitted to the input of the multiplexer based on a first logic value of the first select signal and a second logic value of the second select signal.

16. The method of claim 15, wherein the multiplexer comprises a first n-channel transistor coupled to a first memory array and a second n-channel transistor coupled to a second memory array.

17. The method of claim 16, wherein the first memory array and the second memory array comprise one-time programmable memory arrays.

18. The method of claim 16, further comprising: transmitting the signal to a control terminal of the second n-channel transistor in response to the first logic value of the first select signal being a logic high value and the second logic value of the second select signal being a logic low value.

19. The method of claim 16, further comprising: transmitting the signal to a control terminal of the first n-channel transistor in response to the first logic value of the first select signal being a logic low value and the second logic value of the second select signal being a logic high value.

20. The method of claim 15, further comprising: transmitting a memory bit from a memory array to a computing system based at least on the first logic value of the first select signal and the second logic value of the second select signal.

Technical Field

The present disclosure relates generally to memories, and more particularly to methods and apparatus to improve performance when reading one-time programmable memories.

Background

A memory typically includes an array of memory cells, each of which is accessible via enabling a corresponding pair of word lines and bit lines. Thus, a memory cell typically includes a word line switching device and a storage element. In one-time programmable (OTP) memories, the word line switching devices are Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and the storage elements are floating gate MOSFETs (fgmos).

Drawings

FIG. 1 is a schematic diagram of a first OTP memory array, a second OTP memory array, a multiplexer, and a sensing circuit.

Fig. 2 is a schematic diagram of an example first OTP memory array, an example second OTP memory array, an example multiplexer, an example sensing circuit, and an example boost circuit to improve performance when reading one or more of the first OTP memory array 202 and/or the second OTP memory array 204.

FIG. 3 is a block diagram illustrating an example implementation of the controller of FIG. 2.

Fig. 4 is a schematic diagram illustrating an example implementation of the boost circuit of fig. 2. .

Fig. 5 is a schematic diagram illustrating further details of an example implementation of the level shifter of fig. 4.

Fig. 6 is a graphical illustration depicting operation of the boost circuit of fig. 2 and/or fig. 3.

Fig. 7 is a graphical illustration depicting operation of the boost circuit of fig. 2 and/or 3 based on a more focused time scale.

Fig. 8 is a flow diagram representing a process that may be implemented by example machine readable instructions that may be executed to implement the controllers of fig. 2 and 3.

Fig. 9 is a flow diagram representing a process that may be implemented by example machine readable instructions that may be executed to implement the boost circuit of fig. 2, 4 and 5.

Fig. 10 is a block diagram of an example processing platform configured to execute the instructions of fig. 8 and 9 to implement the example controller of fig. 2 and 3, the example boost circuit of fig. 2 and 4, and/or the example level shifter of fig. 4 and 5.

The figures are not drawn to scale. Generally, the same reference numbers will be used throughout the drawings and the following written description to refer to the same or like parts. Unless otherwise specified, connection references (e.g., attached, coupled, connected, and joined) are to be construed broadly and may include intermediate members between a collection of elements and relative movement between elements. Thus, joinder references do not necessarily infer that two elements are directly connected and in fixed relation to each other.

The descriptors "first", "second", "third", etc. are used herein when identifying a plurality of elements or components that may be referred to individually. Unless otherwise indicated or understood according to their context of use, such descriptors are not intended to confer any meaning of priority, physical order or arrangement, or temporal order in the list, but are merely used as labels to refer to a plurality of elements or components, respectively, to facilitate understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in a particular embodiment, while different descriptors (e.g., "second" or "third") may be used in the claims to refer to the same element. In this case, it should be understood that such descriptors are used only for convenience to refer to a plurality of elements or components.

Detailed Description

The memory cells are used to store binary digital data (e.g., a bit value of 1 or 0, a logic high or low value, etc.) in a computing device and/or any suitable computing architecture (e.g., microcontroller, etc.). The memory cells may be included in an array of memory cells located in either volatile memory (e.g., Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc.) or nonvolatile memory (e.g., Read Only Memory (ROM), mask ROM, Programmable Read Only Memory (PROM), OTP memory (e.g., one time programmable memory array), Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory, etc.).

As previously mentioned, OTP memory is one type of non-volatile memory that may be programmed by an end user. The OTP memory array may include one or more memory cells, each memory cell including one or more memory devices (e.g., FGMOS). Non-volatile memory (e.g., OTP memory) stores binary data representing firmware code and/or low-level programs for read-only access. Where such firmware code and/or any low-level program is to be used, the corresponding memory bits stored in the memory cells may be sensed and/or otherwise read for use in volatile memory or elsewhere in the computing system and/or computing device.

Some types of non-volatile memories, such as OTP memories, are programmed using hot carrier injection. When hot carrier injection is utilized, a voltage (e.g., 8 volts (V)) that is higher than the rating (e.g., 5V) of the storage device (e.g., FGMOS) is applied to the storage device for a period of time. To avoid damaging and/or damaging the storage device, the nominal voltage of the storage device is selected such that it is high enough to withstand a higher voltage for the duration of the period. Non-volatile memories and memories in general typically include a multiplexer or other circuitry to read and/or otherwise sense the bit values stored in the memory cells. Because these multiplexers and/or other circuitry are coupled to the memory cells, they are similarly rated for higher voltages.

However, when reading non-volatile memory cells (e.g., OTP memory cells), power is saved with a voltage (e.g., 1.5V) that is lower than the nominal voltage (e.g., 5V). However, due to the higher voltage rating of the memory device (e.g., FGMOS), the read operation is slower, especially under the limitations of the operating region of the memory.

FIG. 1 is a schematic diagram 100 of a first OTP memory array 102, a second OTP memory array 104, a multiplexer 106, and a sense circuit 108. In fig. 1, first OTP memory array 102 includes a first OTP memory cell 110 and a second OTP memory cell 112. Also, in fig. 1, second OTP memory array 104 includes a third OTP memory cell 114 and a fourth OTP memory cell 116.

In fig. 1, the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114, and the fourth OTP memory cell 116 include respective positive channel (P-channel) mosfets (pmoss) 118, 120, 122, 124 (e.g., positive channel switch (s)). Furthermore, the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114 and the fourth OTP memory cell 116 include respective FGMOS switches 126, 128, 130, 132. In fig. 1, controller 134 is operable to load a respective memory bit in any one of first OTP memory cell 110, second OTP memory cell 112, third OTP memory cell 114, and/or fourth OTP memory cell 116 via a first word line (line 105) or a second word line (line 107).

In fig. 1, multiplexer 106 is a two-to-one pass-through multiplexer that includes a first array of PMOS switches 136, a first array (negative channel) n-channel mosfet (NMOS) switches 138 (e.g., negative channel switches), a second array of PMOS switches 140, a second array of NMOS switches 142, and a decoder 144. The multiplexer 106 may operate based on a memory address value associated with a control signal (line 113) decoded by the decoder 144 to conduct current through the first array PMOS switch 136 and the first array NMOS switch 138 or to conduct current through the second array PMOS switch 140 and the second array NMOS switch 142.

To read a bit value stored in a selected one of the first, second, third, or fourth OTP memory cells 110, 112, 114, or 116, the controller 134 generates a control signal (line 113) for use by the controller 134The multiplexers 106 are used to enable and/or disable the respective first array PMOS switches 136, first array NMOS switches 138, second array PMOS switches 140, or second array NMOS switches 142. At substantially the same time (e.g., within a few microseconds), the reference signal (line 115) is transmitted to the reference current generator 146. In operation, the reference signal (line 115) instructs the reference current generator 146 to generate a reference current (I) for the sensing circuit 108_REF). Likewise, multiplexer 106 conducts a bit current (I) based on a memory address value associated with a control signal (line 113) and whether a memory bit is stored in a selected one of first OTP memory cell 110, second OTP memory cell 112, third OTP memory cell 114, or fourth OTP memory cell 116_BIT)。

In fig. 1, the voltage rating of each of the multiplexer 106, the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114, and the fourth OTP memory cell 116 is much higher than the voltages of the sensing circuit 108, the reference current generator 146, and the computing system 148 (e.g., 5V versus 1.5V).

In fig. 1, when performing a read operation of a memory bit stored in one or more of first OTP memory cell 110, second OTP memory cell 112, third OTP memory cell 114, or fourth OTP memory cell 116, controller 134 generates a control signal (line 113) for use by decoder 144. Based on the control signal (line 113), the decoder 144 generates at least one signal to operate the multiplexer 106 at a voltage much lower than the rated voltage of the multiplexer 106 (e.g., 1.5V versus 5V). Threshold voltage (Vthreshold) of one or more of the first array PMOS switch 136, the first array NMOS switch 138, the second array PMOS switch 140, and the second array NMOS switch 142 due to the fabrication process of one or more of the first array PMOS switch 136, the first array NMOS switch 138, the second array PMOS switch 140, and the second array NMOS switch 142_t) Above the threshold voltage of the lower rated components. Therefore, in order to make the bit current (I)_BIT) The voltage level capable of conducting through the multiplexer 106, the control signal (line 113) and/or the resulting signal generated by the decoder 144 should be high enough for the firstOne or more of the array PMOS switch 136, the first array NMOS switch 138, the second array PMOS switch 140, and the second array NMOS switch 142 saturate.

In fig. 1, the speed of the read operation is affected because the voltage of the control signal (line 113) and the resulting signal and/or signals generated by the decoder 144 are not high enough to saturate one or more of the first array PMOS switch 136, the first array NMOS switch 138, the second array PMOS switch 140, and the second array NMOS switch 142 of the multiplexer 106. For example, particularly under the limitations of the operating region of the multiplexer 106, read operations can be so greatly affected as to hinder the function of the multiplexer. More specifically, access times (e.g., the time it takes to read and/or sense data, instructions, and information stored in first OTP memory array 102 or second OTP memory array 104) and cycle times (e.g., the time between one access of first OTP memory array 102 or second OTP memory array 104 and a subsequent access to first OTP memory array 102 or second OTP memory array 104) may cause a bit current (I) depending on first OTP memory array 102 or second OTP memory array 104_BIT) The speed of conduction of. As shown in fig. 1, the read operation (e.g., access time and cycle time above (e.g., meeting) the threshold) may be limited to a voltage of the control signal (line 113) and/or a voltage of one or more signals generated by the decoder 144 being 1.35V or below 1.35V. As shown in fig. 1, read operations (e.g., access times and cycle times above (e.g., meeting) a threshold) may be limited to temperatures at or below-40 ℃.

Examples disclosed herein include methods and apparatus to improve performance while reading and/or otherwise detecting memory bits stored in a memory. In examples disclosed herein, the reliable operating region over which read operations of OTP memories are reliable is improved. Further, when utilizing examples disclosed herein, memory bits, instructions, and/or other information stored in first OTP memory unit 110, second OTP memory unit 112, third OTP memory unit 114, and/or fourth OTP memory unit 116 may be read by a processor, CPU, and/or other computing system without the use of additional volatile memory architectures.

Fig. 2 is a schematic diagram 200 of an example first OTP memory array 202, an example second OTP memory array 204, an example multiplexer 206, an example sense circuit 208, and an example boost circuit 236 to improve performance when reading one or more of the first OTP memory array 202 and/or the second OTP memory array 204. In fig. 2, first OTP memory array 202 includes an example first OTP memory cell 210 and an example second OTP memory cell 212. Also, in fig. 2, second OTP memory array 204 includes an example third OTP memory cell 214 and an example fourth OTP memory cell 216. The schematic diagram 200 of fig. 2 also includes an example controller 234, an example boost circuit 236, an example decoder 246, an example inverter 247, an example reference current generator 248, and an example computing system 250. In other examples disclosed herein, there may be any number of OTP memory arrays configured in schematic diagram 200.

In fig. 2, first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and fourth OTP memory cell 216 include respective PMOS 218, 220, 222, 224. Furthermore, the first OTP memory cell 210, the second OTP memory cell 212, the third OTP memory cell 214 and the fourth OTP memory cell 216 include respective FGMOS switches 226, 228, 230, 232. In fig. 2, controller 234 is operable to load a respective memory bit into any of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and/or fourth OTP memory cell 216 via an example first word line (line 205) or an example second word line (line 207). In the example shown in fig. 2, charge is stored in the floating gates of the respective FGMOS switches 226, 228, 230, 232 in response to generating a logic low on either the first word line (line 205) or the second word line (line 207).

In the example of fig. 2, the voltage ratings (e.g., 5 volts) of the first OTP memory array 202, the second OTP memory array 204, and the multiplexer 206 are higher than the voltage ratings (e.g., 1.5 volts) of the sense circuit 208 and the reference current generator 248. Although fig. 2 illustrates the voltage rating (e.g., 5 volts) of the first OTP memory array 202, the second OTP memory array 204, and the multiplexer 206 being higher than the voltage rating (e.g., 1.5 volts) of the sense circuit 208 and the reference current generator 248, any suitable voltage rating may be used to implement the first OTP memory array 202, the second OTP memory array 204, the multiplexer 206, the sense circuit 208, and/or the reference current generator 248.

In fig. 2, the multiplexer 206 is a two-to-one pass-through multiplexer that includes an example first array of PMOS switches 238, an example first array of NMOS switches 240, an example second array of PMOS switches 242, and an example second array of NMOS switches 244. The first array of PMOS switches 238 includes a gate (e.g., a control terminal) coupled to an output of the decoder 246 (e.g., a first select signal (line 221)), sources (e.g., current terminals) coupled to the first OTP memory cell 210 and the second OTP memory cell 212, and a drain (e.g., a current terminal) coupled to the sense circuit 208. The first array NMOS switch 240 includes a gate (e.g., a control terminal) coupled to an output (e.g., a boosted control signal (line 215a)) of the boost circuit 236, drains (e.g., current terminals) coupled to the first OTP memory cell 210 and the second OTP memory cell 212, and a source (e.g., a current terminal) coupled to the sense circuit 208. The second array PMOS switch 242 includes a gate (e.g., a control terminal) coupled to the output of the inverter 247, sources (e.g., current terminals) coupled to the third OTP memory cell 214 and the fourth OTP memory cell 216, and a drain (e.g., a current terminal) coupled to the sense circuit 208. The second array NMOS switch 244 includes a gate (e.g., a control terminal) coupled to an output of the boost circuit 236 (e.g., a supplemental (compensated) boosted control signal (line 215b)), a drain (e.g., a current terminal) coupled to the third OTP memory cell 214 and the fourth OTP memory cell 216, and a source (e.g., a current terminal) coupled to the sense circuit 208.

In the example of fig. 2, multiplexer 206 may operate based on the polarity of the example select signals (lines 221, 223) generated by decoder 246 and/or the example boosted control signal (line 215a) and/or the example supplemented boosted control signal (line 215b) generated by boost circuit 236. In operation, the controller 234 transmits the example control signal (line 213) to the boost circuit 236 and the boost circuit 236 generates and transmits the example boosted control signal (line 215a) and/or the example supplemental boosted control signal (line 215b) to the multiplexer 206 based on the polarity of the select signal (lines 221, 223). Further, the controller 234 transmits an example decoded signal (line 231) to the decoder 246. As a result, the decoder 246 generates select signals (lines 221, 223) based on the decoded signal (line 231) to cause current to conduct through the first array PMOS switch 238 and the first array NMOS switch 240 or to cause current to conduct through the second array PMOS switch 242 and the second array NMOS switch 244 in conjunction with the boosted control signal (line 215a) and/or the supplemental boosted control signal (line 215 b).

For example, if the first word line (line 205) is a logic low value, the second word line (line 207) is a logic high value, the first select signal (line 221) is a logic high value, the second select signal (line 223) is a logic low value, and the control signal (line 213) is a logic high value, then the boosted control signal (line 215a) is a logic low value, the voltage level of the supplemental boosted control signal (line 215b) is boosted and the memory bit (if any) stored in the third OTP memory cell 214 will be sensed and/or otherwise read. Further in such an example, if a memory bit is stored in third OTP memory cell 214 and a select signal (lines 221, 223) and/or a control signal (line 213) indicate sensing and/or otherwise reading the memory bit stored in third OTP memory cell 214, then a bit current (I) is exemplified_BIT) Will pass through the second array PMOS switch 242 and the second array NMOS switch 244.

Alternatively, in another example disclosed herein, if the first word line (line 205) is a logic high value, the second word line (line 207) is a logic low value, the first select signal (line 221) is a logic low value, the second select signal (line 223) is a logic high value, and the control signal (line 213) is a logic high value, the voltage level of the boosted control signal (line 215a) is boosted, the supplemental boosted control signal (line 215b) is a logic low value, and the memory bit stored in the second OTP memory cell 212 (if the first word line (line 205) is a logic high value, the second word line (line 207) is a logic low value, and the control signal (line 213) is a logic high valueIf any) will be sensed and/or otherwise read. Further in such an example, if a memory bit is stored in second OTP memory cell 212 and the select signal (lines 221, 223) and/or the control signal (line 213) indicate sensing and/or otherwise reading the memory bit stored in second OTP memory cell 212, the bit current (I) is_BIT) Will conduct through the first array PMOS switch 238 and the first array NMOS switch 240. In examples disclosed herein, the bit current (I) is if the memory bit is stored in a selected one of the first OTP memory cell 210, the second OTP memory cell 212, the third OTP memory cell 214, or the fourth OTP memory cell 216_BIT) May be 0.5 milliamps, 1.0 milliamps, etc. Table 1 below illustrates example voltage values when reading memory cells of the first OTP memory array 202.

Signal	Voltage level (volt)
		Control signal (line 213)	1.5
Boosted control signal (line 215a)	2.4
		Supplemental boosted control signal (line 215b)	0
First selection signal (line 221)	0
		Second selection signal (line 223)	1.5
Decoding signal (line 231)	0

TABLE 1

Table 2 below illustrates example voltage values when reading memory cells of the second OTP memory array 204.

Signal	Voltage level (volt)
		Control signal (line 213)	1.5
Boosted control signal (line 215a)	0
		Supplemental boosted control signal (line 215b)	2.4
First selection signal (line 221)	1.5
		Second selection signal (line 223)	0
Decoding signal (line 231)	1

TABLE 2

In the example shown in fig. 2, sensing circuit 208 is operable to sense and/or otherwise read a memory bit (if any) stored in a selected one of first OTP memory cell 210, second OTP memory cell 212, first OTP memory cell 210. In the example of fig. 2, if a memory bit is stored in a selected one of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216, and such corresponding memory cell is selected to be sensed and/or otherwise read via a select signal (lines 221, 223) and/or a control signal (line 213), the bit current (I) is_BIT) Passes through the multiplexer 206.

In the example shown in fig. 2, controller 234 is coupled to first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, fourth OTP memory cell 216, boost circuit 236, decoder 246, and reference current generator 248. In the examples disclosed herein, the controller 234 is implemented as a single controller operable to at least: a memory bit loaded in any of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and/or fourth OTP memory cell 216, which of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216 is selected for sensing and/or otherwise reading via a control signal (line 213) and/or a decode signal (line 231), and/or a reference current is generated and/or otherwise caused to be generated via a reference signal (line 217). In the example of fig. 2, the controller 234 is a CPU that includes a memory controller. In other examples disclosed herein, any number of suitable controllers may be configured to perform the operations of controller 234.

In fig. 2, controller 234 is operable to load a memory bit into first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and/or fourth OTP memory cell 216 based on a logic value on either a first word line (line 205) or a second word line (line 207)Any one of (1). In such an example, a user may indicate that certain programs and/or low-level codes are to be converted to binary digital data by controller 234 and stored in a selected one of first OTP memory unit 210, second OTP memory unit 212, third OTP memory unit 214, and/or fourth OTP memory unit 216. Controller 234 is operable to generate and/or otherwise provide control signals (line 213) and/or decode signals (line 231) to boost circuit 236 and/or decoder 246 to indicate which of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216 is to be sensed and/or otherwise read (e.g., sense a memory bit, if any). Further, the controller 234 may be operable to generate the reference signal (line 217) and/or otherwise provide the reference signal (line 217) to the reference current generator 248 to generate the reference current (I)_REF). Further operation of the controller 234 will be explained below in conjunction with fig. 3.

In the example shown in fig. 2, the voltage boost circuit 236 is a voltage level (V) to the control signal (line 213) and/or the select signal (lines 221, 223)_CONTROL) A circuit for applying a boost voltage. For example, if the voltage level of the control signal (line 213) is 1.5V, the boosting circuit 236 applies a boosting of about 500-900 millivolts (mV) to the control signal (line 213). The resulting control signal, i.e., the boosted control signal (line 215a) or the supplemental boosted control signal (line 215b), is selected based on the polarity of the select signal (lines 221, 223). The voltage level of the resulting control signal (e.g., the boosted control signal (line 215a) and/or the supplemental boosted control signal (line 215b)) is at a voltage level (V) between 2.0V and 2.4V_BOOST). Further operation of the boost circuit 236 is explained below in conjunction with fig. 4.

In fig. 2, the example reference current generator 248 senses the circuit 208 and the controller 234. In the examples disclosed herein, the reference current generator 248 is implemented external to the controller 234. Alternatively, in other examples disclosed herein, the reference current generator 248 may be implemented internally within the controller 234. The reference current generator 248 is configured to obtain and/or toOther ways of receiving an indication of the reference current (I)_REF) A reference signal of desired amplitude (line 217). For example, the reference signal (line 217) may indicate a desired reference current (I) of 0.1 milliamps (mA)_REF) Thus, the reference current generator 248 is configured to generate the reference current (I) at a desired current of 0.1mA_REF). In some examples disclosed herein, the sensing circuitry 208 may be included in the controller 234.

In the example shown in fig. 2, a computing system 250 is coupled to the output of the sensing circuit 208. In examples disclosed herein, the computing system 250 may be a volatile memory configured to receive an indication of sensed and/or otherwise read memory bits. In such examples disclosed herein, computing system 250 may download and/or otherwise load memory bits from any of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and/or fourth OTP memory cell 216 for reprogramming, use, and/or any other suitable application. In other examples disclosed herein, computing system 250 may be a processor and/or suitable processing device configured to obtain memory bits stored in any of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and/or fourth OTP memory cell 216.

In some examples disclosed herein, the sensing circuit 208, the boost circuit 236, the reference current generator 248, and/or the decoder 246 may be included in the controller 234.

Fig. 3 is a block diagram 300 illustrating the example controller 234 of fig. 2. The controller 234 of fig. 3 includes an example signal analyzer 302, an example signal generator 304, and an example sensing interface 306. In examples disclosed herein, any of signal analyzer 302, signal generator 304, and/or sensing interface 306 may communicate wired and/or wireless communications to a respective device internal to controller 234 and/or external to controller 234 via any suitable method.

In the example shown in fig. 3, signal analyzer 302 is configured to determine whether an indication of a sensed and/or read memory bit is obtained and/or otherwise received. In fig. 3, signal analyzer 302 operates in controller 234 based on a command indicating a pre-initialization of sensing and/or otherwise reading a memory bit. For example, during boot-up of controller 234, signal analyzer 302 may respond to a pre-initialized command that instructs sensing and/or otherwise reading of memory bits stored in non-volatile memory (e.g., first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216). In other examples disclosed herein, signal analyzer 302 may be configured to determine whether to obtain an indication of sensing and/or reading a memory bit based on communication with a user interface and/or any suitable input device. In response to an indication to sense and/or read a memory bit, signal analyzer 302 analyzes the indication to determine which of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216 is to be accessed for sensing and/or reading. In examples disclosed herein, the signal analyzer 302 may be a signal analyzer controller.

In the example shown in fig. 3, signal generator 304 is configured to obtain an indication and/or determination from signal analyzer 302 to generate a corresponding logical value on a signal associated with a word line of a selected memory cell to be read. For example, signal generator 304 may generate a logic low value on an example word line (e.g., first word line (line 205) and/or second word line (line 207)) to store a memory bit in any of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and/or fourth OTP memory cell 216, respectively. Further, the signal generator 304 may generate the example reference signal of fig. 2 (line 217) for use by the reference current generator 248 of fig. 2. In examples disclosed herein, the signal generator 304 may be a signal generator controller.

In the example shown in fig. 3, the sense interface 306 is configured to generate the example control signal (line 213) of fig. 2 for use by the boost circuit 236 of fig. 2. Further, the sensing interface 306 is configured to generate the example decoded signal of fig. 2 (line 231) for use by the decoder 246 of fig. 2. In examples disclosed herein, the sensing interface 306 is configured to generate a control signal (line 213) to cause the boost circuit 236 to generate a boosted control signal (line 215a) and/or a supplemental boosted control signal (line 215 b). In examples disclosed herein, the sensing interface 306 may be a sensing interface controller.

In some examples disclosed herein, the signal generator 304 and/or the sensing interface 306 may be included in a memory controller. Alternatively, in other examples disclosed herein, the controller 234 may include the boost circuit 236 and/or the reference current generator 248 of fig. 2.

Fig. 4 is a schematic diagram illustrating an example implementation of the boost circuit 236 of fig. 2. The boost circuit 236 of fig. 4 includes an example boost network 402, an example first level shifter 404a, an example second level shifter 404b, and a voltage input 406. The example boost network 402 includes an example first input 408, an example second input 410, and an example output 412, an example first inverter 414, an example second inverter 416, an example third inverter 418, an example fourth inverter 420, an example fifth inverter 422, an example first switch 424, an example second switch 426, an example third switch 428, and an example capacitor 430. The example first level shifter 404a includes an example first input 432a, an example second input 434a, an example third input 436a, an example fourth input 437a, and an example output 438 a. The example second level shifter 404b includes an example first input 432b, an example second input 434b, an example third input 436b, an example fourth input 437b, and an example output 438 b.

In the example of fig. 4, the example first switch 424 is an NMOS transistor that includes an example gate 440 (e.g., a control terminal), an example source 442 (e.g., a current terminal), and an example drain 444 (e.g., a current terminal). The example second switch 426 is a PMOS transistor that includes an example gate 446 (e.g., a control terminal), an example source 448 (e.g., a current terminal), and an example drain 450 (e.g., a current terminal). The example third switch 428 is a PMOS transistor that includes an example gate 452 (e.g., a control terminal), an example source 454, and an example drain 456. The example capacitor 430 includes an example first terminal 458 (e.g., a first plate) and an example second terminal 460 (e.g., a second plate).

In the example of fig. 4, the boost network 402 is a network that receives a control signal (line 213) at a first input 408 and an input voltage V at a voltage input 406_DDThe circuit of (1). For example, the voltage level at the voltage input 406 may be 1.5 volts (e.g., V)_DD1.5V). In operation, the boost network 402 boosts the voltage level of the control signal (line 213) to improve the operating area over which the controller can sense the memory. For example, boost network 402 may increase the voltage level of the control signal (line 213) by 500 mV. In operation, the boost network 402 outputs a boosted signal at output 412. For example, when a controller (e.g., controller 234) sends a control signal (line 213) and/or a decoder (e.g., decoder 246) transmits a select signal (lines 221, 223) to read a bit from a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), the logic values of the control signal (line 213), the select signal (lines 221, 223) may vary depending on which memory array (e.g., first OTP memory array 202 versus second OTP memory array 204) is selected. Further, when a controller (e.g., controller 234) sends a control signal (line 213) to not read a bit from the memory array, the logic value of the control signal (line 213) may be a logic low value.

In the example shown in fig. 4, the first level shifter 404a is a device that receives a first input signal and shifts the voltage level of an output signal to a voltage level specified by a second input signal. In fig. 4, the first level shifter 404a receives the second selection signal (line 223) at the first input 432a and the first selection signal (line 221) at the second input 434 a. For example, a first input 432a and a second input 434a are coupled to the output of the decoder 246. In the example of fig. 4, the third input 436a is coupled to the output 412, the fourth input 437a is coupled to a reference voltage node (e.g., GND, zero volts, etc.), and the output 438a is coupled to the first array NMOS switch 240. In operation, the first level shifter 404a receives a first selection signal (line 221) at the second input 434a, a second selection signal (line 223) at the first input 432a, and a signal at the output 412 of the boost network 402. In operation, the first level shifter 404a shifts the voltage level of the signal at the output 438a (e.g., the boosted control signal (line 215a)) from the voltage level of the signal at the first input 432a (e.g., a logic high value or a logic low value) to the voltage level of the signal at the third input 436a (e.g., the voltage level of the signal at the output 412) when the logic value at the first input 432a (e.g., the second select signal (line 223)) and the logic value at the second input 434a (e.g., the first select signal (line 221)) are a logic high value and a logic low value, respectively.

In the example shown in fig. 4, the second level shifter 404b is a device that receives the first input signal and shifts the voltage level of the output signal to the voltage level specified by the second input signal. In fig. 4, the second level shifter 404b receives a first selection signal (line 221) at a first input 432b and a second selection signal (line 223) at a second input 434 b. For example, a first input 432b and a second input 434b are coupled to the output of the decoder 246. In the example of fig. 4, the third input 436b is coupled to the output 412, the fourth input 437b is coupled to a reference voltage node (e.g., GND, zero volts, etc.), and the output 438b is coupled to the second array NMOS switch 244. In operation, the second level shifter 404b receives a first selection signal (line 221) at a first input 432b, a second selection signal (line 223) at a second input 434b, and a signal at the output 412 of the boost network 402. In operation, the second level shifter 404b shifts the voltage level of the signal at the output 438b (e.g., the supplemental boosted control signal (line 215a)) from the voltage level of the signal at the first input 432b (e.g., a logic high value or a logic low value) to the voltage level of the signal at the third input 436b (e.g., the voltage level of the signal at the output 412) when the logic value at the first input 432b (e.g., the first selection signal line 221) and the logic value of the second input 434b (e.g., the second selection signal (line 223)) are a logic high value and a logic low value, respectively.

In the example shown in fig. 4, each of the first inverter 414, the second inverter 416, the third inverter 418, the fourth inverter 420, and the fifth inverter 422 is a not gate including an input and an output. An input of the first inverter 414 is coupled to the first input 408 and an output of the first inverter 414 is coupled to an input of the second inverter 416. In operation, the first inverter 414 receives the control signal (line 213) and inverts the logic value of the control signal (line 213).

In the example shown in fig. 4, an input of the second inverter 416 is coupled to an output of the first inverter 414 and an output of the second inverter 416 is coupled to an input of the third inverter 418 and an input of the fourth inverter 420. In operation, the second inverter 416 receives the signal at the output of the first inverter 414 and inverts the logic value of the signal at the output of the first inverter 414.

In the example of fig. 4, the input of the third inverter 418 is coupled to the output of the second inverter 416 and the output of the third inverter 418 is coupled to the gate 440 of the first switch 424 and the gate 452 of the third switch 428. In operation, the third inverter 418 receives the signal at the output of the second inverter 416 and inverts the logic value of the signal at the output of the second inverter 416.

In the example shown in fig. 4, an input of the fourth inverter 420 is coupled to an output of the second inverter 416 and an output of the fourth inverter 420 is coupled to an input of the fifth inverter 422. In operation, the fourth inverter 420 receives the signal at the output of the second inverter 416 and inverts the logic value of the signal at the output of the second inverter 416.

In the example shown in fig. 4, the input of the fifth inverter 422 is coupled to the output of the fourth inverter 420 and the output of the fifth inverter 422 is coupled to the second terminal 460 of the capacitor 430. In operation, the fifth inverter 422 receives the signal at the output of the fourth inverter 420 and inverts the logic value of the signal at the output of the fourth inverter 420.

In the example of fig. 4, the gate 440 of the first switch 424 is coupled to the output of the third inverter 418 and the gate 452 of the third switch 428. The source 442 of the first switch 424 is coupled to a reference voltage node (e.g., GND, zero volts, etc.). Drain 444 of first switch 424 is coupled to drain 456 of third switch 428 and to gate 446 of second switch 426. In operation, during a read operation of a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), the logic value at gate 440 of first switch 424 can be a logic low value. Additionally, when a bit is not being read from the memory array, the logic value at the gate 440 of the first switch 424 may be a logic high value.

Thus, prior to a read operation of a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), first switch 424 is enabled and a voltage level at drain 450 of first switch 424 may correspond to zero volts. During a read operation of the memory arrays (e.g., first OTP memory array 202, second OTP memory array 204), first switch 424 is disabled.

In the example of fig. 4, the gate 446 of the second switch 426 is coupled to the drain 444 of the first switch 424 and the drain 456 of the third switch 428. The source 448 of the second switch 426 is coupled to the voltage input 406 (e.g., V) via the second input 410_DD). A drain 450 of the second switch 426 is coupled to a source 454 of the third switch 428 and a first terminal 458 (e.g., output 412) of the capacitor 430. In operation, during a read operation of a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), the logic value at gate 446 of second switch 426 may be floating (e.g., at an indeterminate voltage level, rather than at a zero voltage level, etc.). Additionally, when a bit is not being read from a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), the logic value at gate 446 of second switch 426 may be a logic low value.

Thus, prior to a read operation of a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), second switch 426 is enabled and a voltage level at drain 450 of second switch 426 may correspond to a voltage level at voltage input 406 (e.g., V_DD). During a read operation of a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), second switch 426 is disabled.

In the example of fig. 4, the gate 452 of the third switch 428 is coupled to the output of the third inverter 418 and the gate 440 of the first switch 424. A source 454 of the third switch 428 is coupled to the drain 450 of the second switch 426 and a first terminal 458 (e.g., output 412) of the capacitor 430. A drain 456 of the third switch 428 is coupled to the gate 446 of the second switch 426 and the drain 444 of the first switch 424. In operation, during a read operation of a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), the logic value at the gate 452 of the third switch 428 may be a logic low value. Additionally, when a bit is not being read from a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), the logic value at the gate 452 of the third switch 428 may be a logic high value.

Thus, prior to a read operation of a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), third switch 428 is disabled. During a read operation of a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), third switch 428 is enabled and a voltage level at source 454 of third switch 428 may be floating and dependent on a voltage level at first terminal 458 of capacitor 430.

In the example of fig. 4, the capacitor 430 is a bulk capacitor. A first terminal 458 of the capacitor 430 is coupled to the output 412, a source 454 of the third switch 428, and a drain 450 of the second switch 426. In operation, the capacitor 430 charges based on the voltage level at the drain 450 of the second switch 426. In operation, the voltage level at the second terminal 460 of the capacitor 430 is used as the reference voltage level for the output 412. For example, when a controller (e.g., controller 234) sends a control signal (line 213) to read a bit from a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), the logical value of the control signal (line 213) may be a logical high value. Thus, the voltage level at the second terminal 460 of the capacitor 430 may be a logic high value voltage level. Additionally, the logical value of the control signal (line 213) may be a logical low value when no bits are read from the memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.). Thus, the voltage level at the second terminal 460 of the capacitor 430 may be zero volts.

Additionally, when a bit is not being read from a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), the voltage value at first terminal 458 (e.g., output 412) may be equal to the voltage level at voltage input 406 (e.g., V_DD) And the voltage level at the second terminal 460 may be a logic low value (e.g., zero volts). Thus, prior to a read operation of a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), capacitor 430 may be charged to a voltage level (e.g., V) of voltage input 406_DD). When a controller (e.g., controller 234) transmits a logic high value as the control signal (line 213) (e.g., initiates a read operation), the control signal (line 213) transitions from a logic low value to a logic high value. The rising edge on the control signal (line 213) increases the voltage level at the second terminal 460 of the capacitor 430 to a logic high value before the capacitor 430 discharges. Thus, as the capacitor 430 discharges, the voltage level at the first terminal 458 (e.g., output 412) of the capacitor 430 is boosted.

Furthermore, because the voltage level of the signal at output 412 is raised by the rising edge of the control signal (line 213), first level shifter 404a and/or second level shifter 404b correspondingly raise the voltage level of the raised control signal (line 215a) and/or the supplemental raised control signal (line 215b), respectively, to multiplexer 206. Accordingly, the reliable operating area over which read operations of the memory arrays (e.g., first OTP memory array 202, second OTP memory array 204, etc.) are reliable is improved. For example, because the voltage level of the signal at the output 412 is boosted, one or more of the first array NMOS switch 240 or the second array NMOS switch 244 may be more fully saturated. Thus, the bit current (I) may be more reliably sensed by the sensing circuit (e.g., the sensing circuit 208)_BIT) And an operation area on which a read operation of the memory array is reliable is improved. Additionally, due to the boosted level at the output 412 of the boost network 402, memory bits, instructions, and/or other information stored in the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.) may be processed by the processor,The CPU and/or other computing system reads without using additional volatile memory architectures.

Fig. 5 is a schematic diagram illustrating further details of an example implementation of the first level shifter 404a and/or the second level shifter 404b of fig. 4. The example first level shifter 404a and/or the example second level shifter 404b includes an example shifting network 502, an example first inverter 504, and an example second inverter 506. The example shift network 502 includes a first switch 508, a second switch 510, a third switch 512, a fourth switch 514, a fifth switch 516, and a sixth switch 518. The example first inverter 504 includes an example seventh switch 520 and an example eighth switch 522. The example second inverter 506 includes an example ninth switch 524 and an example tenth switch 526.

In the example of fig. 5, each of the first switch 508, the second switch 510, the eighth switch 522, and the tenth switch 526 is an NMOS transistor that includes an example gate (e.g., a control terminal), an example drain (e.g., a current terminal), and an example source (e.g., a current terminal). In addition, each of the third, fourth, fifth, sixth, seventh and ninth switches 512, 514, 516, 518, 520 and 524 is a PMOS transistor that includes an example gate (e.g., a control terminal), an example drain (e.g., a current terminal) and an example source (e.g., a current terminal).

In the example shown in fig. 5, the gate of the first switch 508 is coupled to the first input 432a of the first level shifter 404a and/or the first input 432b of the second level shifter 404b and the gate of the fifth switch 516. The gate of the first switch 508 receives a signal at a first input 432a (e.g., the second selection signal (line 223)) and/or a first input 432b (e.g., the first selection signal (line 221)). The drain of the first switch 508 is coupled to the drain of the fifth switch 516 and to the gate of the third switch 512. The source of the first switch 508 is coupled to a reference voltage node (e.g., GND, zero volts, etc.) at the fourth input 437a and/or 437 b.

In the example shown in fig. 5, the gate of the second switch 510 is coupled to the second input 434a and/or 434b and the gate of the fourth switch 514. The gate of the second switch 510 receives a signal at a second input 434a (e.g., the first selection signal (line 221)) and/or a second input 434b (e.g., the second selection signal (line 223)). The drain of the second switch 510 is coupled to the drain of the fourth switch 514, the gate of the sixth switch 518, the gate of the seventh switch 520, and the gate of the eighth switch 522. The source of the second switch 510 is coupled to a reference voltage node (e.g., GND, zero volts, etc.) at the fourth input 437a and/or 437 b.

In the example shown in fig. 5, the gate of the third switch 512 is coupled to the drain of the first switch 508 and the drain of the fifth switch 516. The drain of the third switch 512 is coupled to the source of the fourth switch 514 and the source of the third switch 512 is coupled to the third input 436a and/or the third input 436b and receives the signal at the output 412.

In the example shown in fig. 5, the gate of the fourth switch 514 is coupled to the gate of the second switch 510 and to the second input 434a and/or the second input 434 b. The gate of the fourth switch 514 receives a signal at a second input 434a (e.g., the first selection signal (line 221)) and/or a second input 434b (e.g., the second selection signal (line 223)). The drain of the fourth switch 514 is coupled to the drain of the second switch 510, the gate of the sixth switch 518, the gate of the seventh switch 520, and the gate of the eighth switch 522. The source of the fourth switch 514 is coupled to the drain of the third switch 512.

In the example of fig. 5, the gate of the fifth switch 516 is coupled to the gate of the first switch 508 and the first input 432a and/or the first input 432 b. The gate of the fifth switch 516 receives a signal at a first input 432a (e.g., the second selection signal (line 223)) and/or a first input 432b (e.g., the first selection signal (line 221)). The drain of the fifth switch 516 is coupled to the drain of the first switch 508 and the gate of the third switch 512. The source of the fifth switch 516 is coupled to the drain of the sixth switch 518.

In the example shown in fig. 5, the gate of sixth switch 518 is coupled to the drain of second switch 510, the drain of fourth switch 514, the gate of seventh switch 520, and the gate of eighth switch 522. A drain of the sixth switch 518 is coupled to a source of the fifth switch 516 and a source of the sixth switch 518 is coupled to the third input 436a and/or the third input 436b and receives the signal at the output 412.

In operation, the voltage level of the signal at the third input 436a and/or the third input 436b may correspond to the voltage level of the signal at the voltage input 406 (e.g., V_DD) And/or a boosted voltage level caused by a rising edge on the second terminal 460 of the capacitor 430 as the capacitor 430 discharges. The first switch 508 may be enabled and/or disabled based on a logic value of a signal at the first input 432a and/or the first input 432 b. The second switch 510 is deactivated. Additionally, the third switch 512 may be enabled and/or disabled based on the operation of the first switch 508 and/or the fifth switch 516. The fourth switch 514 is enabled. Further, the fifth switch 516 may be enabled and/or disabled based on a logic value of a signal at the first input 432a and/or the first input 432 b. The sixth switch 518 may be enabled and/or disabled based on operation of the second switch 510 and/or the fourth switch 514.

For example, when the shift network 502 receives a logic high value at the first input 432a and/or the first input 432b, the first switch 508 is enabled and the logic value at the gate of the third switch 512 is a logic low value, thereby enabling the third switch 512. Since the second switch 510 is disabled and the fourth switch 514 is enabled, the voltage levels at the drain of the second switch 510, the drain of the fourth switch 514, the gate of the sixth switch 518, the gate of the seventh switch 520, and the gate of the eighth switch 522 are set to the voltage levels of the signals at the third input 436a and/or the third input 436 b.

When the shift network 502 receives a logic low value at the first input 432a and/or the first input 432b, the first switch 508 is disabled, the fifth switch 516 is enabled and the logic value at the gate of the third switch 512 may be floating (e.g., at an indeterminate voltage level, rather than at a zero voltage level, etc.). Thus, the voltage levels at the drain of the second switch 510, the drain of the fourth switch 514, the gate of the sixth switch 518, the gate of the seventh switch 520, and the gate of the eighth switch 522 may be floating (e.g., at an indeterminate voltage level, rather than at a zero voltage level, etc.).

In the example shown in fig. 5, the gate of seventh switch 520 is coupled to the drain of second switch 510, the drain of fourth switch 514, the gate of sixth switch 518, and the gate of eighth switch 522. The drain of seventh switch 520 is coupled to the drain of eighth switch 522, the gate of ninth switch 524, and the gate of tenth switch 526. A source of the seventh switch 520 is coupled to the third input 436a and/or the third input 436b and receives the signal at the output 412.

In the example of fig. 5, a gate of eighth switch 522 is coupled to a drain of second switch 510, a drain of fourth switch 514, a gate of sixth switch 518, and a gate of seventh switch 520. A drain of eighth switch 522 is coupled to a drain of seventh switch 520, a gate of ninth switch 524, and a gate of tenth switch 526. The source of eighth switch 522 is coupled to second input 434a and/or second input 434b and receives a first select signal (line 221) and/or a second select signal (line 223).

When the first inverter 504 receives a logic high value at the gate of the seventh switch 520 and the gate of the eighth switch 522, the eighth switch 522 is enabled and the voltage levels at the drain of the seventh switch 520, the drain of the eighth switch 522, the gate of the ninth switch 524, and the gate of the tenth switch 526 are logic low values. When the first inverter 504 receives a logic low value at the gate of the seventh switch 520 and the gate of the eighth switch 522, the seventh switch 520 is enabled and the voltage levels at the drain of the seventh switch 520, the drain of the eighth switch 522, the gate of the ninth switch 524, and the gate of the tenth switch 526 are the voltage levels of the signals at the third input 436a and/or the third input 436 b.

In the example shown in fig. 5, the gate of the ninth switch 524 is coupled to the drain of the seventh switch 520 and the drain of the eighth switch 522. A drain of the ninth switch 524 is coupled to a drain of the tenth switch 526 and to the output 438a and/or the output 438 b. A source of the ninth switch 524 is coupled to the third input 436a and/or the third input 436b and receives the signal at the output 412.

In the example of fig. 5, the gate of the tenth switch 526 is coupled to the drain of the seventh switch 520 and the drain of the eighth switch 522. A drain of the tenth switch 526 is coupled to a drain of the ninth switch 524 and to the output 438a and/or the output 438 b. A source of the tenth switch 526 is coupled to the second input 434a and/or the second input 434b and receives the first selection signal (line 221) and/or the second selection signal (line 223).

When the second inverter 506 receives a logic high value at the gate of the ninth switch 524 and the gate of the tenth switch 526, the tenth switch 526 is enabled and the voltage levels at the drain of the ninth switch 524, the drain of the tenth switch 526, and the outputs 438a and/or 438b are logic low values. When the second inverter 506 receives a logic low value at the gate of the ninth switch 524 and the gate of the tenth switch 526, the ninth switch 524 is enabled and the voltage level at the drain of the ninth switch 524, the tenth switch 526, and the output 438a and/or the output 438b is the voltage level of the signal at the third input 436a and/or the third input 436 b.

Fig. 6 is a graphical illustration 600 depicting operation of the boost circuit 236 of fig. 2 and/or fig. 3. The illustration 600 includes an example first graph 602 and an example second graph 604. The example first graph 602 includes an example first line 606 and the example second graph 604 includes an example second line 608.

In the example of fig. 6, the first plot 602 is a plot of control signal (line 213) versus time. The first graph 602 includes a voltage axis (V)610 and a time axis (t) 612. The first line 606 corresponds to a voltage value of a signal (e.g., control signal (line 213)) at an input (e.g., first input 408) of the boost circuit 236.

In the example shown in fig. 6, the second plot 604 is a plot of boosted control signal (line 215a) and/or supplemental boosted control signal (line 215b) versus time. The second graph 604 includes a voltage axis (V)610 and a time axis (t) 612. The second line 608 corresponds to a voltage value of a signal (e.g., the boosted control signal (line 215a) and/or the supplemental boosted control signal (line 215b)) at an output (e.g., output 438a and/or output 438b) of the boost circuit 236.

In the example of fig. 6, each of the first graph 602 and the second graph 604 includes a first time 614t₁A second time 616t₂A third time 618t₃And a fourth time 620t₄. At the first timeAt time 614, first line 606 transitions from a logic low value (e.g., zero volts) to a logic high value (e.g., 1.5 volts) and second line 608 is at a voltage level of 1.5 volts. Due to the rising edge of the first line 606 at the first time 614, the voltage boost network 402 of the voltage boost circuit 236 boosts the voltage value of the output 438a of the first level shifter 404a and/or the output 438b of the second level shifter 404b from 1.5 volts to 2.4049 volts. For example, a rising edge on the first line 606 causes the voltage level at the first terminal 458 (e.g., output 412) of the capacitor 430 to be raised as the capacitor 430 discharges.

In the example shown in fig. 6, at a second time 616, the first line 606 is at a logic high value (e.g., 1.5 volts) and the second line 608 transitions from a voltage level of 2.4049 volts to a voltage level of 1.5 volts. For example, the second time 616 may correspond to a time when the capacitor 430 is discharged due to a voltage change caused by a rising edge on the first line 606 at the first time 614.

In the example of fig. 6, at a third time 618, first line 606 transitions from a logic low value (e.g., zero volts) to a logic high value (e.g., 1.5 volts) and second line 608 is at a voltage level of 1.5 volts. Due to the rising edge of the first line 606 at the third time 618, the voltage boost network 402 of the voltage boost circuit 236 boosts the voltage value of the output 438a of the first level shifter 404a and/or the output 438b of the second level shifter 404b from 1.5 volts to 2.4049 volts. For example, a rising edge on the first line 606 causes the voltage level at the first terminal 458 (e.g., output 412) of the capacitor 430 to be raised as the capacitor 430 discharges.

In the example shown in fig. 6, at a fourth time 620, first line 606 is at a logic high value (e.g., 1.5 volts) and second line 608 transitions from a voltage level of 2.4049 volts to a voltage level of 1.5 volts. For example, the fourth time 620 may correspond to a time when the capacitor 430 is discharged due to a voltage change caused by a rising edge on the first line 606 at the third time 618.

In the example of fig. 6, the reliable operating region over which the read operation of the first memory array (e.g., second OTP memory array 204) is improved due to the boosted voltage level of the second line 608 between the first time 614 and the second time 616 and between the third time 618 and the fourth time 620. Additionally, due to the boosted voltage level of the second line 608 between the first time 614 and the second time 616 and between the third time 618 and the fourth time 620, memory bits, instructions, and/or other information stored in the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.) may be read by the processor, CPU, and/or other computing system without using an additional volatile memory architecture.

Fig. 7 is a graphical illustration 700 depicting operation of the boost circuit 236 of fig. 2 and/or 3 based on a more centralized time scale. The illustration 700 includes an example graph 702. The example graph 702 includes an example first line 704 and an example second line 706.

In the example of fig. 7, the graph 702 is a plot of control signal (line 213) and boosted control signal (line 215a) and/or supplemental boosted control signal (line 215b) versus time. Graph 702 includes a voltage axis (V)708 and a time axis (t) 710. The first line 704 corresponds to a voltage value of a signal (e.g., the control signal (line 213)) at an input (e.g., the first input 408) of the boost circuit 236. The second line 706 corresponds to a voltage value of a signal (e.g., the boosted control signal (line 215a) and/or the supplemental boosted control signal (line 215b)) at an output (e.g., output 438a and/or output 438b) of the boost circuit 236.

In the example of fig. 7, the graph 702 includes a first time 712t₁A second time 714t₂And a third time 716t₃. At a first time 712, the first line 704 transitions from a logic low value (e.g., zero volts) to a logic high value (e.g., 1.5 volts) and the second line 706 is at a voltage level of 1.5 volts. Due to the rising edge of the first line 704 at the first time 712, the voltage boost network 402 of the voltage boost circuit 236 boosts the voltage value of the output 438a of the first level shifter 404a and/or the output 438b of the second level shifter 404b from 1.5 volts to 2.4049 volts at the second time 714. For example, a rising edge on the first line 704 causes the voltage level at the first terminal 458 (e.g., output 412) of the capacitor 430 to be raised as the capacitor 430 discharges.

In the example shown in fig. 7, at a third time 716, first line 704 is at a logic high value (e.g., 1.5 volts) and second line 706 transitions from a voltage level of 2.4049 volts to a voltage level of 1.5 volts. For example, the third time 716 may correspond to a time when the capacitor 430 is discharged due to a voltage change caused by a rising edge on the first line 704 at the first time 712.

In the example of fig. 7, due to the boosted voltage level of the second line 706 between the second time 714 and the third time 716, a reliable operating area over which a read operation of a memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.) is improved. Additionally, due to the boosted voltage level of the second line 706 between the second time 714 and the third time 716, memory bits, instructions, and/or other information stored in the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.) may be read by the processor, CPU, and/or other computing system without using an additional volatile memory architecture.

While example manners of implementing the controller 234 and/or the boost circuit 236 of fig. 2 are illustrated in fig. 3, 4, and 5, one or more of the elements, processes, and/or devices illustrated in fig. 3, 4, and 5 may be combined, divided, rearranged, omitted, eliminated, and/or implemented in any other manner. Further, the example signal analyzer 302, the example signal generator 304, the example sensing interface 306, and/or more generally, the example controller 234 and/or the example boost network 402, the example first level shifter 404a, the example second level shifter 404b, the example voltage input 406, the example first inverter 414, the example second inverter 416, the example third inverter 418, the example fourth inverter 420, the example fifth inverter 422, the example first switch 424, the example second switch 426, the example third switch 428, the example capacitor 430, and/or more generally, the example boost circuit 236 of fig. 2 and 4, and/or the example shift network 502, the example first inverter 504, the example second inverter 506, the example first switch 508, the example second switch 510, the example third switch 512, the example fourth switch 514 of fig. 2 and 4, The example fifth switch 516, the example sixth switch 518, the example seventh switch 520, the example eighth switch 522, the example ninth switch 524, the example tenth switch 526, and/or, more generally, the example first level shifter 404a and/or the example second level shifter 404b of fig. 4 and/or fig. 5 may be implemented by hardware, software, firmware, and/or any combination of hardware, software, and/or firmware. Thus, for example, the example signal analyzer 302, the example signal generator 304, the example sensing interface 306, and/or, more generally, the example controller 234 of fig. 2 and 3, and/or the example boost network 402, the example first level shifter 404a, the example second level shifter 404b, the example voltage input 406, the example first inverter 414, the example second inverter 416, the example third inverter 418, the example fourth inverter 420, the example fifth inverter 422, the example first switch 424, the example second switch 426, the example third switch 428, the example capacitor 430, and/or, more generally, the example boost circuit 236 of fig. 2 and 4, and/or the example shift network 502, the example first inverter 504, the example second inverter 506, the example first switch 508, the example second switch 510, the example third switch 512, the example fourth switch 514 of fig. 2 and 4, Any of example fifth switch 516, example sixth switch 518, example seventh switch 520, example eighth switch 522, example ninth switch 524, example tenth switch 526, and/or, more generally, example first level shifter 404a and/or example second level shifter 404b of fig. 4 and 5 may be implemented by one or more analog or digital circuits, logic circuits, programmable processor(s), programmable controller(s), graphics processing unit(s) (GPU), digital signal processor(s) (DSP), application specific integrated circuit(s) (ASIC), programmable logic device(s) (PLD), and/or field programmable logic device(s) (FPLD). When reading any apparatus or system claims of this patent to encompass pure software and/or firmware implementations, the example signal analyzer 302, the example signal generator 304, the example sensing interface 306, and/or, more generally, the example controller 234 of fig. 2 and 3, and/or the example boost network 402, the example first level shifter 404a, the example second level shifter 404b, the example voltage input 406, the example first inverter 414, the example second inverter 416, the example third inverter 418, the example fourth inverter 420, the example fifth inverter 422, the example first switch 424, the example second switch 426, the example third switch 428, the example capacitor 430, and/or, more generally, the example boost circuit 236 of fig. 2 and 4, and/or the example shift network 502, the example first inverter 504, the example second inverter 506, At least one of the example first switch 508, the example second switch 510, the example third switch 512, the example fourth switch 514, the example fifth switch 516, the example sixth switch 518, the example seventh switch 520, the example eighth switch 522, the example ninth switch 524, the example tenth switch 526, and/or more generally, the example first level shifter 404a and/or the second level shifter 404b of fig. 4 and 5 are expressly defined herein to include a non-transitory computer-readable storage device or storage disk, e.g., memory, Digital Versatile Disk (DVD), Compact Disk (CD), blu-ray disk, etc., containing software and/or firmware. Still further, the example controller 234 of fig. 2 and 3, the example boost circuit 236 of fig. 2 and 4, and/or the example first level shifter 404a and/or the example second level shifter 404b of fig. 4 and 5 may include one or more elements, processes and/or devices in addition to or in place of those illustrated in fig. 2, 3, 4 and/or 5, and/or may include one or more of any or all of the illustrated elements, processes and devices. As used herein, the phrase "communication," including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediate components and does not require direct physical (e.g., wired) communication and/or continuous communication, but additionally includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals, and/or one-time events.

A flowchart representative of example hardware logic, machine readable instructions, a hardware implemented state machine, and/or any combination thereof to implement the example controller 234 of fig. 2 and 3, the example boost circuit 236 of fig. 2 and 4, and/or the example first and/or second level shifters 404a, 404b of fig. 4 and 5 is shown in fig. 8 and 9. The machine-readable instructions may be one or more executable programs or portion(s) of executable programs that are executed by a computer processor, such as processor 1012 shown in the example processor platform 1000 discussed below in connection with fig. 10. The program may be embodied in software stored on a non-transitory computer readable storage medium such as a CD-ROM, a floppy disk, a hard drive, a DVD, a blu-ray disk, or a memory associated with the processor 1012, but the entire program and/or parts thereof could alternatively be executed by a device other than the processor 1012 and/or embodied in firmware or dedicated hardware. Further, although the example program is described with reference to the flowcharts illustrated in fig. 8 and 9, many other methods of implementing the example controller 234 of fig. 2 and 3, the example boost circuit 236 of fig. 2 and 4, and/or the example first and/or second level shifters 404a and 404b of fig. 4 and 5 may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and/or integrated analog and/or digital circuits, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuitry, etc.) configured to perform the respective operations without executing software or firmware.

The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented (fragmented) format, a packed format, and the like. Machine-readable instructions as described herein may be stored as data (e.g., portions, code representations, etc.) that may be used to create, fabricate, and/or generate machine-executable instructions. For example, machine-readable instructions may be fragmented and stored on one or more storage devices and/or computing devices (e.g., servers). The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combining, supplementing, configuring, decrypting, decompressing, unpacking, distributing, redistributing, etc., so that they may be directly read and/or executed by the computing device and/or other machine. For example, machine-readable instructions may be stored in multiple portions that are separately compressed, encrypted, and stored on separate computing devices, where the portions, when decrypted, decompressed, and combined, form a set of executable instructions that implement a program, such as the programs described herein. In another example, machine-readable instructions may be stored in a state where they are readable by a computer, but require the addition of libraries (e.g., Dynamic Link Libraries (DLLs)), Software Development Kits (SDKs), Application Programming Interfaces (APIs), and the like, in order to execute the instructions on a particular computing device or other device. In another example, machine readable instructions (e.g., stored settings, data input, recorded network address, etc.) may need to be configured before the machine readable instructions and/or corresponding program(s) can be executed in whole or in part. Accordingly, the disclosed machine readable instructions and/or corresponding program(s) are intended to encompass such machine readable instructions and/or program(s), regardless of the particular format or state of the machine readable instructions and/or program(s) when stored or otherwise at rest or in transit.

The machine-readable instructions described herein may be represented in any past, present, or future instruction language, scripting language, programming language, or the like. For example, the machine-readable instructions may be represented using any one of the following languages: C. c + +, Java, C #, Perl, Python, JavaScript, HyperText markup language (HTML), Structured Query Language (SQL), Swift, and the like.

As described above, the example processes of fig. 8 and 9 may be implemented using executable instructions (e.g., computer and/or machine readable instructions) stored on a non-transitory computer and/or machine readable medium (e.g., a hard disk drive, a flash memory, a read-only memory, a compact disk, a digital versatile disk, a cache, a random-access memory, and/or any other storage device or storage disk) wherein information is stored for any duration (e.g., for extended periods of time, permanently, for brief instances, for temporarily buffering, and/or for caching of the information). As used herein, the term non-transitory computer-readable medium is expressly defined to include any type of computer-readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media.

The terms "comprising" and "including" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim employs any form of "including" or "comprising" (e.g., including, comprising, having, etc.) as a preamble or in any type of claim recitation, it is to be understood that additional elements, terms, etc. may be present without departing from the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transitional term, e.g., in the preamble of the claims, it is open-ended in the same manner that the terms "comprising" and "including" are open-ended. The term "and/or" when used in the form of, for example A, B and/or C, refers to any combination or subset of A, B, C, such as (1) a alone, (2) B alone, (3) C alone, (4) a and B, (5) a and C, (6) B and C, and (7) a and B and C. As used herein in the context of describing structures, components, items, objects, and/or things, the phrase "at least one of a and B" is intended to refer to embodiments that include any one of (1) at least one a, (2) at least one B, and (3) at least one a and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and/or things, the phrase "at least one of a or B" is intended to refer to embodiments that include any one of (1) at least one a, (2) at least one B, and (3) at least one a and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, and/or steps, the phrase "at least one of a and B" is intended to refer to embodiments that include any one of (1) at least one a, (2) at least one B, and (3) at least one a and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities, and/or steps, the phrase "at least one of a or B" is intended to refer to embodiments that include any of (1) at least one a, (2) at least one B, and (3) at least one a and at least one B.

As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude a plurality. As used herein, the term "a" or "an" entity refers to one or more of that entity. The terms "a" (or "an"), "one or more" and "at least one" are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements or method acts may be implemented by e.g. a single unit or processor. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.

Fig. 8 is a flow chart representing a process 800, which process 800 may be implemented by example machine readable instructions executable to implement the controller 234 of fig. 2 and 3. In the example shown in fig. 8, the signal analyzer 302 of fig. 3 determines whether an indication to sense and/or read a memory bit is obtained and/or otherwise received (block 802). If control of block 802 returns no (e.g., if an indication to sense and/or read a memory bit is not obtained or received), control proceeds to block 802 and waits. Alternatively, if control of block 802 returns yes (e.g., if signal analyzer 302 obtains or receives an indication to sense and/or read a memory bit), signal analyzer 302 determines which memory cell (e.g., first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and/or fourth OTP memory cell 216) to access based on the received indication (block 804). In response to execution of the control of block 806, control proceeds to block 808.

At block 806, the sense interface 306 determines the memory array in which the selected one of the memory cells is included. At block 808, the sensing interface 306 generates a control signal (e.g., control signal (line 213)) and/or a decode signal (e.g., decode signal (line 231)) to enable conduction of the respective PMOS switches and the respective NMOS switches of the multiplexer 206 (block 808). In response to execution of the control of block 808, control proceeds to block 810.

In response, the controller 234 of fig. 2 and 3 determines whether to continue operation (block 810). If control of block 810 returns yes (e.g., the controller 234 determines to continue operation), control returns to block 802. Alternatively, if control of block 810 returns no (e.g., the controller 234 determines not to continue operation), the process 800 stops.

Fig. 9 is a flow diagram representing a process 900, which process 900 may be implemented by example machine readable instructions that may be executed to implement the boost circuit 236 of fig. 2, 4 and 5. In fig. 9, the boost network monitors the signal at the first input 408 (block 902). In response to a rising edge of the signal at the first input 408 (block 904: yes), the boost network 402 boosts the voltage level of the signal to be transmitted to the first level shifter 404a and/or the second level shifter 404b (e.g., boosts the voltage level of the signal at the output 412 of the boost network 402) (block 908). When no rising edge is detected on the signal at the first input 408 (block 904: No), the boost network 402 will voltage the signal at the input 406 (e.g., V)_DD) To the first level shifter 404a and/or the second level shifter 404b, which transmits the signal to the multiplexer 206 (block 906).

Upon receiving the signal at the output 412 of the boost network 402, the first level shifter 404a and/or the second level shifter 404b determines whether the select signal (lines 221, 223) indicates transmission of a complementary (compensated) boosted control signal (line 215b) to the multiplexer (block 910). For example, if the first select signal (line 221) is a logic low value and the second select signal (line 223) is a logic high value, the first level shifter 404a may transmit the boosted control signal (line 215a) to the first array NMOS switch 240 and the second level shifter 404b may transmit the reference voltage to the second array NMOS switch 244. For example, if the first select signal (line 221) is a logic high value and the second select signal (line 223) is a logic low value, the first level shifter 404a may transmit the reference voltage to the first array NMOS switch 240 and the second level shifter 404b may transmit the supplemental boosted control signal (line 215b) to the second array NMOS switch 244. In response to the selection signal (lines 221, 223) indicating transmission of the supplemental boosted control signal (block 910: yes), the second level shifter 404b transmits the supplemental boosted control signal (line 215a) to the multiplexer 206 (block 914). In response to the selection signal (lines 221, 223) indicating that the boosted control signal is transmitted (block 910: no), the first level shifter 404a transmits the boosted control signal (line 215a) to the multiplexer 206 (block 912). After transmitting the signal at the output 412 of the boost network 402 to the multiplexer 206 (boosted at block 914, boosted at block 912, or not boosted at block 906), the boost circuit 236 determines whether to continue operation (block 916). If the boost circuit 236 determines to continue operation (e.g., execution of block 916 returns yes), control proceeds to block 902. Alternatively, in response to boost circuitry 236 determining not to continue operation (e.g., execution of block 916 returns no), process 900 stops.

Fig. 10 is a block diagram of an example processing platform configured to execute the instructions of fig. 8 and 9 to implement the example controller 234 of fig. 2 and 3, the example boost circuit 236 of fig. 2 and 4, and/or the example first and/or second level shifters 404a, 404b of fig. 4 and 5. For example, the processor platform 1000 may be a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, a tablet such as an ipad), a Personal Digital Assistant (PDA), an internet appliance, a DVD player, a CD player, a digital video recorder, a blu-ray player, a game console, a personal video recorder, a set-top box, a headset, or other wearable device, or any other type of computing device.

The processor platform 1000 of the illustrated example includes a processor 1012. The processor 1012 of the illustrated example is hardware. For example, the processor 1012 may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The hardware processor may be a semiconductor-based (e.g., silicon-based) device. In this example, the processor implements the example signal analyzer 302, the example signal generator 304, the example sensing interface 306, and/or more generally the example controller 234 of fig. 2 and 3, and/or the example boost network 402, the example first level shifter 404a, the example second level shifter 404b, the example voltage input 406, the example first inverter 414, the example second inverter 416, the example third inverter 418, the example fourth inverter 420, the example fifth inverter 422, the example first switch 424, the example second switch 426, the example third switch 428, the example capacitor 430, and/or more generally the example boost circuit 236 of fig. 2 and 4, and/or the example shift network 502, the example first inverter 504, the example second inverter 506, the example first switch 508, the example second switch 510, the example third switch 512, An example fourth switch 514, an example fifth switch 516, an example sixth switch 518, an example seventh switch 520, an example eighth switch 522, an example ninth switch 524, an example tenth switch 526, and/or, more generally, an example first level shifter 404a and/or an example second level shifter 404b of fig. 4 and 5.

The processor 1012 of the illustrated example includes local memory 1013 (e.g., a cache). The processor 1012 of the illustrated example communicates with a main memory including a volatile memory 1014 and a non-volatile memory 1016 via a bus 1018. The volatile memory 1014 may be comprised of Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM),Dynamic random access memoryAnd/or any other type of random access memory device. The non-volatile memory 1016 may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory 1014, 1016 is controlled by a memory controller.

The processor platform 1000 of the illustrated example also includes interface circuitry 1020. The interface circuit 1020 may be implemented by any type of interface standard, such as an Ethernet interface, Universal Serial Bus (USB), or the like,An interface, a Near Field Communication (NFC) interface, and/or a PCI express interface.

In the example shown, one or more input devices 1022 are connected to the interface circuit 1020. Input device(s) 1022 allow a user to enter data and/or commands into processor 1012. The input device(s) may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touch screen, a touch pad, a trackball, an equivalent point (isopoint), and/or a voice recognition system.

One or more output devices 1024 are also connected to the interface circuit 1020 of the illustrated example. The output devices 1024 may be implemented, for example, by display devices (e.g., Light Emitting Diodes (LEDs), Organic Light Emitting Diodes (OLEDs), Liquid Crystal Displays (LCDs), cathode ray tube displays (CRTs), in-plane switching (IPS) displays, touch screens, etc.), tactile output devices, printers, and/or speakers. Thus, the interface circuit 1020 of the illustrated example generally includes a graphics driver card, a graphics driver chip, and/or a graphics driver processor.

The interface circuit 1020 of the illustrated example also includes communication devices such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and/or network interfaces to facilitate the exchange of data with external machines (e.g., any kind of computing device) via the network 1026. The communication may be via, for example, an ethernet connection, a Digital Subscriber Line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site (line-of-site) wireless system, a cellular telephone system, or the like.

The processor platform 1000 of the illustrated example also includes one or more mass storage devices 1028 for storing software and/or data. Examples of such mass storage devices 1028 include floppy disk drives, hard drive disks, compact disk drives, blu-ray disk drives, Redundant Array of Independent Disks (RAID) systems, and Digital Versatile Disk (DVD) drives.

The machine-executable instructions 1032 of fig. 8 and 9 may be stored in the mass storage device 1028, the volatile memory 1014, the non-volatile memory 1016, and/or a removable non-transitory computer-readable storage medium, such as a CD or DVD.

From the foregoing, it may be appreciated that example methods, apparatus, and articles of manufacture to reduce power consumption of a computing device have been disclosed. Example methods, apparatus, and articles of manufacture improve the operating area over which read operations of a memory array are reliable. Additionally, the example methods, apparatus, and articles of manufacture disclosed herein read memory bits, instructions, and/or other information stored in a memory array without using an additional volatile memory architecture. Examples disclosed herein reduce the computational burden of accessing memory. The disclosed methods, apparatus, and articles of manufacture improve the efficiency of using a computing device by reducing the power consumption of the computing device and increasing the operating area over which memory may be read. The disclosed methods, apparatus, and articles of manufacture are therefore directed to one or more improvements in computer functionality.

Although certain example methods, apparatus, and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus, and articles of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.