阅读说明：本技术 三维存储器及其制备方法 (Three-dimensional memory and preparation method thereof ) 是由 张坤 周文犀 于 2021-09-06 设计创作，主要内容包括：本申请提供三维存储器及其制备方法。该三维存储器可以包括：位于衬底或半导体层一侧的叠层结构；栅线隙结构,贯穿叠层结构；以及多个连接结构,位于栅线隙结构上,并连接叠层结构分别位于栅线隙结构两侧的部分,使得栅线隙结构的顶部部分分段。根据本申请的三维存储器具有改善的结构稳定性和晶圆翘曲度,且工艺窗口大、实施成本低。(The application provides a three-dimensional memory and a preparation method thereof. The three-dimensional memory may include: a laminated structure on one side of the substrate or the semiconductor layer; a gate line gap structure penetrating the stacked structure; and a plurality of connecting structures located on the gate line gap structure and connected to the parts of the stacked structure respectively located at two sides of the gate line gap structure, so that the top part of the gate line gap structure is segmented. The three-dimensional memory according to the application has the advantages of improved structural stability and wafer warping degree, large process window and low implementation cost.)

1. A three-dimensional memory, comprising:

a laminated structure on one side of the substrate or the semiconductor layer;

a gate line gap structure penetrating the stacked structure; and

and the connecting structures are positioned on the grid line gap structure and are connected with the parts of the laminated structures respectively positioned at two sides of the grid line gap structure, so that the top part of the grid line gap structure is segmented.

2. The three-dimensional memory according to claim 1, wherein the gate line gap structures extend along a first direction parallel to the substrate or the semiconductor layer and are arranged in parallel at predetermined intervals along a second direction parallel to the substrate or the semiconductor layer, the second direction being perpendicular to the first direction, and the plurality of connection structures are located on one or more of the gate line gap structures.

3. The three-dimensional memory according to claim 2, wherein adjacent connection structures of the plurality of connection structures are aligned with each other or staggered with respect to each other in the second direction.

4. The three-dimensional memory according to claim 2, wherein the connection structures of the plurality of connection structures located on the same gate slit structure are uniformly distributed at the same interval in the first direction.

5. The three-dimensional memory according to claim 2, wherein the plurality of connection structures are located on a group consisting of two adjacent ones of the gate line gap structures, and adjacent ones of the plurality of connection structures are staggered from each other in the second direction, and connection structures located on the same gate line gap structure among the plurality of connection structures are uniformly distributed at the same interval in the first direction, wherein the groups are spaced apart from each other by one gate line gap structure on which the plurality of connection structures are not formed.

6. The three-dimensional memory of claim 1, wherein the connection structure comprises an insulating material.

7. The three-dimensional memory of claim 1, further comprising:

a plurality of channel structures extending through the stacked structure and distributed between adjacent ones of the gate gap structures,

wherein the stacked structure includes gate layers and insulating layers alternately stacked, and a barrier layer is formed between the gate layers and the channel structure.

8. The three-dimensional memory of claim 7, wherein the gate line gap structure comprises an insulating material such that portions of the gate layer respectively on both sides of the gate line gap structure are electrically insulated from each other.

9. A method of fabricating a three-dimensional memory, comprising:

forming a stacked structure on one side of a substrate;

forming a gate line gap penetrating through the laminated structure; and

and forming a plurality of connecting structures in the top area of the grid line gap so as to connect the parts of the laminated structure respectively positioned at two sides of the grid line gap, so that the top area of the grid line gap is segmented.

10. The method of claim 9, wherein the step of forming the plurality of connection structures comprises:

arranging a filler in the gate line gap;

forming a groove at a preset position of the filler, wherein the depth of the groove is smaller than that of the gap of the grid line;

filling an insulating material in the groove to form the connecting structure; and

and removing the filler.

11. The method of claim 10, wherein forming the groove comprises: the grooves are formed by a photolithographic method.

12. The method of claim 9, wherein the stacked structure comprises alternately stacked sacrificial layers and insulating layers, the method further comprising:

removing the sacrificial layer through the gate line gap to form a gate gap;

forming a barrier layer to cover the inner wall of the gate gap and the side wall of the gate line gap;

forming a gate layer on the barrier layer on the inner wall of the gate gap; and

and forming a grid line gap structure in the grid line gap.

13. The method of claim 10 or 12, wherein the filler comprises the same material as the sacrificial layer.

14. The method of claim 12, wherein removing the filler comprises removing the sacrificial layer together.

15. The method of claim 9, further comprising: and forming a channel structure penetrating through the laminated structure between adjacent gate line gaps.

Technical Field

The present application relates to the field of semiconductor design and manufacturing, and more particularly, to a structure of a three-dimensional memory and a method for fabricating the same.

Background

Currently, a three-dimensional memory provides gate layers of a select transistor and a memory transistor through a gate stack structure, and channel layers and gate dielectric layers of the select transistor and the memory transistor through a channel structure.

The three-dimensional memory manufacturing process involves multiple etching, deposition and heat treatment processes, and the wafer warpage problem caused by the processes may not enable the wafer to be processed in the machine. In order to alleviate the wafer warpage problem, technicians usually need to finely adjust the stress of each layer of film grown in the process, or additionally grow a stress adjustment film on the back surface of the wafer, so that the warpage of the wafer meets the process specification. However, the adjustment of the stress of each layer of film requires a technician to perform corresponding adjustment and optimization for different products and processes, which not only increases the complexity of the process, but also has a limited effect on improving the warpage of the wafer, and the addition of the stress adjustment film additionally increases the production cost and reduces the competitiveness of the product.

In addition, in order to form the gate electrode layer, the sacrificial layer in the stacked structure needs to be etched first through the gate line gap to form the gate gap. After the sacrificial layer is removed, the stability of the stacked structure as the memory body portion may be greatly reduced, and as the number of layers of the stacked structure is increased, collapse of the body structure may even occur.

Disclosure of Invention

The present application provides a three-dimensional memory and a method of fabricating the same that can solve, at least in part, the above-mentioned problems in the prior art.

One aspect of the present application provides a three-dimensional memory, which may include: a laminated structure on one side of the substrate or the semiconductor layer; a gate line gap structure penetrating the stacked structure; and a plurality of connecting structures located on the gate line gap structure and connected with the parts of the laminated structure respectively located at two sides of the gate line gap structure, so that the top part of the gate line gap structure is segmented.

In one embodiment, the gate line gap structures may extend in a first direction parallel to the substrate or the semiconductor layer and be arranged in parallel at predetermined intervals in a second direction parallel to the substrate or the semiconductor layer, which is perpendicular to the first direction, and a plurality of connection structures may be positioned on one or more of the gate line gap structures. In one embodiment, adjacent connection structures of the plurality of connection structures may be aligned with each other or staggered with each other in the second direction. In one embodiment, the connection structures located on the same gate slit structure among the plurality of connection structures may be uniformly distributed at the same interval in the first direction. In one embodiment, the plurality of connection structures may be located on a group consisting of two adjacent ones of the gate line gap structures, and adjacent ones of the plurality of connection structures may be staggered from each other in the second direction, and connection structures located on the same gate line gap structure of the plurality of connection structures may be uniformly distributed at the same interval in the first direction, wherein the group may be spaced apart from each other by one gate line gap structure on which the connection structure is not formed. In one embodiment, the connection structure may comprise an insulating material. In one embodiment, the three-dimensional memory may further include: and the plurality of channel structures penetrate through the laminated structure and are distributed between adjacent grid line gap structures in the grid line gap structures. The stacked structure may include gate layers and insulating layers that are alternately stacked, and a barrier layer may be formed between the gate layers and the channel structure. In one embodiment, the gate line gap structure may include an insulating material such that portions of the gate electrode layer respectively located at both sides of the gate line gap structure are electrically insulated from each other.

Another aspect of the present application provides a method for manufacturing a three-dimensional memory, which may include: forming a stacked structure on one side of a substrate; forming a gate line gap penetrating through the laminated structure; and forming a plurality of connection structures in the top region of the gate line gap to connect the parts of the laminated structure respectively positioned at the two sides of the gate line gap, so that the top region of the gate line gap is segmented.

In one embodiment, the step of forming the plurality of connection structures may comprise: arranging a filler in the gap of the grid line; forming a groove at a preset position of the filler, wherein the depth of the groove is less than that of the gap of the grid line; filling an insulating material in the groove to form a connecting structure; and removing the filler. In one embodiment, forming the groove may include forming the groove by a photolithography method. In one embodiment, the stacked structure may include a sacrificial layer and an insulating layer alternately stacked, and the preparation method may further include: removing the sacrificial layer through the gate line gap to form a gate gap; forming a barrier layer to cover an inner wall of the gate gap and a side wall of the gate line gap; forming a gate layer on the barrier layer on the inner wall of the gate gap; and forming a gate line gap structure in the gate line gap. In one embodiment, the filler may include the same material as that of the sacrificial layer. In one embodiment, removing the filler may include removing the sacrificial layer together. In one embodiment, the preparation method may further comprise: and forming a channel structure penetrating through the laminated structure between adjacent gate line gaps in the gate line gaps.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. In the drawings:

FIG. 1 is a schematic top view of a three-dimensional memory according to an exemplary embodiment of the present application;

FIG. 2 is a schematic cross-sectional view of a three-dimensional memory according to an exemplary embodiment of the present application;

FIG. 3 is a schematic top view of a three-dimensional memory according to an exemplary embodiment of the present application;

FIG. 4 is a flow chart of a method of fabricating a three-dimensional memory according to an exemplary embodiment of the present application;

fig. 5 to 12 are process diagrams of a method of manufacturing a three-dimensional memory according to an exemplary embodiment of the present application; and

fig. 13 to 19 are process diagrams of a method of manufacturing a three-dimensional memory according to another exemplary embodiment of the present application.

Detailed Description

The present application will now be described in detail with reference to the drawings, wherein the exemplary embodiments are provided for the purpose of illustration only and are not intended to limit the scope of the present application. Like reference numerals refer to like elements throughout the specification.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "about," "approximately," and the like are used as approximations, not as degrees of expression, and are intended to indicate inherent deviations in measured or calculated values that will be recognized by those of ordinary skill in the art.

It should also be understood that the expression "and/or" includes any and all combinations of one or more of the associated listed items. Expressions such as "comprising," "including," "having," "including," and/or "containing" are open rather than closed expressions in this specification that indicate the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. When describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to mean exemplary or illustrative.

Further, in this application, when expressions such as "connected," "covered," and/or "formed at …" are used, direct or indirect contact between the respective components may be meant, unless there is an explicit other limitation or can be inferred from the context.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Furthermore, unless otherwise indicated herein, words defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. Further, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 is a schematic top view of a three-dimensional memory according to an exemplary embodiment of the present application. Fig. 2A to 2D are schematic sectional views taken along line AA ', line BB', line CC ', and line DD' in fig. 1, respectively.

Referring to fig. 1 and 2, a three-dimensional memory 10 according to an exemplary embodiment of the present application includes:

a substrate 100 comprising at least one of single crystal silicon (Si), single crystal germanium (Ge), a group III-V compound semiconductor, a group II-VI compound semiconductor, or other semiconductor materials known in the art;

the stacked structure 110 includes a plurality of gate layers 111 and a plurality of insulating layers 112 stacked alternately, wherein the gate layers 111 include, but are not limited to, tungsten (W), and the insulating layers 112 include, but are not limited to, silicon oxide (SiO)_X) And the number of layers of the stacked structure 110 is not limited to the number of layers shown in fig. 2, but may be additionally provided as needed, for example, 32 layers, 64 layers, 128 layers, etc.;

a plurality of gate line gap structures 120 penetrating the stack structure 110 and extending in a first direction (e.g., x-direction in fig. 1) parallel to the substrate 100 and arranged in parallel at a predetermined interval d (refer to fig. 1) in a second direction (e.g., y-direction in fig. 1) parallel to the substrate 100 and perpendicular to the first direction;

a plurality of connection structures 130, including but not limited to oxides, on the at least one gate line gap structure 120 and connecting portions of the stacked structure 110 respectively located at both sides of the at least one gate line gap structure 120, such that a top portion of the at least one gate line gap structure 120 is segmented;

a plurality of channel structures 140 penetrating the stack structure 110 and distributed between adjacent gate-gap structures 120, providing a channel layer and a dielectric layer of the select transistor and a channel layer, a dielectric layer and a charge storage layer of the memory transistor;

top select gate isolation structures 150 between the gate line gap structures 120, extending along a first direction (e.g., x-direction in fig. 1), and separating at least one layer on top in the gate layer 111 into a plurality of top select gate partitions F (see fig. 1); and

the barrier layer 160, including but not limited to a high dielectric constant material, is located between the gate layer 111 and the channel structure 140, it being understood that in other embodiments, the barrier layer 160 may be omitted.

As shown in fig. 1 and 2, portions of the stacked structure 110 respectively located at both sides of the gate line gap structure 120 are electrically insulated from each other by the gate line gap structure 120, or the gate line gap structure 120 and the connection structure 130, and thus the stacked structure 110 is divided into a plurality of access regions M (refer to fig. 1). The plurality of connecting structures 130 are disposed at different positions of the one or more gate line gap structures 120, and the connecting structures 130 connect portions of the stacked structure 110 located at two sides thereof, so that a reinforcing effect can be achieved in a subsequent manufacturing process, a wafer warpage problem can be alleviated, and the stacked structure can be prevented from collapsing as the number of layers is increased.

Fig. 3 is a schematic top view of a three-dimensional memory according to an exemplary embodiment of the present application, illustrating an example of an alternative location of the connection structure 130.

Referring to fig. 3, the adjacent connection structures 130 may be aligned with each other or staggered with each other in the second direction (e.g., the y direction in fig. 3). The connection structures 130 located on the same gate slit structure 120 may be uniformly distributed at the same interval in the first direction (e.g., x direction in fig. 3). It should be understood that the location of the connection structure 130 is not limited to the location shown in fig. 1 and 3, but may have a variety of arrangements. For example, the connection structures 130 may be arranged in such a way that an etch process window for forming gate gaps (described below) is optimized. For example, referring to fig. 3E, in a preferred embodiment, the connection structures 130 may be disposed on two adjacent gate line gap structures 120 ', the adjacent connection structures 130 may be staggered with each other in the second direction (e.g., y direction in fig. 3), the connection structures 130 located on the same gate line gap structure 120 ' may be uniformly distributed at the same interval in the first direction (e.g., x direction in fig. 3), and the group consisting of the two gate line gap structures 120 ' are spaced apart from each other by one gate line gap structure 120 ″ on which the connection structures 130 are not formed. It should be understood that in fig. 3E, the gate slit structures 120 are divided into two groups (the gate slit structure 120' and the gate slit structure 120 ") for distinction purposes only. In this case, since the connection structures 130 can be provided as little as possible and uniformly while performing a supporting function, a relatively large operation window and relatively small stress and balance of the body lamination structure in operation are secured.

Fig. 4 is a flowchart of a method of manufacturing a three-dimensional memory according to an exemplary embodiment of the present application. As shown in fig. 4, the preparation method 1000 includes the following steps:

s1, forming a laminated structure on one side of the substrate;

s2, forming a gate line gap penetrating through the laminated structure; and

s3, forming a plurality of connection structures in the top region of the gate line slit to connect portions of the stacked structure respectively located at both sides of the gate line slit, so that the top region of the gate line slit is segmented.

The specific processes of the steps of the above-described preparation method 1000 will be described in detail below with reference to fig. 5 to 12.

Fig. 5 is a schematic cross-sectional view of a three-dimensional memory device after forming a gate line slit 170 according to an exemplary embodiment of the present application, wherein fig. 5A to 5D are schematic cross-sectional views taken along lines AA ', BB', CC ', and DD' in fig. 1, respectively. Referring to fig. 5, forming the stacked structure 110 'on one side of the substrate 100 (step S1) may include forming the stacked structure 110' on one side of the substrate 100 using a Deposition process such as Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD). Wherein substrate 100 includes, but is not limited to, at least one of single crystal silicon (Si), single crystal germanium (Ge), a III-V compound semiconductor, a II-VI compound semiconductor, or other semiconductor materials known in the art. The stack 110' includes an alternationA plurality of insulating layers 112 and a plurality of sacrificial layers 113 are stacked. Insulating layer 112 includes, but is not limited to, silicon oxide (SiO)_X) The sacrificial layer 113 includes, but is not limited to, silicon nitride (SiN)_X)。

In an embodiment, after forming the stacked structure 110 ', a step of forming a channel structure 140 penetrating the stacked structure 110' may be further included. A plurality of trench holes penetrating the stacked structure 110' may be formed at predetermined positions and the trench structure 140 may be formed in the trench holes using anisotropic etching (e.g., dry etching such as ion mill etching, plasma etching, reactive ion etching, laser ablation, etc.) and by controlling the etching time.

Forming the plurality of gate line slits 170 through the stacked structure 110 '(step S2) may include forming the plurality of gate line slits 170 through the stacked structure 110' at predetermined positions using anisotropic etching (e.g., dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, etc.) and by controlling etching time. The plurality of gate line slits 170 extend along a first direction (e.g., x-direction in fig. 1) parallel to the substrate 100 and are arranged in parallel at a predetermined interval along a second direction (e.g., y-direction in fig. 1) parallel to the substrate 100 perpendicular to the first direction, wherein the channel structure 140 is located between the adjacent gate line slits 170.

Fig. 6 to 12 are schematic cross-sectional views of a process of forming a connection structure according to an exemplary embodiment of the present application, wherein fig. a to D in fig. 6 to 12 are schematic cross-sectional views taken along line AA ', line BB', line CC ', and line DD' in fig. 1, respectively.

Forming a plurality of connection structures in the top region of the gate line slit (step S3) may include: arranging a filler in the gap of the grid line; forming a groove at a preset position of the filler; filling an insulating material in the groove to form a connecting structure; and removing the filler.

Specifically, referring to fig. 6, the filler 180 may be formed in the gate line slit 170 (referring to fig. 5) by a deposition process such as ALD, PVD, CVD, or the like. The filler 180 may include, but is not limited to, silicon nitride (SiN)_X). Refer to the drawings7, the filler 180 may be dry etched to remove a portion of the filler 180 located outside the gate line slit 170 (refer to fig. 5). Referring to fig. 8, a mask layer 190 may be formed on the stacked structure 110' and the filler 180, and a patterned mask layer 190 may be formed by processes of spin-on photoresist, exposure development, and the like to define the position of the connection structure. Referring to fig. 9, an anisotropic etch may be used to form a recess 200 at a location defined by the mask layer 190 (refer to fig. 8) in the filler 180 by controlling an etch time, wherein a depth of the recess 200 is less than a depth of the gate line slit 170 (refer to fig. 5), and may be adjusted according to, for example, a requirement for stress reduction. The mask layer 190 (refer to fig. 8) may be removed after the groove 200 is formed. Referring to fig. 10, the groove 200 (referring to fig. 9) may be filled with an insulating material 130' by a deposition process such as ALD, PVD, CVD, or the like. Referring to fig. 11, the insulating material 130' may be dry etched to remove a portion thereof located outside the recess 200 (refer to fig. 9) to form the connection structure 130. Referring to fig. 12, after the connection structure 130 is formed, the filler 180 may be removed by isotropic etching (refer to fig. 9). The isotropic etching includes wet etching or vapor etching. In wet etching, an etching solution is used as an etchant, and a structure to be etched is immersed in the etching solution. In vapor phase etching, an etching gas is used as an etchant, and a structure to be etched is exposed to the etching gas. In the case where the filler 180 (refer to fig. 9) is silicon nitride, a phosphoric acid solution or a hydrofluoric acid solution may be used as an etchant in wet etching, and C may be used in vapor etching₄F₈、C₄F₆、H₂F₂And O₂As an etchant. Due to the selectivity of the etchant, the filler 180 (refer to fig. 9) in the gate line slit 170 (refer to fig. 5) may be removed. The connection structure 130 segments a top portion of the gate line slit 170 (refer to fig. 5) and connects portions of the stacked structure 110' located at both sides of the connection structure 130.

When the material of the sacrificial layer 113 and the filler 180 (refer to fig. 9) is the same, the process of etching the filler 180 may remove the sacrificial layer 113 in the stack structure 110' together, and thus form a gate gap at the original position of the sacrificial layer 113. Subsequently, a barrier layer 160 (refer to fig. 2) may be formed on the inner wall of the gate gap and the sidewall of the gate line gap 170 (refer to fig. 5). The barrier layer 160 may include, but is not limited to, a high dielectric constant material.

Subsequently, a gate layer 111 may be formed on the barrier layer 160 in the gate gap (refer to fig. 2). The gate layer 111 includes, but is not limited to, tungsten (W). Since the gate layer 111 has a low adhesion to the barrier layer 160, an adhesion layer 114 (refer to fig. 2) is optionally formed between the gate layer 111 and the barrier layer 160. The adhesion layer 114 includes, but is not limited to, tantalum nitride (TaN) or titanium nitride (TiN). The step of forming the adhesion layer 114 comprising tantalum nitride (TaN) or titanium nitride (TiN) may include: introducing inert gas into a vacuum cavity, applying high-voltage direct current on the metal target and the area to be deposited, generating plasma by electron collision generated by glow discharge and exciting the inert gas, bombarding the surface of the metal target by the plasma with high kinetic energy, enabling metal particles to be sputtered and deposited on the surface of the area to be deposited in a gas phase state to form a thin film, and introducing nitrogen (N) after bombarding the metal target for several seconds₂) To form a nitride, i.e., tantalum nitride (TaN) or titanium nitride (TiN). The step of forming the gate layer 111 including tungsten (W) may include: introducing e.g. monosilane (SiH)₄) Diborane (B)₂H₆) Hydrogen (H)₂) And the like with a reducing agent such as tungsten hexafluoride (WF)₆) Etc. to react the two. During the reaction, a thin tungsten layer and hydrogen gas are formed. The thin tungsten layer may serve as a seed layer for subsequent bulk deposition of tungsten. With Silane (SiH)₄) For example, the specific reaction process is as follows:

3SiH₄+2WF₆→2W(s)+3SiF₄+6H₂

thereafter, hydrogen (H) may be mainly passed through₂) Reduction of tungsten hexafluoride (WF)₆) The gate layer 111 is deposited by the following specific reaction process:

WF₆+3H₂→W(s)+6HF

since the above embodiments employ a non-selective blanket method to deposit the adhesion layer 114 and the gate electrode layer 111, the method further includes removing the adhesion layer 114 and the gate electrode layer 111 outside the gate gap after the deposition. Wherein the adhesion layer 114 and the portion of the gate layer 111 outside the gate gap may be removed by wet etching (e.g., by high temperature mixed acid). Alternatively, in other embodiments, tungsten oxide may be formed at the exposed surface of the gate electrode layer 111 by an oxygen-containing anneal, and then removed by an acid solution, and an etching solution having a high selectivity to the adhesion layer 114 and the gate electrode layer 111 is used to remove the adhesion layer 114 and the gate electrode layer 111 outside the gate gap and a portion of the adhesion layer 114 and the gate electrode layer 111 inside the gate gap, and finally form a recess in the gate gap, as shown in fig. 2, but the embodiment is not limited thereto. For example, in other embodiments, the etched adhesion layer 114 and the gate layer 111 may be aligned with the sidewalls of the gate line slit 170 (refer to fig. 5) without forming a recess.

Subsequently, a gate line gap structure 120 (refer to fig. 2) may be formed in the gate line gap 170 (refer to fig. 5). In one embodiment, the gate line gap structure 120 may include an insulating material. The step of forming the gate gap structure 120 including an insulating material may include: the gate line gap structure 120 is formed by first depositing at a lower temperature (e.g., about 50 deg.c) through a deposition process such as ALD and then raising the temperature to a higher temperature (e.g., about 300 deg.c), but the embodiment is not limited thereto. For example, the entire process of depositing the gate line gap structure 120 described above may be performed at a lower temperature (e.g., about 50 ℃). In another embodiment, the cascode structure 120 may include a common source (not shown), wherein the common source may include, but is not limited to, metal tungsten (W). The common source may be used to connect with the channel layer in the channel structure, thereby bringing the source of the channel structure out of the top of the stack.

Subsequently, a top select gate isolation structure 150 (refer to fig. 1) may be formed along a first direction (e.g., x-direction in fig. 1) between the gate line gap structures 120 to separate at least one layer of the top in the gate layer 111 (refer to fig. 2) into a plurality of top select gate partitions F (refer to fig. 1).

The method 1000 for fabricating a three-dimensional memory according to the above-described exemplary embodiment may be applied to fabricate a three-dimensional memory based on an Xtacking architecture. The three-dimensional memory based on the XBacking architecture can comprise a first wafer used for forming a memory array and a second wafer used for forming peripheral circuits. After the separate fabrication is completed, the first wafer and the second wafer may be connected to each other by bonding, and the backside (i.e., the side where the memory array or peripheral circuitry is not formed) of the first wafer or the second wafer may be used to form the back-end-of-line structure. The method 1000 for fabricating a three-dimensional memory according to the above-described exemplary embodiment may be used to form a core region including a memory array in a first wafer.

The method 2000 for fabricating the Xtacking architecture-based three-dimensional memory according to another exemplary embodiment of the present application may include:

s4, forming a first wafer comprising a core area with storage units and a step area;

s5, connecting the first wafer to a second wafer including peripheral circuits; and

and S6, forming a semiconductor layer connected with the channel layer in the channel structure on the side of the first wafer far away from the second wafer so as to realize the electrical signal transmission with an external control circuit.

Fig. 13 to 19 are process diagrams of a method of manufacturing a three-dimensional memory according to another exemplary embodiment of the present application. The preparation method 2000 will be described in detail below with reference to fig. 13 to 19. Since the manufacturing method 1000 and the manufacturing method 2000 are different in steps after forming the gate gap structure 120, a repetitive description will be omitted in the following description.

Referring to fig. 13, the first wafer 20 may include a core region a having a channel structure 140, a gate line gap structure 120, and a connection structure 130 (not shown, refer to fig. 2) as a memory cell, and a stepped region S including a through via 210, a conductive via 220, and a dummy channel structure 230. The channel structure 140 may include a functional layer 240 and a channel layer 250 in that order from the outside inward. The functional layer 240 may have an ONO (silicon oxide-silicon nitride-silicon oxide) structure, but the embodiment is not limited thereto. The channel layer 250 may include a semiconductor material such as amorphous silicon, polycrystalline silicon, single crystal silicon, or the like. The functional layer 240 and the channel layer 250 in the channel structure 140 form a memory cell together with a corresponding portion of each gate layer 111 and each gate layer 111 in the stacked-layer structure 110. The gate layer 111 may correspond to a control terminal of the memory cell. The plurality of memory cells in the channel structure 140 are arranged in series in a direction perpendicular to the substrate 100 and share the channel layer 250. The through channel 210 may pass through a portion of the stepped region S corresponding to the stack structure 110. The through vias 210 may include a conductive material such as tungsten, cobalt, copper, aluminum, or a doped semiconductor material for passing electrical signals between the two wafers and enabling interaction of the electrical signals of the two wafers with external control circuitry after the first wafer 20 is bonded to the second wafer 30. The conductive via 220 may extend to the gate layers 111 in a direction perpendicular to the substrate 100 such that one end thereof contacts the corresponding gate layer 111. The conductive via 220 may comprise a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof. The dummy channel structure 230 may extend through a portion of the step region S corresponding to the stack structure 110 and into the substrate 100. Dummy channel structure 230 may include an insulating material and is used to provide support. Forming the first wafer 20 including the core region a having the memory cells and the step region S (step S4) may include: forming a core region a having a connection structure 130 (refer to fig. 2), a gate-gap structure 120, and a channel structure 140 by a method including the preparation method 1000; and forming a step region S including the through via 210, the conductive via 220, and the dummy channel structure 230. The method of forming the step region S may be any technical means understood by those skilled in the art and will not be described herein. In addition, forming the first wafer 20 (step S4) may further include forming a plurality of interconnect structures 260 on a side of the stacked structure 110 away from the substrate 100. The interconnect structure 260 may include interconnect channels extending in a direction perpendicular to the substrate 100 and interconnect lines (not shown) extending in a direction parallel to the substrate 100. The interconnect structure 260 may comprise a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof, and is used to pass electrical signals to and from the second wafer 30.

Referring to fig. 14, the second wafer 30 may include peripheral circuits formed therein. The peripheral circuits may include any suitable semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Bipolar Junction Transistors (BJTs), diodes, resistors, inductors, and capacitors. These devices may constitute a circuit module that supports a mix of digital, analog, and/or digital-analog functions of channel structure 140. The second wafer 30 may be formed simultaneously during the process of forming the first wafer 20, so that the two are processed in parallel, thereby improving the production efficiency. The second wafer 30 may include an interconnect structure 260' for passing electrical signals to and from the first wafer 20. Interconnect structure 260' may have a similar structure and material as interconnect structure 260. Connecting the first wafer 20 to the second wafer 30 (step S5) may include bonding a side of the first wafer 20 away from the substrate 100 (a side having the interconnection structures 260) to a side of the second wafer 30 having the interconnection structures 260 'by a bonding connection, and the first wafer 20 and the second wafer 30 may be positioned by aligning the connection structures 260 and the connection structures 260' as bonding contact points so that they are electrically connected at the aligned bonding contact points, i.e., structures such as the channel structures 140 and the through vias 210 in the first wafer 20 may be electrically coupled to peripheral circuits in the second wafer 30.

After the bonding connection, a side of the first wafer 20 away from the second wafer 30 may be processed to form a semiconductor layer connected to the channel layer 250 in the channel structure 140 (step S6). Referring to fig. 14, the first wafer 20 may further include a first stop layer 270, a replacement layer 280, a second stop layer 290, and a polysilicon layer 300 between the substrate 100 and the stacked structure 110, but the embodiment is not limited thereto. The first stop layer 270 and the second stop layer 290 may include, but are not limited to, silicon oxide. The displacement layer 280 may include, but is not limited to, polysilicon.

Referring to fig. 15, the substrate 100 and portions of the dummy channel structures 230 extending into the substrate 100 may be removed by an etching process or a Chemical Mechanical Polishing (CMP) process. The removal process may stop at the first stop layer 270 such that the first stop layer 270 is exposed. It is understood that in some embodiments, the first stop layer 270 may be omitted and the substrate 100 may be removed to expose the displacement layer 280, for example, by controlling process parameters such as etch time or etch rate. Referring to fig. 16, a portion of the first stop layer 270 corresponding to the channel structure 140 and corresponding to the through via 210 may be removed using an etching process to expose a corresponding portion of the displacement layer 280. The portions of the first stopper layer 270 that are not removed may correspond to the dummy channel structure 230 and the gate gap structure 120, respectively. Referring to fig. 17, in an embodiment, a multi-pass etching process may be employed to remove portions of the replacement layer 280 corresponding to the channel structure 140 and the through via 210, portions of the channel structure 140 where the functional layer 240 extends into the second stop layer 290 and the replacement layer 280, remaining portions of the first stop layer 270, portions of the second stop layer 290 corresponding to the channel structure 140, and portions of the second stop layer 290 and the polysilicon layer 300 corresponding to the through via 210, so as to expose the channel layer 250 and the through via 210. It should be understood that the step of processing the side of the first wafer 20 away from the second wafer 30 to expose the channel layer 250 and the through via 210 is not limited to the above-described steps.

Referring to fig. 18, a deposition process may be used to form a semiconductor layer 310 on the stack structure 110 such that the semiconductor layer 310 covers and surrounds the channel structure 140, covers a surface of the replacement layer 280 corresponding to the dummy channel structure 230, and corresponding to the gate gap structure 120. Alternatively, the surface of the semiconductor layer 310 may be planarized using, for example, a CMP process. The semiconductor layer 310 may contact the channel layer 250 to achieve electrical connection and may serve as a common source region of the channel structure 140. The doped region 320 may be formed at a portion of the channel layer 250 adjacent to the semiconductor layer 310 using, for example, an ion implantation process and a laser annealing process. The height of the doped region 320 in a direction perpendicular to the semiconductor layer 310 may be greater than the height of the at least one gate layer 111. The doped region 320 of the channel layer 250 and the corresponding functional layer 240 may be used to form a bottom selection transistor, and the bottom selection transistor may have different threshold voltages by adjusting the doping concentration of the doped region 320.

Referring to fig. 19, a portion of the semiconductor layer 310 corresponding to the through via 210 may be removed by an etching process. The space formed by removing the portion of the semiconductor layer 310 corresponding to the through via 210 may be filled with an insulating material 330 through a deposition process. Insulating material 330 may include, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride. An insulating material 330 may cover the semiconductor layer 310. Next, a first contact 340 contacting the through via 210 and a second contact 350 contacting the semiconductor layer 310 may be formed using, for example, photolithography and etching processes and a deposition process. The material of the first and second contacts 340, 350 may include a conductive material such as tungsten, cobalt, copper, aluminum, or combinations thereof. The first contact 340 and the second contact 350 may serve as an electrical connection structure through the via 210 and the semiconductor layer 310, respectively, to enable electrical signal transmission with an external control circuit.

In summary, compared with the prior art, at least one embodiment of the present application has at least one of the following advantages:

(1) the grid line gap structure is provided with the plurality of connecting structures which are connected and fixed with the top of the laminated structure, so that the structural stability of the device in the process of manufacturing is improved, the problem of wafer warping caused by a plurality of etching, depositing and heat treatment processes is solved, and the laminated structure is prevented from collapsing possibly along with the continuous increase of the number of layers;

(2) by arranging the barrier layer between the gate layer and the channel structure, the risk of communication between the channel structure and the gate layer in the preparation process is reduced, and therefore, the thickness of the gate gap structure can be reduced, so that the size of a chip is reduced under the condition of the same storage capacity;

(3) the operation is not limited by the layer number of the laminated structure, no additional manufacturing process is needed, and only the layout is needed to be modified and designed in the existing process steps, so the process window is large, and the implementation cost is low.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.