阅读说明：本技术 锁存电路 (Latch circuit ) 是由 王科竣 于 2020-03-23 设计创作，主要内容包括：本发明涉及一种锁存电路。所述锁存电路包括：锁存模块、置位控制模块、复位控制模块和时钟模块。其中,所述锁存模块用于锁存数据模块输入的数据；所述置位控制模块用于控制所述锁存模块输出高电平信号,所述置位控制模块的输入信号包括控制信号和置位信号；所述复位控制模块用于控制所述锁存模块输出低电平信号,所述复位控制模块的输入信号包括所述置位控制模块的输出信号、自测试使能信号和复位信号；所述时钟模块用于为所述锁存模块提供读取时钟信号；其中,所述自测试使能信号决定所述锁存器处于自测试模式或正常工作模式。(The present invention relates to a latch circuit. The latch circuit includes: the device comprises a latch module, a setting control module, a resetting control module and a clock module. The latch module is used for latching data input by the data module; the setting control module is used for controlling the latch module to output a high-level signal, and input signals of the setting control module comprise control signals and setting signals; the reset control module is used for controlling the latch module to output a low-level signal, and input signals of the reset control module comprise an output signal of the set control module, a self-test enabling signal and a reset signal; the clock module is used for providing a reading clock signal for the latch module; wherein the self-test enable signal determines whether the latch is in a self-test mode or a normal operating mode.)

1. A latch circuit, comprising:

the latch module is used for latching the data input by the data module;

the setting control module is used for controlling the latch module to output a high-level signal, and input signals of the setting control module comprise control signals and setting signals;

the reset control module is used for controlling the latch module to output a low-level signal, and input signals of the reset control module comprise an output signal of the set control module, a self-test enabling signal and a reset signal;

the clock module is used for providing a reading clock signal for the latch module;

wherein the self-test enable signal determines whether the latch is in a self-test mode or a normal operating mode.

2. The latch circuit of claim 1, wherein the input signal of the set control block further comprises a self-test coded signal, and wherein the output of the set control block is connected to the set terminal of the latch block.

3. The latch circuit according to claim 1, wherein the set control block comprises a first and unit for outputting the control signal, the set signal and the self-test coded signal to the latch block and the reset control block after being logically anded.

4. The latch circuit of claim 1, wherein the output of the reset control block is connected to the reset terminal of the latch block.

5. The latch circuit according to claim 1, wherein the reset control module comprises:

the reverse operation unit is used for performing reverse processing on the output signal of the setting control module;

the second logical AND unit is used for performing logical AND processing on the output signal of the setting control module and the self-test enabling signal after reverse processing; and

and the logic OR unit is used for performing logic OR on the output of the second logic AND unit and the reset information and then outputting the logic OR to the latch module.

6. The latch circuit of claim 1, wherein the input signals to the clock block comprise a fuse select signal and a fuse clock signal, and wherein the output of the clock block is coupled to a clock terminal of the latch block.

7. The latch circuit according to claim 1, wherein the clock block comprises a third and unit for logically and-outputting the fuse selection signal and the fuse clock signal to the latch block.

8. The latch circuit of claim 1, wherein the data termination of the latch module is a fuse data signal.

9. The latch circuit of claim 1, wherein the latch module is a D flip-flop.

10. The latch circuit according to claim 9, wherein the D flip-flop comprises:

the setting unit is used for receiving and outputting the high-level signal provided by the first power supply when the output of the setting control module is high level in the self-test mode;

the fuse unit is used for receiving and outputting a fuse data signal according to the reading clock signal in a normal working mode;

a reset unit for receiving and outputting the low level signal provided by a second power supply when the output of the reset control signal is a high level;

a latch for receiving and latching a high level signal output from the set unit, the fuse data signal output from the fuse unit, or the low level signal output from the reset unit; and

an output unit for outputting the latched high level signal, the fuse data signal, or the low level signal.

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a latch circuit.

Background

In modern DRAM chips, a large number of fuse devices or antifuse devices are used, and a large number of latches are required to store the state of the fuse devices or antifuse devices. Also, latches are used to store self-test signals for test purposes.

However, thousands or even tens of thousands of latches may be used in a DRAM chip, and an excessive number of latches consumes a large amount of die area, resulting in an increase in chip area.

Disclosure of Invention

In view of the above, it is necessary to provide a latch circuit in order to solve the problem of the increase in chip area caused by the conventional latch circuit.

An embodiment of the present invention provides a latch circuit, including:

the latch module is used for latching the data input by the data module;

the setting control module is used for controlling the latch module to output a high-level signal, and input signals of the setting control module comprise control signals and setting signals;

the reset control module is used for controlling the latch module to output a low-level signal, and input signals of the reset control module comprise an output signal of the set control module, a self-test enabling signal and a reset signal;

the clock module is used for providing a reading clock signal for the latch module;

wherein the self-test enable signal determines whether the latch is in a self-test mode or a normal operating mode.

In one embodiment, the input signal of the setting control module further comprises a self-test coding signal, and the output of the setting control module is connected to the setting end of the latch module.

In one embodiment, the set control module includes a first and unit, configured to output the control signal, the set signal, and the self-test coded signal to the latch module and the reset control module after logically anding them.

In one embodiment, the output of the reset control module is connected to the reset terminal of the latch module.

In one embodiment, the reset control module comprises:

the reverse operation unit is used for performing reverse processing on the output signal of the setting control module;

the second logical AND unit is used for performing logical AND processing on the output signal of the setting control module and the self-test enabling signal after reverse processing; and

and the logic OR unit is used for performing logic OR on the output of the second logic AND unit and the reset information and then outputting the logic OR to the latch module.

In one embodiment, the input signals of the clock module comprise a fuse selection signal and a fuse clock signal, and the output of the clock module is connected to the clock terminal of the latch module.

In one embodiment, the clock module includes a third and unit, configured to perform a logical and operation on the fuse selection signal and the fuse clock signal and output the result to the latch module.

In one embodiment, the data of the latch module terminates the fuse data signal.

In one embodiment, the latch module is a D flip-flop.

In one embodiment, the D flip-flop includes:

the setting unit is used for receiving and outputting the high-level signal provided by the first power supply when the output of the setting control module is high level in the self-test mode;

the fuse unit is used for receiving and outputting the fuse data signal according to the reading clock signal in a normal working mode;

a reset unit for receiving and outputting the low level signal provided by a second power supply when the output of the reset control signal is a high level;

a latch for receiving and latching a high level signal output from the set unit, the fuse data signal output from the fuse unit, or the low level signal output from the reset unit; and

an output unit for outputting the latched high level signal, the fuse data signal, or the low level signal.

According to the invention, a latch module, a set control module, a reset control module and a clock module are arranged, the latch module is controlled to output a high level signal through the set control module in a self-test mode, the high level signal for testing is output through a latch, and the latch module reads data from a data module according to the read clock signal and latches the data in a normal working mode, so that the function of latching the data input by the data module and the DFT function are realized, the structure of the latch circuit is simplified, and the required chip area is reduced.

Drawings

FIG. 1 is an electrical schematic of a latch circuit according to the present invention;

FIG. 2 is a schematic circuit diagram of another latch circuit according to the present invention;

FIG. 3 is a timing diagram of a plurality of input signals of the setting control module according to the present invention;

fig. 4 is a schematic circuit structure of a latch module according to the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as broadly as the present invention is capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

Referring to fig. 1 and fig. 2, an embodiment of the invention provides a latch circuit, which includes a latch module 100, a set control module 200, a reset control module 300, and a clock module 400.

The latch module 100 is used for latching data input by the data module.

The SET control module 200 is configured to control the latch module 100 to output a high level signal, and input signals of the SET control module 200 include a control signal CTRL and a SET signal SET.

The Reset control module 300 is configured to control the latch module 100 to output a low level signal, and input signals of the Reset control module 300 include an output signal of the set control module, a self-test enable signal DFTEN, and a Reset signal Reset; wherein the self-test enable signal DFTEN determines whether the latch is in a self-test mode or a normal operation mode.

The clock module 400 is used for providing a read clock signal for the latch module 100.

In this embodiment, the latch circuit enables a self-test mode or a normal operation mode through the self-test enable signal DFTEN. When the self-test enable signal DFTEN is 1, the latch circuit enters a self-test mode, the control signal CTRL is 1, the SET signal SET is 1, the clock module 400 is grounded, the output of the SET control module 200 is a high-level signal, the output of the SET control module controls the latch module 100 to output the high-level signal, and the high-level signal is used to implement a feasibility test function. When the self-test enable signal DFTEN is 0, the latch circuit enters a normal operation mode, the SET signal SET input terminal is grounded, and the latch module 100 receives and latches data input by the data module according to the read clock signal. It can be seen that in this embodiment, by providing the latch module 100, the set control module 200, the reset control module 300, and the clock module 400, and combining the DFT latch and the fuse latch into one flip-flop, not only the latch function of the input data can be realized, but also the DFT function can be realized, the number of latches used is reduced, the structure of the latch circuit is simplified, and further, the required chip area is reduced.

In one embodiment, the input signal of the set control module 200 further includes a self-test code signal DFTCODE, and the output of the set control module 200 is connected to the set terminal of the latch module 100. It can be understood that the test of the latch requires high-speed mixed signal test equipment, and the self-test is realized by inputting the self-test coding signal DFTCODE in the implementation, so that the requirement on automation equipment can be reduced. Meanwhile, a plurality of latches can be synchronously tested, so that the time required by testing is reduced, and the testing efficiency is improved. Referring to fig. 3, in the embodiment, when the latch circuit is selected for testing, three self-test encoding signals are selected, that is, the three self-test encoding signals include the self-test encoding signal DFTCODE0, the self-test encoding signal DFTCODE1, and the self-test encoding signal DFTCODE 2. The setting control module 200 controls the latch module 100 to output a high level signal according to the received self-test encoding signal DFTCODE, the control signal CTRL and the setting signal; specifically, when the self-test encoding signal DFTCODE, the control signal CTRL, and the set signal are all at a high level, the latch module 100 outputs the high-level signal, so as to implement the feasibility test.

In one embodiment, the data of the latch module 100 terminates the fuse data signal FuseData. It can be understood that in the DRAM, the latch fuse signal is one of the main functions of the latch module 100, and therefore the data terminal of the latch module 100 receives the fuse data signal FuseData to implement the storage and the erasure of data.

In one embodiment, the SET control module 200 includes a first and unit 210 for outputting the control signal CTRL, the SET signal SET, and the self-test encoding signal DFTCODE after being logically anded to the latch module 100 and the reset control module 300.

In this embodiment, the first and unit 210 is provided with a control signal terminal, a set signal terminal, and a plurality of self-test encoding signal terminals, wherein the number of the self-test encoding signal terminals can be set according to actual test requirements, for example, 3. In the test mode, when the self-test encoding signal DFTCODE0, the self-test encoding signal DFTCODE1, the self-test encoding signal DFTCODE2, the SET signal SET, and the control signal CTRL are all at a high level, the latch module 100 outputs a high level.

Specifically, in this embodiment, the setting control module 200 includes a first logic and gate 211 and a fourth logic and gate 212, where the first logic and gate 211 is a two-input and gate, and the fourth logic and gate 212 is a four-input and gate. The four input ends of the four-input logic AND gate are respectively connected with the self-test coding signal DFTCODE0, the self-test coding signal DFTCODE1, the self-test coding signal DFTCODE2 and the setting signal SET, and carry out logic AND on the self-test coding signal DFTCODE0, the self-test coding signal DFTCODE1, the self-test coding signal DFTCODE2 and the setting signal SET; one input end of the two-input logic AND gate is connected with the output end of the four-input logic AND gate, the other input end of the two-input logic AND gate is connected with the control signal CTRL, and the two-input logic AND gate is used for logically AND-ing the output data of the four-input logic AND gate and the control signal CTRL and then outputting the output data to a setting end of the latch signal, and testing is carried out through setting 0 or 1. In the normal operating mode, the SET signal terminal is grounded, the SET signal SET is 0, and after the logic and processing is performed through the four-input logic and gate and the two-input logic and gate, the output of the SET control module 200 is at a low level.

In one embodiment, the output of the reset control module 300 is connected to the reset terminal of the latch module 100. In this embodiment, in the test mode, the terminal of the self-test enable signal DFTEN is connected to the high-level voltage signal VDD, and the self-test enable signal DFTEN is 1. In the time period when the SET signal SET is 1, the SET control module 200 controls the latch module 100 to output a high level, and the output signal of the reset control module 300 is a low level; when SET is changed to a low level at 0, the latch needs to be reset, and the reset control module 300 controls the latch signal to be reset through the output signal of the SET control module and the self-test enable signal DFTEN, so that the latch module 100 outputs a low level signal, thereby implementing a test function by setting 0 or 1. In a normal operation mode, the set signal terminal and the self-test enable signal DFTEN terminal are grounded, the latch module 100 receives and latches data input by the data module according to the read clock signal, and resets the latch module 100 through the Reset signal Reset after the data is written.

In one embodiment, the reset control module 300 includes an inverse operation unit 310, a second logical and unit 320, and a logical or unit 330.

The inverse operation unit 310 is configured to perform inverse processing on the output signal of the setting control module. In this embodiment, the inverse operation unit 310 includes a second inverter 311, an input end of which is connected to an output end of the two-input logic and gate in the setting control module 200, and is configured to perform inverse processing on the output signal of the setting control module.

The second and logic unit 320 is configured to perform and processing on the inverted output signal of the setting control module and the self-test enable signal. In this embodiment, the second and logic unit 320 includes a second and gate 321, connected to the output end of the second inverter 311 and the self-test enable signal DFTEN terminal, and is configured to perform a logic and process on the inverted output signal of the set control module and the self-test enable signal, and provide the inverted output signal and the self-test enable signal to the or gate.

The or logic unit 330 is configured to perform a logical or operation on the output of the second and logic unit 320 and the reset information, and then output the logical or operation to the latch module 100. In this embodiment, the or logic unit 330 includes an or logic gate 331, and the or logic gate 331 is connected to the output end of the second and logic gate 321 and the Reset signal terminal, and is configured to perform an or logic process on the output signal of the second and logic gate 321 and the Reset signal Reset, and provide the or logic signal and the Reset signal Reset to the Reset end of the latch module 100, and control the latch module 100 to output a low level signal.

Specifically, in the test mode, when the test encoding signal DFTCODE0, the self-test encoding signal DFTCODE1, the self-test encoding signal DFTCODE2, the SET signal SET, and the control signal CTRL are all at a high level, when the output signal of the SET control module is at a high level, the output signal of the SET control module processed by the second inverter is at a low level, and at this time, the output signal after passing through the second logic and gate and the self-test signal is logically anded is at a low level; when the SET signal SET changes to the low level and the output signal of the SET control module changes to the low level, the output signal of the SET control module processed by the second inverter is the high level, and the latch module 100 can be reset by the output signal of the second logic and gate to control the latch module to output the low level signal. In the normal operation mode, the set signal terminal and the self-test enable signal DFTEN terminal are grounded, the output signal of the second logic and gate 321 is at a low level, and the latch module 100 needs to be controlled to Reset by the Reset signal Reset. Specifically, when the Reset signal Reset is at a high level, the latch module 100 is Reset.

In one embodiment, the input signals of the clock module 400 include a fuse selection signal FuseSel and a fuse clock signal fusetck, and the output of the clock module 400 is connected to the clock terminal of the latch module 100. In this embodiment, the read clock signal is generated and output by performing a logical and process on the fuse selection signal FuseSel and the fuse clock signal FuseClk, so that the latch module 100 latches the fuse data signal FuseData.

In one embodiment, the clock module 400 includes a third and unit 410, configured to output the fuse selection signal FuseSel and the fuse clock signal FuseClk to the latch module 100 after performing a logical and operation. Specifically, the third and unit 410 performs a logical and operation on the fuse selection signal FuseSel and the fuse clock signal FuseClk, and outputs the logical and operation to the clock terminal of the latch module 100.

In one embodiment, the latch module 100 is a D flip-flop. It is understood that, in the test mode, the self test enable signal DFTEN terminal is connected to the high level voltage signal VDD, and the self test enable signal DFTEN is 1. In the time period when the SET signal SET is 1, the SET control module 200 controls the latch module 100 to output a high level, and the output signal of the reset control module 300 is a low level; when SET is changed to a low level, the reset control module 300 controls the latch signal to be reset through the output signal of the SET control module and the self-test enable signal DFTEN, so that the latch module 100 outputs a low level signal, thereby implementing a test function by setting 0 or 1. In addition, in the normal operation mode, the set signal terminal and the self-test enable signal DFTEN terminal are grounded, the latch module 100 receives and latches data input by the data module according to the read clock signal, and the latch module 100 is Reset by the Reset signal Reset after the data is written, so the latch module 100 may be a D flip-flop.

Referring to fig. 4, in one embodiment, the D flip-flop includes a set unit 110, a fuse unit 120, a reset unit 130, a latch 140, and an output unit 150.

The set unit 110 is configured to receive and output the high level signal provided by the first power supply when the output of the set control module 200 is at a high level in the self-test mode. In this embodiment, the setting unit 110 includes a first inverter 111 and a first switch transistor K1. The first inverter 111 is connected to an output end of a first logic and gate 211 in the set control module 200, and configured to perform inverse processing on an output signal of the first logic and gate 211, where the output end of the first logic and gate 211 is the output end of the set control module 200. The first switch transistor K1 is a P-type MOS transistor, and a gate thereof is connected to the output end of the first logic and gate 211, and is configured to receive a high level signal provided by a first power supply when an output signal of the setting control module after the reverse processing is at a low level.

The fuse unit 120 is configured to receive and output the fuse data signal FuseData according to the read clock signal in a normal operating mode. In this embodiment, the fuse unit 120 includes a transmission gate T, wherein a control terminal of the transmission gate is equivalent to the clock terminal of the latch module 100 and is connected to the output terminal of the clock module 400, and an input terminal of the transmission gate is equivalent to the data terminal of the latch module 100 and receives data input by the data module, for example, a fuse data signal FuseData. When the read clock signal is at a high level, the transmission gate T is turned on to receive the fuse data signal FuseData.

The reset unit 130 is configured to receive and output the low level signal provided by the second power supply when the output of the reset control signal CTRL is at a high level. In this embodiment, the reset unit 130 includes a second switch tube K2, and the second switch tube K2 is an N-type MOS transistor. The control terminal of the second switch tube K2 is equivalent to the Reset terminal of the latch module 100, and is connected to the output terminal of the or gate 331 in the Reset control module 300, and when the Reset signal Reset is at a high level or the output signal of the second and gate 321 is at a high level, the second switch tube K2 is turned on, so as to ground the output terminals of the fuse unit 120 and the set unit 110, or provide a low level signal for the output terminals of the fuse unit 120 and the set unit 110. The first power supply and the second power supply may be working power supplies of the latch module 100, or may be separately provided power supplies.

The latch 140 is configured to receive and latch the high level signal output by the setting unit 110, the fuse data signal FuseData output by the fuse unit 120, or the low level signal output by the reset unit 130. In this embodiment, the latch 140 receives and latches the high level signal provided by the setting unit 110 in the test mode, and receives and latches the fuse data signal FuseData provided by the fuse unit 120 in the normal operation mode.

The output unit 150 is configured to output the latched high level signal, the fuse data signal FuseData, or the low level signal.

For a clearer description of the present invention, the operation of the latch circuit shown in fig. 2 and 4 will be described in detail.

In the test mode, the fuse selection signal terminal is grounded, and the self-test enable signal DFTEN is connected to a high level. When the test coding signal DFTCODE0, the self-test coding signal DFTCODE1, the self-test coding signal DFTCODE2, the SET signal SET and the control signal CTRL are all at a high level, an output signal of the SET control module obtained through logic and processing is at a high level, then the output signal of the SET control module is processed by a first inverter and is provided to the first switching tube K1, and the first switching tube K1 is turned on to receive a high level signal provided by a first power supply. When the SET signal SET is at a low level, the reset control module 300 controls the latch module 100 to reset, so that the latch module 100 outputs a low level signal, thereby implementing a test function by setting 0 or 1.

In the normal operation mode, the self-test enable signal DFTEN terminal and the set signal terminal are grounded. When the fuse selection signal FuseSel and the fuse clock signal FuseClk are both at a high level, the transmission gate T is turned on, and the latch 140 latches the fuse data signal FuseData transmitted through the transmission gate. And resetting the latch module 100 by the Reset signal Reset after writing the fuse data signal FuseData.

In summary, the embodiments of the present invention provide a latch circuit. The latch circuit includes: a latch module 100, a set control module 200, a reset control module 300, and a clock module 400. The latch module 100 is configured to latch data input by the data module; the SET control module 200 is configured to control the latch module 100 to output a high level signal, and input signals of the SET control module 200 include a control signal CTRL and a SET signal SET; the Reset control module 300 is configured to control the latch module 100 to output a low level signal, and input signals of the Reset control module 300 include an output signal of the set control module, a self-test enable signal DFTEN, and a Reset signal Reset; the clock module 400 is used for providing a read clock signal for the latch module 100; wherein the self-test enable signal DFTEN determines that the latch 140 is in a self-test mode or a normal operation mode. In the invention, by arranging the latch module 100, the set control module 200, the reset control module 300 and the clock module 400, controlling the latch module 100 to output a high level signal through the set control module 200 in a self-test mode, and outputting the high level signal for testing through the latch 140, and reading and latching data from a data module by the latch module 100 according to the read clock signal in a normal working mode, the function of latching the data input by the data module and the DFT function are realized, the structure of the latch 140 circuit is simplified, and the required chip area is reduced.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.