阅读说明：本技术 层叠型半导体装置、承载部件组、基体及凸块连接体 (Stacked semiconductor device, carrier member set, base, and bump connector ) 是由 元吉真 于 2020-11-26 设计创作，主要内容包括：本申请提供层叠型半导体装置、承载部件组、基体及凸块连接体,容易进行承载的承载元件的修复处理,可进行多次修复处理,缩短制造时间,防止资源浪费。具备：主基板(81),具有基板承载面和与该基板承载面相对的基体背面；承载元件(X-(ij)),具有承载元件侧电路和面向基板承载面的连接面；母凸块(11),设置于基板承载面,具有与基板承载面垂直的壁状的基体侧曲面；及修复凸块(21、22、23),设置于连接面,具有与连接面垂直的壁状的修复侧曲面,在从连接面的法线方向观察到的平面图案中的基体侧曲面与修复侧曲面的交点处与母凸块彼此相互咬入。在基体侧曲面与修复侧曲面的交点处,母凸块和修复凸块中任一方含有硬度比剩余部分高的导电体。(The present application provides a stacked semiconductor device, a carrier member group, a substrate, and a bump connector, which can easily perform a repair process of a carrier element to be carried, can perform a repair process a plurality of times, can shorten a manufacturing time, and can prevent waste of resources. The disclosed device is provided with: a main substrate (81) having a substrate-supporting surface and a base back surface opposite to the substrate-supporting surface; bearing element (X) ij ) A circuit on the side of the bearing element and a connecting surface facing the bearing surface of the substrate; the female bump (11) is arranged on the substrate bearing surface and is provided with a wall-shaped base body side curved surface vertical to the substrate bearing surface; and repair projections (21, 22, 23) provided on the connection surface, having wall-shaped repair-side curved surfaces perpendicular to the connection surface, and located at intersections of the base-side curved surfaces and the repair-side curved surfaces in the planar pattern as viewed from a normal direction of the connection surfaceAnd the female protrusions bite into each other. At the intersection of the base-side curved surface and the repair-side curved surface, either the female bump or the repair bump contains an electrical conductor having a higher hardness than the remaining portion.)

1. A stacked semiconductor device is characterized by comprising:

a main substrate having a substrate carrying surface and a base back surface opposite to the substrate carrying surface, and provided with a main substrate circuit;

a carrier having a carrier-side circuit and a connection surface facing the substrate carrying surface;

the female bump is arranged on one side of the substrate bearing surface, is provided with a wall-shaped base body side curved surface vertical to the substrate bearing surface and is electrically connected with the main substrate circuit; and

a repair bump provided on one side of the connection surface, having a wall-shaped repair side curved surface perpendicular to the connection surface, and electrically connected to the carrier-side circuit, the repair bump and the female bump biting into each other at an intersection of the base-side curved surface and the repair side curved surface in a planar pattern viewed from a normal direction of the connection surface,

conductors having different hardness are unevenly contained in a space at and near an intersection point of the base-side curved surface and the repair-side curved surface which are mutually engaged.

2. The stacked semiconductor device according to claim 1,

at least one of the base-side curved surface and the repair-side curved surface has a laminated structure of two or more conductor layers, and two layers adjacent to each other in the laminated structure have different hardness from each other.

3. The stacked semiconductor device according to claim 1,

the first bearing part is formed by the combination of the bearing element and the repair lug,

the second bearing component with the same structure, the same size and the same function as the first bearing component is borne on the substrate bearing surface.

4. The stacked semiconductor device according to claim 1,

the stacked semiconductor device further includes a field insulating film interposed between the main substrate and the mother bump.

5. The stacked semiconductor device according to claim 4,

the stacked semiconductor device further includes a mother-bump-side land electrically connected to the mother bump in the field insulating film or on the upper surface of the field insulating film.

6. The stacked semiconductor device according to claim 1,

a plurality of wiring insulating layers are interposed between the carrier element and the repair bump.

7. The stacked semiconductor device according to claim 6,

the multilayer semiconductor device further includes a repair bump-side land electrically connected to the repair bump in the multilayer wiring insulating layer or on a surface of the multilayer wiring insulating layer facing the substrate mounting surface.

8. A carrier set characterized in that the carrier set is a set of a plurality of carriers prepared so that at least a part of the total number is carried on a base having a main substrate having a substrate carrying surface and a base back surface opposite to the substrate carrying surface and provided with a main substrate circuit, and female bumps provided on the substrate carrying surface side, having a wall-like base-side curved surface perpendicular to the substrate carrying surface, and electrically connected to the main substrate circuit, each carrier comprising:

a carrier having a carrier-side circuit and a connection surface facing the substrate carrying surface; and

a repair bump provided on one side of the connection surface, having a wall-shaped repair side curved surface perpendicular to the connection surface, and electrically connected to the carrier-side circuit, the repair bump and the female bump biting into each other at an intersection of the base-side curved surface and the repair side curved surface in a planar pattern viewed from a direction perpendicular to the connection surface,

at the intersection of the base-side curved surface and the repair-side curved surface, the repair bump contains an electrical conductor having a hardness higher than that of the female bump.

9. The carrier pack of claim 8,

in each of the bearing members, the repair-side curved surface has a laminated structure of two or more conductor layers, and two layers adjacent to each other in the laminated structure have different hardness from each other.

10. The carrier pack of claim 8,

in each of the carrier members, a multilayer wiring insulating layer is interposed between the carrier element and the repair bump.

11. The carrier component group of claim 10,

in each of the carrier members, a repair bump-side land electrically connected to the repair bump is further provided in the multilayer wiring insulating layer or on a surface of the multilayer wiring insulating layer facing the substrate mounting surface.

12. A substrate carrying a carrier member, the carrier member having: a carrier element provided with a connection face and a carrier-element-side circuit; and a repair bump provided on the connection surface side, having a wall-shaped repair side curved surface perpendicular to the connection surface, and electrically connected to the carrier element side circuit, the base body including:

the main substrate is provided with a substrate bearing surface and a base body back surface opposite to the substrate bearing surface, and is provided with a main substrate circuit, and the substrate bearing surface is opposite to the connecting surface and is used for bearing the bearing part; and

a female bump provided on one side of the substrate carrying surface, having a wall-shaped base-side curved surface perpendicular to the substrate carrying surface, and electrically connected to the main substrate circuit, the female bump and the repair bump biting into each other at an intersection of the base-side curved surface and the repair-side curved surface in a planar pattern viewed from a normal direction of the substrate carrying surface,

the female bump includes a conductor having a hardness higher than that of the repair bump at an intersection between the base-side curved surface and the repair-side curved surface.

13. The matrix of claim 12,

the curved surface on the base side has a laminated structure of two or more conductor layers, and two layers adjacent to each other in the laminated structure have different hardness from each other.

14. A bump connector that mutually couples a main substrate and a carrier, the main substrate having a substrate carrying surface and a base back surface opposite to the substrate carrying surface and provided with a main substrate circuit, the carrier having a connection surface and a carrier-side circuit, the bump connector electrically connecting the main substrate circuit and the carrier-side circuit, the bump connector comprising:

the female bump is arranged on one side of the substrate bearing surface, is provided with a wall-shaped base body side curved surface vertical to the substrate bearing surface and is electrically connected with the main substrate circuit; and

a repair bump provided on one side of the connection surface, having a wall-shaped repair side curved surface perpendicular to the connection surface, and electrically connected to the carrier-side circuit, the repair bump and the female bump biting into each other at an intersection of the base-side curved surface and the repair side curved surface in a planar pattern viewed from a normal direction of the connection surface,

conductors having different hardness are unevenly contained in a space at and near an intersection point of the base-side curved surface and the repair-side curved surface which are mutually engaged.

15. The bump connector according to claim 14,

at least one of the base-side curved surface and the repair-side curved surface has a laminated structure of two or more conductor layers, and two layers adjacent to each other in the laminated structure have different hardness from each other.

Technical Field

The present invention relates to a stacked semiconductor device, a carrier member set used for the stacked semiconductor device, and a base and bump connector used for the stacked semiconductor device, and more particularly to a large-diameter main substrate and a defective repair technique for sorting carrier members that do not operate normally and carrying only a plurality of carrier chips that operate normally on the main substrate.

Background

Patent document 1 discloses a radiation two-dimensional detector having: an active matrix substrate including a pixel electrode; and a counter substrate bonded to the active matrix substrate via conductive bumps connected to the pixel electrodes. In such flip chip bonding, there are problems as follows: when the pitch of the pixel electrodes is fine, it is not easy to perform connection by uniform bumps. In contrast, patent document 2 discloses a solid-state detector in which each pixel electrode of a signal readout chip as a carrier chip is reliably connected to a cylindrical electrode connected between a counter substrate.

However, in a stacked semiconductor device in which a plurality of small-diameter carrier chips are carried on a large-diameter main substrate, there are problems as follows: if there is a defect in the carrier chip in which the fine carrier chip side circuit is integrated, the stacked semiconductor device does not operate. In the case of a large-diameter main substrate used for an image sensor or the like, the main substrate having detection elements arranged as pixels can be manufactured with a relaxed design rule, and a chip-side circuit is also simple, so that the manufacturing is easy and the probability of occurrence of defects is low. In addition, even if there are defects in the main board circuit, the connection wiring, and the like of the main board, they are random and hardly visible in the output of the main board.

On the other hand, the carrier chip carried on the large-diameter main substrate is highly integrated and is manufactured with a design rule much finer than that of the main substrate, and therefore, the probability of occurrence of defects is high. However, by carrying the carrier chip on the main substrate by connection using bumps or the like and performing a test, it is known that the carrier chip side circuit integrated on the carrier chip is good or bad. Therefore, when the yield of the carrier chip is high or when there is a block defect, the entire stacked semiconductor device is defective, the manufacturing efficiency is low, and the main substrate and the carrier chip which is normally operating and is carried on the main substrate are wasted.

In view of such circumstances, it is desirable to peel off only the defective carrier chip from the main substrate and replace only the defective carrier chip with another carrier chip that normally operates. However, in the current state of the art, it is not known that bumps or the like capable of simply peeling off only a specific carrier chip and simply connecting other carrier chips in the presence of a defect are able to be obtained.

Patent document 1: international publication No. 2014/006812

Patent document 2: international publication No. 2017/081798

Disclosure of Invention

In view of the above problems, it is an object of the present invention to provide a stacked semiconductor device in which a repair process of a carrier element mounted on a main substrate is easily performed, a plurality of repair processes can be performed, a manufacturing time can be shortened, and waste of resources can be prevented, a carrier member set at least a part of which is used for the stacked semiconductor device, and a base and a bump connected body used for the stacked semiconductor device.

In order to achieve the above object, a first aspect of the present invention is directed to a stacked semiconductor device including: (a) a main substrate having a substrate carrying surface and a base back surface opposite to the substrate carrying surface, and provided with a main substrate circuit; (b) a bearing element having a bearing element side circuit and a connecting surface facing the bearing surface of the substrate; (c) the female bump is arranged on the substrate bearing surface, has a wall-shaped base body side curved surface vertical to the substrate bearing surface and is electrically connected with the main substrate circuit; and (d) a repair bump provided on the connection surface, having a wall-like repair side curved surface perpendicular to the connection surface, and electrically connected to the carrier-side circuit, the repair bump and the female bump biting into each other at an intersection of the base-side curved surface and the repair side curved surface in the planar pattern as viewed from a normal direction of the connection surface. The laminated semiconductor device according to the first aspect of the present invention is characterized in that conductors having different hardnesses are unevenly contained in a space at and near an intersection between the base-side curved surface and the repair-side curved surface, which are mutually engaged with each other.

A second aspect of the present invention relates to a carrier set including a set of a plurality of carrier members prepared as predetermined, the carrier set being carried on a base including: a main substrate having a substrate carrying surface and a base back surface opposite to the substrate carrying surface, and provided with a main substrate circuit; and the female bump is arranged on the substrate bearing surface, has a wall-shaped base body side curved surface vertical to the substrate bearing surface and is electrically connected with the main substrate circuit. A carrier member set according to a second aspect of the present invention is a carrier member set comprising: the load bearing members of the group are each provided with: a bearing element having a bearing element side circuit and a connecting surface facing the bearing surface of the substrate; and a repair bump provided on the connection surface, having a wall-like repair side curved surface perpendicular to the connection surface, and electrically connected to the carrier-side circuit, the repair bump and the female bump biting into each other at an intersection of the base-side curved surface and the repair side curved surface in the planar pattern viewed from a direction perpendicular to the connection surface. In the first aspect of the present invention, the repair side curved surface is formed on the base side curved surface, and the repair side curved surface is formed on the base side curved surface.

A third aspect of the invention relates to a base body that carries a carrier member having: a carrier element having a connection face and a carrier-element-side circuit; and the repair lug is arranged on the connecting surface, has a wall-shaped repair side curved surface vertical to the connecting surface, and is electrically connected with the bearing element side circuit. A substrate according to a third aspect of the present invention includes: the main substrate is provided with a substrate bearing surface and a base body back surface opposite to the substrate bearing surface, and is provided with a main substrate circuit, and the substrate bearing surface is opposite to the connecting surface and is used for bearing the bearing part; and a female bump provided on the substrate carrying surface, having a wall-shaped base-side curved surface perpendicular to the substrate carrying surface, and electrically connected to the main substrate circuit, the female bump and the repair bump biting into each other at an intersection of the base-side curved surface and the repair-side curved surface in the planar pattern as viewed from a normal direction of the substrate carrying surface. In the substrate according to the third aspect of the present invention, the female bump includes a conductor having a hardness higher than that of the repair bump at an intersection between the substrate-side curved surface and the repair-side curved surface.

A fourth aspect of the invention relates to a bump connector that mutually couples a main substrate having a substrate carrying surface and a back surface of a base opposite to the substrate carrying surface and provided with a main substrate circuit and a carrier having a connection surface and a carrier-side circuit, and a carrier element that electrically connects the main substrate circuit and the carrier-side circuit. A bump connector according to a fourth aspect of the present invention includes: the female bump is arranged on the substrate bearing surface, has a wall-shaped base body side curved surface vertical to the substrate bearing surface and is electrically connected with the main substrate circuit; and a repair bump provided on the connection surface, having a wall-shaped repair side curved surface perpendicular to the connection surface, and electrically connected to the carrier side circuit, the repair bump and the female bump biting into each other at an intersection of the base side curved surface and the repair side curved surface in the planar pattern as viewed from a normal direction of the connection surface. In the bump connected body according to the fourth aspect of the present invention, the conductors having different hardnesses are unevenly contained in the space at and near the intersection of the base-side curved surface and the repair-side curved surface, which are mutually engaged with each other.

Effects of the invention

According to the present invention, it is possible to provide a stacked semiconductor device in which a repair process of a carrier element mounted on a main substrate is easily performed, a plurality of repair processes can be performed, a manufacturing time can be shortened, and waste of resources can be prevented, a carrier member set at least a part of which is used for the stacked semiconductor device, and a base and a bump connector which are used for the stacked semiconductor device.

Drawings

Fig. 1 is a plan view illustrating a stacked semiconductor device (solid-state imaging device) according to a first embodiment of the present invention.

Fig. 2 is a sectional view seen from the direction II-II of fig. 1.

Fig. 3A is a schematic partial cross-sectional view, as viewed from a specific direction, illustrating a state before temporary connection of the bump connector in the stacked semiconductor device according to the first embodiment.

Fig. 3B is a view corresponding to fig. 3A, and is a schematic partial cross-sectional view, as viewed from a specific direction, illustrating a state of temporary connection of the bump connector in the stacked semiconductor device according to the first embodiment.

Fig. 4 is a plan view illustrating the position and direction of a cross-sectional plane of the cross-sectional views shown in fig. 3A and 3B.

Fig. 5A is a schematic plan view illustrating a notch-shaped dimple formed in a mother bump of the stacked semiconductor device according to the first embodiment.

Fig. 5B is a schematic side view corresponding to fig. 5A for explaining the notch-shaped dent formed in the mother bump of the stacked semiconductor device according to the first embodiment.

Fig. 6 is a plan view illustrating four intersections between the mother bumps and the repair bumps in the stacked semiconductor device according to the first embodiment of the present invention.

Fig. 7A is a schematic cross-sectional view illustrating a state where the repair bump and the mother bump are separated before reaching the structure of the bump connector of the stacked semiconductor device according to the first embodiment, as viewed from the VIIB-VIIB direction in fig. 6.

Fig. 7B is a schematic cross-sectional view of the bump connector of the stacked semiconductor device according to the first embodiment, as viewed from a VIIB-VIIB direction in fig. 6.

Fig. 8 is a schematic bird's eye view illustrating a relationship between a repair bump and a mother bump in the stacked semiconductor device according to the first modification of the first embodiment of the present invention.

Fig. 9 is a schematic bird's eye view illustrating a relationship between a repair bump and a mother bump in the stacked semiconductor device according to the second modification of the first embodiment of the present invention.

Fig. 10 is a schematic bird's eye view illustrating a relationship between a repair bump and a mother bump in the stacked semiconductor device according to the second embodiment of the present invention.

Fig. 11 is a schematic bird's eye view illustrating a relationship between a repair bump and a mother bump in the stacked semiconductor device according to the first modification of the second embodiment of the present invention.

Fig. 12 is a schematic bird's eye view illustrating a relationship between a repair bump and a mother bump in a stacked semiconductor device according to a second modification of the second embodiment of the present invention.

Fig. 13 is a schematic bird's eye view illustrating a relationship between a repair bump and a mother bump in the stacked semiconductor device according to the third embodiment of the present invention.

Fig. 14 is a schematic bird's eye view illustrating a relationship between a repair bump and a mother bump in the stacked semiconductor device according to the first modification of the third embodiment of the present invention.

Fig. 15 is a schematic bird's eye view illustrating a relationship between a repair bump and a mother bump in a stacked semiconductor device according to a second modification of the third embodiment of the present invention.

Fig. 16 is a schematic bird's eye view illustrating a relationship between a repair bump and a mother bump in the stacked semiconductor device according to the fourth embodiment of the present invention.

Fig. 17 is a schematic bird's eye view illustrating a relationship between a repair bump and a mother bump in the stacked semiconductor device according to the first modification of the fourth embodiment of the present invention.

Fig. 18 is a schematic bird's eye view illustrating a relationship between a repair bump and a mother bump in a stacked semiconductor device according to a second modification of the fourth embodiment of the present invention.

Fig. 19A is a partial cross-sectional view illustrating a state before temporary connection of bump connectors in a stacked semiconductor device according to another embodiment.

Fig. 19B is a schematic partial cross-sectional view illustrating a state after temporary connection of the bump connector in the stacked semiconductor device according to the other embodiment shown in fig. 19A.

Fig. 20A is a schematic partial cross-sectional view, as viewed from a specific direction, illustrating a state before temporary connection of a bump connector in a stacked semiconductor device according to still another embodiment.

Fig. 20B is a schematic partial cross-sectional view, as viewed from a specific direction, illustrating a state after temporary connection of the bump connector in the stacked semiconductor device according to still another embodiment shown in fig. 20A.

Fig. 21 is a schematic partial cross-sectional view, as viewed from a specific direction, illustrating a state of temporary connection of bump connectors in a stacked semiconductor device according to still another embodiment.

Fig. 22 is a schematic partial cross-sectional view, as viewed from a specific direction, illustrating a state before temporary connection of a bump connector in a stacked semiconductor device according to still another embodiment.

FIG. 23 is a cross-sectional view of the section IIIA including FIG. 4_d-IIIA_dA SEM (scanning electron microscope) photograph explaining a state where the repair bump is removed after the step of main connection of the stacked semiconductor device according to the first embodiment of the present invention is performed at the position of (a).

Description of the reference numerals

1 … base, 2 … carrier, 11, 14a, 14B, 15, 16 … mother bump, 12a, 12B … mother bump-side land, 19a, 19B … repair bump-side land, 20 … multilayer wiring insulating layer, 21, 31 … outermost layer, 22, 32 … intermediate layer, 23, 33 … innermost layer, 25 … intermediate layer, 27 … low hardness layer (first layer), 28 … intermediate layer (second layer: high hardness layer), 29 … third layer, 41 … repair bump, 81 … main substrate, 82 … field insulating film, B … field insulating film₁₁、B₁₂、B₁₃、B₂₁、B₂₂、B₂₃、B_uv… bump connector, X₂₁、X₂₂、X_2m、X_ij、X_st、X_xy… bearing element

Detailed Description

First to fourth embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and overlapping description is omitted. However, the drawings are schematic, and the relationship between the thickness and the planar size, the ratio of the thicknesses of the respective layers, and the like may be different from those in practice. In addition, the drawings may include portions having different dimensional relationships and ratios. The first to fourth embodiments described below illustrate apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is not to specify the materials, shapes, structures, arrangements, and the like of the constituent members as follows.

The definitions of the directions such as the top and bottom in the following description are for convenience of description and do not limit the technical idea of the present invention. For example, it goes without saying that the vertical conversion is performed to the left and right for observation with the object rotated by 90 °, and the vertical conversion is performed for observation with the object rotated by 180 °.

(first embodiment)

As shown in fig. 1 and 2, a stacked semiconductor device according to a first embodiment of the present invention has a large-diameter main substrate 81 and a plurality of rectangular carrier elements X mounted on a substrate mounting surface (first main surface) which is one main surface of the main substrate 81_ij(i is 1 to n: j is 1 to m: n, and m is a positive integer of 1 or more). That is, the stacked semiconductor device according to the first embodiment may have a stacked structure of 1 chip (carrier element) with n ═ m ═ 1. The main substrate 81 has a parallel flat plate structure in which a substrate-supporting surface and a base back surface (second main surface) are opposed in parallel. If the stacked semiconductor device is a solid-state imaging device, the back surface (second main surface) of the base of the main substrate 81 facing the substrate-carrying surface is configured to receive the electromagnetic wave Φ as shown in fig. 2_xAn input face for incidence. On the other hand, if the stacked semiconductor device is a solid-state display device such as a micro LED display, several hundred thousand to several million LED chips are mounted in a matrix on a driving panel serving as a main substrate 81 as a mounting element X_ijThus, a laminated structure is formed. A pixel region divided along the macro-grid (first grid) is defined on the substrate carrying surface (first main surface) of the main substrate 81, and a detection element array constituting a main substrate circuit is arranged in the pixel region.

The substrate-carrying surface of the main substrate 81 is divided into a macro-lattice having a mesh ratioA small number of substrate-bearing regions defined by the grid (second grid). Carrying element X_ijAnd reading out signals from the divided substrate carrying regions. In reverse, with the carrier element X_ijThe substrate mounting surface of the main substrate 81 is divided into substrate mounting areas constituting a substrate mounting lattice having a mesh number smaller than p × q (p < n, q < m) of the macro lattice in accordance with the arrangement position of (b). The main substrate 81 has a structure in which main substrate circuits are integrated, for example, 10cm × 10cm, and in this structure, detection elements such as p-n diodes, n-i-n diodes, and p-i-p diodes are arranged in pixel regions divided along a macro lattice. Carrying element X_ijIs smaller than the area of the main substrate 81, a plurality of carrier elements X_ijThe main board 81 is arranged so as to cover substantially the entire surface of the main board 81 in a region defined by a board carrying grid of 2 × 2 to 8 × 8 or the like in accordance with the size of the main board 81.

In fig. 1, along the uppermost carrier element X₁₁、X₁₂、X₁₃、……、X_1mIn the arrangement of the bonding pads P arranged on the periphery of the main substrate 81_k1、P_k2、P_k3、……、P_ks. If the bonding pads P are to be arranged_k1、P_k2、P_k3、……、P_ksThe side of the main substrate 81 is defined as a "first side", and the bonding pads P are arranged on the periphery of the main substrate 81 along a second side of the main substrate 81 continuous with the first side and orthogonal to the first side_l1、P_l2、P_l3、……、P_lt. Along a third side of the main substrate 81 continuous with the second side and orthogonal to the second side, bonding pads P are arranged on the periphery of the main substrate 81_m1、P_m2、P_m3、……、P_ms. Along a fourth side of the main substrate 81 continuous with the third side and orthogonal to the third side, the bonding pads P are arranged on the periphery of the main substrate 81_n1、P_n2、P_n3、……、P_nt。

As shown in the cross-sectional view of fig. 2, a field insulating film 82 is formed on the main substrate 81. In the cross-sectional view of fig. 2, a carrier is disposed at the left end of the main substrate 81 with a field insulating film 82 interposed therebetweenElement X₂₁And shows at the carrier element X₂₁Bump connectors B arranged in the region of a connection lattice (third lattice) having the same mesh number as the macro lattice with the main substrate 81₁₁、B₁₂、B₁₃、……、B_1pIs arranged in one column. On the carrier element X₂₁A multilayer wiring insulating layer 20 is provided on top (lower surface in fig. 2). Arranged on the carrier element X as shown in FIG. 2₂₁Is formed inside the multilayer wiring insulating layer 20 so as to be disposed on the carrier element X₂₁Multiple wiring layers such as an upper wiring layer, an intermediate wiring layer, and a lower wiring layer are embedded so as to be separated from each other in a manner corresponding to the carrier-side circuit. For example, the multilayer wiring insulating layer 20 may have: arranged on a carrier element X as a supporting substrate₂₁A plurality of first wiring pattern layers on the surface (lower surface in fig. 2), a plurality of through holes penetrating from the upper surface of the multilayer wiring insulating layer 20 toward the lower surface, a plurality of second wiring pattern layers disposed under the multilayer wiring insulating layer 20, and the like. "Circuit" refers to the "path of current" (the broad term is used in the fourth edition). In general, active elements such as transistors and diodes, and passive elements such as resistors, capacitors, and coils are often included. However, in view of the concept of a high-frequency distributed constant circuit, a simple current path also includes a resistor, a capacitor, and a coil, and thus is an electronic circuit (electric circuit). Thus, even if the element X is carried₂₁(more generally, the carrier element X_ij) The diode circuit is a simple diode circuit such as an LED chip constituting a micro LED display, and also corresponds to a "carrier element side circuit". The main board circuit is also the same, and may be a simple diode circuit, a wiring circuit not including an active element, or the like. In addition, is arranged on the bearing element X_ijThe carrier-side circuit of (a) may be a simple resistance circuit such as a temperature sensor or a heating element, and thus various electronic circuit elements can be used as the carrier element X_ij。

The multilayer wiring insulating layer 20 may be formed of three or more multilayer insulating layers, and may further include, for example, a third wiring pattern layer, a fourth wiring pattern layer, a fifth wiring pattern layer, … …And the like. First wiring pattern layer and carrier element X₂₁Are electrically connected, respectively. The through holes of the multilayer wiring insulating layer 20 electrically connect the first wiring pattern layer and the second wiring pattern layer, respectively. Solder bumps for bonding to an external circuit can be arranged on the lower surface of the second wiring pattern layer of the multilayer wiring insulating layer 20.

Alternatively, each carrier-side circuit (signal readout circuit) may be configured by a thin film integrated circuit provided inside the multilayer wiring insulating layer 20 as in the SOI structure. In this case, a switching element or a readout capacitor including a thin film transistor may be formed in the multilayer interconnection insulating layer 20 through a multilayer interconnection layer such as an upper interconnection layer, an intermediate interconnection layer, and a lower interconnection layer with an interlayer insulating film interposed therebetween. Alternatively, the support member X may be made of a metal_ijThe structure of fig. 2 is considered such that the carrier-side circuit on the lower layer wiring side in the multilayer wiring insulating layer 20 corresponds to an integrated circuit formed on the surface of a silicon (Si) substrate, and the interlayer wiring in the multilayer wiring insulating layer 20 corresponds to the surface wiring layer in the interlayer insulating film. In addition, the unit of the carrier-side circuit composed of a group of a readout capacitor and a switching element corresponding to the arrangement of the unit elements of the main substrate circuit of the main substrate 81 may be integrated into the carrier X composed of an Si substrate₂₁Is formed by the upper part of the upper part. Aligned bump connector B₁₁、B₁₂、B₁₃、……、B_1pThe mesh pitch of the connecting lattice of (2) may be the same as that of the macro lattice, or may be a pitch obtained by pitch conversion of the macro lattice.

On the field insulating film 82 of FIG. 2, on the carrier element X₂₁Is provided with a bearing element X at the right side₂₂And shows at the carrier element X₂₂Bump connectors B arranged in the region of connection lattices having the same mesh number as the macroscopic lattices between the main substrate 81 and the bump connectors B₂₁、B₂₂、B₂₃、……、B_2pIs arranged in one column. On the carrier element X₂₂And the lower surface of the carrier element X₂₁A plurality of wiring insulating layers 20 are similarly provided. In the inside of the multilayer wiring insulating layer 20,to and from the carrier element X₂₂Multiple wiring layers such as an upper wiring layer, an intermediate wiring layer, and a lower wiring layer are embedded so as to be separated from each other in a manner corresponding to the carrier-side circuit. Likewise, in the carrier element X_2(m-1)Between the main substrate 81, bump connectors B arranged in the region of the connection lattice are shown_(m-1)1、B_(m-1)2、B_(m-1)3、……、B_(m-1)pIs arranged in one column. On the carrier element X_2(m-1)And the lower surface of the carrier element X₂₁A plurality of wiring insulating layers 20 are similarly provided. Inside the multi-layer wiring insulation layer 20 and arranged on the carrier element X_2(m-1)Multiple wiring layers such as an upper wiring layer, an intermediate wiring layer, and a lower wiring layer are embedded so as to be separated from each other in a manner corresponding to the carrier-side circuit.

Further, a carrier element X is arranged on the right end side of the main substrate 81 via a field insulating film 82_2mAnd shows at the carrier element X_2mBump connector B arranged in connection grid region with main substrate 81_m1、B_m2、B_m3、……、B_mpIs arranged in one column. On the carrier element X_2mLower surface and carrier element X₂₁A plurality of wiring insulating layers 20 are similarly provided. Inside the multi-layer wiring insulation layer 20 and arranged on the carrier element X_2mMultiple wiring layers such as an upper wiring layer, an intermediate wiring layer, and a lower wiring layer are embedded so as to be separated from each other in a manner corresponding to the carrier-side circuit.

That is, in the cross-sectional structure of the arrangement in which fig. 2 illustrates one column, the carrier element X is shown_ijA plurality of bump connectors B arranged in the region of the connection lattice corresponding to the arrangement defined by the macro lattice of the detection element array constituting the main substrate circuit between the main substrates 81_uv(u is 1 to m, v is 1 to p, and m and p are positive integers of 2 or more), but it is needless to say that the same structure is present except for the cross section of fig. 2. The carrier element X in FIG. 2₂₁、X₂₂、X₂₃、……、X_2mShows the bonding pad P on the left side of the arrangement_n(t-3)In the carrier element X₂₁、X₂₂、X₂₃、……、X_2mShows the bonding pad P on the right side of the arrangement_l4. In the following description, the bump connectors including the other bump connectors existing outside the cross section of fig. 2 are collectively referred to as "bump connector B_uv". Bump connector B_uvEach of the detection element arrays constituting the main substrate circuit arranged in the pixel regions divided along the macro lattice on the substrate carrying surface (first main surface) of the main substrate 81 and the corresponding carrying element X_ijEach electrically connected independently of the other.

The main board 81 is manufactured with a loose design rule and is simple in layout, so that the manufacturing is easy and the probability of occurrence of defects is low. In addition, even if there are defects in the main substrate circuit (detection element array) and the connection wiring of the main substrate 81, they are random and hardly visible in the output of the main substrate 81. On the other hand, the carrier element X_ijHigh integration by connecting the body B with bumps_uvTo carry the component X_ijThe test is performed by connecting to the main substrate 81, and it is known that the carrier element X is integrated_ijOn the carrier side circuit. Provided at a plurality of connected carriers X_ijWhen the defective rate is high or when a block defect is present, the stacked semiconductor device according to the first embodiment is defective. On the other hand, in the micro LED display, since a large number of LED chips up to several hundred thousand to several million are stacked on the driving panel, there is a possibility that defective products are mixed in the large number of LED chips. For this purpose, the carrying elements X are arranged_ijTemporarily connected to the main substrate 81 and integrated on a specific carrier element X_stWhen the circuit on the carrier side is defective, the carrier X needs to be mounted_stStripping and temporarily joining other carrier elements X_xyTo confirm whether there is no problematic repair work. Due to the scheduled repair work, the carrier element X is carried_ijThe number of the holes is prepared to be larger than the number of the meshes of the board supporting grid defined on the main board 81.

The bump connector B_uvThe details of the above will be described later with reference to fig. 3A, 3B to 7B. Convex partBlock connector B_uvConfigured to independently transmit a signal from a main substrate circuit integrated on the main substrate 81 to the carrier elements X respectively integrated on the carrier elements X_ijUpper carrier side circuitry. If the stacked semiconductor device according to the first embodiment is a solid-state imaging device, the arrangement of the detection element array constituting the main substrate circuit arranged on the substrate mounting surface (first main surface) of the main substrate 81 corresponds to the arrangement of the pixels of the image sensor (stacked semiconductor device), but in the case of a micro LED display, corresponds to the arrangement of the LED chips. In addition, the array of temperature sensors corresponds to the arrangement of the temperature sensors. In the case of a solid-state imaging device, the carrier element X_ijEach of the carrier-side circuits (signal read-out circuits) of (1) includes a switching element (Q)_ijAnd an active element circuit such as a buffer amplifier. Carrying element X_ijSignals from the macro lattices of the pixels arranged at the corresponding division portions on the substrate carrying surface of the main substrate 81 are read out, respectively.

In the following description of the first embodiment, the material and use of the main substrate 81 are not limited. That is, if the stacked semiconductor device according to the first embodiment is a solid-state imaging device, the main substrate 81 is made of silicon (Si), so that the stacked semiconductor device according to the first embodiment is suitable as an image sensor in a wavelength region of visible light as a solid-state imaging device. In the case where the stacked semiconductor device according to the first embodiment is a solid-state imaging device, if the unit elements (detection elements) constituting the main substrate circuit arranged on the main substrate 81 are cadmium telluride (CdTe), zinc telluride (ZnTe), or cadmium zinc telluride (Cd)_1-xZn_xTe) and gallium arsenide (GaAs) are suitable as radiation image sensors. In addition, if mercury cadmium telluride (Hg) is used_1-xCd_xTe), semimetals such as indium antimonide (InSb), or infrared detection elements such as germanium (Ge) are arranged on the main substrate 81, and thus an infrared image sensor is obtained. Therefore, the stacked semiconductor device according to the first embodiment of the present invention can be applied to, for example, an image sensor having electromagnetic waves of various wavelengths, but is not limited to thisIs fixed on a solid-state imaging device (image sensor).

In the case where the stacked semiconductor device according to the first embodiment is a solid-state imaging device, a signal generated as a pair of electron and hole in a carrier generation layer of a unit element of a main substrate circuit arranged in a pixel region partitioned along a macro lattice inside the main substrate 81 is read from an opening (contact hole) of a field insulating film 82 of each main substrate circuit. As shown in fig. 3A and 3B, the region of the main substrate 81 under the field insulating film 82 forms a detection element of one pixel amount that outputs a signal corresponding to the amount of the received electromagnetic wave. If the stacked semiconductor device according to the first embodiment is a solid-state imaging device, the opening (contact hole) provided in the field insulating film 82 is formed in the carrier element X_ijAre two-dimensionally arranged apart from each other, and signals indicating carriers generated in the main substrate 81 are read from output electrodes embedded in the field insulating film 82. Thus, the main substrate 81 functions as a detection substrate for detecting electromagnetic waves, and the female bump-side land (surface electrode) provided at the opening in the field insulating film 82 functions as an output electrode of the main substrate circuit that outputs a carrier signal for each main substrate circuit (pixel).

The main substrate 81 has bump connectors B formed on a substrate mounting surface (first main surface) where one electrode of a unit element (detection element) constituting a main substrate circuit is exposed, the bump connectors B corresponding to the arrangement of a pixel array of the main substrate circuit_uvThe female bumps (first bumps) 11 of each bump connector are arranged in the region of the connection lattice. The female bump 11 has a rectangular box shape having a wall-shaped base-side curved surface perpendicular to the substrate receiving surface of the main substrate 81. Since the base-side curved surface is a flat plate because of the rectangular box shape, the flat plate-shaped wall is also referred to as a "curved surface" in this specification because the straight line is a curve having an infinite curvature radius mathematically. As shown in fig. 3A, 3B, and the like, the bottom of the female bump 11 is electrically connected to the surface electrode (female bump-side land) 12 via a contact through-hole (through-hole plug) 17, and further electrically connected to a main substrate circuit integrated on the main substrate 81. As illustrated in fig. 3A and 3B, etc., the contact via 17 and the motherThe bump-side land 12 is embedded in the field insulating film 82 disposed on the main substrate 81. The contact through-hole 17 is provided in the center of the bottom of the female bump 11 as shown in fig. 4. As shown in fig. 3A, 3B, and the like, the contact via hole 17 is provided inside a contact hole (via hole) that is formed in the field insulating film 82 directly below the bottom of the female bump 11 so as to expose a part of the upper surface of the female bump-side land 12, and connects the bottom of the female bump 11 and the female bump-side land 12 metallurgically. The contact via hole 17 is formed as a thin film along the side wall of the contact hole, and has a box-like structure in which a hollow portion is present between the side wall and the side wall facing each other. The contact via 17 may be formed of the same metal as the female bump 11 in a continuous integral structure with the female bump 11. However, fig. 3A and 3B illustrate the contact via hole 17, and the contact via hole may be formed in a form of a plug (via plug) that completely fills a contact hole provided directly below the bottom of the female bump 11, and no hollow portion may be present. Fig. 3A and 3B illustrate examples, and the female bump-side land 12 may be the uppermost layer of a multilayer wiring structure embedded in the field insulating film 82. As shown in fig. 3A, a "substrate 1" is formed by a main substrate 81, a field insulating film 82, and mother bumps 11, and this "substrate 1" is an element of the laminated semiconductor device according to the first embodiment.

On the other hand, with respect to the carrier element X shown in FIG. 3A_ijThe following is illustrated: to carry the component X_ijThe surface (lower surface in fig. 3A) of (a) is a connection surface (main surface of the readout circuit) and a connection-opposing surface opposite to the connection surface forms a parallel-plate structure, but is not limited to the parallel-plate structure. For example, if the carrier element X is carried_ijIs a shell-type LED element, then the bearing element X_ijNot a parallel plate structure. The opposite side of the connection opposite to the connection side may be in the shape of a fish cake or dome, or may be a complex curved surface. For example, the carrier element X_ijThe semiconductor integrated circuit is formed as a semiconductor substrate on which a circuit on the carrier substrate side is formed, but a simple electronic circuit such as an LED chip may be provided as the circuit on the carrier substrate side. For convenience of explanation, the stacked semiconductor package according to the first embodimentThe following is exemplified: a semiconductor substrate is used as a supporting base, and as shown in fig. 3A, a composite structure is formed by the semiconductor substrate and a plurality of wiring insulating layers 20 arranged on the semiconductor substrate. On the carrier element X_ijAs shown in fig. 3A, 3B to 7B, and the like, repair bumps (21, 22, 23) are provided on the multilayer wiring insulating layer 20 above the connection surface, and the repair bumps (21, 22, 23) have wall-shaped repair-side curved surfaces perpendicular to the connection surface and are electrically connected to the carrier-side circuit. As shown in fig. 3A, by means of a carrier element X_ijThe multilayer wiring insulating layer 20 and the repair bumps (21, 22, 23) constitute a "carrier member 2", and the "carrier member 2" is an element of the laminated semiconductor device according to the first embodiment, and a carrier member group is formed by a plurality of the carrier members 2. The repair bumps (21, 22, 23) are provided on the carrier element X via repair-bump-side lands (not shown) embedded in the multilayer wiring insulating layer 20_ijIs electrically connected to the carrier side circuit. Surface wiring (repair bump land) embedded in the multilayer wiring insulating layer 20 and a wiring pattern provided on the carrier element X_ijIs electrically connected to the carrier side circuit. Although not shown, the tops of the repair bumps (21, 22, 23) are electrically connected to the repair-bump-side lands (surface electrodes) via contact through-holes (via plugs), and are further connected to the carrier element X_ijIs electrically connected to the carrier side circuit. The contact via hole on the repair side and the land on the repair bump side are respectively embedded in the carrier element X_ijIn the multilayer wiring insulating layer 20 above the lower surface. The repair-side contact via hole is also provided in the center of the top of the repair bump (21, 22, 23) inside a contact hole formed in the multilayer wiring insulating layer 20 directly above the top of the repair bump (21, 22, 23) so as to expose a part of the upper surface of the repair bump-side land, and the top of the repair bump (21, 22, 23) is metallically connected to the repair bump-side land. The contact via hole on the repair side is formed as a thin film along the side wall of the contact hole, and has a box-like structure in which a hollow portion is present between the side wall and the side wall facing each other, and the same metal as the repair bump (21, 22, 23) may be used so as to be continuous with the repair bump (21, 22, 23)The structure is integrated. However, the contact via on the repair side may be a via plug that completely fills the contact hole provided directly above the top of the repair bump (21, 22, 23), and a hollow portion may not be present. The repair bump land may be the uppermost layer of the multilayer wiring structure embedded in the multilayer wiring insulating layer 20. In the planar pattern (planar pattern) shown in fig. 4, the base-side curved surface and the repair-side curved surface intersect at four intersection points, as viewed from the normal direction of the connection surface. The base-side curved surface and the repair-side curved surface are both rectangular in shape, but as described above, the straight line is mathematically a curve having an infinite radius of curvature, and therefore the flat-plate-like wall is also a type of "curved surface". Note that, in the stacked semiconductor device according to the first embodiment, the carrier element X which does not normally operate is repaired by temporary connection_ijAfter the screening, the "formal connection" is performed. That is, the bump connector B at the actual product stage after the "formal connection" is performed_uvAs illustrated in fig. 23, the female bump 11 and the repair bumps (21, 22, and 23) are formed into a structure in which pieces having disorder and irregularity (indeterminate shape) are gathered, and the topological planar form before joining is lost, so that the repair bumps are formed into various curved surfaces having a plurality of radii of curvature. Fig. 23 is an SEM photograph showing changes in the shape of the mother bump 11 observed by forcibly removing the repair bump after the step of main connection of the stacked semiconductor device according to the first embodiment. After the formal connection, the repair bump is forcibly removed and is arranged on the cutting plane IIIA including FIG. 4_d-IIIA_dThe repair bumps (21, 22, 23) remain in a part of the mother bump 11 at the position(s), but lose the topology before bonding as shown in fig. 3A.

As is known from fig. 3A, 3B to 7B, etc., the repair bumps (21, 22, 23) have a three-layer structure composed of a box-shaped outermost layer 21, an intermediate layer 22, and an innermost layer 23. The hardness of the intermediate layer 22 is a higher value than the hardness of the outermost layer 21 and the innermost layer 23. The hardness of the outermost layer 21 and the innermost layer 23 is the same degree as the hardness of the female bump 11. That is, the intermediate layer 22 has a higher hardness than the female bump 11. For example, in makingWhen gold (Au) is used as the conductor of the outermost layer 21 and the innermost layer 23 of the mother bump 11 and the repair bumps (21, 22, 23), cobalt (Co), nickel (Ni), iridium (Ir), chromium (Cr), tungsten (W), titanium (Ti), titanium Tungsten (TiW), aluminum oxide (Al) can be used as the conductor of the intermediate layer 22₂O₃) And metals or compounds such as silicon (Si) having a hardness 2 times or more higher than that of Au. For example, when Ti is selected as the intermediate layer 22, the sidewall of the repair bump (21, 22, 23) has a three-layer structure of Au/Ti/Au. Alternatively, even when an alloy or a mixture of Au-Co, Au-Ni, Au-Ir, Au-Cr, Au-W, Au-Ti, Au-Si, or the like is used as the conductor of the intermediate layer 22, the hardness can be increased by 2 times or more than that of Au. Two or more materials selected from Co, Ni, Ir, Cr, W, Ti, Si, etc. may be alloyed with Au less than 75%, i.e., ternary alloy, quaternary alloy, etc. In order to exhibit high conductivity of Au, an alloy containing 70% or more of Au is preferred. On the other hand, an alloy having less than 30% of Au is preferable in order to exhibit high hardness of Co, Ni, Ir, Cr, W, Ti, Si, and the like.

Although it depends on the composition, generally, the hardness of the metal increases by alloying. Since the Vickers hardness of simple substance Au is about 25Hv, the Vickers hardness of an Au-20Sn alloy containing 20% of tin (Sn) is about 118Hv, and the Vickers hardness of an Au-12Ge alloy containing 12% of germanium (Ge) is about 108Hv, the single substance Au has a hardness 4.7 times and 4.3 times that of simple substance Au, and Au-Sn alloys and Au-Ge alloys can be used as the conductors of the intermediate layer 22. Since the vickers hardness of the Au-3.15Si alloy containing 3.15% silicon (Si) is about 86Hv, the hardness thereof is 3.4 times that of simple substance Au, and thus the alloy can be used as a conductor of the intermediate layer 22. On the other hand, the vickers hardness of an Au-90Sn alloy containing 90% Sn is about 16Hv because of the low hardness of Sn, and is lower than that of simple Au, and is not suitable as a conductor for the intermediate layer 22. The Au-90Sn alloy can be used as the conductor of the outermost layer 21 and the innermost layer 23 of the mother bump 11 and the repair bumps (21, 22, 23). As the conductors of the outermost layer 21 and the innermost layer 23 of the mother bump 11 and the repair bumps (21, 22, 23), in addition to the Au-90Sn alloy, an alloy such as Au-tin (Sn), Au-lead (Pb), Au-zinc (Zn), or the like containing less than 30% of Au may be used.

As a result of selecting such combinations of conductors having different hardnesses, as shown in fig. 4, the intermediate layer 22 of the repair bump (21, 22, 23) has a higher hardness than the female bump 11 at four intersections of the base-side curved surface and the repair-side curved surface where the female bump 11 and the repair bump (21, 22, 23) intersect, and therefore, as shown in fig. 3B, the repair bump (21, 22, 23) bites (bites) into the female bump 11 to form solid-phase diffusion bonding. That is, at the intersection of the base-side curved surface and the repair-side curved surface, one of the female bump 11 and the repair bump (21, 22, 23) contains a conductor having a higher hardness than the remaining portion. A bump connector B is formed by the female bump 11 and the repair bumps (21, 22, 23) as shown in FIG. 3B_uvThe bump connector B_uvThe element of the stacked semiconductor device according to the first embodiment is described.

The bump connector B of the stacked semiconductor device according to the first embodiment_uvIn the intermediate layer 22 of the three-layer box-shaped repair bump (21, 22, 23) structure, a material having a hardness higher than that of the metal used for the female bump 11 is added, and by the pressure applied at the time of bonding, as shown in fig. 5A and 5B, dents 13a, 13B, 13c, 13d are formed by biting into the opposing female bump 11, thereby forming solid-phase diffusion bonding. That is, the intermediate layer 22 having high hardness is cut out into the deep dents 13a and 13B like a knife edge as shown in fig. 5B to form solid-phase diffusion bonding, and therefore, the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples as shown in fig. 3B, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals (clean metals) is increased. The repair bumps (21, 22, 23) and the mother bump 11 can be bonded by solid-phase diffusion even at low temperatures.

As mentioned above, depending on the application, there is a bearing element X_ijHigh integration level. In the case of a highly integrated structure, the connection body B is connected by a bump_uvTo carry the component X_ijIs connected to the main substrate 81 and tested, so that the mounting position on the carrier element X is known first_ijOf the circuit on the carrier sideGood and bad. On the other hand, in the case of a micro LED display, a large number of LED chips up to several hundred thousand to several million are stacked on the main substrate 81 as a driving panel. Since the LED chip has strict specifications for brightness and the like, a large number of LED chips may contain defective products. If it is arranged on a specific bearing element X_stIf there is a failure in the carrier-side circuit, the entire stacked semiconductor device according to the first embodiment shown in fig. 1 and 2 is defective. Therefore, each carrying element X needs to be arranged_ijTemporarily connecting to the main substrate 81 to confirm the mounting of the specific carrier element X_stWhether or not there is a defect in the carrier side circuit. Therefore, the bump connector B of the stacked semiconductor device according to the first embodiment_uvAs shown in fig. 3A and 3B, the mother bump 11 having a bottom portion bonded to the mother bump-side land (surface electrode) embedded in the field insulating film 82 and the repair bumps (21, 22, 23) having a bottom surface bonded to the surface wiring (repair bump-side land) embedded in the multilayer wiring insulating layer 20 are brought into contact with each other to perform temporary connection. Note that the mother bump-side land and the repair bump-side land may also be structures exposed from the field insulating film 82 and the multilayer wiring insulating layer 20 as described later using fig. 19A, 19B, and the like.

Bump connector B for stacked semiconductor device according to first embodiment_uvSince most of the bumps other than the solid-phase diffusion bonded portion are suppressed from being deformed by pressing the repair bumps (21, 22, 23) against the female bumps 11 with a relatively small pressure, if temporary connection is performed by pressing with a weak force and there is a defect after electrical evaluation, the temporary connection can be performed again by replacing (repairing) another carrier member 2 from among the plurality of carrier members 2 constituting the group. If the electrical evaluation based on the re-provisional connection after repair is passed, the process of proceeding to the screening of the connection of the formal connection can be performed. Note that, in the stacked semiconductor device according to the first embodiment, the intermediate layer 22 that is a part of the repair bumps (21, 22, 23) may be added with the metal of the mother bump 11 to be bump-bondedA compound which acts to locally and largely deform or crack the metal of the mating female bump 11, and which has a higher hardness than the bump metal. In the case of joining side walls (sidewalls) of the same or equivalent hardness, both the repair bump and the female bump are considerably crushed and deformed in one provisional joining. However, only by this deformation, the exposed area of clean gold (clean gold) is not large, and the gold is peeled off immediately. On the other hand, by making the intermediate layer 22 of the repair bumps (21, 22, 23) harder than the other portions and making the thicknesses of the outermost layer 21 and the innermost layer 23 of the repair bumps (21, 22, 23) thinner, the hard material bites into the side wall of the other side like a knife, the exposed area increases, and peeling is less likely to occur after temporary bonding. Since the temporary joining is not easily peeled off, a significant effect of increasing the number of repairs is obtained.

On the other hand, the carrier element X is temporarily connected or temporarily connected again by the female bump 11 and the repair bumps (21, 22, 23)_ijThe motion of (2) is confirmed and the carrier element X is confirmed_ijIn the case of normal operation of the motor, the carrier element X is further enlarged_ijThe force pressing against the main substrate 81 further shortens the carrier element X_ijThe interval from the main substrate 81. When the carrier member X is to be carried_ijWhen the force pressing toward the main substrate 81 is further increased, the bearing member X_ijIs formally connected to the main board 81. When the female bump 11 is formally connected to the repair bumps (21, 22, 23), the vertical side wall portions of the female bump 11 are further deformed by the pressing, and the top portions of the lower end sides of the repair bumps (21, 22, 23) are metallurgically joined to the bottom portions of the female bump 11. Main substrate 81 and carrier X_ijIs compressed by the pressing, so that the bump connector B in the final connection stage_uvIs higher than the bump connector B at the time of temporary connection shown in FIGS. 3A and 3B_uvThe height of (2) is low, and the female bump 11 and the repair bumps (21, 22, 23) are brought together in a disordered and fragmented manner as shown in fig. 23, and lose a box-like form. In a disordered state in which the conductive material is randomly gathered, the pattern of the conductor having high hardness constituting the intermediate layer 22 is brokenThe sheet residue is unevenly distributed on the bump connector B along the irregular shape in the distorted box-shaped trace_uvOf the inner part of (a). As a result, the conductors having different hardnesses are unevenly contained in the space at and near the intersection of the base-side curved surface and the restoration-side curved surface, which are mutually engaged with each other. As described above, fig. 23 shows the structure of the mother bump 11 side after forcibly removing the repair bumps (21, 22, 23) after the step of main connection of the stacked semiconductor device according to the first embodiment, but residues of the repair bumps (21, 22, 23) remain in a part of the mother bump 11. As can be seen from the SEM photograph shown in fig. 23, the topology of the mother bump 11 before bonding shown in fig. 3A is lost. The cutting plane IIIA is shown in the center of FIG. 23 in the horizontal direction_d-IIIA_d(see FIG. 4.) is cut into section IIIA_d-IIIA_dA hole corresponding to the contact through hole 17 is observed in the center of the position of (a).

By formal connection, a carrier element X is formed_ijThe carrier-side circuit (signal readout circuit) is connected to the repair bumps (21, 22, 23) via the surface wiring (repair bump-side land) embedded in the multilayer wiring insulating layer 20, the repair bumps (21, 22, 23) are metallurgically connected to the female bump 11, and the carrier-side circuit is electrically connected to the main substrate circuit of the main substrate 81 via the surface wiring (female bump-side land) embedded in the field insulating film 82. Namely, the main substrate 81 provided with the main substrate circuit and the carrier X provided with the carrier-side circuit_ijThe stacked semiconductor device according to the first embodiment shown in fig. 3B is configured by electrically connecting the bump connectors. The laminated semiconductor device comprises a substrate 1 and a carrier 2, wherein the substrate 1 comprises a main substrate 81, a field insulating film 82 and a mother bump 11, and the carrier 2 comprises a carrier element X_ijA multilayer wiring insulating layer 20 and repair bumps (21, 22, 23). The number of the carrier members 2 to be mounted on the stacked semiconductor device is selected from a part of the total number of the carrier members 2 constituting the group, and assuming that all of the carrier members 2 constituting the group are normally operated, a part of the carrier members 2 are left without being mounted on the base 1.

The carrier member 2 of the stacked semiconductor device according to the first embodiment may be formed by constituting the carrier element X_ijThe carrier-side circuit (signal read circuit) may be formed by an integrated circuit on the surface of the Si substrate, or may be formed by a plurality of wiring layers such as an upper wiring layer, an intermediate wiring layer, and a lower wiring layer, or may have a simple structure including a separate element such as an LED element. The repair bumps (21, 22, 23) constituting the carrier member 2 are connected to the carrier-side circuit via surface wirings (repair-bump-side lands) embedded in the multilayer wiring insulating layer 20, and the carrier-side circuit is metallurgically connected to the mother bumps 11 of the base 1 via the repair bumps (21, 22, 23). The mother bump 11 is electrically connected to a main substrate circuit integrated on the main substrate 81 via a surface wiring (mother bump-side land) embedded in the field insulating film 82. Bump connector B_uvThe repair bumps (21, 22, 23) and the female bump 11. As a result, the carrier-side circuit of the carrier member 2 is connected to the bump connector B via the bump_uvElectrically connected to the main substrate circuit of the base 1.

For example, the carrier X is formed by transmitting a signal from the main substrate 81 to a carrier-side circuit (signal readout circuit) via surface wiring (mother bump-side land) embedded in the field insulating film 82_ijA plurality of carrier-side circuits (signal readout circuits) for reading out signals from the main board 81 can function as a readout circuit carrier (readout chip) having input electrodes arranged along the connection grid in accordance with the arrangement of the pixels. In this case, the surface wiring (repair bump land) embedded in the multilayer wiring insulating layer 20 functions as an input electrode for reading out a signal for each main substrate circuit from the surface wiring (mother bump land) embedded in the field insulating film 82 and inputting the signal to the carrier elements X integrated with the carrier elements X_ijAn integrated circuit as described above.

As shown in fig. 3A and 3B, a bump connector B constituting the stacked semiconductor device according to the first embodiment_uvOf each bump connectorThe female bump 11 has a box-like shape having a bottom portion contacting the female-bump-side land embedded in the field insulating film 82 and a vertical side wall portion connected to the outer periphery of the bottom portion and constituting a surrounding wall surrounding the bottom portion. Form each bump connector B_uvThe repair bumps (21, 22, 23) of (a) are box-shaped multilayer structures having bottom surfaces in contact with surface wirings (repair bump lands) embedded in the multilayer wiring insulating layer 20. The planar pattern of the surface wiring (repair bump land) of embedded field insulating film 82 and multilayer wiring insulating layer 20 may be, for example, a rectangle, but is not limited to a rectangle. Form a bump connector B_uvThe height of the female bump 11 before temporary connection can be determined to be, for example, 1 μm or more and less than 5 μm. The height of the wall of the repair bump (21, 22, 23) may be set higher than the depth of the box-shaped vertical side wall portion constituting the female bump 11.

The surface wiring (mother bump land) embedded in field insulating film 82 and the surface wiring (repair bump land) embedded in multilayer wiring insulating layer 20 may be formed of, for example, Au or an alloy containing 80% or more of Au, such as Au — Si, Au — Ge, Au — Sb, Au — Sn, Au — Pb, Au — Zn, or Au — Cu, or may have a multilayer structure in which a metal layer such as nickel (Ni) is used as a base. By a carrier element X_ijThe multilayer structure including the wiring insulating layers 20 and a plurality of layers may have, for example, the following structure: a first lower layer wiring and a second lower layer wiring which are arranged on the upper surface of the supporting base body and separated from each other; a first insulating layer which is disposed so as to embed the first lower layer wiring and the second lower layer wiring from above; a first interlayer wiring and a second interlayer wiring which are arranged on the upper surface of the first insulating layer and are separated from each other; and a second insulating layer which is disposed so as to embed the first interlayer wiring and the second interlayer wiring from above. For example, a metal layer such as aluminum (Al), an aluminum-copper alloy (Al — Cu alloy), or copper (Cu) damascene (damascone) can be used for the first lower layer wiring, the second lower layer wiring, the first intermediate layer wiring, and the second intermediate layer wiring. The first insulating layer and the second insulating layer correspond to the multilayer wiring insulating layer 20 shown in fig. 2 and the like.

Multilayer wiring insulating layer 20 other than usable examplesSuch as a silicon oxide film (SiO)₂Film), silicon nitride film (Si)₃N₄As the insulating film, in addition to an inorganic insulating layer such as a phosphosilicate glass film (PSG film), a fluorine-containing oxide film (SiOF film), or a carbon-containing oxide film (SiOC film), an organic insulating layer such as a methylpolysiloxane (SiCOH), a Hydrogenpolysiloxane (HSQ), a porous methylsilsesquioxane film, or a polyarylene film may be used, and a variety of multilayer wiring insulating layers 20 having a multilayer structure can be formed by stacking these various insulating film layers. The second interlayer wiring may be arranged in a row so as to face the second lower layer wiring with the first insulating layer interposed therebetween. The second intermediate layer wiring is electrically connected to the surface wiring (repair bump land) embedded in the multilayer wiring insulating layer 20 via a conductor, and the second lower layer wiring is connected to the ground potential. Thus, when the stacked semiconductor device according to the first embodiment is a solid-state imaging device, the second intermediate layer wiring and the second lower layer wiring constitute a readout capacitor which is a thin film capacitor for accumulating a signal generated in the main substrate circuit as electric charge.

Although not shown, the carrier element X is in contact with the multilayer wiring insulating layer 20_ijA channel region is formed inside the first lower layer wiring to form a channel between the first intermediate layer wiring and the second intermediate layer wiring by applying a voltage to the first lower layer wiring. Thus, in the case where the stacked semiconductor device according to the first embodiment is a solid-state imaging device, the first lower layer wiring, the first intermediate layer wiring, and the second intermediate layer wiring constitute a switching element which is a thin film transistor for reading out the electric charge stored in the readout capacitor as a signal. The first lower layer wiring functions as a gate electrode, and the first intermediate layer wiring and the second intermediate layer wiring function as a drain electrode, a source electrode, and the like, respectively.

The first lower layer wiring, which is a gate electrode of the switching element, is connected to a gate signal line extending in the row direction (X-axis direction) of the pixel. The gate signal line is arranged for each pixel row and connected to each gate electrode in the same row. Each gate signal line is connected to a gate drive carrier side circuit, not shown, and a gate drive signal is sequentially applied from the gate drive carrier side circuit. The gate driving signals are sequentially applied in the column direction at a predetermined scanning period. The first intermediate layer wiring, which is the drain electrode of the switching element, is connected to a signal readout line 82 extending in the column direction of the pixel. The signal readout line 82 is disposed for each pixel column, and is connected to each drain electrode in the same column. Each signal read line 82 is connected to a read drive carrier side circuit (not shown), and is sequentially scanned in the row direction (X-axis direction) by the read drive carrier side circuit. In this way, the readout drive carrier side circuit sequentially reads out the signals of the main substrate circuits of the rows to which the gate drive signals are applied in the column direction in each scanning period of the gate drive carrier side circuit.

In this way, when the stacked semiconductor device according to the first embodiment is a solid-state imaging device, the signals of the respective main substrate circuits (pixels) that are read out are converted into pixel values in the image processing carrier-side circuit (not shown), and are mapped in correspondence with the respective main substrate circuits, thereby generating an image that represents the two-dimensional distribution of the amount of the incident electromagnetic wave. As described above, according to the stacked semiconductor device according to the first embodiment of the present invention, it is possible to provide the plurality of carrier elements X supported on the large-diameter main substrate 81_ijLaminated semiconductor device in which a defective carrier element is selectively subjected to a repair process or the like, and a plurality of carrier elements X used in the laminated semiconductor device_ijAnd the like. As a result, the stacked semiconductor device according to the first embodiment includes a large number of carrier elements X arranged in a matrix on a large-diameter main substrate 81_ijThe manufacturing time of various stacked semiconductor devices including the stacked semiconductor device of (1) is shortened, and the main substrate 81 and the carrier element X which are normally operated are not lost_ijAnd the number of times of repair processing can be increased, thereby preventing waste of resources.

(first modification of the first embodiment)

A stacked semiconductor device according to a first modification of the first embodiment of the present invention has a stacked structure including a substrate and a plurality of carrier members, which are similar to the structure shown in fig. 3B and the like. The number of the carrier members 2 mounted on the stacked semiconductor device is smaller than the total number of the carrier members 2 constituting the group. As can be inferred from fig. 3A and 3B, the laminated semiconductor device according to the first modification also includes a main substrate, not shown, and a field insulating film provided on the main substrate, and the plate-shaped mother bump 14a shown in fig. 8 is provided on the field insulating film. On the other hand, the carrier members constituting the group each include a carrier element, not shown, and a multilayer wiring insulating layer provided on the lower surface of the carrier element, and a structure in which repair bumps (21, 22, 23) having a rectangular box-like multilayer structure shown in fig. 8 are provided on the lower surface of the multilayer wiring insulating layer is conceivable, but the carrier element may be a structure of a separate element such as an LED chip.

The female bump 14a is a plate-like parallel flat plate having a wall-like base-side curved surface perpendicular to the substrate-receiving surface of the main substrate. Since the straight line is a curved line having an infinite radius of curvature as described above, the flat plate-like wall is also referred to as a "curved surface" in the present specification and is generalized. The mother bump 14a has a bottom surface in contact with a surface electrode embedded in the field insulating film, and is electrically connected to a main substrate circuit integrated on the main substrate. The repair bumps (21, 22, 23) have wall-shaped repair-side curved surfaces perpendicular to the connection surface of the carrier element, and are electrically connected to the carrier-element-side circuit. The repair bumps (21, 22, 23) are electrically connected to a carrier-side circuit provided in the carrier via surface wirings embedded in the multilayer wiring insulating layer. As can be seen from fig. 8, the base-side curved surface and the repair-side curved surface intersect at two intersection points.

The repair bumps (21, 22, 23) have a three-layer structure composed of a box-shaped outermost layer 21, an intermediate layer 22, and an innermost layer 23. The hardness of the intermediate layer 22 is a higher value than the hardness of the outermost layer 21 and the innermost layer 23. The hardness of the outermost layer 21 and the innermost layer 23 is the same degree as the hardness of the female bump 14 a. That is, the intermediate layer 22 has a higher hardness than the female bump 14 a. For example, Au is used as the outermost layer 21 of the mother bump 14a and the repair bumps (21, 22, 23)And the innermost layer 23, a metal having high hardness such as Co, Ni, Ir, Cr, W, Ti, TiW, or the like can be used as the conductor of the intermediate layer 22. Alternatively, as the conductor of the intermediate layer 22, Au-Co, Au-Ni, Au-Ir, Au-Cr, Au-W, Au-Ti, Au-Al containing 70% or more of Au can be used₂O₃Alloys or mixtures thereof of Au-Si, Au-Ge, etc. The alloy may be a ternary alloy, a quaternary alloy, or the like of Au and two or more materials selected from Co, Ni, Ir, Cr, W, Ti, Si, Ge, or the like.

Since the Vickers hardness of an Au-20Sn alloy containing 20% Sn is about 118Hv and that of an Au-90Sn alloy containing 90% Sn is about 16Hv, the Au-Sn alloy needs to be given attention in terms of composition. At two intersections of the base-side curved surface and the repair-side curved surface where the mother bump 14a and the repair bumps (21, 22, 23) intersect, the intermediate layer 22 of the repair bumps (21, 22, 23) has a higher hardness than the mother bump 14a, and therefore the repair bumps (21, 22, 23) can bite into the inside of the mother bump 14a to form solid-phase diffusion bonding. That is, the stacked semiconductor device according to the first modification of the first embodiment has the following configuration: at the intersection of the base-side curved surface and the repair-side curved surface, one of the female bump 14a and the repair bump (21, 22, 23) contains an electrical conductor having a higher hardness than the remaining portion. The mother bump 14a and the repair bumps (21, 22, 23) constitute a bump connected body that is an element of the laminated semiconductor device according to the first modification of the first embodiment.

In the bump connector of the stacked semiconductor device according to the first modification of the first embodiment, a material having a hardness higher than that of the metal used for the mother bumps 14a is added to the intermediate layer 22 having a structure of the box-shaped repair bumps (21, 22, 23) having a three-layer structure, and a pressure applied at the time of bonding causes the mother bumps 14a of the other pair to bite into and dent, thereby forming solid-phase diffusion bonding. That is, the intermediate layer 22 having high hardness is cut into a deep notch like a knife edge to form solid-phase diffusion bonding, and therefore, the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The repair bumps (21, 22, 23) and the mother bump 14a can be bonded by solid-phase diffusion even at low temperatures.

In the bump connector of the stacked semiconductor device according to the first modification of the first embodiment, since the repair bumps (21, 22, 23) and the female bumps 14a are pressed against each other with a relatively small pressure to suppress most of the bump deformation except for the solid diffusion bonding portion, if the temporary connection is performed with a weak pressure and there is a defect after the electrical evaluation, the carrier member in which the defect is found can be replaced with another component member from among the members prepared as a group and the temporary connection can be performed again. If the electrical evaluation based on the provisional connection again passes, the joining to the formal connection can be entered. Note that, in the laminated semiconductor device according to the first modification of the first embodiment, a material that is a combination of metals of the mother bumps 14a to be bump-bonded and has a higher hardness of a compound than that of the bump metal may be added to the intermediate layer (22) that is a part of the repair bumps (21, 22, 23), so that the compound acts to locally and largely deform or crack the metal of the mother bump 14a of the other.

On the other hand, when the normal operation of the carrier is confirmed by confirming the operation of the carrier in a state where the female bump 14a and the repair bumps (21, 22, 23) are temporarily connected or temporarily connected again, the force pressing the carrier against the main substrate is further increased, and the interval between the carrier and the main substrate is further shortened. When the force pressing the carrier member toward the main substrate is further increased, the carrier member is formally connected to the main substrate. When the female bump 14a is formally connected to the repair bumps (21, 22, 23), the vertical side wall portions of the female bump 14a are further deformed by the pressing, and the top portions of the repair bumps (21, 22, 23) on the lower end side are metallurgically joined to the bottom portions of the female bump 14 a. Since the distance between the main substrate and the carrier is compressed by the pressing, the height of the bump connector in the final connection stage is lower than the height of the bump connector in the temporary connection, and the female bump 14a and the repair bumps (21, 22, 23) are randomly gathered in a chip shape. In a disordered state in which the chips are randomly gathered, the debris that forms the pattern of the conductor having high hardness of the intermediate layer 22 is unevenly distributed inside the bump connected body along the irregular shape in the distorted box-like trace. As a result, the conductors having different hardnesses are unevenly contained in the space at and near the intersection of the base-side curved surface and the restoration-side curved surface, which are mutually engaged with each other.

The repair bumps (21, 22, 23) are metallically connected to the female bumps 14a by the main connection, and the main board provided with the main board circuit and the carrier provided with the carrier-side circuit are electrically connected by the bump connector, whereby the stacked semiconductor device according to the first modification of the first embodiment can be configured. As described above, according to the stacked semiconductor device according to the first modification of the first embodiment of the present invention, it is possible to provide a stacked semiconductor device in which, when only a defective carrier element is selectively subjected to a repair process or the like from among a plurality of carrier elements carried on a large-diameter main substrate, the repair process is easily performed, and a carrier element used in the stacked semiconductor device. As a result, according to the stacked semiconductor device according to the first modification of the first embodiment, the manufacturing time of various stacked semiconductor devices including the stacked semiconductor device in which a large number of mounting elements are arranged on a large-diameter main substrate is shortened, the number of times of repair processing can be increased without causing an end loss of the normally operating main substrate and the normally operating mounting elements, and thus waste of resources can be prevented.

(second modification of the first embodiment)

A stacked semiconductor device according to a second modification of the first embodiment of the present invention has a stacked structure including a base body having the same structure as the stacked semiconductor device according to the first embodiment shown in fig. 3A and 3B and a constituent member that is at least a part of a carrier member group. As can be understood from fig. 3A and 3B, the base of the stacked semiconductor device according to the second modification also includes a main substrate, not shown, and a field insulating film provided on the main substrate, and the cylindrical mother bump 15 shown in fig. 9 is provided on the field insulating film. On the other hand, each of the carrier members constituting the group includes a carrier element, not shown, and a multilayer wiring insulating layer provided on the lower surface of the carrier element, and a structure of repair bumps (21, 22, 23) having a rectangular box-like multilayer structure shown in fig. 9 can be assumed on the lower surface of the multilayer wiring insulating layer, but a structure of a separate element such as an LED chip different from fig. 3A and 3B may be employed.

The female bump 15 is a cylindrical disk having a wall-shaped curved surface on the base side perpendicular to the substrate-receiving surface of the main substrate. The female bump 15 contacts the bottom surface of the cylindrical disk with the surface electrode of the embedded field insulating film, and is electrically connected to a main substrate circuit integrated on the main substrate. The repair bumps (21, 22, 23) have wall-shaped repair-side curved surfaces perpendicular to the connection surface of the carrier element and are electrically connected to the carrier-element-side circuit. The repair bumps (21, 22, 23) are electrically connected to a carrier-side circuit provided in the carrier via surface wirings embedded in the multilayer wiring insulating layer. As can be seen from fig. 9, the base-side curved surface and the repair-side curved surface intersect at four intersection points.

The repair bumps (21, 22, 23) have a three-layer structure composed of a box-shaped outermost layer 21, an intermediate layer 22, and an innermost layer 23. The hardness of the intermediate layer 22 is a higher value than the hardness of the outermost layer 21 and the innermost layer 23. The hardness of the outermost layer 21 and the innermost layer 23 is the same degree as the hardness of the female bump 15. That is, the intermediate layer 22 has a higher hardness than the female bump 15. For example, when Au is used as the conductor of the mother bump 15 and the outermost layer 21 and the innermost layer 23 of the repair bumps (21, 22, 23), a metal having high hardness such as Co, Ni, Ir, Cr, W, Ti, TiW, or the like can be used as the conductor of the intermediate layer 22. Alternatively, as the conductor of the intermediate layer 22, Au-Co, Au-Ni, Au-Ir, Au-Cr, Au-W, Au-Ti, Au-Al containing 70% or more of Au can be used₂O₃Alloys or mixtures thereof of Au-Si, Au-Ge, etc. The alloy may be a ternary alloy, a quaternary alloy, or the like of Au and two or more materials selected from Co, Ni, Ir, Cr, W, Ti, Si, Ge, or the like.

Since the Vickers hardness of an Au-20Sn alloy containing 20% Sn is about 118Hv and that of an Au-90Sn alloy containing 90% Sn is about 16Hv, the Au-Sn alloy needs to be given attention in terms of composition. At four intersections of the base-side curved surface and the repair-side curved surface where the mother bump 15 and the repair bumps (21, 22, 23) intersect, the intermediate layer 22 of the repair bumps (21, 22, 23) has a higher hardness than the mother bump 15, and therefore the repair bumps (21, 22, 23) can bite into the inside of the mother bump 15 to form solid-phase diffusion bonding. That is, the stacked semiconductor device according to the second modification of the first embodiment has the following configuration: at the intersection of the base-side curved surface and the repair-side curved surface, one of the female bump 15 and the repair bump (21, 22, 23) contains an electrical conductor having a higher hardness than the remaining portion. The mother bump 15 and the repair bumps (21, 22, 23) constitute a bump connected body that is an element of the laminated semiconductor device according to the second modification of the first embodiment.

In the bump connector of the stacked semiconductor device according to the second modification of the first embodiment, a material having a higher hardness than the metal used for the mother bumps 15 is added to the intermediate layer 22 having a three-layer box-shaped repair bump (21, 22, 23), and the female bumps 15 of the other pair are engaged with each other by a pressure applied at the time of bonding to form dents, thereby forming solid-phase diffusion bonding. That is, the intermediate layer 22 having high hardness is cut into a deep notch like a knife edge to form solid-phase diffusion bonding, and therefore, the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The repair bumps (21, 22, 23) and the mother bump 15 can be bonded by solid-phase diffusion even at low temperatures.

In the bump connector of the stacked semiconductor device according to the second modification of the first embodiment, since the repair bumps (21, 22, 23) are pressed against the female bumps 15 with a relatively small pressure to suppress most of the bump deformation except for the solid diffusion bonding portions, if the temporary connection is performed with a weak pressure and there is a defect after the electrical evaluation, the carrier member in which the defect is found can be replaced with another normal component member from among the members included in the group and prepared as the repair portion, and the temporary connection can be performed again. If the electrical evaluation based on the provisional connection again passes, the joining to the formal connection can be entered. Note that, in the laminated semiconductor device according to the second modification of the first embodiment, a material that is a combination of the metal of the mother bump 15 to be bump-bonded and has a higher hardness of the compound than the bump metal may be added to the intermediate layer 22 that is a part of the repair bumps (21, 22, 23), so that the compound may locally and largely deform the metal of the mother bump 15 of the other side or cause cracks.

On the other hand, when the normal operation of the carrier is confirmed by confirming the operation of the carrier in a state where the female bump 15 and the repair bumps (21, 22, 23) are temporarily connected or temporarily connected again, the force pressing the carrier against the main substrate is further increased, and the interval between the carrier and the main substrate is further shortened. When the force pressing the carrier member toward the main substrate is further increased, the carrier member is formally connected to the main substrate. When the female bump 15 is formally connected to the repair bumps (21, 22, 23), the vertical side wall portions of the female bump 15 are further deformed by the pressing, and the top portions of the lower end sides of the repair bumps (21, 22, 23) are metallurgically joined to the bottom portions of the female bump 15. Since the distance between the main substrate and the carrier is compressed by the pressing, the height of the bump connector in the final connection stage is lower than the height of the bump connector in the temporary connection, and the female bump 15 and the repair bumps (21, 22, 23) are randomly gathered in a chip shape. In a disordered state in which the chips are randomly gathered, the debris that forms the pattern of the conductor having high hardness of the intermediate layer 22 is unevenly distributed inside the bump connected body along the irregular shape in the distorted box-like trace. As a result, the conductors having different hardnesses are unevenly contained in the space at and near the intersection of the base-side curved surface and the restoration-side curved surface, which are mutually engaged with each other.

By the formal connection, a carrier-side circuit provided in the carrier is connected to the repair bumps (21, 22, 23) via surface wirings embedded in the multilayer wiring insulating layer, the repair bumps (21, 22, 23) are metallurgically connected to the female bumps 15, and the carrier-side circuit is electrically connected to the main substrate circuit of the main substrate via the surface wirings embedded in the field insulating film. That is, the main board provided with the main board circuit and the carrier provided with the carrier-side circuit are electrically connected by the bump connector, whereby the stacked semiconductor device according to the second modification of the first embodiment can be configured.

As described above, according to the stacked semiconductor device according to the second modification of the first embodiment of the present invention, it is possible to provide a stacked semiconductor device in which, when only a defective carrier element is selectively subjected to a repair process or the like from among a plurality of carrier elements carried on a large-diameter main substrate, the repair process is easily performed, and a carrier element used in the stacked semiconductor device. As a result, according to the stacked semiconductor device according to the second modification of the first embodiment, the manufacturing time of various stacked semiconductor devices including the stacked semiconductor device in which a large number of mounting elements are arranged on a large-diameter main substrate is shortened, the number of times of repair processing can be increased without causing an end loss of the normally operating main substrate and the normally operating mounting elements, and thus waste of resources can be prevented.

(second embodiment)

A stacked semiconductor device according to a second embodiment of the present invention has a stacked structure including a base and a constituent member that is at least a part of a carrier member group, the base having the same structure as the stacked semiconductor device according to the first embodiment shown in fig. 3A and 3B. As can be understood from fig. 3A and 3B, the base of the stacked semiconductor device according to the second embodiment also includes a main substrate, not shown, and a field insulating film provided on the main substrate, and the rectangular box-shaped mother bump 16 shown in fig. 10 is provided on the field insulating film, which is similar to fig. 3A and 3B. On the other hand, each of the carrier members constituting the group includes a carrier element, not shown, and a multilayer wiring insulating layer provided on the lower surface of the carrier element, and a structure in which repair bumps (24, 25, 26) having a bottomed cylindrical (tea can-shaped) structure shown in fig. 10 are provided on the lower surface of the multilayer wiring insulating layer is conceivable, but the carrier element may be a structure of a separate element such as an LED chip. Although not shown, in the same manner as in fig. 3A and the like, a contact via (contact via) and a mother bump-side land (land) are embedded in the field insulating film, and the mother bump 16 is electrically connected to the mother bump-side land through the contact via. Similarly, a contact via hole and a repair bump land are embedded in the multilayer wiring insulating layer, and the repair bumps (24, 25, 26) are electrically connected to the repair bump land through the contact via hole.

The female bump 16 is a rectangular box having a wall-shaped base-side curved surface perpendicular to the substrate-receiving surface of the main substrate. The female bump 16 contacts the bottom surface of the rectangular case with the surface electrode embedded in the field insulating film, and is electrically connected to the main substrate circuit integrated on the main substrate. The repair bumps (24, 25, 26) have wall-shaped repair-side curved surfaces perpendicular to the connection surface of the carrier element, and are electrically connected to the carrier-element-side circuit. The repair bumps (24, 25, 26) are electrically connected to a carrier-side circuit provided in the carrier via surface wirings embedded in the multilayer wiring insulating layer. As can be seen from fig. 10, the base-side curved surface and the repair-side curved surface intersect at four intersection points.

The repair bumps (24, 25, 26) have a three-layer structure consisting of a bottomed cylindrical outermost layer 24, an intermediate layer 25, and an innermost layer 26. The hardness of the intermediate layer 25 is a higher value than the hardness of the outermost layer 24 and the innermost layer 26. The outermost layer 24 and the innermost layer 26 are of the same hardness as the female bump 16. That is, the intermediate layer 25 has a higher hardness than the female bump 16. For example, when Au is used as the conductor of the outermost layer 24 and the innermost layer 26 of the mother bump 16 and the repair bumps (24, 25, 26), a metal having high hardness such as Co, Ni, Ir, Cr, W, Ti, TiW, or the like can be used as the conductor of the intermediate layer 25. Alternatively, as the conductor of the intermediate layer 25, Au-Co, Au-Ni, Au-Ir, Au-Cr, Au-W, Au-Ir, or Au-W containing 70% or more of Au can be used,Au-Ti、Au-Al₂O₃Alloys or mixtures thereof of Au-Si, Au-Ge, etc. The alloy may be a ternary alloy, a quaternary alloy, or the like of Au and two or more materials selected from Co, Ni, Ir, Cr, W, Ti, Si, Ge, or the like.

Since the Vickers hardness of an Au-20Sn alloy containing 20% Sn is about 118Hv and that of an Au-90Sn alloy containing 90% Sn is about 16Hv, the Au-Sn alloy needs to be given attention in terms of composition. At four intersections of the base-side curved surface and the repair-side curved surface where the female bump 16 and the repair bumps (24, 25, 26) intersect, the intermediate layer 25 of the repair bumps (24, 25, 26) has a higher hardness than the female bump 16, and therefore the repair bumps (24, 25, 26) can bite into the female bump 16 to form solid-phase diffusion bonding. That is, the stacked semiconductor device according to the second embodiment has the following configuration: at the intersection of the base-side curved surface and the repair-side curved surface, one of the female bump 16 and the repair bump (24, 25, 26) contains an electrical conductor having a higher hardness than the remaining portion. The mother bump 16 and the repair bumps (24, 25, 26) constitute a bump connector, which is an element of the stacked semiconductor device according to the second embodiment.

In the bump connector of the stacked semiconductor device according to the second embodiment, a material having a hardness higher than that of the metal used for the mother bumps 16 is added to the intermediate layer 25 having a structure of the bottomed cylindrical repair bumps (24, 25, 26) having a three-layer structure, and a dent is formed by biting into the mother bump 16 of the other side by a pressure applied at the time of bonding, thereby forming solid-phase diffusion bonding. That is, the intermediate layer 25 having high hardness is cut into a deep notch like a knife edge to form solid-phase diffusion bonding, and therefore, the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The repair bumps (24, 25, 26) and the mother bump 16 can be bonded by solid phase diffusion even at low temperatures.

In the bump connector of the stacked semiconductor device according to the second embodiment, since the repair bumps (24, 25, 26) are pressed against the female bumps 16 with a relatively small pressure to suppress deformation of most of the bumps except for the solid diffusion bonding portions, if temporary connection is performed with a weak pressure and there is a defect after electrical evaluation, the carrier member in which the defect is found can be replaced with another normal component member from among the members included in the group prepared as the repair portion and temporarily connected again. If the electrical evaluation based on the provisional connection again passes, the joining to the formal connection can be entered. Note that, in the laminated semiconductor device according to the second embodiment, a material that is a combination of metals of the mother bumps 16 to be bump-bonded and has a higher hardness of a compound than that of the bump metal may be added to the intermediate layer 25 that is a part of the repair bumps (24, 25, 26), so that the compound acts to locally greatly deform or crack the metal of the mother bump 16 on the other side. In the case of joining side walls (sidewalls) of the same or equivalent hardness, both the repair bump and the female bump are considerably crushed and deformed by one time of temporary joining. However, only by this deformation, the exposed area of the clean gold is not large, and therefore, the gold is peeled off immediately. On the other hand, by making the intermediate layer 25 of the repair bumps (24, 25, 26) harder than the other portions and making the thicknesses of the outermost layer 24 and the innermost layer 26 of the repair bumps (24, 25, 26) thinner, the hard material bites into the side wall of the other side like a knife, the exposed area increases, and peeling is less likely to occur after temporary bonding. Since the temporary joining is not easily peeled off, a significant effect of increasing the number of repairs is obtained.

On the other hand, when it is confirmed that the carrier element is normally operated in a state where the female bump 16 is temporarily connected or temporarily connected again to the repair bumps (24, 25, 26), the force pressing the carrier element toward the primary base plate is further increased, and the interval between the carrier element and the primary base plate is further shortened. When the force pressing the carrier member toward the main substrate is further increased, the carrier member is formally connected to the main substrate. When the female bump 16 is formally connected to the repair bumps (24, 25, 26), the vertical side wall portions of the female bump 16 are further deformed by the pressing, and the top portions of the lower end sides of the repair bumps (24, 25, 26) are metallurgically joined to the bottom portions of the female bump 16. Since the distance between the main board and the carrier is compressed by the pressing, the height of the bump connector in the final connection stage is lower than the height of the bump connector in the temporary connection, and the female bump 16 and the repair bumps (24, 25, 26) are brought together in a mutually disordered and fragmented manner. In a disordered state in which the chips are randomly gathered, the debris that forms the pattern of the conductor having high hardness of the intermediate layer 25 is unevenly distributed inside the bump connected body along the irregular shape in the distorted bottomed cylindrical trace. As a result, the conductors having different hardnesses are unevenly contained in the space at and near the intersection of the base-side curved surface and the restoration-side curved surface, which are mutually engaged with each other.

The repair bumps (24, 25, 26) are metallically connected to the female bumps 16 by the main connection, and the main board provided with the main board circuit and the carrier provided with the carrier-side circuit are electrically connected by the bump connector, whereby the stacked semiconductor device according to the second embodiment can be configured. As described above, according to the stacked semiconductor device according to the second embodiment of the present invention, it is possible to provide a stacked semiconductor device in which, when only a defective carrier element is selectively subjected to a repair process or the like from among a plurality of carrier elements carried on a large-diameter main substrate, the repair process can be easily performed, and a carrier element used for the stacked semiconductor device and the like. As a result, according to the stacked semiconductor device of the second embodiment, the manufacturing time of various stacked semiconductor devices including a stacked semiconductor device in which a large number of mounting elements are arranged on a large-diameter main substrate is shortened, the number of times of repair processing can be increased without causing an end loss of the normally operating main substrate and the normally operating mounting elements, and therefore, waste of resources can be prevented.

(first modification of the second embodiment)

A stacked semiconductor device according to a first modification of the second embodiment of the present invention has a stacked structure including a base body having the same structure as the stacked semiconductor device according to the first embodiment shown in fig. 3A and 3B and a constituent member that is at least a part of a carrier member group. As can be understood from fig. 3A and 3B, the laminated semiconductor device according to the first modification example of the second embodiment is also similar to the laminated semiconductor device according to the first modification example of the first embodiment shown in fig. 8 in that the base includes a main substrate, not shown, and a field insulating film provided on the main substrate, and the field insulating film has the parallel flat plate-like mother bumps 14a shown in fig. 11. On the other hand, each of the carrier members constituting the group includes a carrier element, not shown, and a multilayer wiring insulating layer provided on the lower surface of the carrier element, and a structure in which repair bumps (24, 25, 26) having a bottomed cylindrical (tea can-shaped) structure shown in fig. 11 are provided on the lower surface of the multilayer wiring insulating layer is conceivable, but the carrier element may be a structure of a separate element such as an LED chip. The other points are the same as those of the stacked semiconductor device according to the second embodiment shown in fig. 10.

The female bump 14a is a rectangular parallel flat plate having a wall-shaped base-side curved surface perpendicular to the substrate-receiving surface of the main substrate. The female bump 14a contacts the lower end surface of the rectangular parallel plate to the surface electrode of the embedded field insulating film, and is electrically connected to the main substrate circuit integrated on the main substrate. The repair bumps (24, 25, 26) have wall-shaped repair-side curved surfaces perpendicular to the connection surface of the carrier element, and are electrically connected to the carrier-element-side circuit. The repair bumps (24, 25, 26) are electrically connected to a carrier-side circuit provided in the carrier via surface wirings embedded in the multilayer wiring insulating layer. As can be seen from fig. 11, the base-side curved surface and the repair-side curved surface intersect at two intersection points.

The repair bumps (24, 25, 26) have a three-layer structure consisting of a bottomed cylindrical outermost layer 24, an intermediate layer 25, and an innermost layer 26. The hardness of the intermediate layer 25 is a higher value than the hardness of the outermost layer 24 and the innermost layer 26. The hardness of the outermost layer 24 and the innermost layer 26 is the same degree as the hardness of the female bump 14 a. That is, the intermediate layer 25 has a higher hardness than the female bump 14 a. For example, the conductors of the outermost layer 24 and the innermost layer 26 of the mother bump 14a and the repair bumps (24, 25, 26) may be formed using a combination of metals and alloys as described in the first embodiment. The mother bump 14a and the repair bumps (24, 25, 26) constitute a bump connector, which is an element of the laminated semiconductor device according to the first modification of the second embodiment.

In the bump connector of the stacked semiconductor device according to the first modification of the second embodiment, a material having a hardness higher than that of the metal used for the mother bumps 14a is added to the intermediate layer 25 having the structure of the bottomed cylindrical repair bumps (24, 25, 26) having a three-layer structure, and a pressure applied at the time of bonding causes the mother bumps 14a of the other pair to bite into and dent, thereby forming solid-phase diffusion bonding. That is, the intermediate layer 25 having high hardness is cut into a deep notch like a knife edge to form solid-phase diffusion bonding, and therefore, the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The repair bumps (24, 25, 26) and the mother bump 14a can be bonded by solid-phase diffusion even at low temperatures.

In the bump connector of the stacked semiconductor device according to the first modification of the second embodiment, since the repair bumps (24, 25, 26) are pressed against the female bumps 14a with a relatively small pressure to suppress most of the bump deformation except for the solid diffusion bonding portion, if the temporary connection is performed with a weak pressure and there is a defect after the electrical evaluation, the carrier member in which the defect is found can be replaced with another normal component member from among the members included in the group and temporarily connected again. If the electrical evaluation based on the provisional connection again passes, the joining to the formal connection can be entered. Note that, in the laminated semiconductor device according to the first modification of the second embodiment, a material that is a combination of the metal of the mother bump 14a to be bump-bonded and has a higher hardness of a compound than that of the bump metal may be added to the intermediate layer 25 that is a part of the repair bumps (24, 25, 26), so that the compound may locally and largely deform or crack the metal of the mother bump 14a of the other side.

On the other hand, when it is confirmed that the carrier element is normally operated in a state where the female bump 14a is temporarily connected or temporarily connected again to the repair bump (24, 25, 26), the force pressing the carrier element toward the primary base plate is further increased, and the interval between the carrier element and the primary base plate is further shortened. When the force pressing the carrier member toward the main substrate is further increased, the carrier member is formally connected to the main substrate. When the female bump 14a is formally connected to the repair bumps (24, 25, 26), the vertical side wall portions of the female bump 14a are further deformed by the pressing, and the top portions of the repair bumps (24, 25, 26) on the lower end side are metallurgically joined to the bottom portions of the female bump 14 a. Since the distance between the main substrate and the carrier is compressed by the pressing, the height of the bump connector at the final connection stage is lower than the height of the bump connector at the time of temporary connection, and the female bump 14a and the repair bumps (24, 25, 26) are brought together in a mutually disordered and fragmented manner. In a disordered state in which the chips are randomly gathered, the debris that forms the pattern of the conductor having high hardness of the intermediate layer 25 is unevenly distributed inside the bump connected body along the irregular shape in the distorted bottomed cylindrical trace. As a result, the conductors having different hardnesses are unevenly contained in the space at and near the intersection of the base-side curved surface and the restoration-side curved surface, which are mutually engaged with each other. That is, the main board provided with the main board circuit and the carrier provided with the carrier-side circuit are electrically connected by the bump connector, whereby the stacked semiconductor device according to the first modification of the second embodiment can be configured.

As described above, according to the stacked semiconductor device according to the first modification of the second embodiment of the present invention, it is possible to provide a stacked semiconductor device, a carrier element, and the like in which repair processing of a defective carrier element is facilitated. As a result, according to the stacked semiconductor device according to the first modification of the second embodiment, the manufacturing time of various stacked semiconductor devices including the stacked semiconductor device in which a large number of mounting elements are arranged on a large-diameter main substrate is shortened, the normally operating main substrate and the normally operating mounting elements are not lost, and the number of repair processes can be increased.

(second modification of the second embodiment)

A stacked semiconductor device according to a second modification of the second embodiment of the present invention has a stacked structure including a base body having the same structure as the stacked semiconductor device according to the first embodiment shown in fig. 3A and 3B and a constituent member that is at least a part of a carrier member group. As can be understood from fig. 3A and 3B, the base of the stacked semiconductor device according to the second modification of the second embodiment also includes a main substrate, not shown, and a field insulating film provided on the main substrate, and the base of the stacked semiconductor device includes the bottomed elliptic cylindrical mother bump 15 shown in fig. 12 on the field insulating film. On the other hand, each of the carrier members constituting the group includes a carrier element, not shown, and a multilayer wiring insulating layer provided on the lower surface of the carrier element, and a structure in which repair bumps (24, 25, 26) having a bottomed cylindrical (tea can-shaped) structure shown in fig. 12 are provided on the lower surface of the multilayer wiring insulating layer is conceivable, but the carrier element may be a structure of a separate element such as an LED chip. The other features are the same as those of the stacked semiconductor device according to the second embodiment shown in fig. 10, but the planar pattern of the repair bumps (24, 25, 26) is preferably an ellipse having a major axis in a direction orthogonal to the major axis of the mother bump 15.

The female bump 15 is a bottomed elliptic cylindrical disk having a wall-shaped base-side curved surface perpendicular to the substrate-receiving surface of the main substrate. The female bump 15 contacts the lower surface of the bottomed elliptic cylindrical disk with the surface electrode embedded in the field insulating film, and is electrically connected to a main substrate circuit integrated on the main substrate. The repair bumps (24, 25, 26) have wall-shaped repair-side curved surfaces perpendicular to the connection surface of the carrier element, and are electrically connected to the carrier-element-side circuit. The repair bumps (24, 25, 26) are electrically connected to a carrier-side circuit provided in the carrier via surface wirings embedded in the multilayer wiring insulating layer. When the repair bumps (24, 25, 26) and the female bump 15 have a relationship of long axes in mutually orthogonal directions, the base-side curved surface and the repair-side curved surface intersect at four intersection points. As is clear from fig. 12, assuming that the planar pattern of the repair bumps (24, 25, 26) is a shape close to a perfect circle, if the long axis of the female bump 15 is longer than the diameter of the repair bump (24, 25, 26), the base-side curved surface and the repair-side curved surface can intersect at four intersections. On the other hand, even if the planar pattern of the female bump 15 is a nearly perfect circle, if the long axis of the repair bump (24, 25, 26) is in a longer relationship than the diameter of the female bump 15, the base-side curved surface and the repair-side curved surface can intersect at four intersections.

The repair bumps (24, 25, 26) have a three-layer structure consisting of a bottomed cylindrical outermost layer 24, an intermediate layer 25, and an innermost layer 26. The intermediate layer 25 has a hardness higher than those of the outermost layer 24 and the innermost layer 26 and that of the female bump 15. For example, the conductors of the outermost layer 24 and the innermost layer 26 of the mother bump 15 and the repair bumps (24, 25, 26) may be formed using a combination of metals and alloys as described in the first embodiment. The mother bump 15 and the repair bumps (24, 25, and 26) constitute a bump connector, which is an element of the stacked semiconductor device according to the second modification of the second embodiment.

In the bump connector of the stacked semiconductor device according to the second modification of the second embodiment, a material having a higher hardness than the metal used for the mother bump 15 is added to the intermediate layer 25 of the structure of the bottomed cylindrical repair bump (24, 25, 26) having a three-layer structure, and a dent is formed by biting into the mother bump 15 of the other by the pressure applied at the time of bonding, thereby forming solid-phase diffusion bonding. That is, the intermediate layer 25 having high hardness is cut into a deep notch like a knife edge to form solid-phase diffusion bonding, and therefore, the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The repair bumps (24, 25, 26) and the mother bump 15 can be bonded by solid phase diffusion even at low temperatures.

In the bump connector of the stacked semiconductor device according to the second modification of the second embodiment, since the repair bumps (24, 25, 26) are pressed against the female bumps 15 with a relatively small pressure to suppress most of the bump deformation except for the solid diffusion bonding portions, if the temporary connection is performed with a weak pressure and there is a failure after the electrical evaluation, the carrier member in which the failure is found can be replaced with another normal component member from among the repair portions included in the total number prepared as a group in advance and the temporary connection can be performed again. If the electrical evaluation based on the provisional connection again passes, the joining to the formal connection can be entered. Note that, in the laminated semiconductor device according to the second modification of the second embodiment, a material that is a combination of the metal of the mother bump 15 to be bump-bonded and has a higher hardness of the compound than the bump metal may be added to the intermediate layer 25 that is a part of the repair bumps (24, 25, 26), so that the compound acts to locally greatly deform or crack the metal of the mother bump 15 of the other.

On the other hand, when it is confirmed that the carrier element is normally operated in a state where the female bump 15 and the repair bump (24, 25, 26) are temporarily connected or the like, the force pressing the carrier element toward the main substrate is further increased, and the interval between the carrier element and the main substrate is further shortened. When the force pressing the carrier member toward the main substrate is further increased, the carrier member is formally connected to the main substrate. When the female bump 15 is formally connected to the repair bumps (24, 25, 26), the vertical side wall portions of the female bump 15 are further deformed by the pressing, and the top portions of the lower end sides of the repair bumps (24, 25, 26) are metallurgically joined to the bottom portions of the female bump 15. Since the distance between the main board and the carrier is compressed by the pressing, the height of the bump connector in the final connection stage is lower than the height of the bump connector in the temporary connection, and the female bump 15 and the repair bump (24, 25, 26) are brought together in a mutually disordered and fragmented manner. In a disordered state in which the chips are randomly gathered, the debris that forms the pattern of the conductor having high hardness of the intermediate layer 25 is unevenly distributed inside the bump connected body along the irregular shape in the distorted bottomed cylindrical trace. As a result, the conductors having different hardnesses are unevenly contained in the space at and near the intersection of the base-side curved surface and the restoration-side curved surface, which are mutually engaged with each other. That is, the main board provided with the main board circuit and the carrier provided with the carrier-side circuit are electrically connected by the bump connector, whereby the stacked semiconductor device according to the second modification of the second embodiment can be configured.

As described above, according to the stacked semiconductor device according to the second modification of the second embodiment of the present invention, it is possible to provide a stacked semiconductor device, a carrier element, and the like in which repair processing of a defective carrier element is facilitated. As a result, according to the stacked semiconductor device according to the second modification of the second embodiment, the manufacturing time of various stacked semiconductor devices including the stacked semiconductor device in which a large number of carrier elements are arranged on a large-diameter main substrate can be shortened, and the number of repair processes can be increased without causing no loss of normal main substrates and normal carrier elements.

(third embodiment)

A stacked semiconductor device according to a third embodiment of the present invention has a stacked structure including a base having the same structure as the stacked semiconductor device according to the first embodiment shown in fig. 3A and 3B, and a predetermined number of components selected from the total number of carrier components prepared in advance as a group. As can be understood from fig. 3A and 3B, the base of the stacked semiconductor device according to the third embodiment also includes a main substrate, not shown, and a field insulating film provided on the main substrate, and the field insulating film has the mother bumps 14B in the form of parallel flat plates as shown in fig. 13. On the other hand, each of the carrier members constituting the group includes a carrier element, not shown, and a multilayer wiring insulating layer provided on the lower end surface of the carrier element, and a structure in which repair bumps (27, 28, 29) having a parallel flat plate-like structure shown in fig. 13 are provided on the lower surface of the multilayer wiring insulating layer is conceivable, but the carrier element may be a structure of a separate element such as an LED chip. The main surfaces of the parallel flat plate-shaped repair bumps (27, 28, 29) and the main surface of the parallel flat plate-shaped mother bump 14b are preferably in a mutually orthogonal relationship. Although not shown, in the same manner as in fig. 3A and the like, a contact via hole and a female bump-side land are buried in the field insulating film, and the female bump 14b is electrically connected to the female bump-side land through the contact via hole. Similarly, a contact via hole and a repair bump land are embedded in the multilayer wiring insulating layer, and the repair bumps (27, 28, 29) are electrically connected to the repair bump land through the contact via hole.

The female bump 14b is a parallel flat plate-like plate having a wall-like base-side curved surface perpendicular to the substrate-bearing surface of the main substrate. The mother bump 14b contacts the lower end surface of the parallel flat plate-like board with the surface electrode of the embedded field insulating film, and is electrically connected to a main substrate circuit integrated on the main substrate. The repair bumps (27, 28, 29) have wall-shaped repair-side curved surfaces perpendicular to the connection surface of the carrier element, and are electrically connected to the carrier-element-side circuit. The repair bumps (27, 28, 29) are electrically connected to a carrier-side circuit provided in the carrier via surface wirings embedded in the multilayer wiring insulating layer. If the repair bump (27, 28, 29) and the female bump 14b are in a relationship in which the main surfaces intersect each other, the base-side curved surface and the repair-side curved surface intersect at one intersection point.

The repair bumps (27, 28, 29) have a three-layer structure including a first layer 27, a second layer 28, and a third layer 29 in the form of parallel flat plates. The hardness of the second layer (intermediate layer) 28 is higher than the hardness of the first layer 27 and the third layer 29 and the hardness of the female bump 14 b. As the electrical conductors of the mother bump 14b and the repair bumps (27, 28, 29), a combination of metals and alloys as described in the first embodiment can be used. The mother bump 14b and the repair bumps (27, 28, 29) constitute a bump connector, which is an element of the stacked semiconductor device according to the third embodiment.

In the bump connector of the stacked semiconductor device according to the third embodiment, a material having a hardness higher than that of the metal used for the mother bumps 14b is added to the intermediate layer 28 of the repair bumps (27, 28, 29) having a three-layer structure and in the form of parallel flat plates, and the pressure applied at the time of bonding causes the mother bumps 14b of the other pair to bite into and dent, thereby forming solid-phase diffusion bonding. That is, the intermediate layer 28 having high hardness is cut into a deep notch like a knife edge to form solid-phase diffusion bonding, and therefore, the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The repair bumps (27, 28, 29) and the mother bump 14b can be bonded by solid-phase diffusion even at low temperatures.

In the bump connector of the stacked semiconductor device according to the third embodiment, since the repair bumps (27, 28, 29) are pressed against the female bumps 14b with a relatively small pressure to suppress deformation of most bumps except for the solid diffusion bonding portions, if temporary connection is performed with a weak pressure and there is a defect after electrical evaluation, the carrier member in which the defect is found can be replaced with another normal component member from among the repair portions included in the total number prepared as a group in advance and temporarily connected again. If the electrical evaluation based on the provisional connection again passes, the joining to the formal connection can be entered. Note that, in the laminated semiconductor device according to the third embodiment, a material that is a combination of metals of the mother bumps 14b to be bump-bonded and has a higher hardness of a compound than that of the bump metal may be added to the intermediate layer 28 that is a part of the repair bumps (27, 28, 29), so that the compound acts to locally greatly deform or crack the metal of the mother bump 14b on the other side. In the case of joining side walls (sidewalls) of the same or equivalent hardness, both the repair bump and the female bump are considerably crushed and deformed by one time of temporary joining. However, only by this deformation, the exposed area of the clean gold is not large, and therefore, the gold is peeled off immediately. On the other hand, by making the intermediate layer (second layer) 28 of the repair bumps (27, 28, 29) a material harder than the other portions and making the thicknesses of the first layer 27 and the third layer 29 of the repair bumps (27, 28, 29) thin, the hard material bites into the side wall of the other side like a knife, the exposed area increases, and the separation after temporary bonding is less likely. Since the temporary joining is not easily peeled off, a significant effect of increasing the number of repairs is obtained.

On the other hand, when it is confirmed that the carrier element is normally operated in a state where the female bump 14b and the repair bump (27, 28, 29) are temporarily connected or the like, the force pressing the carrier element toward the main substrate is further increased, and the interval between the carrier element and the main substrate is further shortened. When the force pressing the carrier member toward the main substrate is further increased, the carrier member is formally connected to the main substrate. When the female bump 14b is formally connected to the repair bumps (27, 28, 29), the vertical side wall portions of the female bump 14b are further deformed by the pressing, and the top portions of the repair bumps (27, 28, 29) on the lower end side are metallurgically joined toward the lower end side of the female bump 14 b.

Since the distance between the main substrate and the carrier is compressed by the pressing, the height of the bump connector at the final connection stage is lower than the height of the bump connector at the time of temporary connection, and the female bump 14b and the repair bump (27, 28, 29) are brought together in a mutually disordered and fragmented manner. In a disordered state in which the chips are randomly gathered, the debris residues constituting the pattern of the conductor having high hardness of the intermediate layer 28 are unevenly distributed inside the bump connector along the irregular shape in the distorted plate-like trace. As a result, the conductors having different hardnesses are unevenly contained in the space at and near the intersection of the base-side curved surface and the restoration-side curved surface, which are mutually engaged with each other. That is, the main board provided with the main board circuit and the carrier provided with the carrier-side circuit are electrically connected by the bump connector, whereby the stacked semiconductor device according to the third embodiment can be configured.

As described above, according to the stacked semiconductor device according to the third embodiment of the present invention, it is possible to provide a stacked semiconductor device, a mounting element, and the like in which repair processing of a defective mounting element is facilitated. As a result, according to the stacked semiconductor device according to the third embodiment, the manufacturing time of various stacked semiconductor devices including a stacked semiconductor device in which a large number of mounting elements are arranged on a large-diameter main substrate can be shortened, and the number of repair processes can be increased without causing no loss of normal main substrates and normal mounting elements.

(first modification of the third embodiment)

A stacked semiconductor device according to a first modification of the third embodiment of the present invention has a stacked structure including a base having the same structure as the stacked semiconductor device according to the first embodiment shown in fig. 3A and 3B, and a predetermined number of components selected from the total number of carrier components prepared in advance as a group. As can be understood from fig. 3A and 3B, the base of the stacked semiconductor device according to the first modification of the third embodiment also includes a main substrate, not shown, and a field insulating film provided on the main substrate, and the bottomed cylindrical mother bump 15 shown in fig. 14 is provided on the field insulating film. On the other hand, each of the carrier members constituting the group includes a carrier element, not shown, and a multilayer wiring insulating layer provided on the lower end surface of the carrier element, and a structure in which repair bumps (27, 28, 29) having a parallel flat plate-like structure shown in fig. 14 are provided on the lower surface of the multilayer wiring insulating layer is assumed as an example. However, this is merely an example, and the carrier element may be a structure of a separate element such as an LED chip.

The female bump 15 is a bottomed cylindrical disk having a wall-shaped base-side curved surface perpendicular to the substrate-receiving surface of the main substrate. The female bump 15 electrically connects the bottom surface of the bottomed cylindrical disk with the surface electrode of the embedded field insulating film to a main substrate circuit integrated on the main substrate. The repair bumps (27, 28, 29) have wall-shaped repair-side curved surfaces perpendicular to the connection surface of the carrier element, and are electrically connected to the carrier-element-side circuit. The repair bumps (27, 28, 29) are electrically connected to a carrier-side circuit provided in the carrier via surface wirings embedded in the multilayer wiring insulating layer. The lower end faces of the repair bumps (27, 28, 29) and the upper end faces of the female bumps 15 intersect at two intersection points as shown in fig. 14.

The repair bumps (27, 28, 29) have a three-layer structure including a first layer 27, a second layer 28, and a third layer 29 in the form of parallel flat plates, as in the structure shown in fig. 13. The hardness of the second layer (intermediate layer) 28 is higher than the hardness of the first layer 27 and the third layer 29 and the hardness of the female bump 15. As the electric conductors of the mother bump 15 and the repair bumps (27, 28, 29), a combination of metals and alloys as described in the first embodiment can be used. The mother bump 15 and the repair bumps (27, 28, 29) constitute a bump connector, which is an element of the laminated semiconductor device according to the first modification of the third embodiment.

In the bump connector of the laminated semiconductor device according to the first modification of the third embodiment, a material having a hardness higher than that of the metal used for the mother bumps 15 is added to the intermediate layer 28 of the repair bumps (27, 28, 29) having a three-layer structure in the form of parallel flat plates, and the opposing mother bumps 15 are indented by the pressure applied during bonding to form a dimple, thereby forming solid-phase diffusion bonding. That is, the intermediate layer 28 having high hardness is cut into a deep notch like a knife edge to form solid-phase diffusion bonding, and therefore, the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The repair bumps (27, 28, 29) and the mother bump 15 can be bonded by solid-phase diffusion even at low temperatures.

In the bump connector of the stacked semiconductor device according to the first modification of the third embodiment, since the repair bumps (27, 28, 29) are pressed against the female bumps 15 with a relatively small pressure to suppress most of the bump deformation except for the solid diffusion bonding portions, if the temporary connection is performed with a weak pressure and there is a failure after the electrical evaluation, the carrier member in which the failure is found can be replaced with another normal component member from among the repair portions included in the total number prepared as a group in advance and the temporary connection can be performed again. If the electrical evaluation based on the provisional connection again passes, the joining to the formal connection can be entered. Note that, in the laminated semiconductor device according to the first modification of the third embodiment, a material that is a combination of the metal of the mother bump 15 to be bump-bonded and has a higher hardness of the compound than the bump metal may be added to the intermediate layer 28 that is a part of the repair bumps (27, 28, 29), so that the compound may locally and largely deform the metal of the mother bump 15 of the other side or cause cracks.

On the other hand, when it is confirmed that the carrier element is normally operated in a state where the female bump 15 and the repair bump (27, 28, 29) are temporarily connected or the like, the force pressing the carrier element against the main substrate is further increased, and the interval between the carrier element and the main substrate is further shortened. When the force pressing the carrier member toward the main substrate is further increased, the carrier member is formally connected to the main substrate. When the female bump 15 is positively connected to the repair bumps (27, 28, 29), the vertical side wall portions of the female bump 15 are further deformed by the pressing, and the top portions of the repair bumps (27, 28, 29) on the lower end side are metallurgically joined toward the lower end side of the female bump 15. Since the distance between the main board and the carrier is compressed by the pressing, the height of the bump connector at the final connection stage is lower than the height of the bump connector at the time of temporary connection, and the female bump 15 and the repair bump (27, 28, 29) are brought together in a mutually disordered and fragmented manner. In a disordered state in which the chips are randomly gathered, the debris residues constituting the pattern of the conductor having high hardness of the intermediate layer 28 are unevenly distributed inside the bump connector along the irregular shape in the distorted plate-like trace. As a result, the conductors having different hardnesses are unevenly contained in the space at and near the intersection of the base-side curved surface and the restoration-side curved surface, which are mutually engaged with each other. That is, the main board provided with the main board circuit and the carrier provided with the carrier-side circuit are electrically connected by the bump connector, whereby the stacked semiconductor device according to the first modification of the third embodiment can be configured.

As described above, according to the stacked semiconductor device according to the first modification of the third embodiment of the present invention, it is possible to provide a stacked semiconductor device, a carrier element, and the like in which repair processing of the carrier element is facilitated. As a result, according to the stacked semiconductor device according to the first modification of the third embodiment, the manufacturing time of various stacked semiconductor devices including the stacked semiconductor device in which a large number of mounting elements are arranged on a large-diameter main substrate is shortened, and the number of repair processes can be increased without causing no loss of normal main substrates and normal mounting elements.

(second modification of the third embodiment)

A stacked semiconductor device according to a second modification of the third embodiment of the present invention has a stacked structure including a base having the same structure as the stacked semiconductor device according to the first embodiment shown in fig. 3A and 3B, and a predetermined number of components selected from the total number of carrier components prepared in advance as a group. As can be understood from fig. 3A and 3B, the base of the stacked semiconductor device according to the second modification of the third embodiment also includes a main substrate, not shown, and a field insulating film provided on the main substrate, and the rectangular box-shaped mother bump 11 shown in fig. 15 is provided on the field insulating film. On the other hand, each of the carrier members constituting the group includes a carrier element, not shown, and a multilayer wiring insulating layer provided on the lower end surface of the carrier element, and a structure in which repair bumps (27, 28, 29) having a parallel flat plate-like structure shown in fig. 15 are provided on the lower surface of the multilayer wiring insulating layer is assumed as an example. However, the carrier element is merely an example, and thus the carrier element may have a structure other than the example including a separate element such as an LED chip.

The female bump 11 is a box-shaped plate having a wall-shaped curved surface on the base side perpendicular to the substrate-receiving surface of the main substrate. The female bump 11 is electrically connected to a main substrate circuit integrated on a main substrate by bonding the bottom surface of the box-shaped disk to the surface electrode of the embedded field insulating film. The repair bumps (27, 28, 29) have wall-shaped repair-side curved surfaces perpendicular to the connection surface of the carrier element, and are electrically connected to the carrier-element-side circuit. The repair bumps (27, 28, 29) are electrically connected to a carrier-side circuit provided in the carrier via surface wirings embedded in the multilayer wiring insulating layer. The lower end faces of the repair bumps (27, 28, 29) and the upper end faces of the female bumps 11 intersect at two intersection points as shown in fig. 15.

The repair bumps (27, 28, 29) have a three-layer structure including a first layer 27, a second layer 28, and a third layer 29 in the form of parallel flat plates, as in the structure shown in fig. 13. The hardness of the second layer (intermediate layer) 28 is higher than the hardness of the first layer 27 and the third layer 29 and the hardness of the female bump 11. As the conductors of the mother bump 11 and the repair bumps (27, 28, 29), combinations of metals and alloys as described in the first embodiment can be used. The mother bump 11 and the repair bumps (27, 28, 29) constitute a bump connector, which is an element of the stacked semiconductor device according to the second modification of the third embodiment.

In the bump connector of the stacked semiconductor device according to the second modification of the third embodiment, a material having a higher hardness than the metal used for the mother bumps 11 is added to the intermediate layer 28 of the repair bumps (27, 28, 29) having a three-layer structure in the form of parallel flat plates, and a dimple is formed by biting into the mother bump 11 of the other by the pressure applied at the time of bonding, thereby forming solid-phase diffusion bonding. That is, the intermediate layer 28 having high hardness is cut into a deep notch like a knife edge to form solid-phase diffusion bonding, and therefore, the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The repair bumps (27, 28, 29) and the mother bump 11 can be bonded by solid-phase diffusion even at low temperatures.

In the bump connector of the stacked semiconductor device according to the second modification of the third embodiment, since the repair bumps (27, 28, 29) are pressed against the female bumps 11 with a relatively small pressure to suppress most of the bump deformation except for the solid diffusion bonding portions, if the temporary connection is performed with a weak pressure and there is a failure after the electrical evaluation, the carrier member in which the failure is found can be replaced with another normal component member from among the repair portions included in the total number prepared as a group in advance and the temporary connection can be performed again. If the electrical evaluation based on the provisional connection again passes, the joining to the formal connection can be entered. Note that, in the laminated semiconductor device according to the second modification of the third embodiment, a material that is a combination of the metal of the mother bump 11 to be bump-bonded and has a higher hardness of the compound than the bump metal may be added to the intermediate layer 28 that is a part of the repair bumps (27, 28, 29), so that the compound may locally and largely deform the metal of the mother bump 11 of the other side or cause cracks.

On the other hand, when it is confirmed that the carrier element is normally operated in a state where the female bump 11 and the repair bumps (27, 28, 29) are temporarily connected or the like, the force pressing the carrier element against the main substrate is further increased, and the interval between the carrier element and the main substrate is further shortened. When the force pressing the carrier member toward the main substrate is further increased, the carrier member is formally connected to the main substrate. When the female bump 11 is positively connected to the repair bumps (27, 28, 29), the vertical side wall portions of the female bump 11 are further deformed by the pressing, and the top portions of the repair bumps (27, 28, 29) on the lower end side are metallurgically joined toward the lower end side of the female bump 11. Since the distance between the main board and the carrier is compressed by the pressing, the height of the bump connector at the final connection stage is lower than the height of the bump connector at the time of temporary connection, and the female bump 11 and the repair bump (27, 28, 29) are brought together in a mutually disordered and fragmented manner. In a disordered state in which the chips are randomly gathered, the debris residues constituting the pattern of the conductor having high hardness of the intermediate layer 28 are unevenly distributed inside the bump connector along the irregular shape in the distorted plate-like trace. As a result, the conductors having different hardnesses are unevenly contained in the space at and near the intersection of the base-side curved surface and the restoration-side curved surface, which are mutually engaged with each other. That is, the main board provided with the main board circuit and the carrier provided with the carrier-side circuit are electrically connected by the bump connector, whereby the stacked semiconductor device according to the second modification of the third embodiment can be configured.

As described above, according to the stacked semiconductor device according to the second modification of the third embodiment of the present invention, it is possible to provide a stacked semiconductor device, a carrier element, and the like in which repair processing of the carrier element is facilitated. As a result, according to the stacked semiconductor device according to the second modification of the third embodiment, the manufacturing time of various stacked semiconductor devices including the stacked semiconductor device in which a large number of carrier elements are arranged on a large-diameter main substrate can be shortened, and the number of repair processes can be increased without causing no loss of normal main substrates and normal carrier elements.

(fourth embodiment)

A stacked semiconductor device according to a fourth embodiment of the present invention has a stacked structure including a base having the same structure as the stacked semiconductor device according to the first embodiment shown in fig. 3A and 3B, and a predetermined number of components selected from the total number of carrier components prepared in advance as a group. As can be understood from fig. 3A and 3B, the base of the laminated semiconductor device according to the fourth embodiment also includes a main substrate, not shown, and a field insulating film provided on the main substrate, and the field insulating film has mother bumps 14B in the form of parallel flat plates as shown in fig. 16. On the other hand, each of the carrier members constituting the group includes a carrier element, not shown, and a multilayer wiring insulating layer provided on the lower end surface of the carrier element, and a structure in which repair bumps (27, 28) having a parallel flat plate-like structure shown in fig. 16 are provided on the lower surface of the multilayer wiring insulating layer is assumed as an example. However, the carrier element is merely an example, and thus the carrier element may have a structure other than the example including a separate element such as an LED chip. The main surfaces of the parallel flat plate-shaped repair bumps (27, 28) and the main surface of the parallel flat plate-shaped mother bump 14b are preferably in a relationship in directions orthogonal to each other. Although not shown, in the same manner as in fig. 3A and the like, a contact via hole and a female bump-side land are embedded in the field insulating film, and the female bump 14b is electrically connected to the female bump-side land via the contact via hole. Similarly, a contact via hole and a repair bump land are embedded in the multilayer wiring insulating layer, and the repair bumps (27, 28) are electrically connected to the repair bump land via the contact via hole.

The female bump 14b is a parallel flat plate-like plate having a wall-like base-side curved surface perpendicular to the substrate-bearing surface of the main substrate. The mother bump 14b contacts the lower end surface of the parallel flat plate-like board with the surface electrode of the embedded field insulating film, and is electrically connected to a main substrate circuit integrated on the main substrate. The repair bumps (27, 28) have wall-shaped repair side curved surfaces perpendicular to the connection surface of the carrier element, and are electrically connected to the carrier element side circuit. The repair bumps (27, 28) are electrically connected to a carrier-side circuit provided in the carrier via surface wirings embedded in the multilayer wiring insulating layer. When the repair bumps (27, 28) and the female bump 14b are in a relationship in which the main surfaces intersect each other, the base-side curved surface and the repair-side curved surface intersect at one intersection point.

The repair bumps (27, 28) have a two-layer structure composed of a low-hardness layer 27 and a high-hardness layer 28 in the form of parallel flat plates. The high-hardness layer 28 has a higher hardness than the low-hardness layer 27 and the female bump 14 b. As the electric conductors of the mother bump 14b and the repair bumps (27, 28), a combination of metals and alloys as described in the first embodiment can be used. The mother bump 14b and the repair bumps (27, 28) constitute a bump connector, which is an element of the laminated semiconductor device according to the fourth embodiment.

In the bump connector of the laminated semiconductor device according to the fourth embodiment, a material having a hardness higher than that of the metal used for the mother bumps 14b is added to the high-hardness layer 28 of the repair bumps (27, 28) having a two-layer structure and having a parallel flat plate shape, and a dent is formed by biting into the mother bump 14b of the other by a pressure applied at the time of bonding, thereby forming solid-phase diffusion bonding. That is, the relatively hard high-hardness layer 28 is cut into a deep notch like a knife edge to form solid-phase diffusion bonding, and therefore, the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The repair bumps (27, 28) and the mother bump 14b can be bonded by solid-phase diffusion even at low temperatures.

In the bump connector of the stacked semiconductor device according to the fourth embodiment, since the repair bumps (27, 28) are pressed against the female bumps 14b with a relatively small pressure to suppress deformation of most bumps except for the solid diffusion bonding portions, if temporary connection is performed with a weak force and there is a defect after electrical evaluation, the carrier member in which the defect is found can be replaced with another normal component member from among the repair portions included in the total number prepared as a group in advance and temporarily connected again. If the electrical evaluation based on the provisional connection again passes, the joining to the formal connection can be entered. Note that, in the laminated semiconductor device according to the fourth embodiment, a material that is a combination of metals of the mother bumps 14b to be bump-bonded and has a higher hardness of a compound than that of the bump metal may be added to the high-hardness layer 28 that is a part of the repair bumps (27, 28), so that the compound acts to locally greatly deform or crack the metal of the mother bump 14b on the other side. In the case of joining side walls (sidewalls) of the same or equivalent hardness, both the repair bump and the female bump are considerably crushed and deformed by one time of temporary joining. However, only by this deformation, the exposed area of the clean gold is not large, and therefore, the gold is peeled off immediately. On the other hand, by making the high-hardness layer 28 of the repair bumps (27, 28) harder than the other portions and making the thickness of the low-hardness layer 27 of the repair bumps (27, 28) thinner, the hard material bites into the side wall of the other side wall like a knife, the exposed area increases, and the separation after temporary bonding is less likely. Since the temporary joining is not easily peeled off, a significant effect of increasing the number of repairs is obtained.

On the other hand, when it is confirmed that the carrier element is normally operated in a state where the female bump 14b is temporarily connected to the repair bumps (27, 28), etc., the force pressing the carrier element against the main substrate is further increased, and the interval between the carrier element and the main substrate is further shortened. When the force pressing the carrier member toward the main substrate is further increased, the carrier member is formally connected to the main substrate. When the female bump 14b is positively connected to the repair bumps (27, 28), the vertical side wall portions of the female bump 14b are further deformed by the pressing, and the top portions of the repair bumps (27, 28) on the lower end side are metallurgically joined to each other toward the lower end side of the female bump 14 b. Since the distance between the main substrate and the carrier is compressed by the pressing, the height of the bump connector at the final connection stage is lower than the height of the bump connector at the time of temporary connection, and the female bump 14b and the repair bumps (27, 28) are brought together in a mutually disordered and fragmented manner. In a disordered state in which the high-hardness layers 28 are randomly gathered, the debris residues constituting the pattern of the high-hardness conductor of the high-hardness layer 28 are unevenly distributed inside the bump connected body along the irregular shape in the distorted plate-like trace. As a result, the conductors having different hardnesses are unevenly contained in the space at and near the intersection of the base-side curved surface and the restoration-side curved surface, which are mutually engaged with each other. That is, the main board provided with the main board circuit and the carrier provided with the carrier-side circuit are electrically connected by the bump connector, whereby the stacked semiconductor device according to the fourth embodiment can be configured.

As described above, according to the stacked semiconductor device according to the fourth embodiment of the present invention, it is possible to provide a stacked semiconductor device, a carrier element, and the like in which repair processing of the carrier element is facilitated. As a result, according to the stacked semiconductor device of the fourth embodiment, the manufacturing time of various stacked semiconductor devices is shortened, and the number of repair processes can be increased without causing no loss of the normal main substrate and the normal mount element.

(first modification of the fourth embodiment)

A stacked semiconductor device according to a first modification of the fourth embodiment of the present invention has a stacked structure including a base having the same structure as the stacked semiconductor device according to the first embodiment shown in fig. 3A and 3B, and a predetermined number of components selected from the total number of carrier components prepared in advance as a group. As can be understood from fig. 3A and 3B, the base of the stacked semiconductor device according to the first modification of the fourth embodiment also includes a main substrate, not shown, and a field insulating film provided on the main substrate, and the bottomed cylindrical mother bump 15 shown in fig. 17 is provided on the field insulating film. On the other hand, each of the carrier members constituting the group includes a carrier element, not shown, and a multilayer wiring insulating layer provided on the lower end surface of the carrier element, and a structure in which repair bumps (27, 28) having a parallel flat plate-like structure shown in fig. 17 are provided on the lower surface of the multilayer wiring insulating layer is assumed as an example. However, the carrier element is merely an example, and thus the carrier element may have a structure other than the example including a separate element such as an LED chip.

The female bump 15 is a bottomed cylindrical disk having a wall-shaped base-side curved surface perpendicular to the substrate-receiving surface of the main substrate. The female bump 15 electrically connects the bottom surface of the bottomed cylindrical disk with the surface electrode of the embedded field insulating film to a main substrate circuit integrated on the main substrate. The repair bumps (27, 28) have wall-shaped repair side curved surfaces perpendicular to the connection surface of the carrier element, and are electrically connected to the carrier element side circuit. The repair bumps (27, 28) are electrically connected to a carrier-side circuit provided in the carrier via surface wirings embedded in the multilayer wiring insulating layer. The lower end faces of the repair bumps (27, 28) and the upper end faces of the female bumps 15 intersect at two intersection points as shown in fig. 17.

The repair bumps (27, 28) have a two-layer structure composed of a low-hardness layer 27 and a high-hardness layer 28 in the form of parallel flat plates, as in the structure shown in fig. 16. The high-hardness layer 28 has a higher hardness than the low-hardness layer 27 and the female bump 15. As the electric conductors of the mother bump 15 and the repair bumps (27, 28), a combination of metals and alloys as described in the first embodiment can be used. The mother bump 15 and the repair bumps (27, 28) constitute a bump connector, which is an element of the laminated semiconductor device according to the first modification of the fourth embodiment.

In the bump connector of the laminated semiconductor device according to the first modification of the fourth embodiment, a material having a higher hardness than the metal used for the mother bumps 15 is added to the high-hardness layer 28 of the repair bumps (27, 28) having a two-layer structure and having a parallel flat plate shape, and a dent is formed by biting into the mother bump 15 of the other by a pressure applied at the time of bonding, thereby forming solid-phase diffusion bonding. That is, the relatively hard high-hardness layer 28 is cut into a deep notch like a knife edge to form solid-phase diffusion bonding, and therefore, the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The repair bumps (27, 28) and the mother bump 15 can be bonded by solid-phase diffusion even at low temperatures.

In the bump connector of the laminated semiconductor device according to the first modification of the fourth embodiment, since the repair bumps (27, 28) are pressed against the female bumps 15 with a relatively small pressure to suppress most of the bump deformation except for the solid diffusion bonding portions, if the temporary connection is performed with a weak pressing force and there is a defect after the electrical evaluation, the carrier member in which the defect is found can be replaced with another normal component member from among the repair portions included in the total number prepared in excess as a group in advance and the temporary connection can be performed again. If the electrical evaluation based on the provisional connection again passes, the joining to the formal connection can be entered. Note that, in the laminated semiconductor device according to the first modification of the fourth embodiment, a material that is a combination of the metal of the mother bump 15 to be bump-bonded and has a higher hardness than the bump metal may be added to the high-hardness layer 28 that is a part of the repair bumps (27, 28), so that the compound may locally and largely deform the metal of the mother bump 15 of the other side or cause cracks.

On the other hand, when it is confirmed that the carrier element is normally operated in a state where the female bump 15 and the repair bumps (27, 28) are temporarily connected or the like, the force pressing the carrier element against the main substrate is further increased, and the interval between the carrier element and the main substrate is further shortened. When the force pressing the carrier member toward the main substrate is further increased, the carrier member is formally connected to the main substrate. When the female bump 15 is positively connected to the repair bumps (27, 28), the vertical side wall portions of the female bump 15 are further deformed by the pressing, and the top portions of the repair bumps (27, 28) on the lower end side are metallurgically joined to each other toward the lower end side of the female bump 15. Since the distance between the main substrate and the carrier is compressed by the pressing, the height of the bump connector at the final connection stage is lower than the height of the bump connector at the time of temporary connection, and the female bump 15 and the repair bumps (27, 28) are brought together in a mutually disordered and fragmented manner. The structure is disordered and is gathered in a chip shape. In a disordered state in which the high-hardness layers 28 are randomly gathered, the debris residues constituting the pattern of the high-hardness conductor of the high-hardness layer 28 are unevenly distributed inside the bump connected body along the irregular shape in the distorted plate-like trace. As a result, the conductors having different hardnesses are unevenly contained in the space at and near the intersection of the base-side curved surface and the restoration-side curved surface, which are mutually engaged with each other. That is, the main board provided with the main board circuit and the carrier provided with the carrier-side circuit are electrically connected by the bump connector, whereby the stacked semiconductor device according to the first modification of the fourth embodiment can be configured.

As described above, according to the stacked semiconductor device according to the first modification of the fourth embodiment of the present invention, it is possible to provide a stacked semiconductor device, a carrier element, and the like in which repair processing of the carrier element is facilitated. As a result, according to the stacked semiconductor device according to the first modification of the fourth embodiment, the manufacturing time of various stacked semiconductor devices is shortened, and the number of repair processes can be increased without causing no loss of the normal main substrate and the normal carrier element.

(second modification of the fourth embodiment)

A stacked semiconductor device according to a second modification of the fourth embodiment of the present invention has a stacked structure including a base having the same structure as the stacked semiconductor device according to the first embodiment shown in fig. 3A and 3B, and a predetermined number of components selected from the total number of carrier components prepared in advance as a group. As can be understood from fig. 3A and 3B, the base of the stacked semiconductor device according to the second modification of the fourth embodiment also includes a main substrate, not shown, and a field insulating film provided on the main substrate, and the rectangular box-shaped mother bump 11 shown in fig. 18 is provided on the field insulating film. On the other hand, each of the carrier members constituting the group includes a carrier element, not shown, and a multilayer wiring insulating layer provided on the lower end surface of the carrier element, and a structure in which repair bumps (27, 28) having a parallel flat plate-like structure shown in fig. 18 are provided on the lower surface of the multilayer wiring insulating layer is assumed as an example. However, the carrier element is merely an example, and thus the carrier element may have a structure other than the example including a separate element such as an LED chip.

The female bump 11 is a box-shaped plate having a wall-shaped curved surface on the base side perpendicular to the substrate-receiving surface of the main substrate. The female bump 11 electrically connects the bottom surface of the box-shaped disk with the surface electrode of the embedded field insulating film, and is electrically connected to a main substrate circuit integrated on the main substrate. The repair bumps (27, 28) have wall-shaped repair side curved surfaces perpendicular to the connection surface of the carrier element, and are electrically connected to the carrier element side circuit. The repair bumps (27, 28) are electrically connected to a carrier-side circuit provided in the carrier via surface wirings embedded in the multilayer wiring insulating layer. The lower end faces of the repair bumps (27, 28) and the upper end faces of the female bumps 11 intersect at two intersection points as shown in fig. 18.

The repair bumps (27, 28) have a two-layer structure composed of a low-hardness layer 27 and a high-hardness layer 28 in the form of parallel flat plates, as in the structure shown in fig. 16. The high-hardness layer 28 has a higher hardness than the low-hardness layer 27 and the female bump 11. As the conductors of the mother bump 11 and the repair bumps (27, 28), combinations of metals and alloys as described in the first embodiment can be used. The mother bump 11 and the repair bumps (27, 28) constitute a bump connector, which is an element of the stacked semiconductor device according to the second modification of the fourth embodiment.

In a bump connector of a stacked semiconductor device according to a second modification of the fourth embodiment, a material having a higher hardness than the metal used for the mother bumps 11 is added to the high-hardness layer 28 of the repair bumps (27, 28) having a two-layer structure and having a parallel flat plate shape, and a dent is formed by biting into the mother bump 11 of the other by a pressure applied at the time of bonding, thereby forming solid-phase diffusion bonding. That is, the relatively hard high-hardness layer 28 is cut into a deep notch like a knife edge to form solid-phase diffusion bonding, and therefore, the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The repair bumps (27, 28) and the mother bump (11) can be bonded by solid-phase diffusion even at low temperatures.

In the bump connector of the laminated semiconductor device according to the second modification of the fourth embodiment, since the repair bumps (27, 28) are pressed against the female bump 11 with a relatively small pressure to suppress most of the bump deformation except for the solid diffusion bonding portion, if the temporary connection is performed with a weak pressing force and there is a failure after the electrical evaluation, the carrier member in which the failure is found can be replaced with another normal component member from among the repair portions included in the total number prepared in excess as a group in advance and temporarily connected again. If the electrical evaluation based on the provisional connection again passes, the joining to the formal connection can be entered. Note that, in the laminated semiconductor device according to the second modification of the fourth embodiment, a material that is a combination of the metal of the mother bump 11 to be bump-bonded and has a higher hardness than the bump metal may be added to the high-hardness layer 28 that is a part of the repair bumps (27, 28), so that the compound acts to locally greatly deform or crack the metal of the mother bump 11 on the other side.

On the other hand, when it is confirmed that the carrier element is normally operated in a state where the female bump 11 and the repair bumps (27, 28) are temporarily connected or the like, the force pressing the carrier element against the main substrate is further increased, and the interval between the carrier element and the main substrate is further shortened. When the force pressing the carrier member toward the main substrate is further increased, the carrier member is formally connected to the main substrate. When the female bump 11 is positively connected to the repair bumps (27, 28), the vertical side wall portions of the female bump 11 are further deformed by the pressing, and the top portions of the repair bumps (27, 28) on the lower end side are metallurgically joined to each other toward the lower end side of the female bump 11.

Since the distance between the main board and the carrier is compressed by the pressing, the height of the bump connector in the final connection stage is lower than the height of the bump connector in the temporary connection, and the female bump 11 and the repair bumps (27, 28) are irregularly and fragmentarily gathered. The structure is disordered and is gathered in a chip shape. In a disordered state in which the high-hardness layers 28 are randomly gathered, the debris residues constituting the pattern of the high-hardness conductor of the high-hardness layer 28 are unevenly distributed inside the bump connected body along the irregular shape in the distorted plate-like trace. As a result, the conductors having different hardnesses are unevenly contained in the space at and near the intersection of the base-side curved surface and the restoration-side curved surface, which are mutually engaged with each other. That is, the main board provided with the main board circuit and the carrier provided with the carrier-side circuit are electrically connected by the bump connector, whereby the stacked semiconductor device according to the second modification of the fourth embodiment can be configured.

As described above, according to the stacked semiconductor device according to the second modification of the fourth embodiment of the present invention, it is possible to provide a stacked semiconductor device, a carrier element, and the like in which repair processing of the carrier element is facilitated. As a result, according to the stacked semiconductor device according to the second modification of the fourth embodiment, the manufacturing time of various stacked semiconductor devices is shortened, and the number of repair processes can be increased without causing no loss of the normal main substrate and the normal mount element.

(other embodiments)

As described above, although the first to fourth embodiments of the present invention have been described, the description and drawings constituting a part of the disclosure should not be construed as limiting the present invention. Various alternative embodiments, examples, and operational techniques will be apparent to those skilled in the art from this disclosure. For example, as shown in fig. 19A, the substrate 1 may have a surface electrode (mother bump-side land) exposed and the carrier may have a surface electrode (repair bump-side land) 19 exposed2 is formed in a laminated structure. In this case, the features that the number of the carrier members 2 mounted on the stacked semiconductor device is smaller than the total number of the carrier members 2 constituting the group are the same as those of the first to fourth embodiments. The base 1 is composed of a main substrate 81, a field insulating film 82 provided on the upper surface of the main substrate 81, female bump-side lands 12 selectively provided on the upper surface of the field insulating film 82, and female bumps 11 provided on the upper surfaces of the female bump-side lands 12. The carrier part 2 is formed by a carrier element X_ijArranged on the bearing element X_ijA multilayer wiring insulating layer 20 provided on the lower surface of the multilayer wiring insulating layer 20, a repair bump side land 19 selectively provided on the lower surface of the multilayer wiring insulating layer 20, and repair bumps (21, 22, 23) provided on the lower surface of the repair bump side land 19.

The main substrate 81 shown in fig. 19A is a parallel flat plate having a substrate-supporting surface and a base back surface opposite to the substrate-supporting surface, and is provided with a main substrate circuit. With respect to the carrier element X_ijThe structure of a parallel flat plate having a connection surface and a surface opposite to the connection surface is exemplified, but the structure is not limited to the parallel flat plate. For example, when the carrier element is a separate element such as an LED chip, the carrier element may have a shell-like structure. Carrying element X_ijA carrier-side circuit is provided, and the connection face faces the substrate carrying face of the main substrate 81. The female bump 11 has a rectangular box shape having a wall-shaped base-side curved surface perpendicular to the substrate receiving surface of the main substrate 81. The female bump 11 contacts the bottom surface of the case with the female bump-side land 12 exposed on the upper surface of the field insulating film 82, and the female bump-side land 12 is provided on the upper surface of the field insulating film 82. The female bump-side land 12 is electrically connected to a main substrate circuit integrated on the main substrate 81 via a contact through hole not shown. The repair projections (21, 22, 23) are rectangular box-shaped having a wall-shaped repair side curved surface perpendicular to the connection surface. The repair bumps (21, 22, and 23) contact the bottom surface (top side in fig. 19A and 19B) of the case with the repair-bump-side land 19 exposed on the lower surface of the multilayer wiring insulating layer 20, and the repair-bump-side land 19 is connected to the wiring in the multilayer wiring insulating layer 20 via contact through holes (not shown). Multiple purposeWiring in the layer wiring insulating layer 20 and the carrier element X_ijThe repair bumps (21, 22, 23) are connected to the carrier-side circuit via the repair-bump-side lands 19. Similarly to the planar pattern shown in fig. 4, the base-side curved surface and the repair-side curved surface intersect at four intersection points.

Although the illustration of the planar pattern of the female bump-side land 12 and the repair bump-side land 19 is omitted, the planar pattern may be, for example, a square, but is not limited to a square. The repair bumps (21, 22, 23) shown in fig. 19A and 19B have a three-layer structure composed of the box-shaped outermost layer 21, the intermediate layer 22, and the innermost layer 23, and have the same characteristics as those of the first embodiment. The intermediate layer 22 has a hardness higher than those of the outermost layer 21 and the innermost layer 23 and that of the female bump 11. As the conductors of the mother bump 11 and the repair bumps (21, 22, 23), combinations of metals and alloys as described in the first embodiment can be used. The female bump-side land 12 is preferably a conductor capable of reducing contact resistance with a metal or an alloy selected as the female bump 11, and the repair bump-side land 19 is preferably a conductor capable of reducing contact resistance with a metal or an alloy selected as the repair bump (21, 22, 23). The mother bump-side land 12 and the repair bump-side land 19 may be formed of, for example, Au or an alloy containing 80% or more of Au, such as Au-Si, Au-Ge, Au-Sb, Au-Sn, Au-Pb, Au-Zn, or Au-Cu, or may have a multilayer structure in which a metal layer of Ni, Cr, or the like is used as a base. As shown in fig. 19B, a bump connector B is constituted by the female bump 11 and the repair bumps (21, 22, 23)_uvThe bump connector B_uvThe laminated semiconductor device according to another embodiment is an element of the laminated semiconductor device according to another embodiment.

FIG. 19B shows a bump connector B of a stacked semiconductor device according to another embodiment_uvIn the method, a material having a hardness higher than that of the metal used for the mother bump 11 is added to the intermediate layer 22 of the box-shaped repair bump (21, 22, 23) having a three-layer structure, and a dent is formed by biting into the mother bump 11 of the other side by the pressure applied at the time of bonding, thereby forming solid-phase diffusion bonding. That is, the relatively hard intermediate layer 22 is formed by cutting a deep notch in a knife edge shape to form solid phase diffusionTherefore, the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The repair bumps (21, 22, 23) and the mother bump 11 can be bonded by solid-phase diffusion even at low temperatures. The rest of the structure is substantially the same as that of the stacked semiconductor device according to the first embodiment, and therefore, redundant description thereof is omitted.

As shown in fig. 20A, in the laminated structure including the base 1 and the carrier member 2, a structure opposite to that of fig. 19A may be employed in which a conductor having high hardness is used on the base 1 side. However, the number of the carrier members 2 mounted on the stacked semiconductor device is smaller than the total number of the carrier members 2 constituting the group. The base 1 shown in fig. 20A is composed of a main substrate 81, a field insulating film 82 provided on the upper surface of the main substrate 81, female bump-side lands 12 selectively provided on the upper surface of the field insulating film 82, and female bumps (31, 32, 33) provided on the upper surface of the female bump-side lands 12. On the other hand, the carrier part 2 is formed by a carrier element X_ijArranged on the bearing element X_ijThe multilayer wiring insulating layer 20 on the lower surface of the multilayer wiring insulating layer 20, the repair bump side land 19 selectively provided on the lower surface of the multilayer wiring insulating layer 20, and the repair bump 41 provided on the lower surface of the repair bump side land 19.

The main board 81 is a parallel flat plate having a board-supporting surface and a base back surface opposite to the board-supporting surface, and is provided with a main board circuit. With respect to the carrier element X_ijThe structure of a parallel flat plate shape having a connection surface and a surface opposite to the connection surface is exemplified, but the structure is not limited to the parallel flat plate shape. For example, when the carrier element is a separate element such as an LED chip, the carrier element may have a shell-like structure. Carrying element X_ijA carrier-side circuit is provided, the connection face facing the substrate carrying face of the main substrate 81. The female bumps (31, 32, 33) are rectangular box-shaped having wall-shaped base-side curved surfaces perpendicular to the substrate-receiving surface of the main substrate 81. The female bumps (31, 32, 33) contact the bottom surface of the case with the female bump-side lands 12 exposed on the upper surface of the field insulating film 82, and the female bump-side lands 12 are provided on the upper surface of the field insulating film 82. The female bump-side land 12 is electrically connected to a main substrate circuit integrated on the main substrate 81 via a contact through hole not shown. The repair bump 41 has a rectangular box shape having a wall-like repair-side curved surface perpendicular to the connection surface, and the bottom surface (top side in fig. 20A and 20B) of the box is in contact with the repair-bump-side land 19 exposed on the lower surface of the multilayer wiring insulating layer 20. The repair bump land 19 is connected to the wiring in the multilayer wiring insulating layer 20 via a contact via hole not shown, and the wiring in the multilayer wiring insulating layer 20 is connected to the carrier element X_ijIs electrically connected, the repair bump 41 is connected to the carrier-side circuit via the repair-bump-side land 19. Similarly to the planar pattern shown in fig. 4, the base-side curved surface and the repair-side curved surface intersect at four intersection points.

The female bump (31, 32, 33) has a three-layer structure composed of a box-shaped outermost layer 31, an intermediate layer 32, and an innermost layer 33. The intermediate layer 32 has a hardness higher than those of the outermost layer 31 and the innermost layer 33 and that of the repair bump 41. As the conductors of the mother bumps (31, 32, 33) and the repair bump 41, a combination of a high-hardness conductor and a low-hardness conductor of a metal or an alloy as described in the first embodiment can be used. The female bump-side land 12 is preferably a conductor capable of reducing contact resistance with a metal or an alloy selected as the female bump (31, 32, 33), and the repair bump-side land 19 is preferably a conductor capable of reducing contact resistance with a metal or an alloy selected as the repair bump 41. The mother bump-side land 12 and the repair bump-side land 19 may be formed of, for example, Au or an alloy such as Au — Si containing 80% or more of Au, or may have a multilayer structure using a metal layer such as Ni or Cr as a base. As shown in fig. 20B, a bump connector B is constituted by the female bumps (31, 32, 33) and the repair bump 41_uvThe bump connector B_uvThe laminated semiconductor device according to still another embodiment is an element of a laminated semiconductor device according to still another embodiment.

Yet other embodiments are shown in FIG. 20BBump connector B of stacked semiconductor device according to the formula_uvIn the method, a material having a hardness higher than that of the metal used for the repair bump 41 is added to the intermediate layer 32 of the box-shaped mother bump (31, 32, 33) having a three-layer structure, and a pressure applied at the time of bonding causes the repair bump 41 to bite into the intermediate layer to form a dent, thereby forming solid-phase diffusion bonding. That is, the relatively hard intermediate layer 32 is formed by cutting a deep notch like a knife edge on the repair bump 41 to form solid-phase diffusion bonding, and therefore, the deformed region is small but the contact area between the clean surfaces is increased. By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The repair bump 41 and the mother bumps (31, 32, 33) can be bonded by solid phase diffusion even at low temperature. The rest of the structure is substantially the same as that of the stacked semiconductor device according to the first embodiment, and therefore, redundant description thereof is omitted. As shown in fig. 20A and 20B, the stacked semiconductor devices according to the second to fourth embodiments may be configured as follows: the structure of the female bump on the base 1 side is a multilayer structure including a layer of a conductor having a high hardness, and the layer of the conductor having a high hardness of the female bump is made to bite into the repair bump on the carrier 2 side.

As a partial structure shown in fig. 21, a structure in which the structure shown in fig. 19B and the structure shown in fig. 20B are mixed may be used. The base 1 shown in fig. 21 is composed of a main substrate 81, a field insulating film 82 provided on the upper surface of the main substrate 81, left and right female bump-side lands 12a and 12b selectively provided on the upper surface of the field insulating film 82, female bumps 11 provided on the upper surface of the left female bump-side land 12a, and female bumps (31, 32, 33) provided on the upper surface of the right female bump-side land 12 b. On the other hand, with respect to the carrier part 2, the carrier element X is exemplarily shown_ijArranged on the bearing element X_ijA multilayer wiring insulating layer 20 on the lower surface of the multilayer wiring insulating layer 20, a left repair bump side land 19a and a right repair bump side land selectively provided on the lower surface of the multilayer wiring insulating layer 20A land 19b, repair bumps (21, 22, 23) provided on the lower surface of the left repair bump-side land 19a, and a repair bump 41 provided on the lower surface of the right repair bump-side land 19b, the carrier element X being mounted on the carrier element X_ijThe shape of (2) is not limited to the parallel flat plate shape. For example, when the carrier element is a separate element such as an LED chip, the carrier element may have a shell-like structure.

The main board 81 is a parallel flat plate having a board-supporting surface and a base back surface opposite to the board-supporting surface, and is provided with a main board circuit. Carrying element X_ijThe substrate carrying device is a parallel flat plate having a connecting surface and a surface opposite to the connecting surface, and is provided with a device-carrying-side circuit, and the connecting surface faces the substrate carrying surface of the main substrate 81. The female bumps 11 and the female bumps (31, 32, 33) are each rectangular box-shaped having a wall-shaped base-side curved surface perpendicular to the substrate-mounting surface of the main substrate 81. The female bump 11 and the female bumps (31, 32, 33) are such that the bottom surface of the case is in contact with the left female-bump-side land 12a and the right female-bump-side land 12b exposed on the upper surface of the field insulating film 82, respectively, and the left female-bump-side land 12a and the right female-bump-side land 12b are provided on the upper surface of the field insulating film 82. The left female-bump-side land 12a and the right female-bump-side land 12b are electrically connected to the main substrate circuit integrated on the main substrate 81 through contact through holes, not shown, independently.

The repair bumps (21, 22, 23) and the repair bump 41 are each rectangular box-shaped having a wall-shaped repair-side curved surface perpendicular to the connection surface, and the bottom surface (top side in fig. 21) of the box is in contact with the left-side repair-bump-side land 19a and the right-side repair-bump-side land 19b exposed on the lower surface of the multilayer wiring insulating layer 20. The left repair bump land 19a and the right repair bump land 19b are each independently connected to the wiring in the multilayer wiring insulating layer 20 via contact through holes, not shown, and the wiring in the multilayer wiring insulating layer 20 is independently connected to the wiring provided in the carrier element X_ijSo that the repair bumps (21, 22, 23) are independently connected to the carrier-side circuit via the left repair-bump-side land 19a, thereby repairing the carrier-side circuitThe bump 41 is independently connected to the carrier-side circuit via the right repair-bump-side land 19 b. The base-side curved surface of the female bump 11 and the repair-side curved surface of the repair bump (21, 22, 23) intersect at four intersections, and the base-side curved surface of the female bump (31, 32, 33) and the repair-side curved surface of the repair bump 41 intersect at four intersections.

The repair bump (21, 22, 23) shown in fig. 21 has a three-layer structure composed of the box-shaped outermost layer 21, the intermediate layer 22, and the innermost layer 23, and the intermediate layer 22 has a higher hardness than the outermost layer 21 and the innermost layer 23 and the female bump 11. The female bump (31, 32, 33) has a three-layer structure composed of a box-shaped outermost layer 31, an intermediate layer 32, and an innermost layer 33, and the intermediate layer 32 has a hardness higher than the hardness of the outermost layer 31 and the innermost layer 33 and the hardness of the repair bump 41. As the conductors of the female bump 11, the female bumps (31, 32, 33), the repair bumps (21, 22, 23), and the repair bump 41, a combination of a high-hardness conductor and a low-hardness conductor of a metal or an alloy as described in the first embodiment can be used. As shown in fig. 21, the bump connector B on the left side is constituted by the female bump 11 and the repair bumps (21, 22, 23)_uvThe right bump connector B is formed by the female bumps (31, 32, 33) and the repair bump 41_uv。

Bump connector B on the left side shown in FIG. 21_uvIn the method, a material having a hardness higher than that of the metal used for the mother bump 11 is added to the intermediate layer 22 of the repair bump (21, 22, 23), and the pressure applied at the time of bonding causes the other mother bump 11 to bite into and dent, thereby forming solid-phase diffusion bonding. Bump connector B on the right_uvIn the method, a material having a hardness higher than that of the metal used for the repair bump 41 is added to the intermediate layer 32 of the mother bump (31, 32, 33), and the repair bump 41 on the other side is dented by the pressure applied at the time of bonding, thereby forming solid-phase diffusion bonding. That is, the relatively hard intermediate layers 22 and 32 form a deep notch in the mating mother bump 11 or repair bump 41 in the form of a notch to form solid-phase diffusion bonding, and therefore the deformed region is small, but the contact area between the clean surfaces is increased. By adopting the structure of solid phase diffusion bonding based on the dents, the deformation amount of the whole bump is larger than that of the conventional bumpThe bonding type bump having the same hardness is small, but the area of the solid-phase diffusion bonding portion between the clean metals is large. The solid-phase diffusion bonding of the repair bumps (21, 22, 23) and the mother bumps (11) and the solid-phase diffusion bonding of the repair bump (41) and the mother bumps (31, 32, 33) can be performed even at low temperatures. The rest of the steps are the same as those of the stacked semiconductor device according to the first embodiment already described, and therefore, redundant description thereof is omitted. As shown in fig. 21, the laminated semiconductor devices according to the second to fourth embodiments may be configured such that a structure in which a conductor region having high hardness is used for a mother bump on the base 1 side and a structure in which a conductor region having high hardness is used for a repair bump on the carrier member 2 side are mixed.

As a partial structure shown in fig. 22, a structure in which the structure shown in fig. 19B and the structure shown in fig. 20B are mixed in the same bump may be used. The base 1 shown in fig. 22 is composed of a main substrate 81, a field insulating film 82 provided on the upper surface of the main substrate 81, female bump-side lands 12 selectively provided on the upper surface of the field insulating film 82, and hybrid female bumps (31, 32, 33) provided on the upper surfaces of the female bump-side lands 12. On the other hand, the carrier part 2 is formed by a carrier element X_ijArranged on the bearing element X_ijA multilayer wiring insulating layer 20 on the lower surface of the multilayer wiring insulating layer 20, a repair bump side land 19 selectively provided on the lower surface of the multilayer wiring insulating layer 20, and a hybrid type repair bump (21, 22, 23) provided on the lower surface of the repair bump side land 19.

The main board 81 is a parallel flat plate having a board-supporting surface and a base back surface opposite to the board-supporting surface, and is provided with a main board circuit. With respect to the carrier element X_ijThe following structure is exemplarily shown: is a parallel flat plate shape having a connection surface and a surface opposite to the connection surface, and is provided with a carrier-side circuit, and the connection surface faces the substrate-carrying surface of the main substrate 81, but the carrier X_ijThe shape of (2) is not limited to the parallel flat plate shape. For example, when the carrier element is a separate element such as an LED chip, the carrier element may have a shell-like structure. The hybrid female bumps (31, 32, 33) are provided withA rectangular box shape having a wall-shaped base-side curved surface perpendicular to the substrate-receiving surface of the main substrate 81. The hybrid mother bump (31, 32, 33) has a bottom surface of the case in contact with the mother bump-side land 12 exposed on the upper surface of the field insulating film 82, and the mother bump-side land 12 is provided on the upper surface of the field insulating film 82. The female bump-side land 12 is electrically connected to a main substrate circuit integrated on the main substrate 81 via a contact through hole not shown.

The hybrid type repair bumps (21, 22, 23) have a rectangular box shape having a wall-shaped repair side curved surface perpendicular to the connection surface, and the bottom surface (top side in fig. 22) of the box is in contact with the repair bump side land 19 exposed on the lower surface of the multilayer wiring insulating layer 20. The repair bump land 19 is connected to the wiring in the multilayer wiring insulating layer 20 via a contact via hole not shown, and the wiring in the multilayer wiring insulating layer 20 is connected to the carrier element X_ijThe hybrid type repair bumps (21, 22, 23) are connected to the carrier-side circuit via the repair-bump-side lands 19. The repair-side curved surfaces of the hybrid-type repair bumps (21, 22, 23) and the base-side curved surfaces of the hybrid-type mother bumps (31, 32, 33) intersect at four intersections.

The hybrid repair bump (21, 22, 23) shown in fig. 22 has a three-layer structure composed of the outermost layer 21, the intermediate layer 22, and the innermost layer 23 on the left side, but has a two-layer structure without the intermediate layer 22 on the right side. The right side of the hybrid mother bump (31, 32, 33) has a three-layer structure composed of an outermost layer 31, an intermediate layer 32, and an innermost layer 33, while the left side has a two-layer structure without the intermediate layer 32. The intermediate layer 22 of the hybrid type repair bump (21, 22, 23) has a higher hardness than the outermost layer 21 and the innermost layer 23 and the outermost layer 31 and the innermost layer 33 of the hybrid type mother bump (31, 32, 33). The intermediate layer 32 of the hybrid type female bump (31, 32, 33) has a hardness higher than the hardness of the outermost layer 31 and the innermost layer 33 and the hardness of the outermost layer 21 and the innermost layer 23 of the hybrid type repair bump (21, 22, 23). As the conductors of the hybrid mother bumps (31, 32, 33) and the hybrid repair bumps (21, 22, 23), a combination of a high-hardness conductor and a low-hardness conductor of a metal or an alloy as described in the first embodiment can be used.

In the left area shown in fig. 22, a material having a hardness higher than that of the metal used on the left side of the opposing hybrid mother bumps (31, 32, 33) is added to the intermediate layer 22 of the hybrid type repair bump (21, 22, 23), and the indentation is formed by biting into the left side of the hybrid type mother bumps (31, 32, 33) by the pressure applied at the time of bonding, thereby forming solid phase diffusion bonding. In the right area shown in fig. 22, a material having a hardness higher than that of the metal used on the right side of the opposing hybrid type repair bump (21, 22, 23) is added to the intermediate layer 32 of the hybrid type mother bump (31, 32, 33), and the indentation is formed by biting into the opposing hybrid type repair bump (21, 22, 23) by the pressure applied at the time of bonding, thereby forming solid phase diffusion bonding. That is, the relatively hard intermediate layers 22 and 32 form solid-phase diffusion bonding by cutting deep dents in the shape of a knife-edge in the regions where the hardness of the hybrid mother bumps (31, 32, 33) or hybrid repair bumps (21, 22, 23) of the opposite side is relatively low, and therefore the deformed region is small but the contact area between the clean surfaces is increased.

By adopting the structure of solid-phase diffusion bonding by dimples, the deformation amount of the entire bump is smaller than that of a conventional equivalent-hardness bonding type bump, but the area of the solid-phase diffusion bonding portion between clean metals is increased. The hybrid type repair bumps (21, 22, 23) and the hybrid type mother bumps (31, 32, 33) can be bonded by solid phase diffusion even at low temperatures. The rest of the steps are the same as those of the stacked semiconductor device according to the first embodiment already described, and therefore, redundant description is omitted. As for the laminated semiconductor devices according to the second to fourth embodiments, as long as a structure other than the structures shown in fig. 13 and 16, that is, as long as two or more structures are generated at the intersection of the repair bump and the mother bump, a structure in which a conductor region having high hardness is applied to the mother bump on the substrate 1 side and a structure in which a conductor region having high hardness is applied to the repair bump on the carrier member 2 side as shown in fig. 22 may be mixed in the same bump.

The laminated semiconductor device according to the first to fourth embodiments of the present invention has been explained mainly by way of example as follows: of large diameterThe main substrate 81 is a detector substrate in which detection elements such as photodiodes are arranged in a matrix form as pixels, and carries the elements X_ijThe semiconductor integrated circuit chip is a semiconductor integrated circuit chip in which a circuit on the side of a readout circuit carrier element (readout chip) for reading out signals from each pixel is integrated, but the stacked semiconductor device of the present invention is not limited to a solid-state imaging device or a micro LED display. For example, the main board 81 may be used as a main memory such as DRAM or SRAM, and the support element X having the ALU integrated therein may be supported on the main memory_ijThus, a stacked semiconductor device is formed. If a load cell X integrating ALU and the like is loaded in a divided area of the main memory_ijThen the carrying element X can be realized_ijA parallel computer performs parallel processing and pipeline processing on signals of each divided block from a main memory. The degree of integration of semiconductor integrated circuits has continued to increase with the advancement of microfabrication technology, which is also considered to have reached the limit. Considering the limit of the microfabrication technology, the main substrate 81 may be used as an interposer (interposer), and a plurality of IC chips each having a repair bump may be mounted on the interposer as the mounting device X_ijAnd a 2.5-dimensional integrated circuit and a 3-dimensional integrated circuit are formed. The interposer includes a silicon substrate, a surface insulating film such as a silicon oxide film provided on a surface of the silicon substrate, and a back insulating film such as a silicon oxide film provided on a back surface of the silicon substrate so as to be laminated on a lower substrate such as a package substrate (resin substrate) as an intermediate substrate. Mother bumps are arranged on the upper surface of the surface insulating film of the interposer in consideration of the size of the IC chip and the arrangement of the repair bumps. A rear surface wiring connected to the substrate of the lower layer is provided on the lower surface of the rear surface insulating film of the interposer. The back-side wiring is electrically connected to the mother bump on the upper surface side of the interposer through a through-silicon via (TSV) penetrating the surface insulating film, the silicon substrate, and the back-side insulating film, and thus a multilayer laminated structure as a 2.5-dimensional integrated circuit or a 3-dimensional integrated circuit can be easily realized.

As described above, the technical contents described in the first to fourth embodiments are merely examples, and the present invention can be applied to any configurations to which the respective configurations of the first to fourth embodiments are applied. Accordingly, the present invention naturally includes various first to fourth embodiments and the like which are not described in the stacked semiconductor devices according to the first to fourth embodiments. Therefore, the technical scope of the present invention is limited only by the specific matters of the invention according to the claims as long as the technical matters can be properly explained from the above description.