阅读说明：本技术 像素阵列和其形成方法 (Pixel array and forming method thereof ) 是由 黄琮伟 张朝钦 郑允玮 郑智龙 陈言彰 蔡文仁 林政翰 池昱勳 李昇展 陈昇照 于 2021-03-03 设计创作，主要内容包括：本公开提供一种像素阵列和其形成方法,像素阵列包括第一像素区域、第二像素区域,以及在第一像素区域与第二像素区域之间的深沟槽隔离结构,其中深沟槽隔离结构以氧化物材料填充,形成在氧化物材料中的气隙包括深沟槽隔离结构中至少75％的面积。(The present disclosure provides a pixel array and method of forming the same, the pixel array including a first pixel region, a second pixel region, and a deep trench isolation structure between the first pixel region and the second pixel region, wherein the deep trench isolation structure is filled with an oxide material, and an air gap formed in the oxide material includes at least 75% of an area in the deep trench isolation structure.)

1. An array of pixels, comprising:

a first pixel region;

a second pixel region; and

a deep trench isolation structure between the first pixel region and the second pixel region, the deep trench isolation structure being filled with an oxide material,

wherein a gas gap formed in the oxide material comprises at least 75% of an area in the deep trench isolation structure.

2. The pixel array of claim 1, wherein the air gap is formed to reduce optical crosstalk between the first pixel region and the second pixel region.

3. The pixel array of claim 1, further comprising:

a high absorption region in the first pixel region; and

an additional air gap is formed in the high absorption region.

4. A method of forming a pixel array, comprising:

forming a photodiode in a substrate of a pixel region of a pixel array;

forming a first deep trench isolation structure on a first side of the photodiode;

forming a second deep trench isolation structure on a second side (opposite side) of the photodiode;

depositing an oxide material in the first deep trench isolation structure such that a first air gap is formed in at least 75% of an area of the first deep trench isolation structure; and

depositing the oxide material in the second deep trench isolation structure such that a second air gap is formed in at least 75% of an area of the second deep trench isolation structure.

5. The method of claim 4, further comprising:

forming an anti-reflective coating over the first deep trench isolation structure, over the second deep trench isolation structure, and over the photodiode;

forming a color filter layer over the anti-reflective coating; and

a microlens is formed over the color filter layer.

6. The method of claim 4, wherein depositing the oxide material in the first deep trench isolation structure comprises:

depositing the oxide material in the first deep trench isolation structure at a deposition rate such that the oxide material fills a top region of the first deep trench isolation structure before the oxide material fills a central region of the first deep trench isolation structure, thereby forming the first air gap.

7. An array of pixels, comprising:

a first pixel region;

a second pixel region;

a deep trench isolation structure between the first pixel region and the second pixel region, the deep trench isolation structure being filled with a first air gap;

a first microlens formed in the first pixel region;

a second microlens formed in the second pixel region,

wherein a second air gap exists between the first microlens and the second microlens;

a plurality of high absorption regions in the first pixel region; and

a respective third air gap is formed in each of the plurality of super-absorbing regions.

8. The pixel array of claim 7, further comprising:

a third pixel region; and

an additional deep trench isolation structure between the first pixel region and the third pixel region, the additional deep trench isolation structure filled with the oxide material and having a fourth air gap formed therein.

9. The array of claim 7, wherein no more than 25% of an area of the deep trench isolation structure is filled with an oxide material, and

wherein at least 75% of the area of the deep trench isolation structure is filled with the first air gap formed by the oxide material in the deep trench isolation structure.

10. The pixel array of claim 7, wherein a height of each of the first and second air gaps is in a range of 1.5 to 10 microns, and

wherein a width of each of the first and second air gaps is in a range of 0.7 to 1.3 microns.

Technical Field

The present disclosure relates to pixel arrays and methods of forming the same, and more particularly to pixel arrays including isolation structures.

Background

Digital cameras and other optical imaging devices employ image sensors. The image sensor converts the optical image into digital data that can be displayed as a digital image. An image sensor, such as a Complementary Metal Oxide Semiconductor (CMOS) image sensor, includes an array of pixel regions and supporting logic elements. The pixel areas in the array are semiconductor devices used to measure incident light (i.e., light directed to the pixel areas), and supporting logic elements facilitate readout of the measurement values. One type of image sensor commonly used in optical imaging devices is a Back Side Illumination (BSI) CMOS image sensor. The BSI CMOS image sensor process can be integrated into a semiconductor process to achieve low cost, small size and high integration. In addition, the BSI CMOS image sensor has low operating voltage, low power consumption, high quantum efficiency, and low readout noise, and allows random access.

Disclosure of Invention

Embodiments in accordance with the present disclosure provide a pixel array including a first pixel region, a second pixel region, and a deep trench isolation structure between the first pixel region and the second pixel region, wherein the deep trench isolation structure is filled with an oxide material, and an air gap formed in the oxide material comprises at least 75% of an area in the deep trench isolation structure.

A method of forming a pixel array is provided according to an embodiment of the present disclosure, including forming a photodiode in a substrate of a pixel region of the pixel array, forming a first deep trench isolation structure on a first side of the photodiode, forming a second deep trench isolation structure on a second side (opposite side) of the photodiode, depositing an oxide material in the first deep trench isolation structure such that a first air gap is formed in at least 75% of an area of the first deep trench isolation structure, and depositing an oxide material in the second deep trench isolation structure such that a second air gap is formed in at least 75% of an area of the second deep trench isolation structure.

There is provided in accordance with an embodiment of the present disclosure a pixel array including a first pixel region, a second pixel region, a deep trench isolation structure between the first pixel region and the second pixel region and filled with a first air gap, a first microlens formed in the first pixel region, a second microlens formed in the second pixel region, a plurality of super-absorbing regions in the first pixel region, and a corresponding third air gap formed in each of the super-absorbing regions, wherein the second air gap exists between the first microlens and the second microlens.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features are not drawn to scale according to standard methods in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic illustration of an example environment in which systems and/or methods described herein may be implemented;

fig. 2A-2D are schematic diagrams of example pixel arrays described herein;

3A-3J are schematic diagrams of examples of forming the pixel arrays of FIGS. 2A-2D described herein;

FIG. 4 is a schematic diagram of another example pixel array described herein;

fig. 5A-5D are schematic diagrams of examples of forming the pixel array of fig. 4 described herein;

FIG. 6 is a schematic diagram of exemplary components of one or more of the devices of FIG. 1;

FIG. 7 is an exemplary process flow diagram for forming a portion of a pixel array.

[ notation ] to show

100 environment (environment)

102 deposition tool

104 exposure tool

106 developing tool

108 etching tool

110 flattening tool

112 implantation tool

114 wafer/die transfer tool

200 pixel array

202 pixel area

202a pixel region

202b pixel area

202c pixel area

202d pixel area

202e pixel area

204 base plate

206 photodiode

208 oxide layer

210 anti-reflective coating

212 color Filter layer

212a color filter region

212b color filter region

212c color filter region

214 microlens layer

214a microlens

214b microlenses

214c micro lens

216 deep trench isolation structure

218 high absorption region

220 air gap

222 air gap

224 close-up view

226 close-up view

300 example

302 top part

304 central part

306 top part

308 central part

400 pixel array

402 pixel region

402a pixel region

402b pixel region

402c pixel region

404 base plate

406 photodiode

408 oxide layer

410 anti-reflective coating

412 color filter layer

412a color filter region

412b color filter region

412c color filter area

414 microlens layer

414a microlens

414b microlens

414c microlens

416 deep trench isolation structure

418 high absorption region

420 air gap

422 air gap

424 micro lens structure

426 dielectric film

428 passivation film

430 air gap

600 device

610 bus

620, processor

630 memory

640 storage component

650 input unit

660 output component

670 communication parts

700, process of preparation

710 a square

720 is a square

730 the square

740 square block

750 square

A-A is a wire

B-B: line

m, x is width

n, y: height

Detailed Description

To achieve the various features of the subject matter referred to, the following disclosure provides many different embodiments, or examples. Specific examples of components, configurations, etc., are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as shown. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Optical crosstalk (optical crosstalk) may occur between adjacent pixel regions in a pixel array, such as a Back Side Illumination (BSI) Complementary Metal Oxide Semiconductor (CMOS) image sensor and/or another type of CMOS image sensor. Optical crosstalk is a phenomenon in which incident light passes through a pixel region at a non-orthogonal angle, and at least part of the incident light is absorbed by a photodiode of an adjacent pixel region. Optical crosstalk in a pixel array of a CMOS image sensor may reduce the spatial resolution of the CMOS image sensor, may reduce the overall sensitivity of the CMOS image sensor, may cause color mixing (color mixing) between pixel areas of the CMOS image sensor, and/or may cause image noise after color correction.

Some implementations described herein provide an isolation structure that can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-point pixel regions) of an image sensor to reduce and/or prevent optical crosstalk. The isolation structure may comprise a Deep Trench Isolation (DTI) structure, or another type of trench having a partial fill material such that an air gap is formed therein. Air has the lowest refractive index of all materials and is closest to the refractive index of a vacuum. Air has a low index of refraction that reduces the critical angle (critical angle) for total internal reflection at the boundary between the material and the air gap in the deep trench isolation structure relative to the index of refraction of the material in the deep trench isolation structure, which may comprise oxide or another type of material. Incident light traveling toward the boundary between the material and the air gap at an angle equal to or greater than the critical angle will likely be totally reflected from the boundary between the material and the air gap. Thus, a lower critical angle increases the likelihood that incident light will undergo total internal reflection within the deep trench isolation structure, which will result in incident light being reflected from the boundary of the material and air gap and absorbed by the associated pixel region, rather than (or in addition to) having the incident light pass through the deep trench isolation structure and be absorbed by an adjacent (or non-adjacent) pixel region. Accordingly, the deep trench isolation structure formed with the air gap may reduce optical crosstalk between pixel regions. Reducing optical crosstalk may increase the spatial resolution of the image sensor, may increase the overall sensitivity of the image sensor, may reduce color mixing between pixel areas of the image sensor, and/or may reduce image noise after color correction of images captured using the image sensor.

FIG. 1 is a schematic diagram of an example environment 100 in which systems and/or methods described herein may be implemented. As shown in fig. 1, the environment 100 may include a plurality of semiconductor processing tools (deposition tool 102 through implantation tool 112) and a wafer/die transport tool 114. The plurality of semiconductor processing tools (deposition tool 102 through implantation tool 112) may include a deposition tool 102, an exposure tool 104, a development tool 106, an etch tool 108, a planarization tool 110, an implantation tool 112, and/or another type of semiconductor processing tool. Such tools included in the example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing and/or manufacturing facility, and/or the like.

The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 comprises a spin-on tool capable of depositing a photoresist layer on a substrate (such as a wafer). In some embodiments, the deposition tool 102 comprises a Chemical Vapor Deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 comprises a Physical Vapor Deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the example environment 100 includes multiple types of deposition tools 102.

The exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an Ultraviolet (UV) light source (e.g., a deep UV light source, an extreme UV light source, and/or the like), an x-ray light source, and/or the like). The exposure tool 104 may expose the photoresist layer to a radiation source to transfer a pattern from the mask to the photoresist layer. Such a pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include a pattern for forming one or more structures of a semiconductor device, may include a pattern for etching various portions of a semiconductor device, and/or the like. In some embodiments, the exposure tool 104 comprises a scanner, stepper (stepper), or similar type of exposure tool.

The etching tool 108 is a semiconductor processing tool that is capable of etching various types of materials of substrates, wafers, or semiconductor devices. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and/or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a particular time period to remove a particular amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may etch one or more portions of the substrate using plasma etching or plasma-assisted etching, which may involve isotropic or directional etching of the one or more portions of the substrate using a free gas.

The development tool 106 is a semiconductor processing tool that is capable of developing the photoresist layer that has been exposed to the radiation source, developing the pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developer tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by dissolving the exposed or unexposed portions of the photoresist layer using a chemical developer.

The planarization tool 110 is a semiconductor processing tool that is capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, the polishing apparatus may include a Chemical Mechanical Polishing (CMP) apparatus and/or another type of polishing apparatus. In some embodiments, the polishing apparatus can polish or planarize a deposited or electroplated material layer.

The wafer/die transport tool 114 may include a mobile robot, trolley or rail car and/or another type of device for transporting wafers and/or dies between semiconductor processing tools (deposition tool 102 to implantation tool 112) and/or to and from other locations, such as wafer shelves, storage chambers, and/or the like. In some embodiments, wafer/die transport 114 may be a programmed device that travels on a particular path and/or may operate semi-autonomously or autonomously.

The number and arrangement of the devices shown in fig. 1 are provided as one or more examples. In practice, there may be additional devices, fewer devices, different devices, or devices in a different configuration than shown in FIG. 1. In addition, two or more of the devices shown in fig. 1 may be implemented within a single device, or a single device shown in fig. 1 may be implemented as multiple, decentralized devices. Additionally or alternatively, a set of devices (e.g., one or more devices) of environment 100 may perform one or more functions described above as being performed by another set of devices of environment 100.

Fig. 2A-2D are schematic diagrams of an example pixel array 200 (or a portion thereof) described herein. The pixel array 200 may be included in an image sensor, such as a CMOS image sensor or another type of image sensor. Fig. 2A shows a top view of the pixel array 200. As shown in fig. 2A, the pixel array 200 may include a plurality of pixel regions 202. As further shown in fig. 2A, the pixel regions 202 may be square or rectangular and may be arranged in a grid. In some embodiments, pixel region 202 may include other shapes, such as a circle, an octagon, a diamond, and/or other shapes.

The pixel array 200 may be electrically connected to a back-end-of-line (BEOL) metallization stack (not shown) of the image sensor. The BEOL metallization stack may electrically connect the pixel array 200 to control circuitry that may be used to measure incident light accumulated in the pixel area 202 and convert the measured values into electrical signals.

Fig. 2B illustrates a cross-sectional view of a portion of the pixel array 200 along line a-a in fig. 2A. The portion of the pixel array 200 depicted in fig. 2B may include a plurality of adjacent pixel regions 202, such as pixel region 202a, pixel region 202B, and pixel region 202 c. As shown in fig. 2B, each of the pixel regions 202 may be formed in a substrate 204, which substrate 204 may comprise a semiconductor die substrate, a semiconductor wafer, or another type of substrate in which semiconductor pixels may be formed. In some embodiments, the substrate 204 is formed of silicon, a material comprising silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), a Silicon On Insulator (SOI), or another type of semiconductor material capable of generating a charge from photons of incident light.

Each pixel region 202 may include a photodiode 206. The photodiode 206 may include a region of the substrate 204 that is doped with various types of ions to form a p-n junction or PIN junction (e.g., a p-type portion, an intrinsic (intrinsic), or a junction between an undoped type portion and an n-type portion). For example, the substrate 204 may be doped with an n-type dopant to form a first portion (e.g., n-type portion) of the photodiode 206 and a p-type dopant to form a second portion (e.g., p-type portion) of the photodiode 206. The photodiode 206 may be configured to absorb photons of incident light. Absorption of the photons causes the photodiode 206 to accumulate charge due to the photoelectric effect (referred to as photocurrent). The photons strike the photodiode 206, causing electron emission from the photodiode 206. The emission of electrons results in the formation of electron-hole pairs, where electrons migrate toward the cathode and holes migrate toward the anode of the photodiode 206, which produces a photocurrent.

The pixel array 200 can include an oxide layer 208 over and/or on the substrate 204 and the photodiode 206. The oxide layer 208 may serve as a passivation layer between the photodiode 206 and upper layers of the pixel array 200. In some embodiments, oxide layer 208 includes an oxide material, such as silicon oxide (SiOx). In some embodiments, silicon nitride (SiNx), silicon carbide (SiCx), or a mixture thereof, such as silicon carbonitride (SiCN), silicon oxynitride (SiON), or another dielectric material, is used as a passivation layer in place of the oxide layer 208.

The pixel array 200 can include an anti-reflective coating 210 over and/or on the oxide layer 208. The anti-reflective coating 210 may comprise a suitable material for reducing reflection of incident light projected toward the photodiode 206. For example, the anti-reflective coating 210 may include a nitrogen-containing material. In some embodiments, the semiconductor processing tool (e.g., deposition tool 102) may form the anti-reflective coating 210 to a thickness in the range of about 200 angstroms to about 1000 angstroms.

The pixel array 200 can include a color filter layer 212 over and/or on the anti-reflective coating 210. The color filter layer 212 may comprise an array of color filter regions, wherein each color filter region filters incident light to allow incident light of a particular wavelength to pass through the photodiode 206 of the associated pixel region 202. For example, the color filter region 212a can filter incident light of the pixel region 202a, the color filter region 212b can filter incident light of the pixel region 202b, the color filter region 212b can filter incident light of the pixel region 202c, and so on. For example, the color filter region may be a blue color filter region that permits portions of incident light near 450 nanometers wavelengths to pass through color filter layer 212 and blocks other wavelengths from passing through. Another color filter region may be a green filter region that permits portions of incident light near 550 nanometers wavelengths to pass through color filter layer 212 and blocks other wavelengths from passing through. Another color filter region may be a red color filter region that permits portions of incident light near 650 nanometers wavelengths to pass through color filter layer 212 and blocks other wavelengths from passing through.

In some embodiments, the color filter layer 212 of one or more pixel regions 202 in the pixel array 200 is omitted. For example, the color filter layer 212 may be omitted from the white pixel region 202 to admit all wavelengths of light into the associated photodiode 206 (e.g., to determine overall brightness to increase the light sensitivity of the image sensor). As another example, the color filter layer 212 may be omitted from the Near Infrared (NIR) pixel region 202 to admit near infrared light into the associated photodiode 206.

The pixel array 200 can include a microlens layer 214 over and/or on the color filter layer 212. The microlens layer 214 may include a microlens for each of the pixel regions 202. For example, the microlens 214a can be formed to focus incident light toward the photodiode 206 of the pixel region 202a, the microlens 214b can be formed to focus incident light toward the photodiode 206 of the pixel region 202b, the microlens 214c can be formed to focus incident light toward the photodiode 206 of the pixel region 202c, and so on.

In some embodiments, the image sensor is a BSI CMOS image sensor. In such examples, oxide layer 208, anti-reflective coating 210, color filter layer 212, and microlens layer 214 may be formed on the backside of substrate 204. In addition, one or more deep trench isolation structures 216 may be formed in the backside of the substrate 204 to provide optical isolation between the pixel regions 202, and thus may be referred to as Backside Deep Trench Isolation (BDTI). The deep trench isolation structures 216 may be trenches (e.g., deep trenches) that are partially filled with a material (e.g., an oxide material such as silicon oxide (SiOx) or another dielectric material) and provide optical isolation between the pixel regions 202. The deep trench isolation structures 216 may be formed in a grid layout, wherein the deep trench isolation structures 216 extend laterally across the image sensor and intersect at various locations of the image sensor.

One or more highly absorbing regions 218 may be formed in each of the photodiodes 206 to increase the absorption of incident light by the photodiode 206. The high absorption region 218 may comprise a shallow v-shaped (or another cross-sectional shape) trench formed in the associated photodiode 206. In some embodiments, a plurality of high absorption regions 218 may be formed in the photodiode 206. In such examples, the plurality of high absorption regions 218 may be arranged in a periodic, zig-zag, or zig-zag structure. In some embodiments, the high absorption regions 218 have a pitch or width in the range of about 0.01 microns to about 8 microns. In some embodiments, the high absorption region 218 has a height in the range of about 2 microns to about 20 microns. In some embodiments, the high absorption area 218 may be conical, pyramidal, or another three-dimensional shape.

In some embodiments, a highly absorbing layer may be formed in the deep trench isolation structures 216 and in the highly absorbing regions 218 to increase the absorption of incident light. The high absorption layer may be formed of a semiconductor material having a low band gap. For example, the low bandgap may be an energy bandgap of less than about 1 electron volt (eV). In addition, the low bandgap may be a bandgap that is less than the bandgap of the substrate 204. For example, the high absorption layer may comprise silicon germanium or single crystal silicon doped with a chalcogen (e.g., sulfur, selenium, or tellurium).

The one or more deep trench isolation structures 216 may each include an air gap 220 to increase optical isolation between the photodiodes 206 and to reduce optical crosstalk between the photodiodes 206. Similarly, each of the one or more highly absorbing regions 218 may include air gaps 222 to increase optical isolation between the photodiodes 206 and reduce optical crosstalk between the photodiodes 206. Air has the lowest refractive index of all materials and is closest to the refractive index of a vacuum. The air has a low index of refraction that reduces the critical angle for total internal reflection at the boundary between the material in the deep trench isolation structure 216 and the air gap 220 relative to the index of refraction of the material in the deep trench isolation structure 216 (which may comprise oxide or another type of material). Therefore, as shown in fig. 2B, incident light traveling toward the boundary between the material and the air gap 220 at an angle equal to or greater than the critical angle will likely be totally reflected from the material-air gap boundary. Thus, a lower critical angle increases the likelihood of total internal reflection of incident light within the deep trench isolation structure 216, which would result in incident light being reflected from the material-air gap boundary and absorbed by the associated pixel region 202 (e.g., pixel region 202b), rather than (or in addition to) having the incident light travel through the deep trench isolation structure 216 and be absorbed by an adjacent (or non-adjacent) pixel region 202 (e.g., pixel region 202 a).

Similarly, the low refractive index of air relative to the refractive index of the material in the high absorption region 218 (which may comprise an oxide or another type of material) reduces the critical angle for total internal reflection at the boundary between the material in the high absorption region 218 and the air gap 222. Thus, as shown in FIG. 2B, incident light traveling toward the boundary between the material and the air gap 222 at an angle equal to or greater than the critical angle will likely be totally reflected from the material-air gap boundary. Thus, a lower critical angle increases the likelihood of total internal reflection of incident light in the highly absorbing region 218, which would result in incident light being reflected from the material-air gap boundary and absorbed by the associated pixel region 202 (e.g., pixel region 202b), rather than (or in addition to) having the incident light travel through the highly absorbing region 218 and be absorbed by an adjacent (or non-adjacent) pixel region 202 (e.g., pixel region 202 c).

In addition, as the physical size of image sensors continues to shrink, the size of the deep trench isolation structures 216 included therein continues to decrease. If the deep trench isolation structure 216 is completely filled with the oxide material (e.g., to at least 95% of the area in the deep trench isolation structure 216), the reduction in the size of the deep trench isolation structure 216 may result in cracking and/or damage to the deep trench isolation structure 216. Incorporating the air gap 220 into the deep trench isolation structure 216 may reduce stress on the deep trench isolation structure 216, which reduces the likelihood of cracking and/or damage caused by continued shrinking of the dimensions of the deep trench isolation structure 216.

Fig. 2C shows a cross-sectional view of a portion of the pixel array 200 along line B-B in fig. 2A. The portion of the pixel array 200 depicted in fig. 2C may include a plurality of non-adjacent pixel regions 202, such as pixel region 202d, pixel region 202b, and pixel region 202 e. As shown in fig. 2C, pixel region 202d, pixel region 202B, and pixel region 202e may include a structure configured similar to that shown in fig. 2B. However, the pixel regions 202d, 202b, and 202e may be diagonally arranged, in which case the size of the deep trench isolation structures 216 (and the air gaps 220 formed therein) between the pixel regions 202d, 202b, and 202e may be slightly larger than the deep trench isolation structures 216 (and the air gaps 220 formed therein) between the pixel regions 202a, 202b, and 202 c.

Fig. 2D shows a close-up view 224 of the example deep trench isolation structure 216 and a close-up view 226 of the example high absorption region 218 from fig. 2B. As shown in the close-up view 224 of the example deep trench isolation structure 216, the air gap 220 in the deep trench isolation structure 216 can be formed such that a width x of the air gap 220 is in a range of approximately 0.7 microns to approximately 1.3 microns. Further, the air gap 220 can be formed in the deep trench isolation structure 216 such that a height y of the air gap 220 is in a range of approximately 1.5 microns to approximately 10 microns. In some embodiments, the air gap 220 is formed to occupy at least 75% of the area in the deep trench isolation structure 216 such that the material (e.g., oxide material) in the deep trench isolation structure 216 occupies 25% or less of the area in the deep trench isolation structure 216. Forming the air gaps 220 to occupy at least 75% of the area in the deep trench isolation structures 216 reduces and/or minimizes cross-talk (including optical cross-talk and electrical cross-talk) between adjacent (or non-adjacent) pixel regions. For example, forming the air gaps 220 to occupy at least 75% of the area in the deep trench isolation structures 216 between the pixel regions 202a and 202b reduces and/or minimizes cross-talk (including optical and electrical cross-talk) between the pixel regions 202a and 202 b.

As shown in the close-up view 226 of the example high absorption region 218, the air gaps 222 in the high absorption region 218 may be formed such that the width m of the air gaps 222 is in a range of about 1500 angstroms to about 4000 angstroms. Further, the air gaps 222 in the high absorption region 218 may be formed such that the height n of the air gaps 222 is in a range of about 2000 angstroms to about 4000 angstroms. In some embodiments, the air gaps 222 are formed to occupy at least 75% of the area in the highly absorbing region 218, such that the material (e.g., oxide material) in the highly absorbing region 218 occupies 25% or less of the area in the highly absorbing region 218.

The number and arrangement of components, structures, and/or layers shown in fig. 2A-2D are provided as one or more examples. In practice, there may be additional components, structures, and/or layers, fewer components, structures, and/or layers, different components, structures, and/or layers, and/or different arrangements of components, structures, and/or layers than shown in fig. 2A-2D.

Fig. 3A-3J are schematic diagrams of an example 300 of forming the pixel array 200 of fig. 2A-2D described herein. In particular, fig. 3A-3J illustrate cross-sectional views of an example 300 of forming the pixel array 200. Pixel array 200 may be formed as part of an image sensor (e.g., CMOS image sensor) manufacturing process. As shown in fig. 3A, the pixel array 200 may be formed in a substrate 204. As described above, the substrate 204 may be a semiconductor die (or portion thereof), a semiconductor wafer (or portion thereof), or another type of substrate in which a pixel array may be formed.

As shown in fig. 3B, a plurality of pixel regions 202 of the pixel array 200 may be formed in a substrate 204. For example, the pixel region 202a may be formed by doping a portion of the substrate 204, the pixel region 202b may be formed by doping another portion of the substrate 204, the pixel region 202c may be formed by doping another portion of the substrate 204, and so on. Some pixel regions 202 may be neighboring pixel regions (e.g., pixel regions that are adjacent to each other and/or share a side), and some pixel regions 202 may be non-neighboring pixel regions (e.g., pixel regions that diagonally intersect each other).

In some embodiments, portions of the substrate 204 are doped with a semiconductor processing tool, such as the implantation tool 112, using ion implantation techniques to form photodiodes 206 in each of the pixel regions 202. In such examples, the semiconductor processing tool may generate ions from a source material, such as a gas or solid, in the arc chamber. A source material may be placed in the arc chamber and an arc voltage is discharged between the cathode and the electrode to generate a plasma containing ions of the source material. One or more extraction electrodes may be used to extract and accelerate ions from the plasma in the arc chamber to form an ion beam. In some embodiments, other techniques and/or types of ion implantation tools are used to form the ion beam. An ion beam may be directed at the pixel regions 202 to implant ions in the substrate 204, thereby doping the substrate 204 to form photodiodes 206 in each of the pixel regions 202.

The substrate 204 may be doped with various types of ions to form the p-n junction of each photodiode 206. For example, the substrate 204 may be doped with an n-type dopant to form a first portion (e.g., n-type portion) of the photodiode 206 and a p-type dopant to form a second portion (e.g., p-type portion) of the photodiode 206.

As shown in fig. 3C, one or more deep trench isolation structures 216 may be formed in the substrate 204. In particular, deep trench isolation structures 216 may be formed between individual photodiodes 206 of the pixel region 202. As an example, the deep trench isolation structure 216 can be formed between the photodiodes 206 of the pixel regions 202a and 202b, the deep trench isolation structure 216 can be formed between the photodiodes 206 of the pixel regions 202b and 202b, and so on. In some embodiments, if the pixel array 200 is a BSI pixel array, the deep trench isolation structure 216 can be a backside deep trench isolation structure formed in the backside of the substrate 204.

In some embodiments, one or more semiconductor processing tools may be used to form one or more deep trench isolation structures 216 in the substrate 204. For example, the deposition tool 102 may form a photoresist layer on the substrate 204, the exposure tool 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, the development tool 106 may develop and remove portions of the photoresist layer to expose the pattern, and the etch tool 108 may etch one or more portions of the substrate 204 to form one or more deep trench isolation structures 216 in the substrate 204. In some embodiments, after the etch tool 108 etches the substrate 204, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using chemical stripping and/or another technique).

As further shown in fig. 3C, one or more high absorption regions 218 may be formed in the substrate 204 and/or the individual photodiodes 206. Each high absorption region 218 may be defined by a shallow trench. A plurality of adjacent high absorption regions 218 may form a periodic or zigzag structure that is etched or otherwise formed in the substrate 204 and/or the photodiode 206. The one or more high absorption regions 218 may be formed on the same side of the substrate 204 as the one or more deep trench isolation structures 216, and may be formed using related techniques and/or semiconductor processes similar to those described above for forming the one or more deep trench isolation structures 216.

As shown in fig. 3D-3E, the one or more deep trench isolation structures 216 and the one or more highly absorbing regions 218 may each be partially filled with a material such that an air gap 220 is formed in each of the one or more deep trench isolation structures 216 and an air gap 222 is formed in each of the one or more highly absorbing regions 218. Specifically, a semiconductor processing tool, such as the deposition tool 102, may deposit an oxide material, such as silicon oxide (SiOx) or another type of oxide, in each of the one or more deep trench isolation structures 216 at a deposition rate such that the oxide material fills the top portions 302 of the one or more deep trench isolation structures 216 before the oxide material can fill the central portions 304 of the one or more deep trench isolation structures 216. This results in an unfilled void being formed in each of the one or more deep trench isolation structures 216, forming an air gap 220. In a similar manner, the semiconductor processing tool may deposit the oxide material in each of the one or more highly absorbing regions 218 at a deposition rate such that the oxide material fills the top portions 306 of the one or more highly absorbing regions 218 before the oxide material may fill the central portions 308 of the one or more highly absorbing regions 218. In some embodiments, the deposition rate can be selected such that the air gaps 220 occupy at least 75% of the area in the deep trench isolation structures 216 (in which case the oxide material occupies 25% or less of the area in the deep trench isolation structures 216) and/or such that the air gaps 222 occupy at least 75% of the area in the high absorption regions 218 (in which case the oxide material occupies 25% or less of the area in the high absorption regions 218). In some embodiments, deposition rates in a range from approximately 2 angstroms per second (A/S) to approximately 300A/S may be used. In addition, various CVD and/or Atomic Layer Deposition (ALD) techniques, such as PECVD, HDP-CVD, SACVD, or PEALD, may be used to deposit the oxide material.

As shown in fig. 3F, a semiconductor processing tool, such as deposition tool 102, may further deposit an oxide material on substrate 204 and one or more photodiodes 206 to form an oxide layer 208. As described above, the oxide layer 208 may function as a passivation layer. In some embodiments, silicon nitride (SiNx), silicon carbide (SiCx), or a mixture thereof, such as silicon carbonitride (SiCN), silicon oxynitride (SiON), or another dielectric material, may be used as a passivation layer in place of the oxide layer 208.

As shown in fig. 3G, a semiconductor processing tool (e.g., the planarization tool 110) may polish or planarize the oxide layer 208 to flatten the oxide layer 208 in preparation for depositing additional layers and/or structures on the oxide layer 208. Oxide layer 208 may be planarized using a polishing or planarization technique, such as CMP. The CMP process may include depositing a slurry (or polishing compound) onto the polishing pad. The semiconductor die or wafer forming the pixel array 200 may be mounted to a carrier that rotates the semiconductor die or wafer while pressing against a polishing pad. The slurry and polishing pad act as an abrasive that grinds or planarizes the oxide layer 208 as the semiconductor die or wafer is rotated. The polishing pad may also be rotated to ensure a continuous supply of slurry is applied to the polishing pad.

As shown in fig. 3H, an antireflective coating 210 can be formed over the oxide layer 208 and/or on the oxide layer 208. Specifically, the semiconductor processing tool (e.g., deposition tool 102) may deposit the anti-reflective coating 210 using CVD techniques, PVD techniques, ALD techniques, or another type of deposition technique. The anti-reflective coating 210 may comprise a suitable material for reducing reflection of incident light projected toward the photodiode 206. For example, the anti-reflective coating 210 may include a nitrogen-containing material. In some embodiments, the semiconductor processing tool may form the anti-reflective coating 210 to a thickness in a range from about 200 angstroms to about 1000 angstroms.

As shown in fig. 3I, a color filter layer 212 may be formed over the anti-reflective coating 210 and/or over the anti-reflective coating 210. Specifically, a semiconductor processing tool (e.g., deposition tool 102) may deposit color filter layer 212 using CVD techniques, PVD techniques, ALD techniques, or another type of deposition technique. The color filter layer 212 may be formed such that each color filter region of the color filter layer 212 is formed over an associated pixel region 202. For example, the color filter layer 212 can be formed such that a color filter region 212a (e.g., to filter a wavelength range of incident light) is formed over the pixel region 202a, a color filter region 212b (e.g., to filter a wavelength range of incident light) is formed over the pixel region 202b, a color filter region 212c (e.g., to filter a wavelength range of incident light) is formed over the pixel region 202c, and so on.

As shown in fig. 3J, a microlens layer 214 can be formed over the anti-reflective coating 210 and/or on the anti-reflective coating 210. The microlens layer 214 can be formed such that each microlens of the microlens layer 214 is formed over an associated pixel region 202. For example, the microlens layer 214 can be formed such that microlenses 214a are formed over the pixel regions 202a, microlenses 214b are formed over the pixel regions 202b, microlenses 214c are formed over the pixel regions 202c, and so on. For example, the microlens layer 214 may be formed by a spin coating process or a deposition process and a reflow operation to bend the upper or top surface of the microlens.

As described above, fig. 3A to 3J are provided as examples. Other examples may differ from those described in fig. 3A to 3J.

Fig. 4 is a schematic diagram of another example pixel array 400 described herein. As shown in fig. 4, the example pixel array 400 may include a similar configuration of components, structures, and/or layers as the example pixel array 200. However, the example pixel array 400 includes a microlens system having air gaps formed therein to further reduce and/or minimize crosstalk (optical and electrical) between adjacent (and non-adjacent) pixel regions. The air gaps in the deep trench isolation structures between adjacent (and non-adjacent) pixel regions and the air gaps in the microlens system may be capable of reflecting incident light over a broad spectrum of incident angles to further improve the quantum efficiency of the pixel array 400.

As shown in fig. 4, pixel array 400 may include one or more pixel regions 402 (e.g., pixel region 402a, pixel region 402b, pixel region 402c, and/or another pixel region) in a substrate 404 of an image sensor (e.g., a CMOS image sensor). Each pixel region 402 may include a photodiode 406. The pixel array 400 may include an oxide layer 408 over the substrate 404 and the photodiode 406 and/or on the substrate 404 and the photodiode 406. The pixel array 400 can include an anti-reflective coating 410 over the oxide layer 408 and/or on the oxide layer 408.

The pixel array 400 may include a color filter layer 412 over the anti-reflective coating 410 and/or on the anti-reflective coating 410. The color filter layer 412 may include an array of color filter regions, where each color filter region filters incident light to allow incident light of a particular wavelength to pass through the photodiode 406 of the associated pixel region 402. For example, color filter region 412a may filter incident light of pixel region 402a, color filter region 412b may filter incident light of pixel region 402b, color filter region 412c may filter incident light of pixel region 402c, and so on.

The pixel array 400 may include a microlens layer 414 over the color filter layer 412 and/or on the color filter layer 412. The microlens layer 414 can include a microlens for each of the pixel regions 402. For example, the microlens 414a can be formed to focus incident light toward the photodiode 406 of the pixel region 402a, the microlens 414b can be formed to focus incident light toward the photodiode 406 of the pixel region 402b, the microlens 414c can be formed to focus incident light toward the photodiode 406 of the pixel region 402c, and so on.

In some embodiments, the image sensor is a BSI CMOS image sensor. In such examples, oxide layer 408, anti-reflective coating 410, color filter layer 412, and microlens layer 414 can be formed on the backside of substrate 404. Further, one or more deep trench isolation structures 416 may be formed in the backside of the substrate 404 to provide optical isolation between the pixel regions 402, and thus may be referred to as backside deep trench isolation structures. A high absorption region 418 may be formed in each of the photodiodes 406 to increase the absorption of incident light by the photodiode 406. The one or more deep trench isolation structures 416 may each include an air gap 420 to increase optical isolation between the photodiodes 406 and reduce optical crosstalk between the photodiodes 406. Similarly, each of the high absorption regions 418 may each include an air gap 422 to increase optical isolation between the photodiodes 406 and to reduce optical crosstalk between the photodiodes 406.

As further shown in FIG. 4, microlens layer 414 can be an air gap in situ micro-lens (AGML) that includes multiple components, structures, and/or layers. For example, the microlens layer 414 may include a plurality of microlens structures 424. The microlens structure 424 may be a tapered structure that includes a transparent material, a dielectric material, or another type of material. Adjacent microlens structures 424 may form tapered trenches. A dielectric film 426 may be included over the microlens structure 424 and in the tapered trench to seal the tapered trench. A passivation film 428 may be formed on the dielectric film 426 and/or on the dielectric film 426 to increase the ability of the microlens layer 414 to focus incident light. The passivation film 428 may include silicon nitride (SiNx) or another material having a high refractive index, which is a higher refractive index relative to the dielectric film 426. The microlens layer 414 can be referred to as AGML because the air gaps 430 are formed in the dielectric film 426 in the tapered trenches. Such air gaps 430 function similarly to air gaps 420 and 422, so air gaps 430 reflect incident light in microlens layer 414 (e.g., due to total internal reflection phenomena), reducing optical crosstalk between adjacent (or non-adjacent) pixel regions (e.g., pixel region 402b and pixel region 402 c).

The number and arrangement of components, structures, and/or layers shown in fig. 4 may be one or more examples. In practice, there may be additional components, structures, and/or layers, fewer components, structures, and/or layers, different components, structures, and/or layers, and/or different configurations of components, structures, and/or layers than shown in fig. 4.

Fig. 5A-5D are schematic diagrams of examples of forming the pixel array 400 of fig. 4 described herein. As shown in fig. 5A, the processes and/or techniques for forming the photodiode 406, the oxide layer 408, the anti-reflective coating 410, the deep trench isolation structure 416, the high absorption region 418, the air gap 420, and the air gap 422 may be similar to the related processes and/or techniques described above with respect to fig. 3A-3J, and thus are omitted.

As shown in fig. 5B, microlens structures 424 can be formed over color filter layer 412 and/or on color filter layer 412. In some embodiments, one or more semiconductor processing tools may form the microlens structure 424. For example, deposition tool 102 may form a photoresist layer over color filter layer 412, exposure tool 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, development tool 106 may develop and remove portions of the photoresist layer to expose the pattern, and deposition tool 102 may deposit material in the removed portions to form microlens structures 424. In some embodiments, the photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using chemical stripping and/or another technique).

As shown in fig. 5C, a dielectric film 426 can be formed over the microlens structures 424 and/or over the microlens structures 424 and in the tapered trenches between the microlens structures 424. For example, a semiconductor processing tool (e.g., deposition tool 102) may deposit the dielectric film 426. In some embodiments, the semiconductor processing tool deposits the dielectric film 426 in the tapered trench such that the dielectric film 426 partially fills the region in the tapered trench, which results in the formation of air gaps 430 therein. Specifically, the semiconductor processing tool may deposit the dielectric film 426 at a deposition rateIn each of the tapered trenches, this deposition rate is such that the air gaps 430 close before the dielectric film 426 can completely fill the tapered trenches. In some embodiments, from about 2 angstroms per second may be usedTo aboutA deposition rate in the range of (a). Furthermore, various CVD and/or atomic layer deposition techniques (such as PECVD, HDP-CVD, SACVD, or PEALD) may be used to deposit the oxide material.

As shown in fig. 5D, a passivation film 428 may be formed on the dielectric film 426 and/or on the dielectric film 426. For example, a semiconductor processing tool, such as the deposition tool 102, may deposit a passivation film 428 on the dielectric film 426 and/or on the dielectric film 426 using an appropriate deposition technique, such as a CVD technique, a PVD technique, an ALD technique, and/or another deposition technique.

As described above, fig. 5A to 5D are provided as examples. Other examples may differ from those described in fig. 5A to 5D.

Fig. 6 is a schematic diagram of example components of an apparatus 600. In some embodiments, one or more of the semiconductor processing tools (deposition tool 102 through implantation tool 112) and/or the wafer/die transport tool 114 may include one or more apparatus 600 and/or one or more components of apparatus 600. As shown in fig. 6, device 600 may include a bus 610, a processor 620, a memory 630, a storage component 640, an input component 650, an output component 660, and a communication component 670.

Bus 610 includes components that enable wired and/or wireless communication between components of device 600. The processor 620 includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and/or another type of processing component. Processor 620 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 620 includes one or more processors that can be programmed to perform functions. The memory 630 may include random access memory, read only memory, and/or another type of memory (e.g., flash memory, magnetic memory, and/or optical memory).

The storage section 640 stores information and/or software related to the operation of the device 600. For example, storage component 640 may include a hard disk drive, a magnetic disk drive, an optical disk drive, a solid state disk drive, a compact disc, a digital versatile disc, and/or another type of non-transitory computer-readable medium. Input component 650 enables device 600 to receive input, such as user input and/or sensed input. For example, the input component 650 may include a touch screen, keyboard, keypad, mouse, buttons, microphone, switches, sensors, global positioning system components, accelerometers, gyroscopes, actuators, and/or the like. Output component 660 enables device 600 to provide output, such as via a display, speaker, and/or one or more light emitting diodes. The communication component 670 enables the device 600 to communicate with other devices, such as via a wired connection and/or a wireless connection. For example, the communication component 670 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, an antenna, and/or the like.

The apparatus 600 may perform one or more of the processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 630 and/or storage 640) may store a set of instructions (e.g., one or more instructions, code, software code, program code, and/or the like) that are executed by processor 620. Processor 620 may execute the set of instructions to perform one or more processes described herein. In some embodiments, execution of the set of instructions by the one or more processors 620 causes the one or more processors 620 and/or the apparatus 600 to perform one or more processes described herein. In some embodiments, hard wired circuitry may be used in place of or in combination with instructions to perform one or more of the processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.

The number and arrangement of components shown in fig. 6 are provided as examples. Apparatus 600 may include additional components, fewer components, different components, or a different configuration of components than shown in fig. 6. Additionally or alternatively, a set of components (e.g., one or more components) of apparatus 600 may perform one or more functions described above as being performed by another set of components of apparatus 600.

Fig. 7 is a flow chart of an example process 700 associated with forming a pixel array. In some embodiments, one or more of the process blocks of fig. 7 may be performed by a semiconductor processing tool (e.g., one or more of the deposition tool 102 through the implantation tool 112 of the semiconductor processing tool described above). Additionally or alternatively, one or more of the process blocks of fig. 7 may be performed by one or more components of device 600, such as processor 620, memory 630, storage component 640, input component 650, output component 660, and/or communications component 670.

As shown in fig. 7, process 700 may include forming a photodiode in a substrate in a pixel region of a pixel array (block 710). For example, as described above, a semiconductor processing tool (e.g., the implantation tool 112) may form a photodiode 206 in the substrate 204 of the pixel region 202 of the pixel array 200. As another example, as described above, a semiconductor processing tool (e.g., the implantation tool 112) may form a photodiode 406 in the substrate 404 of the pixel region 402 of the pixel array 400.

As further shown in fig. 7, the process 700 may include forming a first deep trench isolation structure at a first side of the photodiode (block 720). For example, as described above, a semiconductor process tool (e.g., deposition tool 102, exposure tool 104, development tool 106, etch tool 108, and/or another semiconductor process tool) may form the first deep trench isolation structure 216 at the first side of the photodiode 206. As another example, as described above, a semiconductor process tool (e.g., deposition tool 102, exposure tool 104, development tool 106, etch tool 108, and/or another semiconductor process tool) may form a first deep trench isolation structure 416 on a first side of the photodiode 406.

As further shown in fig. 7, the process 700 can include forming a second deep trench isolation structure on a second side (opposite side) of the photodiode (block 730). For example, as described above, a semiconductor process tool (e.g., deposition tool 102, exposure tool 104, development tool 106, etch tool 108, and/or another semiconductor process tool) may form the second deep trench isolation structure 216 at a second (opposite) side of the photodiode 206. As another example, as described above, a semiconductor process tool (e.g., deposition tool 102, exposure tool 104, development tool 106, etch tool 108, and/or another semiconductor process tool) may form a second deep trench isolation structure 416 on a second (opposite) side of the photodiode 406.

As further shown in fig. 7, the process 700 can include depositing an oxide material in the first deep trench isolation structure such that a first air gap is formed in at least 75% of an area of the first deep trench isolation structure (block 740). For example, as described above, a semiconductor processing tool (e.g., deposition tool 102) may deposit an oxide material in the first deep trench isolation structure 216 such that a first air gap 220 is formed in at least 75% of the area of the first deep trench isolation structure 216. As another example, as described above, a semiconductor processing tool (e.g., deposition tool 102) may deposit an oxide material in the first deep trench isolation structure 416 such that a first air gap 420 is formed in at least 75% of the area of the first deep trench isolation structure 416.

As further shown in fig. 7, the process 700 can include depositing an oxide material in the second deep trench isolation structure such that a second air gap is formed in at least 75% of an area of the second deep trench isolation structure (block 750). For example, as described above, a semiconductor processing tool (e.g., the deposition tool 102) may deposit an oxide material in the second deep trench isolation structure 216 such that the second air gap 220 is formed in at least 75% of the area of the second deep trench isolation structure 216. As another example, as described above, a semiconductor processing tool (e.g., the deposition tool 102) can deposit an oxide material in the second deep trench isolation structure 416 such that a second air gap 420 is formed in at least 75% of an area of the second deep trench isolation structure 416.

Process 700 may include additional implementation steps, such as any single implementation step or any combination of implementation steps including any combination of the implementations described below and/or in conjunction with one or more other processes described herein.

In a first embodiment, depositing an oxide material in the first deep trench isolation structure includes depositing an oxide material in the first deep trench isolation structure by at least one of a PECVD process, an HDP-CVD process, a SACVD process, or a PEALD process. In a second embodiment, separately or in conjunction with the first embodiment, the process 700 includes forming a plurality of highly absorbing regions (e.g., highly absorbing region 218, highly absorbing region 418) over the photodiode, and depositing an oxide material in the plurality of highly absorbing regions such that a respective third air gap (e.g., air gap 222, air gap 422) is formed in each of the plurality of highly absorbing regions.

In a third embodiment, separately or in combination with one or more of the first and second embodiments, the process 700 includes forming an anti-reflective coating (e.g., anti-reflective coating 210, anti-reflective coating 410) over the first deep trench isolation structure, over the second deep trench isolation structure, and over the photodiode, forming a color filter layer (e.g., color filter layer 212, color filter layer 412) over the anti-reflective coating, and forming a microlens (e.g., microlens layer 214, microlens layer 414) over the color filter layer. In a fourth embodiment, process 700 includes depositing an oxide material on the photodiode and substrate to form oxide layers (e.g., oxide layer 208, oxide layer 408), and planarizing the oxide layers, either alone or in combination with one or more of the first through third embodiments.

In a fifth embodiment, alone or in combination with one or more of the first through fourth embodiments, depositing an oxide material in the first deep trench isolation structure includes depositing an oxide material in the first deep trench isolation structure at a deposition rate such that the oxide material fills a top region of the first deep trench isolation structure before the oxide material can fill a center region of the first deep trench isolation structure, thereby forming a first air gap.

Although fig. 7 illustrates example blocks of process 700, in some embodiments, process 700 may include additional blocks, fewer blocks, different blocks, or a different configuration of blocks than illustrated in fig. 7. Additionally or alternatively, two or more of the blocks of process 700 may be performed in parallel.

In this manner, isolation structures may be formed between adjacent and/or non-adjacent pixel regions of the image sensor (e.g., between diagonal or cross-point pixel regions) to reduce and/or prevent optical crosstalk. Such an isolation structure may comprise a deep trench isolation structure, or another type of trench partially filled with a material such that an air gap is formed therein. The deep trench isolation structure with the air gap formed therein can reduce optical crosstalk between pixel regions. The reduction in optical crosstalk may increase the spatial resolution of the image sensor, may increase the overall sensitivity of the image sensor, may reduce color mixing between pixel areas of the image sensor, and/or may reduce image noise after color correction of images captured using the image sensor.

As described in more detail above, some embodiments described herein provide a pixel array including a first pixel region, a second pixel region, and a deep trench isolation structure between the first pixel region and the second pixel region, the deep trench isolation structure being filled with an oxide material. The air gap formed in the oxide material comprises at least 75% of the area in the deep trench isolation structure.

In some embodiments, the height of the air gap is in the range of about 1.5 microns to about 10 microns. In some embodiments, the width of the air gap is in a range from about 0.7 microns to about 1.3 microns. In some embodiments, an air gap is formed to reduce optical crosstalk between the first pixel region and the second pixel region. In some embodiments, the pixel array further includes a high absorption region in the first pixel region and an additional air gap formed in the high absorption region. In some embodiments, the height of the additional air gaps is in the range of about 1500 angstroms to about 4000 angstroms. In some embodiments, the width of the additional air gap is in the range of about 2000 angstroms to about 4000 angstroms. In some embodiments, the first pixel region and the second pixel region are adjacent pixel regions. In some embodiments, the first pixel region and the second pixel region are non-adjacent pixel regions in the pixel array.

As described in more detail above, some embodiments described herein provide a method of forming a pixel array. The method includes forming a photodiode in a substrate of a pixel region of a pixel array. The method includes forming a first deep trench isolation structure at a first side of a photodiode. The method includes forming a second deep trench isolation structure on a second (opposite) side of the photodiode. The method includes depositing an oxide material in the first deep trench isolation structure such that a first air gap is formed in at least 75% of an area of the first deep trench isolation structure. The method includes depositing an oxide material in the second deep trench isolation structure such that a second air gap is formed in at least 75% of an area of the second deep trench isolation structure.

In some embodiments, depositing the oxide material in the first deep trench isolation structure includes depositing the oxide material in the first deep trench isolation structure by at least one of a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process, or a plasma enhanced atomic layer deposition process. In some embodiments, the method further includes forming a plurality of high absorption regions over the photodiodes, and depositing an oxide material in the high absorption regions such that a respective third air gap is formed in each of the high absorption regions. In some embodiments, the method further includes forming an anti-reflective coating over the first deep trench isolation structure, over the second deep trench isolation structure, and over the photodiode, forming a color filter layer over the anti-reflective coating, and forming a microlens over the color filter layer. In some embodiments, the method further includes depositing an oxide material on the photodiode and the substrate to form an oxide layer, and planarizing the oxide layer. In some embodiments, depositing the oxide material in the first deep trench isolation structure includes depositing the oxide material in the first deep trench isolation structure at a deposition rate such that the oxide material fills a top region of the first deep trench isolation structure before the oxide material fills a center region of the first deep trench isolation structure, thereby forming the first air gap.

As described in more detail above, some embodiments described herein provide an array of pixels. The pixel array includes a first pixel region. The pixel array includes a second pixel region. The pixel array includes a deep trench isolation structure between a first pixel region and a second pixel region. The pixel array includes a first microlens formed in a first pixel region. The pixel array includes a second microlens formed in the second pixel region. The pixel array includes a second air gap formed between the first and second microlenses. The pixel array includes a plurality of high absorption regions in a first pixel region. The pixel array includes a respective third air gap formed in each of the high absorption regions. No more than 25% of the area of the deep trench isolation structure is filled with an oxide material. At least 75% of the area of the deep trench isolation structure is filled with a first air gap formed by an oxide material in the deep trench isolation structure.

In some embodiments, the pixel array further includes a third pixel region and an additional deep trench isolation structure between the first pixel region and the third pixel region, the additional deep trench isolation structure filled with an oxide material and having a fourth air gap formed therein. In some embodiments, the pixel array further includes a third microlens formed in the third pixel region and a fifth air gap formed between the first microlens and the third microlens. In some embodiments, no more than 25% of an area of the deep trench isolation structure is filled with an oxide material, and at least 75% of an area of the deep trench isolation structure is filled with a first air gap formed by the oxide material in the deep trench isolation structure. In some embodiments, the height of each of the first and second air gaps is in a range of about 1.5 microns to about 10 microns, and the width of each of the first and second air gaps is in a range of about 0.7 microns to about 1.3 microns.

The foregoing outlines features of some embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.