阅读说明：本技术 高线性输入和输出轨到轨放大器 (High linearity input and output rail-to-rail amplifier ) 是由 维巴夫·潘迪 博德夫·库马尔 于 2020-04-30 设计创作，主要内容包括：一种放大器包括接收输入信号的输入跨导器,该输入信号具有电压摆幅。电源侧电流镜生成作为输入信号电压的函数的栅极电压,并且电流源提供作为栅极电压的函数的输入跨导器的偏置电流,以在输入信号的电压摆幅上保持恒定的偏置电流。电阻器平均化跨导消除跨导器的源极电压以提供平均源极电压,并且将平均源极电压施加到所述跨导消除跨导器的输入器件的阱以减小反向偏置效应。输入器件布置在相同阱中并具有公共质心以消除工艺不匹配。第一I-DAC修整第一跨导器的偏移,并且第二I-DAC修整第二跨导器的偏移,以在轨到轨输入共模范围内实现低偏移。(An amplifier includes an input transconductor to receive an input signal having a voltage swing. The power supply side current mirror generates a gate voltage as a function of the input signal voltage, and the current source provides a bias current of the input transconductor as a function of the gate voltage to maintain a constant bias current over the voltage swing of the input signal. Resistors average the source voltage of a transconductance cancellation transconductor to provide an average source voltage, and apply the average source voltage to a well of an input device of the transconductance cancellation transconductor to reduce a reverse bias effect. The input devices are arranged in the same well and have a common centroid to eliminate process mismatches. The first I-DAC trims the offset of the first transconductor and the second I-DAC trims the offset of the second transconductor to achieve a low offset in the rail-to-rail input common mode range.)

1. A method for maintaining a constant bias current over a voltage swing of an input signal received by an input transconductor of an amplifier, comprising:

generating a power supply side current mirror gate voltage as a function of the input signal voltage, an

Using the gate voltage for controlling a bias current source to the input transconductor, wherein a bias current of the input transconductor is kept constant.

2. The method of claim 1, further comprising:

wherein the gate voltage turns off the bias current source to the input transconductor and the tail current source to the input transconductor when the input signal voltage is low; and is

Wherein the gate voltage is turned on to the bias current source of the input transconductor and a tail current source of the input transconductor when the input signal voltage is not low.

3. The method of claim 1, further comprising:

wherein an integrated circuit comprises the amplifier, wherein the integrated circuit comprises an input pin for connecting to a sensor external to the integrated circuit, wherein the integrated circuit comprises a switch connected between the pin and a gate terminal of an input device of the amplifier, wherein the input device comprises the input transconductor;

comparing a voltage on the pin to a reference voltage generated internally to the integrated circuit; and

controlling the switch based on the comparison to disconnect the input transconductor from the pin in response to detecting a short circuit condition at the pin.

4. The method of claim 1, further comprising:

wherein a transimpedance amplifier (TIA) comprises the amplifier and a transimpedance gain element, wherein the TIA receives a current from a sensor and outputs a voltage proportional to the sensor current based on a value of the transimpedance gain element;

applying an external Direct Current (DC) current from an external DC current source to a non-inverting input of the TIA;

measuring a voltage across the transimpedance gain element using at least two analog-to-digital converters (ADCs) within the TIA;

determining a value of the transimpedance gain element by using the measured voltage and the external DC current; and

using a digital calibration loop within the TIA to determine a calibrated value of the transimpedance gain element using an output of the digital calibration loop.

5. The method of claim 1, further comprising:

averaging source voltages of at least two of the transconductors to provide an average source voltage;

applying the average source voltage to a well of an input device of the at least two transconductors to reduce reverse bias effects; and is

Wherein the input devices are arranged in the same well and have a common centroid to eliminate process mismatches.

6. The method of claim 1, further comprising:

wherein a first one or more of the input transconductors process the input signal when the input signal voltage is high, and a second one or more of the input transconductors process the input signal when the input signal voltage is low;

trimming an offset of the first one or more transconductors using a first current digital-to-analog converter (I-DAC);

trimming an offset of the second one or more transconductors using a second I-DAC; and is

Wherein the using the first I-DA and the second I-DA achieves a low offset in a rail-to-rail input common mode range of the amplifier.

7. An apparatus, comprising:

an amplifier, the amplifier comprising:

an input transconductor to receive an input signal, the input signal having a voltage swing;

a power-side current mirror that generates a gate voltage as a function of an input signal voltage; and

a current source that provides a bias current of the input transconductor as a function of the gate voltage to maintain a constant bias current over a voltage swing of the input signal.

8. The apparatus of claim 7, further comprising:

wherein the gate voltage turns off the bias current source to the input transconductor and the tail current source to the input transconductor when the input signal voltage is low; and is

Wherein the gate voltage is turned on to the bias current source of the input transconductor and a tail current source of the input transconductor when the input signal voltage is not low.

9. The apparatus of claim 7, further comprising:

an input pin for connection to a sensor external to an integrated circuit, the integrated circuit including the amplifier;

a comparator to compare a voltage on the pin to a reference generated internally to the integrated circuit;

a switch connected between the pin and a gate terminal of an input device of the amplifier, wherein the input device includes the input transconductor; and is

Wherein the comparator output voltage controls the switch to disconnect the input transconductor from the pin in response to detecting a short circuit condition at the pin.

10. The apparatus of claim 7, further comprising:

a transimpedance amplifier (TIA), comprising:

an amplifier;

a transimpedance gain element; and

at least two analog-to-digital converters (ADCs);

wherein the TIA receives a current from a sensor and outputs a voltage proportional to the sensor current based on a value of the transimpedance gain element;

wherein the at least two ADCs are operable to measure a voltage across the transimpedance gain element in response to application of an external Direct Current (DC) current from an external DC current source to a non-inverting input of the TIA;

wherein a value of the transimpedance gain element is determined by using the measured voltage and the external DC current; and is

Wherein the calibrated value of the transimpedance gain element is determined using an output of a digital calibration loop within the TIA.

11. The apparatus of claim 7, further comprising:

a resistor that averages the source voltages of at least two of the transconductors to provide an average source voltage and applies the average source voltage to the wells of the input devices of the at least two transconductors to reduce the reverse bias effect; and is

Wherein the input devices are arranged in the same well and have a common centroid to eliminate process mismatches.

12. The apparatus of claim 7, further comprising:

wherein the input transconductor comprises:

a first one or more transconductors that process an input voltage when the input voltage is high; and

a second one or more transconductors that process the input voltage when the input voltage is low;

a first current digital-to-analog converter (I-DAC) to trim offset of the first one or more transconductors;

a second I-DAC to trim an offset of the second one or more transconductors; and is

Wherein a lower offset is achieved using the first I-DAC and the second I-DAC within a rail-to-rail input common mode range over which the amplifier operates.

13. A method for increasing linearity of an amplifier having a transconductance cancellation transconductor, comprising:

averaging the source voltages of the transconductance cancellation transconductors to provide an average source voltage;

applying the average source voltage to a well of an input device of the transconductance cancellation transconductor to reduce a reverse bias effect; and is

Wherein the input devices are arranged in the same well and have a common centroid to eliminate process mismatches.

14. The method of claim 13, further comprising:

generating a power supply side current mirror gate voltage as a function of the input signal voltage, an

Providing a bias current for the transconductor using the gate voltage, wherein the bias current is held constant.

15. The method of claim 13, further comprising:

wherein the transconductor comprises:

a first one or more transconductors that process an input voltage when the input voltage is high; and

a second one or more transconductors that process the input voltage when the input voltage is low;

trimming an offset of the first one or more transconductors processing a high level input voltage using a first current digital-to-analog converter (I-DAC);

using a second I-DAC to trim an offset of the second one or more transconductors that handle low level input voltages; and is

Wherein a lower offset is achieved in the rail-to-rail input common mode range using the first I-DAC and the second I-DAC.

16. An amplifier, comprising:

a transconductance cancellation transconductor;

a resistor that averages a source voltage of the transconductance cancellation transconductor to provide an average source voltage and applies the average source voltage to a well of an input device of the transconductance cancellation transconductor to reduce a reverse bias effect; and is

Wherein the input devices are arranged in the same well and have a common centroid to eliminate process mismatches.

17. The amplifier recited in claim 16 further comprising:

wherein the transconductor receives an input signal, the input signal having a voltage swing;

a power-side current mirror that generates a gate voltage as a function of the input signal voltage; and

a current source that provides a bias current of the transconductor as a function of the gate voltage to maintain a constant bias current over a voltage swing of the input signal.

18. The amplifier recited in claim 16 further comprising:

a first one or more transconductors that process an input voltage when the input voltage is high;

a second one or more transconductors that process the input voltage when the input voltage is low;

a first current digital-to-analog converter (I-DAC) to trim offset of the first one or more transconductors;

a second I-DAC to trim an offset of the second one or more transconductors;

wherein a lower offset is achieved using the first I-DAC and the second I-DAC within a rail-to-rail input common mode range over which the amplifier operates;

a resistor that averages a source voltage of the first one or more transconductors to provide an average source voltage and applies the average source voltage to a well of an input device of the first one or more transconductors to reduce a reverse bias effect; and is

Wherein the input devices of the first one or more transconductors are arranged in the same well and have a common centroid to eliminate process mismatch.

19. A method of trimming the offset of a transconductor of an amplifier to increase its linearity in a common mode range of rail-to-rail inputs, wherein the amplifier receives an input voltage and comprises a first one or more transconductors that process the input voltage when it is high and a second one or more transconductors that process the input voltage when it is low, the method comprising:

trimming an offset of the first one or more transconductors processing a high level input voltage using a first current digital-to-analog converter (I-DAC);

using a second I-DAC to trim an offset of the second one or more transconductors that handle low level input voltages; and is

Wherein the use of the first I-DAC and the second I-DAC achieves a lower offset in the rail-to-rail input common mode range.

20. The method of claim 19, further comprising:

generating a power supply side current mirror gate voltage as a function of the input signal voltage, an

Providing a bias current for the transconductor using the gate voltage, wherein the bias current is held constant.

21. The method of claim 19, further comprising:

averaging source voltages of the first one or more transconductors to provide an average source voltage, wherein the first one or more transconductors comprise a transconductance cancellation transconductor;

applying the average source voltage to a well of an input device of the transconductance cancellation transconductor to reduce a reverse bias effect; and is

Wherein the input devices are arranged in the same well and have a common centroid to eliminate process mismatches.

22. An amplifier, comprising:

a first one or more transconductors that process an input voltage when the input voltage is high;

a second one or more transconductors that process the input voltage when the input voltage is low;

a first current digital-to-analog converter (I-DAC) to trim offset of the first one or more transconductors;

a second I-DAC to trim an offset of the second one or more transconductors; and is

Wherein a lower offset is achieved using the first I-DAC and the second I-DAC within a rail-to-rail input common mode range over which the amplifier operates.

23. The amplifier recited in claim 22 further comprising:

wherein the transconductor receives an input signal, the input signal having a voltage swing;

a power-side current mirror that generates a gate voltage as a function of the input signal voltage; and

a current source that provides a bias current of the transconductor as a function of the gate voltage to maintain a constant bias current over a voltage swing of the input signal.

24. The amplifier recited in claim 22 further comprising:

wherein the first one or more transconductors comprise a transconductance cancellation transconductor;

a resistor that averages a source voltage of the first one or more transconductors to provide an average source voltage and applies the average source voltage to a well of an input device of the transconductance cancellation transconductor to reduce a reverse bias effect; and is

Wherein the input devices are arranged in the same well and have a common centroid to eliminate process mismatches.

Background

The paper "Constant-slope-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries", IEEE j.solid-State Circuits, 38, No.8, pp.1364-1372, aug.2003 (hereinafter "Carrillo paper"), which is incorporated herein by reference in its entirety for all purposes, describes a "universal low-voltage rail-to-rail (rail-to-rail) input stage" that "provides Constant small and large signal behavior over the entire input common-mode voltage range, while imposing no significant restrictions on high frequency operation". A disadvantage of the circuit described in the Carrillo paper is that it may not provide the linear performance required for some applications.

Disclosure of Invention

In one embodiment, the present disclosure provides a method for maintaining a constant bias current over a voltage swing of an input signal received by an input transconductor (transconductor) of an amplifier. The method includes generating a supply side current mirror (supply current mirror) gate voltage as a function of an input signal voltage and using the gate voltage for controlling a bias current source to an input transconductor, wherein a bias current of the input transconductor is held constant.

In another embodiment, the present disclosure provides an apparatus comprising an amplifier comprising an input transconductor to receive an input signal, the input signal having a voltage swing. The amplifier further comprises: a power-side current mirror that generates a gate voltage as a function of an input signal voltage; and a current source that provides a bias current of the input transconductor as a function of the gate voltage to maintain a constant bias current over the voltage swing of the input signal.

In another embodiment, the present disclosure provides a method for increasing linearity of an amplifier having a transconductance-cancelling transconductor. The method includes averaging a source voltage of the transconductance cancellation transconductor to provide an average source voltage, and applying the average source voltage to a well (well) of an input device of the transconductance cancellation transconductor to reduce a reverse bias effect. The input devices are arranged in the same well and have a common centroid (common centroid) to eliminate process mismatches.

In another embodiment, the present disclosure provides an amplifier having a transconductance cancellation transconductor and resistors that average a source voltage of the transconductance cancellation transconductor to provide an average source voltage, and apply the average source voltage to a well of an input device of the transconductance cancellation transconductor to reduce a reverse bias effect. The input devices are arranged in the same well and have a common centroid to eliminate process mismatches.

In another embodiment, the present disclosure provides a method of trimming the offset of a transconductor of a (trim) amplifier to increase its linearity within a rail-to-rail input common mode range, wherein the amplifier receives an input voltage and comprises a first transconductor or transconductors that process the input voltage when the input voltage is high and a second transconductor or transconductors that process the input voltage when the input voltage is low. The method includes using a first current digital-to-analog converter (I-DAC) to trim an offset of a first one or more transconductors that process the high level input voltage. The method also includes trimming an offset of the second one or more transconductors handling the low level input voltage using the second I-DAC. Using the first and second I-DACs achieves a lower offset in the rail-to-rail input common mode range.

In another embodiment, the present disclosure provides an amplifier comprising a first one or more transconductors that process an input voltage when the input voltage is high, a second one or more transconductors that process the input voltage when the input voltage is low, a first current digital-to-analog converter (I-DAC) for trimming an offset of the first one or more transconductors, and a second I-DAC for trimming an offset of the second one or more transconductors. The use of the first and second I-DACs may enable a lower offset in the rail-to-rail input common mode range over which the amplifier operates.

Drawings

Fig. 1 is a diagram illustrating a subsystem employing an amplifier exhibiting high linear input and output rail-to-rail characteristics according to an embodiment of the present disclosure.

Fig. 2 is a circuit diagram illustrating portions of a high linearity input and output rail-to-rail amplifier according to an embodiment of the present disclosure.

Fig. 3 is a circuit diagram illustrating portions of a high linearity input and output rail-to-rail amplifier according to an embodiment of the present disclosure.

Fig. 4 is a diagram illustrating the same wells in which transconductance input devices are arranged and having a common centroid, according to an embodiment of the present disclosure.

Fig. 5 is a circuit diagram illustrating portions of a high linearity input and output rail-to-rail amplifier according to an embodiment of the present disclosure.

Fig. 6 is a diagram illustrating an input protection circuit of a protection amplifier according to an embodiment of the present disclosure.

Fig. 7 is a diagram illustrating digital calibration of a transimpedance gain element (transimpedance gain element) according to an embodiment of the present disclosure.

Detailed Description

Referring now to fig. 1, a diagram is shown illustrating a subsystem 100 employing an amplifier 102 exhibiting high linear input and output rail-to-rail characteristics, in accordance with an embodiment of the present disclosure. Using processor (not shown) driverPulse-code modulation (PCM) data is supplied to a digital-to-analog converter (DAC) 104. The DAC 104 converts the PCM data into an analog differential voltage, which the amplifier 106 converts into an analog single-ended stimulus output voltage V_EXO. Excitation output voltage V_EXOIs provided to the first analog-to-digital converter (ADC1)108 and a pin EXOUT, which is also coupled to an external load, which may be modeled by a parallel combination of a resistor R1 and a capacitor C1. Excitation output voltage V_EXOThe values may be read from the ADC 1108 and processed as desired. Excitation output voltage V_EXOA non-inverting input (non-inverting input) coupled to the amplifier 102, which amplifies the driving output voltage V_EXO. Excitation output voltage V_EXOAmplified by amplifier 102 and copied to node V_SNSWhich is coupled to the inverting input of amplifier 102 and pin SENSE. Capacitor C_pCoupled between pin SENSE and ground.

Excitation output voltage V_EXOExcitation generating current I_SNSOf the passive sensor 112. Current I_SNSCan pass through node V_SNSPin SENSE at (a) and processed as desired. The resistor network is coupled at node V_SNSAnd node V_TIAOIn the meantime. Node V_TIAOCoupled to the output of amplifier 102 and pin ZOOT. Node V_TIAOSensed by the second ADC 118. Excitation output voltage V_EXOIs amplified to a node V_TIAOThe above. The current generated by amplifier 102 through the feedback resistor network is at node V_TIAOA voltage is generated.

Advantageously, as described in more detail below, the amplifier 102 is a high linearity input and output rail-to-rail amplifier. More specifically, the amplifier 102 includes improvements over conventional amplifiers (e.g., over Carrillo's amplifiers) to improve its linearity and thereby reduce its Total Harmonic Distortion (THD). In one embodiment, the amplifier 102 input ranges from zero to 3 volts, and the open loop gain of the amplifier 102 is approximately 80 dB. In the exemplary embodiment of fig. 1, the resistor network includes a variable capacitor C_EXTParallel variable resistor R_f. In one embodiment, passive sensor 112 includes a coupling node coupled between ground and node V_SNSCapacitor C in between_SNSParallel resistor R_SNS. The embodiment of FIG. 1 also includes coupling between passive sensor 112 and node V_SNSWith the capacitor Cs in between. In one embodiment, passive sensor 112 is off-chip with respect to the rest of subsystem 100.

In the embodiment of fig. 1, the combination of the sensor 112 and the amplifier 102 operates as a transimpedance amplifier (TIA) such that the output voltage V is_TIAOAnd current I_SNSHighly linearly proportional, and feedback resistor R_fOperating as a transimpedance gain element to determine an output voltage V_TIAOAnd current I_SNSI.e. the transimpedance gain of the TIA. In one embodiment, the amplifier 102 is calibrated using the on-chip ADC 1108 and ADC2118 to determine the transimpedance gain element R_fAs described in more detail below, so that the transimpedance gain is accurate to within 1%.

Referring now to fig. 2, a circuit diagram illustrating portions of a high linearity input and output rail-to-rail amplifier 102 (e.g., the amplifier 102 of fig. 1) in accordance with an embodiment of the present disclosure is shown. The amplifier 102 is based on the input stage described in the Carrillo paper, but includes improvements that can increase its linearity performance, thereby reducing its THD. The amplifier 102 comprises a current summer 222 or output stage comprising constant current sources IB5 and IB6 which receive a supply voltage V_DDAnd provides bias currents to the input transconductor GM1 on respective nodes a and B. In one embodiment, current summer 222 is a folded cascode load to which current sources IB5 and IB6 also provide bias currents.

Transconductor GM1 includes a pair of n-channel MOSFETs M11 and M12 whose source terminals share a common node with a ground-side current source MNTAIL0B controlled by the voltage at node NBIAS, which will be described in more detail below. In one embodiment, current source MNTAIL0B includes an n-channel MOSFET with a gate coupled to a node holding voltage NBIAS. The gate of the transistor M11 receives the input signal voltage V_IPAnd the gate of transistor M12 receives the input signal voltage V_IN. In one embodiment, the input signal voltage V_IPAnd V_INIncluding respective positive and negative portions of the differential input signal voltage. In one embodiment, the input signal voltage V_IPAnd V_INTo the input of a unity gain source follower amplifier comprising transistors M9 and M10. The drain of transistor M11 is coupled to node A, and the drain of transistor M12 is coupled to node B. Node a and node B are collectively referred to as a summing node. As described in more detail below, the embodiment of fig. 2 advantageously maintains an effectively constant DC bias current at the summing node (even in the presence of large swings in the input signal voltage) to improve the linearity of the amplifier 102 and reduce its THD relative to conventional amplifiers.

The amplifier 102 also includes a p-channel MOSFET M9 with a gate receiving a positive input signal voltage V_IPIts drain coupled to ground and its source coupled to a constant supply side current source I2. The transistor M9 generates a voltage V at its source_{IP_LS}The voltage is a positive input signal voltage V_IPA level shifted version of (a). The amplifier 102 also includes a p-channel MOSFET M10 with a gate receiving a positive input signal voltage V_INIts drain coupled to ground and its source coupled to a constant supply side current source I3. The transistor M10 generates a voltage V at its source_{IN_LS}The voltage is a negative input signal voltage V_INA level shifted version of (a).

The transconductor GM2 comprises a pair of n-channel MOSFETs M5 and M6 whose source terminals share a common node with a constant ground side current source MNTAIL 1. The gate of transistor M5 receives the positive level shifted input signal voltage V_{IP_LS}And the gate of transistor M6 receives the negative level shifted input signal voltage V_{IN_LS}. The drain of transistor M5 is coupled to node A, and the drain of transistor M6 is coupled to node B.

The transconductor GM3 comprises a pair of n-channel MOSFETs M7 and M8 whose source terminals share a common node with a ground-side current source MNTAIL0A controlled by a voltage NBIAS. The gate of transistor M7 receives the positive level shifted input signal voltage V_{IP_LS}And the gate of transistor M8 receives the negative level shifted input signal voltage V_{IN_LS}. The drain of transistor M7 is coupled to node B, and the drain of transistor M8 is coupled to node A.

The amplifier 102 also includes a pair of p-channel MOSFETs M2 and M3, the gates of which are coupled together at a node PBIAS. The sources of transistors M2 and M3 are coupled to the supply voltage V_DD. The n-channel MOSFET M4 has its source coupled to ground and its drain coupled to the drain of transistor M3 at node NBIAS to which the gate of transistor M4 is also coupled. As described above, the voltage NBIAS controls the current sources MNTAIL0A and MNTAIL 0B.

The amplifier 102 also includes a pair of n-channel MOSFETs M0 and M1 having their drains coupled together and to the drain of transistor M2 at node PBIAS. The sources of transistors M0 and M1 are coupled together and to a constant ground-side current source I1. The gate of the transistor M0 receives a positive input signal voltage V_IPAnd the gate of transistor M1 receives the negative input signal voltage V_IN. Transistors M2 and M3 operate as a supply side current mirror that generates the input signal voltage V at node PBIAS_IPAnd V_INThe gate voltage as a function of. The gate voltage PBIAS is used to control the supply-side current sources IB1, IB2, IB3, and IB 4. Current sources IB1 and IB2 provide the bias current of transconductor GM2 and current sources IB3 and IB4 provide the bias current of transconductor GM 3. Under control of the voltage PBIAS, the current sources IB 1-IB 4 operate to provide the input signal voltage V at the summing node_IPAnd V_INMaintains a constant DC bias current over the voltage swing, which advantageously improves the linearity of the amplifier 102 and reduces THD. More specifically, current source IB1 is coupled to supply voltage V_DDAnd node a to provide a bias current to the drain of transistor M5 to provide a bias current at the input signal voltage V_IPAnd V_INMaintaining a constant bias current over the voltage swing; the current source IB2 is coupled to the supply voltage V_DDAnd node B to provide a bias current to the drain of transistor M6 to provide a bias current at the input signal voltage V_IPAnd V_INMaintaining a constant bias current over the voltage swing; a current source IB3 is coupled toSupply voltage V_DDAnd node a to provide a bias current to the drain of transistor M11 to provide a bias current at the input signal voltage V_IPAnd V_INMaintaining a constant bias current over the voltage swing; and a current source IB4 coupled to the supply voltage V_DDAnd node B to provide a bias current to the drain of transistor M12 to provide a bias current at the input signal voltage V_IPAnd V_INMaintains a constant bias current across the voltage swing. Preferably, the current sources IB1, IB2, IB3 and IB4 comprise transistors of the same size and are connected to the same supply voltage V_DDIn the case of (2), the same current is supplied to the transistors M5, M6, M11, and M12, respectively. In one embodiment, current sources IB 1-IB 4 each comprise a p-channel MOSFET whose gate is coupled to node PBIAS. The voltage at PBIAS is used to control current sources IB 1-IB 4, as described in more detail below.

In general, the amplifier 102 operates as follows. When the signal voltage (i.e. V) is inputted_IPAnd V_IN) At low levels (e.g., below 0.8 volts), transconductors GM1 and GM3 are inactive and transconductor GM2 is active and provides output signal current on nodes a and B. Transconductors GM1 and GM3 are inactive because the NBIAS voltage controls current sources MNTAIL0A and MNTAIL0B to suppress the tail current from transconductors GM1 and GM 3. The control voltage NBIAS operates as follows to turn off the current sources MNTAIL0B and MNTAIL 0A. When the input signal voltage is low (e.g., below 0.8 volts), transistors M0 and M1 turn off, thereby turning off the current mirror formed by transistors M2 and M3, which turns off the current flowing into transistor M4, and voltage NBIAS approaches zero volts. When the input signal voltage is high (e.g., above 2.2 volts), transconductors GM2 and GM3 are inactive and transconductor GM1 is active and provides the output signal current on nodes a and B. The transconductors GM2 and GM3 are turned off because of the sources of transistors M9 and M10 (which are level shifted by V, respectively)_IPAnd V_IN) Becomes too high so that current sources I2 and I3 are turned off. Therefore, there is no signal content on the inputs of the transconductors GM2 and GM3, which results in the transconductors GM2 and GM3 not generating any signal current. When the input signal voltage is in the middle of the input voltage range (e.g., between 0.8 and 2.2 volts)All three transconductors are active; however, the transconductors G2 and G3 effectively cancel each other out (because their outputs are coupled back to node a and node B, and as explained further below with reference to fig. 3), so that the transconductor GM1 provides an output signal current on node a and node B. Thus, the three transconductors operate together to generally provide high linearity of the input and output rail-to-rail characteristics, since only one transconductor generates a signal current for any given input voltage.

In general, the supply side bias currents to the input transconductors GM2 and GM3 switch with the input signal level. When the input signal level is low (e.g., below 0.8 volts), transistors M0 and M1 turn off, thereby turning off the current mirror formed by transistors M2 and M3, and voltage PBIAS approaches supply voltage V_DDAnd the voltage NBIAS is close to zero volts, which turns off the current sources IB1, IB2, IB3, IB4, MNTAIL0A, and MNTAIL 0B. During this condition, the current flowing into nodes a and B is set by current sources IB5 and IB6, and the current flowing into nodes a and B is equal to the current flowing into current source MNTAIL 1. When the input signal voltage is not low (e.g., above 0.8 volts), transistors M0 and M1 turn on, thereby turning on the current mirror formed by transistors M2 and M3, and voltage PBIAS is set to the desired operating voltage, which turns on current sources IB1, IB2, IB3, IB4, MNTAIL0A, and MNTAIL 0B. During this operating condition, currents IB1 and IB2 are equal to the current flowing into current source MNTAIL0A, and currents IB3 and IB4 are equal to the current flowing into current source MNTAIL 0B. Meanwhile, the current flowing into MNTAIL1 was set by IB5 and IB 6. Thus, the current into summing nodes a and B remains constant at all input voltage levels, thereby reducing the voltage swing on summing nodes a and B. In this manner, the voltage non-linearity introduced from summing nodes a and B is reduced. As a result, the bias current in the output stage does not vary with the swing in the input signal, and the amplifier 102 enjoys improved linearity or lower THD compared to conventional amplification conventions that do not maintain a constant bias current. In one embodiment, amplifier 102 is capable of inputting a 0 to 3 volt peak-to-peak single ended input signal while inputting the signalLinearity of greater than 80dB is maintained over the sign swing.

Referring now to fig. 3, a circuit diagram illustrating portions of a high linearity input and output rail-to-rail amplifier 102 (e.g., the amplifier 102 of fig. 2) in accordance with an embodiment of the present disclosure is shown. Fig. 3 shows, for example, transconductors GM2 and GM3, current sources I2 and I3, transistors M9 and M10, and current sources MNTAIL0A and MNTAIL1 of fig. 2. The transconductors GM2 and GM3 operate as a transconductance cancellation transconductor pair. In the embodiment of fig. 3, the input devices M5 and M6 of transconductor GM2 and the input devices M7 and M8 of transconductor GM3 are n-channel MOSFETs; however, other embodiments are contemplated in which the input device is of other types. A transconductance canceling transconductor pair is formed when two transconductors generating equal and opposite currents are coupled together at their outputs such that the signal current generated by one transconductor is cancelled by the other transconductor and virtually no current flows to the outputs. The sources of transconductor GM2 (i.e. the sources of input devices M5 and M6) are coupled to node C through resistor R2 and the sources of transconductor GM3 (i.e. the sources of input devices M7 and M8) are coupled to node C through resistor R3 of equal value to resistor R2 so that the voltage at node C is the average of the voltages at the sources of transconductors GM2 and GM 3. Node C is coupled to the well of input devices M5-M8 such that the voltage at node C is applied to the well, which tends to advantageously eliminate the reverse bias effect, which increases the linearity of amplifier 102 and reduces THD. In addition, the input devices M5-M8 are arranged in the same well (e.g., P-well 402 of fig. 4, surrounded by deep N-well (DNW)404 on P-substrate 406) and have a common centroid (as shown in fig. 4), which tends to advantageously cancel process mismatch, which increases linearity of amplifier 102 and reduces THD. A MOS semiconductor transistor manufactured in a CMOS process has 4 terminals: a gate, a drain, a source, and a body. The gate and body terminals have associated gate and body transconductances, respectively. The bulk and source voltages must track each other so that the current generated by the bulk/body transconductance is zero. Otherwise, the transconductance associated with the body terminal will inject a current between the body terminal and the source terminal that is proportional to the voltage. The injected current is signal dependent and thus non-linear. Because in normal operation the amplifier102 force V_IPAnd V_INEqual, so the source terminals of transistors M5-M8 see from V_IP/V_INLevel-shifted voltages. Due to V_IPAnd V_INThe voltage at (a) can swing between 0 and 3 volts, with the source terminals of transistors M5 through M8 seeing a large voltage excursion. By connecting the resistors in the above manner, the tracking V is generated_IPAnd V_INA common node of the average voltage. By connecting node C to the well/body/bulk of the transistor, the bulk transconductance is negated. Also, by connecting all the body terminals to a common network, the transistors M5 to M8 can be concentrated in the same well, which enables the transistors M5 to M8 to be centered in common. As a result, any process variations are advantageously cancelled out and the transconductance of GM2 and GM3 are very similar and cancel out due to the drain connection.

Additionally, the source of input device M9 is coupled to node D through resistor R4, and the source of input device M10 is coupled to node D through resistor R5, which is equal to the value of R4, such that the second voltage at node D is the average of the source voltages of input devices M9 and M10. Node D is coupled to the wells of input devices M9 and M10 such that the voltage at node D is applied to the wells, which tends to advantageously eliminate the reverse bias effect. In addition, the input devices M9 and M10 are arranged in the same well and have a common center of mass, which tends to be beneficial in counteracting process mismatches.

Referring now to fig. 5, a circuit diagram illustrating portions of a high linearity input and output rail-to-rail amplifier 102 (e.g., the amplifier 102 of fig. 2) in accordance with an embodiment of the present disclosure is shown. More specifically, fig. 5 illustrates a system and method of trimming the offset of the transconductors GM1 through GM3 within the amplifier 102 to improve its linearity over the entire rail-to-rail input common mode voltage range. The portions of the amplifier 102 shown in fig. 5 are similar to those shown in fig. 2. However, the embodiment of FIG. 5 also includes a first current digital-to-analog converter (I-DAC)502 having outputs coupled to summing nodes (i.e., nodes A and B of FIG. 1) and an input voltage V having an output coupled to generate a corresponding level shift_{IP_LS}And V_{IN_LS}And a second current digital-to-analog converter 504 of respective drains of the PMOS transistors M9 and M10.

As described above, depending on the input signal level, the amplifier 102 processes the input voltage using different combinations of transconductors GM1, GM2 and GM3 to generate the output current to operate in a highly linear manner in the rail-to-rail input common mode range. In one embodiment, the rail-to-rail input common mode range is from zero volts down rail to 3 volts up rail. In particular, the amplifier 102 may operate in three different modes: GM2 provides an output current when the input voltage is near the lower rail; GM1 provides an output current when the input voltage is near the upper rail; and when the input voltage is in the middle, all three transconductors provide the output current, but GM2 and GM3 cancel each other out so that GM1 effectively provides the output current.

During the manufacture of the amplifier 102, process gradients may create offsets or current mismatches within the transconductor. For example, if the threshold voltages of the NMOS transistors M11 and M12 are slightly different, the transconductor GM1 may generate a current with an offset. A similar current offset may be generated by the transconductor GM2 if the threshold voltages of NMOS transistors M5 and M6 are slightly different, and a current offset may be generated by the transconductor GM3 if the threshold voltages of NMOS transistors M7 and M8 are slightly different. Additionally, if the threshold voltages of the PMOS transistors M9 and M10 are slightly different, then the input voltage V at level shift_{IP_LS}And V_{IN_LS}Voltage offsets may occur, which may result in offsets of the currents output by the transconductors GM2 and GM 3. These offsets may be measured during manufacture of the amplifier 102 and stored so that they may be trimmed using the I-DAC 1502 and the I-DAC 2504 during operation of the amplifier 102.

During operation, a control circuit (not shown) provides a digital value representative of the current value to the I-DAC 1502, and in response, when instructed to do so by the control circuit, the I-DAC 1502 generates an analog current at the summing node corresponding to the digital value. The current generated by the I-DAC 1502 is equal in magnitude and opposite in sign to the offset measured during manufacturing in order to nullify the measured offset, i.e., trim offset. Similarly, the control circuit provides digital values representative of the current values to the I-DAC 2504, and the I-DAC 2504 responsively generates corresponding analog currents equal in magnitude and opposite in sign to offsets measured during manufacturing in order to trim the offsets. Advantageously, the control circuit causes the I-DAC 1502 and I-DAC 2504 to trim the respective offsets at the appropriate times depending on the mode in which the amplifier 102 is operating. More specifically, the I-DAC 1502 trims the offset associated with the NMOS devices M5, M6, M7, M8, M11, and M12 that are active during some of the operating modes (e.g., when the input voltage is near mid-range or higher, e.g., above 0.8 volts), forming transconductors GM1, GM2, and GM3, while the I-DAC 2504 trims the offset associated with the PMOS devices M9 and M10 and transconductors GM2 and GM3 that are active during other operating modes (e.g., when the input voltage is near ground, e.g., below mid-range). In this manner, during operation of the amplifier 102, the offset is trimmed over the rail-to-rail common mode input voltage range, advantageously increasing the linearity of the amplifier 102 and reducing THD. More specifically, significant non-linearity may be observed without the benefit of the two I-DACs trimming offset across the entire rail-to-rail common mode input voltage range. For example, assume that only the I-DAC 1502 is present and the I-DAC 2504 is not. In this case, the I-DAC 1502 will compensate for the offset associated with operation in the high input voltage range; however, when the input voltage is close to ground (e.g., below 0.8 volts), an offset in the output current may be observed, as there is no compensation for the offset associated with the PMOS device, which may result in second order non-linearity. That is, each time the input voltage crosses a certain level, a step in the output current occurs, which may appear as an undesired gray scale.

Referring now to fig. 6, a diagram of an input protection circuit 600 to protect an amplifier according to an embodiment of the present disclosure is shown. The protected amplifier may be an amplifier, such as the employed amplifier 102 of the subsystem 100 of fig. 1. The protection circuit 600 includes a pair of switches 601. One side of each of the switches 601 is coupled to a gate of an input device of the amplifier 102, e.g., the gates of transistors M0, M1, M9, M10, M11, and M12 of fig. 2. The other side of the switch 601 is connected to the input; more specifically, one of the switches 601 is connected to an external sensor via a pin SENSE, andthe other of the switches 601 is connected to an external load via a pin EXOUT. The gate of switch 601 is coupled to a switch driver 608 controlled by the output of and gate 605. One input of the and gate 605 receives the PWRDWNB signal, which is normally true and becomes false when a power down should be performed by the system 100. The other input of the and gate 605 is an inverted version of the output of the comparator 606. The comparator 606 receives on one input a signal from a current source I coupled to ground_bgThe resistance R6 in between (e.g., about 1.25 volts). Comparator 606 receives at its other input the voltage V at the SENSE pin of FIG. 1_SNSStep down versions of (a). The resistor R5 coupled to ground and the resistor R4 coupled in series between the resistor R5 and the SENSE pin implement a voltage step down (e.g., about 0.35 times the voltage at the SENSE pin). As described above with respect to FIG. 1, the SENSE pin may be used to SENSE the output voltage V responsive to excitation by the passive sensor 112_EXOWhile the generated current I_SNS。

Typically, the comparator 606 output is false and since the PWRDWNB signal is typically true, the output of the and gate 605 is typically true, which causes the switch 601 to close. However, when a fault short condition occurs at the SENSE pin such that the voltage on the SENSE pin rises above a threshold (e.g., 3.6 volts), the comparator 606 generates a true signal on its output, which causes the and gate 605 to generate a false output, which causes the switch 601 to open, thereby disconnecting the shorted SENSE pin from the amplifier 102 and protecting the input devices of the amplifier 102. Additionally, the output of the comparator 606 is provided as an interrupt to a digital circuit (e.g., a control processor).

Referring now to fig. 7, a diagram illustrating digital calibration of a transimpedance gain element according to an embodiment of the present disclosure is shown. The parts of the system 100 of fig. 1 are shown, namely the amplifier 102, the ADC 1108, the ADC2118, the external current source I_SNSA SENSE pin and a transimpedance gain element Rf. Additionally, calibration engine 702 receives the outputs of ADC 1108 and ADC 2118. Calibration engine 702 calibrates transimpedance gain element Rf using ADC 108/118 as follows.

Output voltage V_TIAOCan be calculated as the sensed current I_SNSHarmony between resistance and energyThe product of the components Rf is shown in equation (1).

V_TIAO＝I_snsR_f (1)

Calibration engine 702 may perform a digital calibration loop according to one embodiment, as described below with respect to equations (2) through (5). Let N be_RfRepresenting a transimpedance gain element R_fIs shown in (a). Let N be_TIAORepresenting the output of the ADC 2118. Let N be_TIAORepresenting the output of ADC 1108. Let k represent the output N_TIAOCurrent of (I)_SNSIs calculated as shown in equation (2).

During manufacture of the system 100, an external current source I may be used_SNSA current k is applied and a digital output N can be read_TLAO-1And the actual value of Rf can be calculated using equations (3) and (4).

Then the calibrated output can be derived in the presence of the excitation output according to equation (5).

Each output sample of the ADC2118 may be calibrated. In this way, a transimpedance gain element R can be realized_fHigh accuracy calibration. The accuracy is effectively limited only by the external current source and the ADC 108/118 accuracy. In one embodiment, alternating current may be used to remove the dependence on any dc offset in the system 100. In one embodiment, a transimpedance gain element accuracy of ± 1% is achieved。

It should be appreciated that those of ordinary skill in the art, having the benefit of the present disclosure in particular, will appreciate that the various operations described herein, and in particular the operations described in connection with the figures, may be implemented by other circuitry or other hardware components. Unless otherwise specified, the order of performing each operation of a given method can be changed, and various elements of the systems illustrated herein can be added, reordered, combined, omitted, modified, and so forth. The disclosure is intended to embrace all such modifications and variations, and therefore the above description should be taken in an illustrative rather than a restrictive sense.

Similarly, while the present disclosure is directed to particular embodiments, certain modifications and changes may be made to these embodiments without departing from the scope and coverage of this disclosure. Moreover, any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element.

As such, additional embodiments having the benefit of the present disclosure will be apparent to those having ordinary skill in the art and should be considered as being encompassed herein. All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions.

The present disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Furthermore, references in the appended claims to a device or system or a component of a device or system adapted, arranged, capable, configured, enabled, operable, or operable to perform a particular function encompass the device, system, or component, whether or not it or the particular function is activated, turned on, or unlocked, provided that the device, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operable.