阅读说明：本技术 采用可变尾数大小的数据压缩 (Data compression with variable mantissa size ) 是由 马可·J·G·贝库伊 费克·戈斯·詹森 于 2021-06-18 设计创作，主要内容包括：示例性方面针对或涉及一种用以经由通信信道发射信号且接收反射雷达信号的雷达收发器。示例性方法包括雷达接收器数据处理电路系统,所述雷达接收器数据处理电路系统可以用于区分接收到的信号的表示的子集。此区分可以用于选择与所述接收到的信号中的其它信号相比更多地指示具有给定距离的目标的信号。接着可以通过使用具有至少部分地基于相应表示的至少一个强度特性而变化的尾数值的可变尾数浮点数来压缩所述接收到的信号的表示。(Exemplary aspects are directed or related to a radar transceiver to transmit signals and receive reflected radar signals via a communication channel. An example method includes radar receiver data processing circuitry that may be used to distinguish a subset of representations of received signals. This distinction may be used to select signals that are more indicative of a target having a given distance than other ones of the received signals. The representation of the received signal may then be compressed by using a variable mantissa floating point number having a mantissa value that varies based at least in part on at least one strength characteristic of the corresponding representation.)

1. An apparatus, comprising:

a radar transceiver to transmit a radar signal and receive a signal in response via a communication channel; and

data processing circuitry to distinguish a subset of representations of received signals as selected ones of the received signals that are more indicative of at least one target having a given distance than other ones of the received signals, and to compress the representations using a variable mantissa floating point number having a mantissa value that varies based at least in part on at least one intensity characteristic of the respective representations.

2. The apparatus of claim 1, further comprising memory circuitry, and wherein the radar transceiver is to store the selected ones of the received signals in the memory circuitry prior to the data processing circuitry to compress the representation via the variable mantissa floating point number having a mantissa value that varies based at least in part on at least one strength characteristic.

3. The apparatus of claim 1, wherein the data processing circuitry comprises Fast Fourier Transform (FFT) circuitry to compress the representation, and wherein the at least one intensity characteristic comprises one or a combination of: an amplitude evaluation, a signal-to-noise ratio evaluation, and an evaluation based on at least one peak parameter associated with the received signal.

4. The apparatus of claim 1, wherein the data processing circuitry comprises Fast Fourier Transform (FFT) circuitry to compress the representation, and wherein after sufficient data is collected to discern a velocity associated with the at least one target, the data processing circuitry is to decompress the compressed representation.

5. The apparatus of claim 1, further comprising memory circuitry and Fast Fourier Transform (FFT) circuitry to compress and store the compressed representation in the memory circuitry, and after sufficient data is collected to discern a velocity associated with the at least one target, the data processing circuitry to decompress the compressed representation, and wherein in response the data processing circuitry is further to detect the at least one target using the corresponding decompressed representation and a range-doppler plot.

6. The apparatus of claim 1, wherein the data processing circuit is further operative to use a corresponding decompressed representation of the compressed representation and a range-doppler plot to detect the at least one target in terms of at least two of: position, velocity, and heading angle.

7. The apparatus of claim 1, further comprising memory circuitry and Fast Fourier Transform (FFT) circuitry to compress the representation and store the compressed representation in the memory circuitry, and wherein the memory circuitry and FFT are part of a single integrated circuit chip.

8. The apparatus of claim 1, further comprising memory circuitry and Fast Fourier Transform (FFT) circuitry to compress the representation and store the compressed representation in a range bin of the memory circuitry, and wherein each of at least one of the variable mantissa floating point numbers is associated with an exponent value that is shared by or common to a plurality of range bins of the range bins of different chirps or chirp sequences.

9. The apparatus of claim 1, further comprising memory circuitry having a temporary memory configuration to store the subset of the representation of the received signal for use prior to the data processing circuitry to compress the representation via the variable mantissa floating point number, wherein the subset of the representation of the received signal is responsive to being processed by the data for each of a plurality of distance-based training operations in which the data processing circuitry is to distinguish the subset of the representation of the received signal.

10. A method, comprising:

in a radar transceiver using a communication channel over which radar signals are transmitted and in response signals are received, distinguishing a subset of representations of received signals as selected ones of the received signals, the selected signals being more indicative of at least one target having a given distance than others of the received signals, and compressing the representations by using a variable mantissa floating point number having a mantissa value that varies based at least in part on at least one strength characteristic of the respective representations.

Technical Field

Aspects of the various embodiments are directed to a radar transceiver system having circuitry to identify targets in noisy environments, and methods for reducing memory requirements in such a system by compressing processed and stored receiver data via variable-size mantissas.

Background

In radar systems, it is crucial to accurately discern the target from noise. This is typically accomplished using signal processing circuitry which may involve, among other techniques, compression circuitry and/or processing transform circuitry, such as Fast Fourier Transforms (FFTs) and memory storage of the resulting data. In methods that calculate terms such as distance and velocity of the target, the memory requirements may become excessive. This memory may occupy a large Integrated Circuit (IC) area and, therefore, may be very expensive to integrate on the same IC as the processor and other desired circuitry. In addition, larger memories may result in higher leakage power, which requires expensive packaging and heat sinks to keep the IC temperature low enough. While aspects of the present disclosure have been shown to be beneficial when used in the context of such received FMCW radar signals, and while the following discussion uses this context as an example to understand such aspects, the present disclosure is not necessarily limited thereto.

These and other issues have presented challenges to the cost and efficiency of radar implementations for various applications.

Disclosure of Invention

Various examples of the present disclosure are directed to problems such as those set forth above and/or other problems that may become apparent from the following disclosure regarding data compression in radar transceiver systems. Various more specific examples in accordance with the present disclosure are described below that are not necessarily limited to or directed to such issues.

In certain example embodiments, aspects of the present disclosure relate to radar transceiver systems having circuitry to identify targets in noisy environments, and methods for reducing memory requirements in such systems by compressing data in received data processed and stored via floating point numbers having variable-size mantissas.

In a more specific example, embodiments are directed or related to a radar transceiver to transmit signals and receive reflected radar signals via a communication channel. An exemplary method in this context includes data processing circuitry (e.g., in a radar receiver) that can be used to distinguish a subset of the representations of received signals. This distinction may be used to select signals that are more indicative of a target having a given distance than other ones of the received signals. The representation of the received signal may then be compressed by using a variable mantissa floating point number having a mantissa value that varies based at least in part on at least one intensity characteristic (e.g., amplitude, SNR, peak value, etc.) of the corresponding representation.

In another specific example embodiment, the radar receiver includes memory circuitry and transform (e.g., FFT or other) circuitry to compress the representation and store the compressed representation in the memory circuitry. After sufficient data is collected, the compressed data may be used to discern velocity information associated with the at least one target. The compressed representation may then be decompressed and used with a range-doppler plot to detect targets.

Another particular example may relate to a radar transceiver using a communication channel over which radar signals are transmitted and signals are received in response. Then, a subset of the representations of the received signals is distinguished as selected ones of the received signals, the selected signals being more indicative of at least one target having a given distance than others of the received signals. The representation may then be compressed by using a variable mantissa floating point number having a mantissa value that varies based at least in part on at least one intensity characteristic of the corresponding representation.

In another related example, this (radar receiver) includes memory circuitry to compress the representation and store the compressed representation in a range bin of the memory circuitry, wherein each of the one or more variable mantissa floating point numbers has a bit having a mantissa value, the mantissa value being associated with an exponent value, the exponent value being shared by or common to multiple range bins of the range bins of different chirps or chirp sequences.

The above discussion/summary is not intended to describe each embodiment or every implementation of the present disclosure. The figures and the detailed description that follow further illustrate various example embodiments.

Circuitry for compressing the representation to be discarded from the temporary memory configuration.

In another related example, the apparatus additionally includes memory circuitry, first transformation circuitry to compress the representation and store the compressed representation in a range bin of the memory circuitry, and second transformation circuitry to decompress the compressed representation for detecting the at least one target.

In another related example, the other of the received signals is more likely to be associated with noise than the selected signal, and wherein the first transformation circuitry is further to use the memory circuitry to store representations of the other signals and the selected signal in the distance library associated with one of a plurality of axes of a storage array in the memory circuitry, and the second transformation circuitry is further to use another axis of the plurality of axes of the storage array to store speed indication data based on decompression of the compressed representation.

In another related example, the apparatus additionally includes memory circuitry to compress the representation and store the compressed representation in a distance library of the memory circuitry, wherein each of the at least one variable mantissa floating point number is associated with an exponent value that is shared by or common to a plurality of the distance libraries of different chirps or chirp sequences.

In another related example, the radar transceiver is to transmit and receive Frequency Modulated Continuous Wave (FMCW) radar signals, and wherein the mantissa values are limited to be selected from a set of predetermined mantissa sizes.

In another related example, the radar transceiver is part of a Frequency Modulated Continuous Wave (FMCW) radar system, wherein the radar transceiver is to transmit and receive FMCW radar signals, and the radar transceiver includes circuitry to compress the representation and store the compressed representation in a range bin, and further to compress data associated with a plurality of subsequent chirps and store the compressed data associated with the plurality of subsequent chirps in a single memory word.

Drawings

Various exemplary embodiments may be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, in which:

fig. 1 is a block diagram illustrating an example of a Frequency Modulated Continuous Wave (FMCW) radar system according to the present disclosure;

fig. 2 is a block diagram illustrating an example of data flow in an FMCW radar system according to the present disclosure;

FIG. 3 is a block diagram illustrating an example of variable mantissa sizes applied to various distance bins in accordance with the present disclosure;

fig. 4 is a block diagram illustrating an example of sharing exponent and mantissa sizes among various range bins for multiple (e.g., two or more) receive antennas in accordance with the present disclosure; and is

FIG. 5 is a block diagram illustrating an example of shared exponents and same mantissa sizes in various range bins for different receive antennas and same range bins in accordance with the present disclosure;

while the various embodiments discussed herein are susceptible to various modifications and alternative forms, various aspects of the various embodiments have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure, including aspects defined in the claims. In addition, the term "example" as used throughout this application is for illustration only, and not for limitation.

Detailed Description

Aspects of the present disclosure are believed to be applicable to a variety of different types of devices, systems, and methods involving circuitry configured to process signals such as received FMCW radar signals (e.g., for use in vehicle collision detection and autonomous driving assistance). Storing the results of the processed radar signal requires a large amount of memory (typically several megabytes of memory). This memory may occupy a large Integrated Circuit (IC) area and, therefore, may be very expensive to integrate on the same IC as the processor and other desired circuitry. In addition, larger memories may result in higher leakage power, which requires expensive packaging and heat sinks to keep the IC temperature low enough. While aspects of the present disclosure have been shown to be beneficial when used in the context of such received FMCW radar signals, and while the following discussion uses this context as an example to understand such aspects, the present disclosure is not necessarily limited thereto.

Thus, in the following description, numerous specific details are set forth to describe specific examples presented herein. It should be apparent, however, to one skilled in the art that one or more other examples and/or variations of these examples may be practiced without all of the specific details set forth below. In other instances, well-known features have not been described in detail so as not to obscure the description of the examples herein. For purposes of illustration, the same reference numbers may be used in different drawings to identify the same elements or additional examples of the same elements. Also, while aspects and features may be described in various figures in some cases, it should be appreciated that features from one figure or embodiment may be combined with features of another figure or embodiment, even if the combination is not explicitly shown or explicitly described as a combination.

In accordance with specific examples of the present disclosure, embodiments are directed to or directed to a radar transceiver to transmit and receive radar signals over a communication channel. Exemplary radar receiver data processing circuitry may be used to distinguish a subset of the representations of the received signals. This distinction may be used to select signals that are more indicative of a target having a given distance than other ones of the received signals. The representation of the received signal may then be compressed by using a variable mantissa floating point number having a mantissa value that varies based at least in part on at least one intensity characteristic (e.g., amplitude, SNR, peak value, etc.) of the corresponding representation. The use of variable mantissa sizes may be helpful, for example, to reduce memory storage allocation size, reduce IC size, reduce power consumption, reduce IC die temperature, and the like.

In more specific examples consistent with the present disclosure, the radar receiver data processing circuitry may include Fast Fourier Transform (FFT) circuitry to compress the representation using one or more intensity characteristics including: an amplitude evaluation, a signal-to-noise ratio evaluation, or an evaluation based on at least one peak parameter associated with the received signal.

In yet another specific example, the radar receiver may have memory circuitry and FFT circuitry to compress the representation and store the compressed representation in the memory circuitry. After sufficient data is collected, the compressed data may be used to discern velocity information associated with the at least one target. The compressed representation can then be decompressed and used with the range-doppler plot to detect targets.

Turning now to the drawings, fig. 1 is a block diagram illustrating an example of a Frequency Modulated Continuous Wave (FMCW) radar system according to the present disclosure. The transmitter 110 generates an FMCW signal (e.g., 77GHz) to be transmitted via the transmit antenna 112. This signal may also contain frequency chirps, and each chirp is typically composed of a frequency ramp, which is a sinusoidal signal with linearly increasing frequency. The transmitted signals are reflected with respect to the target and these reflections are received by the RX antenna 114 of the radar system. A low frequency beat signal may be obtained after mixing the received signal with the transmitted signal in RX block 120. This beat signal may be digitized by an analog-to-digital converter (ADC) 130. The digitized beat signal may then be processed through an FFT 140 (or "range FFT"). The peaks resulting from this FFT processing may correspond to targets at different distances (spacings) from the radar. For example, for an N-point FFT, N output values may be generated, and each value may belong to one of N FFT bins. The output of each range FFT may be stored in memory 150. It should be noted that storing the results of the distance FFT (first FFT)140 may require a large amount of memory (e.g., several megabytes of memory). The array may be created by storing the distance FFT results for a predetermined number of chirps in the memory 150. Each row in this array may contain the results of a single range FFT. After transposing this array, a second FFT160 ("velocity FFT") may be computed on each row of the array. The results of this processing may be stored as an array in memory 150. This resulting array comprises a so-called range-doppler plot. The peak in magnitude in this range-doppler plot may correspond to a target having a particular range and velocity as distinguished by the detection block 170.

Fig. 2 shows an example block diagram of the hardware architecture of an FMCW radar system including data flow through the system (dashed lines). An RF front end, labeled FE 220, transmits the chirp and receives a reflection of the chirp, and may downmix the received signal into an analog beat signal. This beat signal may be digitized and sent to a Digital Signal Processor (DSP) 230. This processor may perform a distance FFT function on each chirp and send the output of the chirp to the compression unit 235.

The (de) compression unit 235 may apply lossy compression to the FFT representation using variable mantissa floating point numbers having mantissa values that vary based on strength characteristics. This data may then be sent to the large L2 memory 240. After all of the processed chirps of the chirp training are received, data may be retrieved from the L2 memory 240. The address generation of this L2 memory 240 is such that array transposing occurs when reading columns in a matrix and storing data in rows. After sufficient data for one velocity FFT is read, the data may be decompressed by (de) compression block 235 and sent to DSP 250.

The DSP 250 may then perform a velocity FFT before obtaining the range-doppler plot. The DSP 250 may then use this range-doppler plot to perform detection of the object. The list of detections is sent to the microprocessor which sends the data to the output interface 255. It should be noted that in the discussion above regarding fig. 2, DSP blocks 230 and 250 may also be implemented in the same physical DSP. Similarly, memory blocks 225 and 245 may also be implemented in the same physical memory.

In another example, this circuitry does not use a shared bus as shown in fig. 2, but the data flow may occur on a more personalized/dedicated set of bus lines.

FIG. 3 is a block diagram illustrating an example of variable mantissa sizes applied to various distance bins. As discussed above, compression of data may involve applying a mantissa size that is not constant. The mantissa size may be different for each value in the distance FFT bin 310-. Larger mantissa sizes may be used where the magnitude in the range bin is larger. A larger mantissa size will result in a larger dynamic distance without introducing additional quantization noise and, therefore, will not mask weak signal components in the larger signal. Because larger mantissa sizes can only be used for distance bins containing larger signals (as may be the case for a small number of bins), the compression ratio can be higher than for compression schemes using fixed mantissa sizes for the same quality end result. It should be noted that the mantissa size may be stored in a table in memory in the compression unit.

FMCW radar systems may also function in so-called multimode operation. During this multi-mode operation, subsequent chirps may differ in frequency band and duration because they belong to different modes. Alternatively, in a so-called MIMO (multiple input multiple output) mode of operation, different parts of the scene may be illuminated or scanned by using multiple antennas. In multi-modal operation, each chirp belonging to a particular mode and the appropriate mantissa size may be calculated for each range bin. Fig. 3 shows an exemplary mantissa size for such subsequent chirps for one particular mode, while for another mode, the mantissa size may be quite different. The main differences are as follows: in multi-mode operation, subsequent chirps of the chirp training may have different mantissa sizes because they belong to different modes. In an improved multi-mode system, even more than two modes may be used.

Other examples according to the present disclosure are directed to usage optimization where it is possible to use one exponent per set of floating point numbers. This optimization does not necessarily introduce additional quantization noise or loss of dynamic distance if these floating point numbers have correlated magnitudes and are therefore comparable. This may be the case if multiple receive antennas are used. Fig. 4 is a block diagram illustrating an example optimization with respect to shared exponents and same mantissa sizes in various range bins for two receive antennas. In such examples, multiple antennas (e.g., two, three, or several antennas) may be used for or with associated FMCW circuitry and/or radar transceivers to allow detection of the angle of arrival of signals, and thus also the position of the target. The amplitude or respectively received signal is similar, since all Receiving (RX) antennas see the same target, and thus each RX antenna receives the signal of the object through the same radar cross section. In such an optimization example, a system similar to that of fig. 1 is used, including memory circuitry and FFT circuitry to compress the representation and store the compressed representation in a distance library of the memory circuitry. In the example shown in FIG. 4, the compressed data representation may have at least one variable mantissa floating point number having a mantissa value associated with an exponent value shared by or common to multiple distance bins of different chirps or chirp sequences.

The received data for several training chirps may be used for each mode of operation to determine a mantissa size for each range bin (e.g., local memory of 225 of fig. 2 may be used to temporarily store data associated with such training chirps as part of a training procedure). The training chirp can be used to discern which distance or distances are likely to have targets, and the scheme will only predict the larger mantissa size if these distances (indicated by the larger peaks as discussed in fig. 1). For example, from this received data, the difference of each data in each range bin belonging to different chirps is determined. After determining the mantissa size, the received data of the training and subsequent chirps may be compressed. In connection with the present disclosure, it has been surprisingly found that chirps belonging to the same so-called chirp training, which produce the same range-doppler image, are typically compressed. After chirp training, it is often assumed that the target may have moved so much that the mantissa size should be determined again using a few training chirps. The data representation from the training chirp may be temporarily stored in memory circuitry (e.g., in L2 memory 240 and/or local memory 225 via a micro memory matrix cube) and then discarded after use by data processing circuitry to compress the representation via, for example, variable mantissa floating point numbers. In such cases, a floating point number may have multiple mantissas and a shared exponent (which may occur, for example, if multiple Rx signals from different receive antennas are compressed together).

In another example in accordance with the present disclosure and further based on the aspects discussed above, data from the same range bin for subsequent chirps may have a shared exponent and the same mantissa size. For example, in the case where mantissas (e.g., 1 or 2 bits) are encoded using only a few bits, the number of bits used for exponent (5 bits) is relatively large. This is still the case if the index is already shared by data from different receive antennas. In this example, 2 x 4 x 1 to 8 bits are used for the mantissa (2 is because the number of bits is complex, 4 is because 4Rx antennas are assumed and each mantissa is 1 bit), and 5 bits are used for the exponent, which is still 5/13 to 38% of the bits used for the exponent. To reduce the consumption of indices, one index may be used that is common to the data of the same distance bin for two subsequent chirps, as shown in fig. 5. This is possible without a large loss of quantization noise, since in some cases the data in the same range bin for subsequent chirps are likely to have similar magnitudes. This may be due to the fact that after a short period of time between (e.g. FMCW) chirps, the scene with the object (in the field of view or field of view of the radar) does not change much. The relative processing cost of this method is: two chirps may be cached instead of one chirp, after which the data may be compressed; and decompression will produce two chirps. In some embodiments, because there is a limited amount of local memory near the processor, there may be a limit as to the number of chirps that this approach can be generalized to even larger numbers.

As an example, embodiments consistent with the present disclosure, the data processing circuitry may include FFT circuitry to compress the representation, which may then be stored in memory. After sufficient data is collected, data processing circuitry, such as a microcontroller or a special purpose computer (e.g., a digital signal processor), may read the compressed data from memory and then decompress the compressed data. The decompressed data may then be used to discern velocities associated with one or more objects of interest. Additionally, a decompressed representation of the compressed representation may be used with the range-doppler plot to detect the target of interest based on at least two of: position, velocity, and heading angle.

Other examples, also consistent with the present disclosure, include the use of memory circuitry and Fast Fourier Transforms (FFTs) to compress the representations and store the compressed representations in the memory circuitry, the examples being implemented as part of a single integrated circuit chip. In yet another example embodiment, an apparatus configured to discriminate a target from noise floor may involve first FFT circuitry and have memory circuitry to store representations of distance bins associated in a plurality of axis storage arrays in the memory circuitry. The second FFT circuit may involve the use of another plurality of axis storage arrays in the memory for storing the speed indication data based on decompressing the compressed representation.

Some further examples consistent with the present disclosure are also directed to the above issues and where the memory and memory controller may be optimized for a particular width of data words (e.g., 64 bits), using additional clock cycles if less than 64 bits are read or written, thereby reducing memory bandwidth (in some cases such memory controllers may not even be able to support words less than 64 bits). It is contemplated that these examples allow only 64-bit words to be read and written, and bits in memory can be designated as unused in a stored word even if there is a problem with the size of floating point numbers after compression not being a multiple of 64 bits. While this may significantly reduce the compression ratio, approaches (consistent with the present disclosure) to address this problem include: only a particular mantissa size is used; and alternatively, the data for the same range bin for multiple subsequent chirps is compressed and the compressed data is placed into a single memory word. In this regard, one example is to use only mantissa sizes of 3, 5, 7, 11 bits. For a 7-bit mantissa size, only 3 bits will be designated as unused in the 64-bit memory word since this would result in 7b 4Rx 2Cplx +5exp being 61 bits (7 bits, 4 antennas, 2 complex bits, and 5 exponent bits). However, for the 3-bit mantissa case, this would result in 3b 4Rx 2Cplx +5exp being 29 bits, and thus 35 bits would be disadvantageously unused in the 64-bit memory word. However, if the data of the same range gate of the 2 subsequent range gates is compressed, only 64-2 × 29-6 bits will remain unused. The downside of compressing and storing 2 range gates together is that: after decompression the data of 2 range gates are obtained, which need to be stored in a memory near the processor. Thus, the number of range gates that can be compressed and stored together in the 64-bit memory word(s) will be limited.

Also consistent with the present disclosure, another example apparatus may involve a radar transceiver that uses a communication channel over which radar signals are transmitted and signals are received in response. Then, the data processing includes distinguishing a subset of the representations of the received signals as selected ones of the received signals, the selected signals being more indicative of at least one target having a given distance than others of the received signals. The table may then be compressed by using a variable mantissa floating point number having a mantissa value that varies based at least in part on the at least one intensity characteristic of the corresponding representation.

In yet further examples, certain of the above aspects may be included as part of a sonar system and/or a radio telescope receiver or transceiver, wherein signals are transmitted and (reflected) signals are received via a communication channel. In these examples, the receiver portion of the device/system may include data processing circuitry that distinguishes a subset of the representations of the received signals. This distinction may be used to select signals that are more indicative of one or more targets having a given distance than other ones of the received signals. Processing (including compression and decompression) may continue as described above. More specifically, in some such examples, the representation of the received signal may then be compressed by using a variable mantissa floating point number having a mantissa value that varies based at least in part on at least one intensity characteristic (e.g., amplitude, SNR, peak value, etc.) of the corresponding representation.

Terms such as up/down or left/right arrows depicting signal or processing flows (e.g., as shown in fig. 1 and 2) may be used herein to refer to the relative positions of such flows as shown in the figures, and may be understood as being associated with signal/processing flows in two directions, even though unidirectional directions may be shown (e.g., block 220 of fig. 2). It is to be understood that the terminology is used for convenience only and that, in actual use, the disclosed structures may be oriented other than as shown in the figures. Accordingly, these terms should not be construed in a limiting manner.

Unless otherwise indicated, those skilled in the art will recognize that various terms as used in the specification, including the claims, imply ordinary meanings in the art. For example, the specification describes and/or illustrates various circuits or circuitry that may be used to implement aspects of the claimed disclosure, such as by way of various block, module, device, system, unit, controller and/or other circuit type depiction terms (e.g., the block/module reference numerals 110 and 220 and 255 of fig. 1 and 2 as described herein). Such circuits or circuitry is used with other elements to illustrate how certain embodiments may be carried out in the form or structure, steps, functions, operations, activities, and so forth. For example, in some of the embodiments discussed above, one or more modules are discrete logic circuits or programmable logic circuits configured and arranged to implement these operations/activities, as may be carried out in the methods shown in fig. 1 and 2. In some embodiments, such programmable circuitry is one or more computer circuits, including memory circuitry for storing and accessing programs to be executed as sets of instructions (and/or used as configuration data to define how the programmable circuitry performs), and the programmable circuitry performs the relevant steps, functions, operations, activities, etc. using algorithms or processes as described above. Depending on the application, the instructions (and/or configuration data) may be configured to be implemented in logic circuitry, where the instructions (whether characterized in the form of object code, firmware, or software) are stored in and accessible from memory (circuitry).

Based on the foregoing discussion and description, one skilled in the art will readily recognize that various modifications and changes may be made to the various embodiments without strictly following the exemplary embodiments and applications illustrated and described herein. For example, a method as illustrated in the figures may involve steps that are performed in various orders, where one or more aspects of embodiments herein are retained, or the method may involve fewer or more steps. Such modifications do not depart from the true spirit and scope of the various aspects of the present disclosure, including the aspects set forth in the claims.