阅读说明：本技术 一种处理电路及处理方法 (Processing circuit and processing method ) 是由 王政治 于 2020-12-29 设计创作，主要内容包括：本发明提供了一种处理电路及处理方法,包括一第一振荡电路、一第二振荡电路、一计数电路以及一控制电路。第一振荡电路接收一输入电压,并根据输入电压,产生一第一时钟信号。第二振荡电路接收一输出电压,并根据输出电压,产生一第二时钟信号。计数电路接收输出电压,并根据第一时钟信号,调整一第一计数值,以及根据第二时钟信号,调整一第二计数值。控制电路接收输出电压,并根据第一及第二计数值,判断输入电压是否受到攻击。本发明的处理电路可用以判断所述输入电压是否受到电源毛刺攻击,当具有安全防护的晶片被攻击而解除安全防护模式时,可及时避免晶片内的重要资料被窃取。(The invention provides a processing circuit and a processing method, comprising a first oscillating circuit, a second oscillating circuit, a counting circuit and a control circuit. The first oscillating circuit receives an input voltage and generates a first clock signal according to the input voltage. The second oscillating circuit receives an output voltage and generates a second clock signal according to the output voltage. The counting circuit receives the output voltage, adjusts a first counting value according to the first clock signal, and adjusts a second counting value according to the second clock signal. The control circuit receives the output voltage and judges whether the input voltage is attacked or not according to the first and second counting values. The processing circuit can be used for judging whether the input voltage is attacked by the power burr or not, and can prevent important data in a wafer from being stolen in time when the wafer with safety protection is attacked and the safety protection mode is released.)

1. A processing circuit, comprising:

the first oscillating circuit receives an input voltage and generates a first clock signal according to the input voltage;

the second oscillating circuit receives an output voltage and generates a second clock signal according to the output voltage;

the counting circuit receives the output voltage, adjusts a first counting value according to the first clock signal and adjusts a second counting value according to the second clock signal; and

the control circuit receives the output voltage and judges whether the input voltage is attacked or not according to the first counting value and the second counting value;

wherein the first oscillator circuit operates in an unprotected power domain and the second oscillator circuit, the counter circuit, and the control circuit operate in a protected power domain.

2. The processing circuit of claim 1, further comprising:

the power supply protection circuit is used for adjusting the input voltage and generating the output voltage;

the first oscillating circuit and the second oscillating circuit are both ring oscillators.

3. The processing circuit of claim 1, wherein the control circuit generates a first setting signal to the first oscillating circuit for setting the frequency of the first clock signal, and the control circuit generates a second setting signal to the second oscillating circuit for setting the frequency of the second clock signal.

4. The processing circuit of claim 1, wherein when the first count value or the second count value equals a preset value, the counting circuit enables an interrupt signal, such that the control circuit reads the first count value and the second count value.

5. The processing circuit of claim 4, wherein the control circuit determines whether a first difference between the first count value and the second count value is greater than a first threshold value when the first count value is equal to the predetermined value, and enables a first warning signal when the first difference is greater than the first threshold value.

6. The processing circuit of claim 5, wherein the control circuit determines whether a second difference between the first count value and the second count value is greater than a second threshold value when the second count value is equal to the predetermined value, and enables a second warning signal when the second difference is greater than the second threshold value.

7. The processing circuit of claim 4, wherein the counting circuit comprises:

a first counter, which adjusts the first count value according to the frequency of the first clock signal; and

and the second counter adjusts the second count value according to the frequency of the second clock signal.

8. A processing method for determining whether an input voltage is attacked, the processing method comprising:

adjusting the input voltage to generate an output voltage;

providing the input voltage to a first oscillating circuit for generating a first clock signal;

providing the output voltage to a second oscillating circuit for generating a second clock signal;

adjusting a first count value according to the first clock signal;

adjusting a second count value according to the second clock signal; and

and reading the first count value and the second count value to judge whether the input voltage is attacked or not.

9. The processing method of claim 8, further comprising:

judging whether the first count value or the second count value is equal to a preset value or not;

enabling an interrupt signal when the first count value or the second count value reaches the preset value; and

reading the first count value and the second count value when the interrupt signal is enabled.

10. The processing method of claim 9, further comprising:

when the first count value is equal to the preset value, judging whether a first difference value of the first count value and the second count value is larger than a first critical value;

when the second count value is equal to the preset value, judging whether a second difference value of the first count value and the second count value is larger than a second critical value; and

when the first difference is greater than the first critical value or the second difference is greater than the second critical value, it indicates that the input voltage is attacked.

Technical Field

The present invention provides a processing circuit, and more particularly, to a processing circuit for determining whether an input voltage is attacked by power glitch (power glitch).

Background

A power glitch (power glitch) attack is a common method for stealing data, so that a chip with security protection is attacked and then the security protection mode is released, thereby stealing important data in the chip.

Disclosure of Invention

The invention provides a processing circuit, which comprises a first oscillating circuit, a second oscillating circuit, a counting circuit and a control circuit. The first oscillating circuit receives an input voltage and generates a first clock signal according to the input voltage. The second oscillating circuit receives an output voltage and generates a second clock signal according to the output voltage. The counting circuit receives the output voltage, adjusts a first counting value according to the first clock signal, and adjusts a second counting value according to the second clock signal. The control circuit receives the output voltage and judges whether the input voltage is attacked or not according to the first and second counting values. The first oscillator circuit operates in an unprotected power domain. The second oscillating circuit, the counting circuit and the control circuit operate in a protected power domain.

The invention also provides a processing method for judging whether an input voltage is attacked or not. The processing method comprises adjusting input voltage to generate an output voltage; providing an input voltage to a first oscillating circuit for generating a first clock signal; providing the output voltage to a second oscillating circuit for generating a second clock signal; adjusting a first count value according to the first clock signal; adjusting a second count value according to the second clock signal; and reading the first and second count values to determine whether the input voltage is attacked.

The processing method of the present invention can be implemented by the processing circuit of the present invention, which is hardware capable of executing specific functions, or can be stored in a storage medium in the form of program code and implemented in combination with specific hardware. When the program code is loaded into and executed by an electronic device, processor, computer, or machine, the electronic device, processor, computer, or machine becomes a processing circuit for practicing the invention.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a processing circuit of the present invention.

FIG. 2 is another schematic diagram of the processing circuit of the present invention.

FIG. 3 is a schematic flow chart of a processing method according to the present invention.

FIG. 4 is another flow chart of the processing method of the present invention.

FIG. 5 is another flow chart of the processing method of the present invention.

Reference numerals:

100. 200: processing circuit

110. 210: power supply terminal

VIN: input voltage

VOUT: output voltage

120. 220, and (2) a step of: power supply protection circuit

130. 140, 230, 2420: oscillating circuit

150: counting circuit

160: control circuit

CK1, CK 2: clock signal

CNT1_ DAT, CNT2_ DAT: count value

PPG _ ALARM, NPG _ ALARM: warning signal

CK1_ FREQ _ SEL, CK2_ FREQ _ SEL: setting signal

INT: interrupt signal

CONT: control signal

CNT1_ SEL, CNT2_ SEL: setting signal

CNT1_ OV, CNT2_ OV: overflow signal

251. 252: counter with a memory

S310 to S314, S411 to S417, S511 to S520: step (ii) of

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. The present description provides various examples to illustrate the technical features of various embodiments of the present invention. The configuration of the elements in the embodiments is for illustration only and not for limiting the invention. In the embodiments, reference numerals and symbols are partially repeated to simplify the description, and do not indicate relevance between different embodiments.

FIG. 1 is a schematic diagram of a processing circuit of the present invention. As shown in fig. 1, the processing circuit 100 has a power source terminal 110 for receiving an input voltage VIN. In one embodiment, the power source terminal 110 is used as an input/output pin of the processing circuit 100 for receiving power (e.g., VIN) from the outside. In the present embodiment, the processing circuit 100 includes an oscillating circuit 130, an oscillating circuit 140, a counting circuit 150, and a control circuit 160.

The oscillating circuit 130 receives an input voltage VIN and generates a clock signal CK1 according to the input voltage VIN. In the present embodiment, the frequency of the clock signal CK1 varies with the input voltage VIN. For example, when the input voltage VIN increases, the frequency of the clock signal CK1 may become larger or smaller, and when the input voltage VIN decreases, the frequency of the clock signal CK1 may become smaller or larger. The present invention is not limited to the architecture of the oscillator circuit 130. Any circuit that adjusts the frequency of an output clock according to the level of an input voltage can be used as the oscillation circuit 130. In one embodiment, the oscillator circuit 130 is a ring oscillator (ring oscillator). In other embodiments, the oscillator circuit 130 is a voltage-controlled oscillator (VCO).

The oscillating circuit 140 receives an output voltage VOUT and generates a clock signal CK2 according to the output voltage VOUT. Since the characteristics of the oscillating circuit 140 are the same as those of the oscillating circuit 130, the details thereof are omitted. In the present embodiment, the difference between the oscillation circuits 130 and 140 is that the output voltage VOUT received by the oscillation circuit 140 is a protected voltage (protected power), and the input voltage VIN received by the oscillation circuit 130 is an unprotected voltage (un-protected power).

The counter circuit 150 receives the output voltage VOUT. In the present embodiment, the output voltage VOUT is an operation voltage of the counter circuit 150. Upon receiving the output voltage VOUT, the counter circuit 150 adjusts a count value CNT1_ DAT according to the clock signal CK1 and adjusts a count value CNT2_ DAT according to the clock signal CK 2. Since the output voltage VOUT is protected, the counting operation of the counting circuit 150 is not affected when the input voltage VIN is attacked by power glitch.

The control circuit 160 receives the output voltage VOUT. In the present embodiment, the output voltage VOUT is an operation voltage of the control circuit 160. After receiving the output voltage VOUT, the control circuit 160 determines whether the input voltage VIN is attacked by a power glitch according to the count value CNT1_ DAT and the count value CNT2_ DAT. In a possible embodiment, when the count value CNT1_ DAT is different from the count value CNT2_ DAT, it indicates that the input voltage VIN is attacked. For example, when the count value CNT1_ DAT is greater than the count value CNT2_ DAT, it indicates that the level of the input voltage VIN may change (e.g., pull up) due to an attack. Therefore, the control circuit 160 enables an ALARM signal PPG _ ALARM. When the count value CNT1_ DAT is smaller than the count value CNT2_ DAT, it indicates that the level of the input voltage VIN may decrease due to an attack. Thus, the control circuit 160 enables another ALARM signal NPG _ ALARM. In other embodiments, the control circuit 160 enables a single alert signal. In the present embodiment, the control circuit 160 enables the single alarm signal as long as the count value CNT1_ DAT is different from the count value CNT2_ DAT.

In other embodiments, the processing circuit 100 further includes a power protection circuit 120. The power protection circuit 120 adjusts the input voltage VIN to generate the output voltage VOUT. In one embodiment, the power protection circuit 120 steps up or down the input voltage VIN and takes the adjusted result as the output voltage VOUT. The present invention is not limited to the architecture of the power protection circuit 120. Any circuit capable of adjusting the input voltage VIN can be used as the power protection circuit 120. In one embodiment, the power protection circuit 120 is a Linear Regulator, such as a Low Dropout Regulator (Low drop out Linear Regulator). In this case, since the LDO does not utilize an external capacitor to stabilize the output voltage VOUT, the output voltage VOUT does not change due to power glitch attack. In the embodiment, the output voltage VOUT is a protected voltage, which is higher than the input voltage VIN.

In some embodiments, the control circuit 160 modifies the value of at least one flag, such as changing from 0 to 1, when the input voltage VIN is attacked. In this case, a tamper event management unit (TAMPER event management unit) performs a specific action according to the flag value, such as immediately stopping the operation of the processing circuit 100. In other embodiments, the tamper event management unit records the number of times the value of the flag changes from a value of 0 to a value of 1. In this case, the tamper event management unit may restore the flag value from a value of 1 to a value of 0. When the input voltage VIN is attacked again, the control circuit 160 modifies the flag again, such as changing from 0 to 1. In one possible embodiment, when the external voltage VIN is attacked for a number of times reaching an upper limit, the tamper event management unit may disable the processing circuit 100, such as instructing the power protection circuit 120 to stop providing the output signal VOUT.

In other embodiments, the control circuit 160 sets the initial frequencies of the clock signals CK1 and CK 2. In this example, the initial frequency of the clock signal CK1 is the same as the initial frequency of the clock signal CK 2. The invention does not limit how the control circuit 160 sets the initial frequencies of the clock signals CK1 and CK 2. In one embodiment, the control circuit 160 generates the setting signal CK1_ FREQ _ SEL to the oscillation circuit 130 for setting the initial frequency of the clock signal CK1, such as 100 MHz. In addition, the control circuit 160 further generates another setting signal CK2_ FREQ _ SEL to the oscillation circuit 140 for setting the initial frequency of the clock signal CK2, such as 100 MHz. Since the initial frequencies of the clock signals CK1 and CK2 are the same, the count value CNT1_ DAT is equal to the count value CNT2_ DAT in a normal case. However, when the level of the input voltage VIN changes due to an attack, the frequency of the clock signal CK1 also changes. At this time, since the frequency of the clock signal CK1 is not equal to the initial frequency, the count value CNT1_ DAT is different from the count value CNT2_ DAT. Therefore, the control circuit 160 knows that the input voltage VIN is under attack.

In one embodiment, when the count value CNT1_ DAT or CNT2_ DAT reaches a predetermined value, the counting circuit 150 enables an interrupt signal INT, so that the control circuit 160 reads the count value CNT1_ DAT and the count value CNT2_ DAT and operates according to the count value CNT1_ DAT and the count value CNT2_ DAT. For example, when the interrupt signal INT is enabled, the control circuit 160 generates a control signal CONT for suspending (stop) the counting circuit 150, so that the counting circuit 150 suspends the adjustment of the count value CNT1_ DAT and the count value CNT2_ DAT. In some embodiments, when the interrupt signal INT is enabled, the control circuit 160 commands the oscillation circuits 130 and 140 to stop generating the clock signals CK1 and CK2 by setting signals CK1_ FREQ _ SEL and CK2_ FREQ _ SEL. Therefore, the count circuit 150 stops adjusting the count value CNT1_ DAT and the count value CNT2_ DAT.

In other embodiments, the counting circuit 150 has a first counter and a second counter. In this example, the first counter adjusts the count value CNT1_ DAT according to the clock signal CK1, and the second counter adjusts the count value CNT2_ DAT according to the clock signal CK 2. In this example, the first counter enables the interrupt signal INT when the count value CNT1_ DAT is equal to a preset value. The second counter enables the interrupt signal INT when the count value CNT2_ DAT is equal to the preset value.

When the interrupt signal INT is enabled, the control circuit 160 determines whether the count value CNT1_ DAT is greater than the count value CNT2_ DAT. When the count value CNT1_ DAT is greater than the count value CNT2_ DAT, the control circuit 160 enables the ALARM signal PPG _ ALARM. When the count value CNT1_ DAT is less than the count value CNT2_ DAT, the control circuit 160 enables the alert signal NPG _ ALARM. In other embodiments, when the count value CNT1_ DAT is equal to the count value CNT2_ DAT, the control circuit 160 resets (reset) the count circuit 150 via the control signal CONT, so that the count value CNT1_ DAT and the count value CNT2_ DAT return to an initial value, such as the value 0. In this example, the control circuit 160 further instructs the counting circuit 150 to adjust the count value CNT1_ DAT and the count value CNT2_ DAT again according to the clock signals CK1 and CK2 through the control signal CONT.

The invention is not limited to how the control circuit 160 controls the counting circuit 150. In one possible embodiment, the control circuit 160 controls the counting circuit 150 by using a single control signal CONT. In this example, the counting circuit 150 performs different operations according to the frequency or voltage level of the control signal CONT. For example, when the control signal CONT is equal to a first level, the counting circuit 150 resets the count value CNT1_ DAT and the count value CNT2_ DAT. When the control signal CONT is equal to a second level, the counting circuit 150 stops adjusting the count value CNT1_ DAT and the count value CNT2_ DAT. When the control signal CONT is equal to a third level, the counting circuit 150 adjusts the count value CNT1_ DAT and the count value CNT2_ DAT according to the clock signals CK1 and CK 2. In other embodiments, the control circuit 160 generates a reset signal, a pause signal, and an enable signal, respectively. In this example, when the reset signal is enabled, the counter circuit 150 resets the count value CNT1_ DAT and the count value CNT2_ DAT. When the suspend signal is enabled, the counter circuit 150 stops adjusting the count value CNT1_ DAT and the count value CNT2_ DAT. When the enable signal is enabled, the counter circuit 150 adjusts the count value CNT1_ DAT and the count value CNT2_ DAT according to the clock signals CK1 and CK 2.

In the embodiment, since the input voltage VIN is vulnerable and serves as the operating voltage of the oscillating circuit 130, the oscillating circuit 130 operates in an unprotected power domain (un-protected power domain). In this example, since the output voltage VOUT is not varied by the variation of the input voltage VIN, and the input voltage VOUT is used as the operating voltage of the oscillation circuit 140, the counting circuit 150, and the control circuit 160, the oscillation circuit 140, the counting circuit 150, and the control circuit 160 operate in a protected power domain (protected power domain). When the input voltage VIN is attacked by the power glitch, the oscillation circuit 140, the counting circuit 150 and the control circuit 160 can still operate normally. In one embodiment, the power protection circuit 120, the oscillation circuit 140, the counting circuit 150 and the control circuit 160 are integrated in an Integrated Circuit (IC).

FIG. 2 is a diagram of another embodiment of a processing circuit according to the present invention. The processing circuit 200 has a power source terminal 210 for receiving an input voltage VIN, and includes a power protection circuit 220, oscillating circuits 230, 240, counters 251, 252, and a control circuit 260. The power protection circuit 220 adjusts the input voltage VIN to generate an output voltage VOUT. Since the characteristics of the power protection circuit 220 are similar to those of the power protection circuit 120 in fig. 1, the description thereof is omitted.

The oscillating circuit 230 receives the input voltage VIN and generates a clock signal CK1 according to the input voltage VIN. The oscillating circuit 240 receives the output voltage VOUT and generates a clock signal CK2 according to the output voltage VOUT. Since the characteristics of the oscillating circuits 230 and 240 are similar to those of the oscillating circuits 130 and 140 in fig. 1, the description thereof is omitted.

The counter 251 adjusts the count value CNT1_ DAT according to the frequency of the clock signal CK 1. In the present embodiment, when the count value CNT1_ DAT reaches a first predetermined value, the counter 251 enables an overflow signal CNT1_ OV. In one possible embodiment, the first preset value is stored in the counter 251. In this case, the control circuit 260 sends a setting signal CNT1_ SEL to the counter 251 for setting the first preset value.

In one embodiment, the counter 251 has a count register (not shown). The count register may have 16 bits (bit), but is not intended to limit the present invention. The count register determines to count using several bits according to the set signal CNT1_ SEL. For example, if the count register uses 8 bits to count the number of pulses of the clock signal CK1, the count register may count to a value of 255. In this example, when the number of pulses of the clock signal CK1 exceeds 255, the count register is overflowed (overfloww). Therefore, the overflow signal CNT1_ OV is enabled.

In the present embodiment, the control circuit 260 determines whether to read the count value CNT1_ DAT according to the overflow signal CNT1_ OV. For example, when the overflow signal CNT1_ OV is enabled, the control circuit 260 reads the count value CNT1_ DAT. At this time, the control circuit 260 also reads the count value CNT2_ DAT. However, when the overflow signal CNT1_ OV is not enabled, the control circuit 260 does not read the count value CNT1_ DAT.

The counter 252 adjusts the count value CNT2_ DAT according to the frequency of the clock signal CK 2. In the present embodiment, the counter 252 enables an overflow signal CNT2_ OV when the count CNT2_ DAT reaches a second predetermined value. When the overflow signal CNT2_ OV is enabled, the control circuit 260 reads the count value CNT2_ DAT. At this time, the control circuit 260 also reads the count value CNT1_ DAT. However, when the overflow signal CNT2_ OV is not enabled, the control circuit 260 does not read the count value CNT2_ DAT. Since the characteristics of the counter 252 are similar to those of the counter 251, they will not be described in detail.

In other embodiments, when overflow signal CNT1_ OV or CNT2_ OV is enabled, control circuit 260 instructs counter 251 and counter 252 to suspend adjusting count values CNT1_ DAT and CNT2_ DAT through control signal CONT. At this time, the control circuit 260 reads the count value CNT1_ DAT and the count value CNT2_ DAT. When the count value CNT1_ DAT and the count value CNT2_ DAT are not the same, it indicates that the input voltage VIN is attacked by a power glitch. Thus, the control circuit 260 enables the alert signal PPG _ ALARM or NPG _ ALARM.

After the ALARM signal PPG _ ALARM or NPG _ ALARM is enabled, the control circuit 260 resets the counter 251 and the counter 252 through the control signal CONT, so as to set the count value CNT1_ DAT and the count value CNT2_ DAT equal to an initial value, such as the value 0. Then, the control circuit 260 commands the counters 251 and 252 to adjust the count values CNT1_ DAT and CNT2_ DAT again according to the clock signal CK1 and the clock signal CK2 through the control signal CONT.

In other embodiments, the control circuit 260 knows whether the input voltage VIN is attacked by the power glitch according to the difference between the count value CNT1_ DAT and the count value CNT2_ DAT. For example, when the overflow signal CNT1_ OV is enabled, the control circuit 260 determines whether a first difference (CNT1_ DAT-CNT2_ DAT) between the count value CNT1_ DAT and the count value CNT2_ DAT is greater than a first threshold value. When the first difference value (CNT1_ DAT-CNT2_ DAT) is greater than the first threshold value, it indicates that the level of the input voltage VIN is pulled up due to the power glitch attack. Accordingly, the control circuit 260 enables the alert signal PPG _ ALARM. However, when the first difference value (CNT1_ DAT — CNT2_ DAT) is not greater than the first threshold value, it indicates that the variation of the input voltage VIN is not attacked by the power glitch, and may be a slight glitch. Therefore, the control circuit 260 does not enable the warning signal PPG _ ALARM and the warning signal NPG _ ALARM. At this time, the control circuit 260 resets the counters 251 and 252 to set the count values CNT1_ DAT and CNT2_ DAT equal to an initial value.

In another embodiment, when the overflow signal CNT2_ OV is enabled, the control circuit 260 determines whether a second difference (CNT2_ DAT-CNT1_ DAT) between the count values CNT2_ DAT and CNT1_ DAT is greater than a second threshold. When the second difference value (CNT2_ DAT-CNT1_ DAT) is greater than the second threshold value, it indicates that the level of the input voltage VIN is pulled down due to the power glitch attack. Accordingly, the control circuit 260 enables the alert signal NPG _ ALARM. However, when the second difference value (CNT2_ DAT — CNT1_ DAT) is not greater than the second threshold value, it indicates that the variation of the input voltage VIN is not due to the power glitch attack. Therefore, the control circuit 260 does not enable the ALARM signals PPG _ ALARM and NPG _ ALARM and resets the counters 251 and 252.

In some embodiments, the control circuit 260 operates according to the clock signal CK 2. In this example, the clock signal CK2 serves as an operation clock for the control circuit 260. In the embodiment, the oscillation circuit 240, the counters 251, 252 and the control circuit 260 all use the output voltage VOUT as the operating voltage, so that the oscillation circuit 240, the counters 251, 252 and the control circuit 260 can still work normally when the input voltage VIN is attacked.

FIG. 3 is a schematic flow chart of a processing method according to the present invention. The processing method of the present invention can be executed by the control circuit 160 of fig. 1 or the control circuit 260 of fig. 2 to determine whether an input voltage is attacked. First, a setting operation is performed (step S310). In the present embodiment, step S310 includes steps S311 and S312. In step S311, an input voltage is adjusted to generate an output voltage. In one possible embodiment, the control circuit 160 of fig. 1 enables the power protection circuit 120. In this example, the power protection circuit 120 adjusts the input voltage VIN and takes the adjusted result as the output voltage VOUT.

Then, a first clock signal is generated according to the input voltage and a second clock signal is generated according to the output voltage (step S312). In one embodiment, a first oscillating circuit (e.g., 130 of FIG. 1) generates a first clock signal (e.g., CK1) according to an input voltage (e.g., VIN of FIG. 1), and a second oscillating circuit (e.g., 140 of FIG. 1) generates a second clock signal (e.g., CK2) according to an output voltage (e.g., VOUT of FIG. 1). In one embodiment, the control circuit 160 sends a first setting signal (e.g., CK1_ FREQ _ SEL) to the first oscillating circuit for setting the initial frequency of the first clock signal. In this case, the control circuit 160 further sends a second setting signal (e.g., CK2_ FREQ _ SEL) to the second oscillating circuit 140 for setting the initial frequency of the second clock signal. In this embodiment, the initial frequency of the first clock signal is the same as the initial frequency of the second clock signal. The present invention is not limited to the first and second oscillating circuits. In some embodiments, the first and second oscillator circuits are both ring oscillators.

The method further includes adjusting a first count value according to the first clock signal, and adjusting a second count value according to the second clock signal (step S313). In one embodiment, the first and second count values are provided by a counting circuit. For example, in fig. 1, the counting circuit 150 may reset the first and second count values (e.g., CNT1_ DAT and CNT2_ DAT) according to a control signal CONT, so that the first and second count values are equal to an initial value. In other embodiments, the counting circuit 150 may stop adjusting the first and second count values or start adjusting the first and second count values according to the control signal.

Then, it is determined whether the input voltage is attacked or not according to the first and second count values (step S314). In a possible embodiment, when the first count value is equal to the second count value, it indicates that the input voltage is not attacked. Therefore, the control circuit may reset the first and second count values such that the first and second count values are equal to an initial value. However, when the first count value is not equal to the second count value, it indicates that the input voltage is attacked. Therefore, the control circuit performs a specific operation, such as enabling an alarm signal.

In one embodiment, the control circuit reads the first and second count values when an interrupt signal is enabled. In this case, when the first or second count value is equal to a predetermined value, the counting circuit stops adjusting the first and second count values and enables an interrupt signal. Therefore, the control circuit reads the first and second count values and determines whether the first count value is equal to the second count value. In one embodiment, when the first count value is greater than the second count value, the level of the input voltage is increased due to the attack, and therefore the control circuit enables a first warning signal. When the first count value is smaller than the second count value, the level of the input voltage is decreased due to the attack, and therefore the control circuit enables a second warning signal. In other embodiments, the control circuitry records the number of attacks. When the number of attacks reaches an upper limit, the control circuit may halt the operation of all components.

FIG. 4 is another flow chart of the processing method of the present invention. Taking fig. 2 of the present invention as an example, first, the oscillation circuits 230 and 240 and the counters 251 and 252 are set (step S411). In one embodiment, the control circuit 260 sets the initial frequencies of the clock signals CK1 and CK2 generated by the oscillation circuits 230 and 240 by using the setting signals CK1_ FREQ _ SEL and CK2_ FREQ _ SEL. In some embodiments, the initial frequency of the clock signal CK1 is the same as the initial frequency of the clock signal CK 2. The control circuit 260 determines the number of bits in the count registers in the counters 251 and 252 by using the setting signals CNT1_ SEL and CNT2_ SEL to set the upper limit values of the counts in the counters 251 and 252. In the present embodiment, the counters 251 and 252 have the same upper limit count value (e.g., the value 6).

The counter 251 and the counter 252 are started (step S412). In the present embodiment, the counter 251 adjusts the count value CNT1_ DAT according to the number of pulses of the clock signal CK1, and the counter 252 adjusts the count value CNT2_ DAT according to the number of pulses of the clock signal CK 2. In one embodiment, the counter 251 counts the number of rising edges (rising edges) or falling edges (falling edges) of the clock signal CK 1. In this example, the counter 252 also counts the number of rising edges or falling edges of the clock signal CK 2.

Then, it is determined whether the overflow signal CNT1_ OV of the counter 251 or the overflow signal CNT2_ OV of the counter 252 is enabled (step S413). In one embodiment, the counter 251 enables the overflow signal CNT1_ OV when the count value CNT1_ DAT reaches a first upper limit value. Similarly, when the count value CNT2_ DAT reaches a second upper limit, the counter 252 enables the overflow signal CNT2_ OV.

When neither of the overflow signals CNT1_ OV nor CNT2_ OV is enabled, the process returns to step S413 to continue counting the number of pulses of the clock signals CK1 and CK 2. However, when the overflow signal CNT1_ OV or CNT2_ OV is enabled, the counting operations of the counter 251 and the counter 252 are stopped (step S414). Accordingly, the counters 251 and 252 stop adjusting the count values CNT1_ DAT and CNT2_ DAT.

Next, it is determined whether the overflow signal CNT1_ OV is enabled (step S415). When the overflow signal CNT1_ OV is enabled, it indicates that the level of the input voltage VIN is rising due to the attack. Accordingly, an ALARM signal PPG _ ALARM is enabled (step S416). In one embodiment, step S416 further resets the counters 251 and 252, such that the count values CNT1_ DAT and CNT2_ DAT return to an initial value (e.g., 0), and step S412, the number of pulses of the clock signals CK1 and CK2 are counted again.

However, when the overflow signal CNT1_ OV is not enabled, it indicates that the overflow signal CNT2_ OV is enabled. At this time, since the level of the input voltage VIN is pulled down by the attack, an ALARM signal NPG _ ALARM is enabled (step S417). In one embodiment, step S417 further resets the counters 251 and 252, such that the count values CNT1_ DAT and CNT2_ DAT return to an initial value (e.g., 0), and then the clock signals CK1 and CK2 are counted again in step S412.

FIG. 5 is another flow chart of the processing method of the present invention. The processing method of fig. 5 may also be accomplished using the control circuit 260 of fig. 2. Since the characteristics of steps S511 to S515 of fig. 5 are similar to those of steps S411 to S415 of fig. 4, detailed description thereof is omitted.

Step S515 determines whether the overflow signal CNT1_ OV is enabled. When the overflow signal CNT1_ OV is enabled, the control circuit 260 determines whether a first difference (CNT1_ DAT-CNT2_ DAT) between the count value CNT1_ DAT and the count value CNT2_ DAT is greater than a first threshold value (step S516). When the first difference value (CNT1_ DAT-CNT2_ DAT) is greater than the first threshold value, it indicates that the level of the input voltage VIN is increased due to an attack. Accordingly, an ALARM signal PPG _ ALARM is enabled (step S517). In one embodiment, step S517 further resets the counters 251 and 252, such that the count values CNT1_ DAT and CNT2_ DAT return to an initial value (e.g., 0), and step S512 re-counts the number of pulses of the clock signals CK1 and CK 2. However, when the first difference value (CNT1_ DAT — CNT2_ DAT) is not greater than the first threshold value, it indicates that the level change of the input voltage VIN is not attacked. Therefore, the control circuit 260 resets the counters 251 and 252, and does not enable the ALARM signals PPG _ ALARM and NPG _ ALARM (step S518).

In step S515, when the overflow signal CNT1_ OV is not enabled, it indicates that the overflow signal CNT2_ OV is enabled. Accordingly, the control circuit 260 determines whether a second difference value (CNT2_ DAT-CNT1_ DAT) between the count value CNT2_ DAT and the count value CNT1_ DAT is greater than a second threshold value (step S519). When the second difference value (CNT2_ DAT-CNT1_ DAT) is greater than the second threshold value, it indicates that the level of the input voltage VIN is decreased due to the attack. Accordingly, an ALARM signal NPPG _ ALARM is enabled (step S520). In one embodiment, step S520 further resets the counters 251 and 252, such that the count values CNT1_ DAT and CNT2_ DAT return to an initial value (e.g., 0), and step S512 re-counts the number of pulses of the clock signals CK1 and CK 2. However, when the second difference value (CNT2_ DAT — CNT1_ DAT) is not greater than the second threshold value, it indicates that the level change of the input voltage VIN is not attacked. Therefore, the control circuit 260 resets the counters 251 and 252, and does not enable the ALARM signals PPG _ ALARM and NPG _ ALARM (step S518).

The processing method of the present invention can exist in the form of program codes. The program code may be stored in a storage medium, such as a floppy disk, a compact disk, a hard disk, or any other machine-readable (e.g., computer-readable) storage medium, or may be a computer product in a non-limiting form, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes a processing circuit for practicing the invention. The program code may also be transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as a computer, the machine becomes a processing circuit for practicing the invention. When implemented in a general-purpose processing unit, the program code combines with the processing unit to provide a unique apparatus that operates analogously to application specific logic circuits.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as commonly understood by one of ordinary skill in the art to which this invention belongs. Moreover, unless expressly stated otherwise, the definition of a term in a general dictionary shall be construed as being consistent with its meaning in the context of the relevant art and shall not be construed as an idealized or overly formal definition.

Although the present invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, the systems, devices, or methods described in the embodiments of the present invention may be implemented in hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be defined by the appended claims.