阅读说明：本技术 一种有效抑制开关漏电的低功耗触发器 (Low-power-consumption trigger capable of effectively inhibiting switch electric leakage ) 是由 王梓淇 雷晓 黄少卿 肖培磊 连瑞 于 2021-09-29 设计创作，主要内容包括：本发明公开一种有效抑制开关漏电的低功耗触发器,属于数字电路领域,包括两个一致的逻辑单元逻辑A110和逻辑B120。逻辑A110中两对对偶连接MOS管交替导通产生高低电平,通过控制两列串联NMOS管的导通与关断产生第一个90°相移；所述逻辑A110的状态输出驱动下一个逻辑B120,完成前半周期触发状态；逻辑B120中两对对偶连接MOS管交替导通产生高低电平,通过控制两列串联NMOS管的导通与关断产生第二个90°相移,输出触发逻辑状态,并反馈至所述逻辑A110,完成后半周期的触发状态；至此两次90°相移叠加,完成180°整周期的下降沿触发,完成信号二分频。这种触发器内部逻辑对称,电平转换速度快,可以有效抑制开关漏电。(The invention discloses a low-power-consumption trigger capable of effectively inhibiting switch leakage, which belongs to the field of digital circuits and comprises a logic A110 and a logic B120 which are consistent. Two pairs of dual-connection MOS tubes in the logic A110 are alternately switched on to generate high and low levels, and a first 90-degree phase shift is generated by controlling the switching on and off of two rows of series NMOS tubes; the state output of the logic A110 drives the next logic B120 to complete the trigger state of the previous half period; two pairs of dual-connection MOS tubes in the logic B120 are alternately conducted to generate high and low levels, a second 90-degree phase shift is generated by controlling the conduction and the disconnection of two rows of series NMOS tubes, a trigger logic state is output and fed back to the logic A110, and the trigger state of a second half cycle is completed; so far, 90-degree phase shift superposition is carried out twice, falling edge triggering of a 180-degree whole period is completed, and signal frequency halving is completed. The trigger has symmetrical internal logic and high level conversion speed, and can effectively inhibit switch leakage.)

1. A low power consumption flip-flop effective to inhibit leakage from a switch, comprising:

the logic A110 is characterized in that two pairs of dual-connection MOS tubes are alternately conducted to generate high and low levels, and a first 90-degree phase shift is generated by controlling the conduction and the disconnection of two rows of series NMOS tubes; the state output of the logic A110 drives the next logic B120 to complete the trigger state of the previous half period;

the logic B120 is that two pairs of dual-connection MOS tubes are alternately conducted to generate high and low levels, a second 90-degree phase shift is generated by controlling the conduction and the disconnection of two series NMOS tubes, a trigger logic state is output and fed back to the logic A110, and the trigger state of the second half cycle is completed; so far, 90-degree phase shift superposition is carried out twice, falling edge triggering of a 180-degree whole period is completed, and signal frequency halving is completed.

2. The low power flip-flop of claim 1, wherein said logic a110 comprises PMOS transistors PM1 and PM2, NMOS transistors NM1, NM2, NM4, NM5, NM6, and NM 7;

the source electrode of the PMOS tube PM1 and the source electrode of the PMOS tube PM2 are both connected with power supply voltage, the grid electrode of the PMOS tube PM1 is connected with the drain electrode of the PMOS tube PM2, and the drain electrode of the PMOS tube PM1 is connected with the source electrode of the PMOS tube PM 2;

the sources of the NMOS transistors NM2, NM4, NM5 and NM7 are all grounded; the drain electrode of the NMOS tube NM1 is connected with the drain electrode of the NMOS tube NM4, the drain electrode of the PMOS tube PM1 and the grid electrode of the NMOS tube NM 5; the source electrode of the NMOS tube NM1 is connected with the drain electrode of the NMOS tube NM 2; the grid electrode of the NMOS tube NM4 is connected with the drain electrode of the NMOS tube NM5, and the grid electrode of the NMOS tube NM5 is connected with the drain electrode of the NMOS tube NM 4; the drain electrode of the NMOS tube NM6 is connected with the drain electrode of the NMOS tube NM5, the drain electrode of the PMOS tube PM2 and the grid electrode of the NMOS tube NM 4; the source electrode of the NMOS tube NM6 is connected with the drain electrode of the NMOS tube NM 7; the gate of the NMOS transistor NM2 and the gate of the NMOS transistor NM7 are simultaneously connected to an external input signal CPN.

3. The low power flip-flop of claim 2, wherein said logic B120 comprises PMOS transistors PM3 and PM4, NMOS transistors NM8, NM9, NM11, NM12, NM13, and NM 14;

the source electrode of the PMOS tube PM3 and the source electrode of the PMOS tube PM4 are both connected with power supply voltage, the grid electrode of the PMOS tube PM3 is connected with the drain electrode of the PMOS tube PM4, and the drain electrode of the PMOS tube PM3 is connected with the source electrode of the PMOS tube PM 4;

the sources of the NMOS transistor NM9, NM11, NM12 and NM14 are all grounded; the drain electrode of the NMOS tube NM8 is connected with the drain electrode of the NMOS tube NM11, the drain electrode of the PMOS tube PM3 and the grid electrode of the NMOS tube NM 12; the source electrode of the NMOS tube NM8 is connected with the drain electrode of the NMOS tube NM 9; the grid electrode of the NMOS tube NM11 is connected with the drain electrode of the NMOS tube NM12, and the grid electrode of the NMOS tube NM12 is connected with the drain electrode of the NMOS tube NM 11; the drain electrode of the NMOS tube NM13 is connected with the drain electrode of the NMOS tube NM12, the drain electrode of the PMOS tube PM4 and the grid electrode of the NMOS tube NM 11; the source electrode of the NMOS tube NM13 is connected with the drain electrode of the NMOS tube NM 14; the gate of the NMOS transistor NM9 and the gate of the NMOS transistor NM14 are simultaneously connected to an external input signal CP.

4. The low power consumption flip-flop according to claim 3, wherein an output terminal of said logic a110 is connected to a logic B120, an output terminal of said logic B120 is a flip-flop output terminal, and is fed back to said logic a110 to form a feedback loop; and the number of the first and second electrodes,

the output end a of the logic a110 is connected to the gate of the NMOS transistor NM13 in the logic B120; the output end B of the logic a110 is connected to the gate of the NMOS transistor NM8 in the logic B120; the output end C of the logic B120 is connected to the gate of the NMOS transistor NM1 in the logic a 110; the output end D of the logic B120 is connected to the gate of the NMOS transistor NM6 in the logic a 110.

5. The low power consumption flip-flop of claim 4, wherein said output C and said output D of said logic B120 are the output QN and Q of the flip-flop.

6. The low power flip-flop effective to suppress switch leakage of claim 5, wherein said low power flip-flop effective to suppress switch leakage further comprises NMOS transistors NM3 and NM 10;

the source electrode of the NMOS tube NM3 is grounded, and the drain electrode of NM3 is connected with the drain electrode of NM 1; NM3 gate connected input enable signal

The source of the NMOS transistor NM10 is grounded, the drain of NM10 is connected with the drain of NM8, the gate of NM10 is connected with an input enable signal

Technical Field

The invention relates to the technical field of digital circuits, in particular to a low-power-consumption trigger capable of effectively inhibiting switch electric leakage.

Background

The logic gate is used as a core unit of the digital circuit and comprises fixed structures such as an inverter, a NAND gate, a NOR gate and the like, and functional logic gates such as an exclusive OR, a trigger and the like. The trigger has wide application, rich structure change and various realization functions. The flip-flops include, but are not limited to, D flip-flops, RS flip-flops, JK flip-flops, T flip-flops, and the like.

Generally speaking, in practical digital systems, a large number of memory cells are often included, and they are often required to act synchronously at the same time; to this end, each memory cell circuit is supplied with a clock pulse CLK as a control signal, and only when CLK comes, the circuit is triggered and changes its output state in accordance with the input signal. Such a memory cell circuit that can only be operated when a clock signal is triggered is called a flip-flop to distinguish a latch that is not controlled by a clock signal. However, the conventional flip-flops often need logic gates to be formed together, which causes the problems of increased chip area and large leakage current.

Disclosure of Invention

The invention aims to provide a low-power-consumption trigger capable of effectively inhibiting switch leakage so as to solve the problems that the traditional trigger needs a logic gate composition to increase the chip area and has large leakage.

In order to solve the above technical problem, the present invention provides a low power consumption trigger for effectively suppressing switch leakage, including:

the logic A110 is characterized in that two pairs of dual-connection MOS tubes are alternately conducted to generate high and low levels, and a first 90-degree phase shift is generated by controlling the conduction and the disconnection of two rows of series NMOS tubes; the state output of the logic A110 drives the next logic B120 to complete the trigger state of the previous half period;

the logic B120 is that two pairs of dual-connection MOS tubes are alternately conducted to generate high and low levels, a second 90-degree phase shift is generated by controlling the conduction and the disconnection of two series NMOS tubes, a trigger logic state is output and fed back to the logic A110, and the trigger state of the second half cycle is completed; so far, 90-degree phase shift superposition is carried out twice, falling edge triggering of a 180-degree whole period is completed, and signal frequency halving is completed.

Optionally, the logic a110 includes PMOS transistors PM1 and PM2, NMOS transistors NM1, NM2, NM4, NM5, NM6, and NM 7;

the source electrode of the PMOS tube PM1 and the source electrode of the PMOS tube PM2 are both connected with power supply voltage, the grid electrode of the PMOS tube PM1 is connected with the drain electrode of the PMOS tube PM2, and the drain electrode of the PMOS tube PM1 is connected with the source electrode of the PMOS tube PM 2;

the sources of the NMOS transistors NM2, NM4, NM5 and NM7 are all grounded; the drain electrode of the NMOS tube NM1 is connected with the drain electrode of the NMOS tube NM4, the drain electrode of the PMOS tube PM1 and the grid electrode of the NMOS tube NM 5; the source electrode of the NMOS tube NM1 is connected with the drain electrode of the NMOS tube NM 2; the grid electrode of the NMOS tube NM4 is connected with the drain electrode of the NMOS tube NM5, and the grid electrode of the NMOS tube NM5 is connected with the drain electrode of the NMOS tube NM 4; the drain electrode of the NMOS tube NM6 is connected with the drain electrode of the NMOS tube NM5, the drain electrode of the PMOS tube PM2 and the grid electrode of the NMOS tube NM 4; the source electrode of the NMOS tube NM6 is connected with the drain electrode of the NMOS tube NM 7; the gate of the NMOS transistor NM2 and the gate of the NMOS transistor NM7 are simultaneously connected to an external input signal CPN.

Optionally, the logic B120 includes PMOS transistors PM3 and PM4, NMOS transistors NM8, NM9, NM11, NM12, NM13, and NM 14;

the source electrode of the PMOS tube PM3 and the source electrode of the PMOS tube PM4 are both connected with power supply voltage, the grid electrode of the PMOS tube PM3 is connected with the drain electrode of the PMOS tube PM4, and the drain electrode of the PMOS tube PM3 is connected with the source electrode of the PMOS tube PM 4;

the sources of the NMOS transistor NM9, NM11, NM12 and NM14 are all grounded; the drain electrode of the NMOS tube NM8 is connected with the drain electrode of the NMOS tube NM11, the drain electrode of the PMOS tube PM3 and the grid electrode of the NMOS tube NM 12; the source electrode of the NMOS tube NM8 is connected with the drain electrode of the NMOS tube NM 9; the grid electrode of the NMOS tube NM11 is connected with the drain electrode of the NMOS tube NM12, and the grid electrode of the NMOS tube NM12 is connected with the drain electrode of the NMOS tube NM 11; the drain electrode of the NMOS tube NM13 is connected with the drain electrode of the NMOS tube NM12, the drain electrode of the PMOS tube PM4 and the grid electrode of the NMOS tube NM 11; the source electrode of the NMOS tube NM13 is connected with the drain electrode of the NMOS tube NM 14; the gate of the NMOS transistor NM9 and the gate of the NMOS transistor NM14 are simultaneously connected to an external input signal CP.

Optionally, the output end of the logic a110 is connected to the logic B120, and the output end of the logic B120 is the output end of the flip-flop and is fed back to the logic a110 to form a feedback loop; and the number of the first and second electrodes,

the output end a of the logic a110 is connected to the gate of the NMOS transistor NM13 in the logic B120; the output end B of the logic a110 is connected to the gate of the NMOS transistor NM8 in the logic B120; the output end C of the logic B120 is connected to the gate of the NMOS transistor NM1 in the logic a 110; the output end D of the logic B120 is connected to the gate of the NMOS transistor NM6 in the logic a 110.

Optionally, the output terminal C and the output terminal D of the logic B120 are output terminals QN and Q of a flip-flop.

Optionally, the low power consumption trigger for effectively suppressing the switch leakage further includes NMOS transistors NM3 and NM 10; .

Optionally, the source of the NMOS transistor NM3 is grounded, and the drain of NM3 is connected to the drain of NM 1; NM3 gate connected input enable signal

The source of the NMOS transistor NM10 is grounded, the drain of NM10 is connected with the drain of NM8, the gate of NM10 is connected with an input enable signal

The low-power-consumption trigger capable of effectively inhibiting the switch from leaking electricity has the following beneficial effects:

(1) the structure is completely symmetrical, 90-degree phase shift is realized by the dual-connected PMOS and NMOS tubes, the structure can effectively inhibit switch electric leakage, the switch electric leakage can be effectively inhibited even if the conversion time of input signals is slow, and the electric leakage is extremely small;

(2) the structure is symmetrical, the later-stage layout drawing and the consistency of the MOS tube are greatly improved, and the layout area is reduced;

(3) the trigger is triggered by a falling edge, and the function of frequency halving is realized at the same time; enable logic may be added to provide the trigger with a clear function.

Drawings

FIG. 1 is a schematic diagram of a conventional flip-flop according to the present invention;

FIG. 2 is a schematic diagram of a flip-flop structure for effectively suppressing the leakage of a switch without an enable structure according to the present invention;

FIG. 3 is a schematic diagram of a flip-flop with an enable structure for effectively suppressing the leakage of a switch according to the present invention;

fig. 4 is a timing diagram of a flip-flop for effectively suppressing the leakage of the switch according to the present invention.

Detailed Description

The invention provides a low-power-consumption trigger for effectively suppressing switch leakage, which is described in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The invention provides a low-power-consumption trigger for effectively inhibiting switch leakage, which has a structure shown in fig. 2 and comprises a logic A110 and a logic B120. In the logic A110, two pairs of dual-connection MOS tubes are alternately switched on to generate high and low levels, and a first 90-degree phase shift is generated by controlling the switching on and off of two rows of series NMOS tubes; the state output of the logic A110 drives the next logic B120 to complete the trigger state of the previous half period; in the logic B120, two pairs of dual-connection MOS tubes are alternately switched on to generate high and low levels, a second 90-degree phase shift is generated by controlling the switching on and off of two rows of series NMOS tubes, a trigger logic state is output and fed back to the logic A110, and the trigger state of the second half cycle is completed; so far, 90-degree phase shift superposition is carried out twice, falling edge triggering of a 180-degree whole period is completed, and signal frequency halving is completed.

Continuing to refer to fig. 2, the logic a110 includes PMOS transistors PM1 and PM2, NMOS transistors NM1, NM2, NM4, NM5, NM6, and NM 7; the source electrode of the PMOS tube PM1 and the source electrode of the PMOS tube PM2 are both connected with power supply voltage, the grid electrode of the PMOS tube PM1 is connected with the drain electrode of the PMOS tube PM2, and the drain electrode of the PMOS tube PM1 is connected with the source electrode of the PMOS tube PM 2; the sources of the NMOS transistors NM2, NM4, NM5 and NM7 are all grounded; the drain electrode of the NMOS tube NM1 is connected with the drain electrode of the NMOS tube NM4, the drain electrode of the PMOS tube PM1 and the grid electrode of the NMOS tube NM 5; the source electrode of the NMOS tube NM1 is connected with the drain electrode of the NMOS tube NM 2; the grid electrode of the NMOS tube NM4 is connected with the drain electrode of the NMOS tube NM5, and the grid electrode of the NMOS tube NM5 is connected with the drain electrode of the NMOS tube NM 4; the drain electrode of the NMOS tube NM6 is connected with the drain electrode of the NMOS tube NM5, the drain electrode of the PMOS tube PM2 and the grid electrode of the NMOS tube NM 4; the source electrode of the NMOS tube NM6 is connected with the drain electrode of the NMOS tube NM 7; the gate of the NMOS transistor NM2 and the gate of the NMOS transistor NM7 are simultaneously connected to an external input signal CPN.

The logic B120 comprises PMOS tubes PM3 and PM4, NMOS tubes NM8, NM9, NM11, NM12, NM13 and NM 14; the source electrode of the PMOS tube PM3 and the source electrode of the PMOS tube PM4 are both connected with power supply voltage, the grid electrode of the PMOS tube PM3 is connected with the drain electrode of the PMOS tube PM4, and the drain electrode of the PMOS tube PM3 is connected with the source electrode of the PMOS tube PM 4; the sources of the NMOS transistor NM9, NM11, NM12 and NM14 are all grounded; the drain electrode of the NMOS tube NM8 is connected with the drain electrode of the NMOS tube NM11, the drain electrode of the PMOS tube PM3 and the grid electrode of the NMOS tube NM 12; the source electrode of the NMOS tube NM8 is connected with the drain electrode of the NMOS tube NM 9; the grid electrode of the NMOS tube NM11 is connected with the drain electrode of the NMOS tube NM12, and the grid electrode of the NMOS tube NM12 is connected with the drain electrode of the NMOS tube NM 11; the drain electrode of the NMOS tube NM13 is connected with the drain electrode of the NMOS tube NM12, the drain electrode of the PMOS tube PM4 and the grid electrode of the NMOS tube NM 11; the source electrode of the NMOS tube NM13 is connected with the drain electrode of the NMOS tube NM 14; the gate of the NMOS transistor NM9 and the gate of the NMOS transistor NM14 are simultaneously connected to an external input signal CP.

The output end of the logic a110 is connected to the logic B120, and the output end of the logic B120 is the output end of the flip-flop and is fed back to the logic a110 to form a feedback loop; the output end a of the logic a110 is connected to the gate of the NMOS transistor NM13 in the logic B120; the output end B of the logic a110 is connected to the gate of the NMOS transistor NM8 in the logic B120; the output end C of the logic B120 is connected to the gate of the NMOS transistor NM1 in the logic a 110; the output end D of the logic B120 is connected to the gate of the NMOS transistor NM6 in the logic a 110. The output terminal C and the output terminal D of the logic B120 are the output terminals QN and Q of the flip-flop.

The invention also provides a low power consumption trigger with an enabling structure for effectively suppressing the switch leakage, which has a structure shown in fig. 3, and compared with the low power consumption trigger with no enabling structure for effectively suppressing the switch leakage shown in fig. 2, the difference is that the low power consumption trigger with the enabling structure for effectively suppressing the switch leakage further comprises NMOS transistors NM3 and NM10, as shown in fig. 3The source of the NMOS tube NM3 is grounded, and the drain of the NM3 is connected with the drain of the NM 1; NM3 gate connected input enable signalThe source of the NMOS transistor NM10 is grounded, the drain of NM10 is connected with the drain of NM8, the gate of NM10 is connected with an input enable signal

Fig. 4 shows a timing diagram of the switch leakage trigger with effective suppression in this embodiment, where the first half is in an enabled state and the second half is disabled, and the working principle is as follows:

enable signalThe high-level zero clearing state is firstly changed into the low-level effective state, in the conversion process, the NMOS tube NM3 and the NMOS tube NM10 are changed into the off state from the on state, the levels of the output end A and the output end C are changed into the high level from the low level, and the output of the trigger is effective.

For logic a110, when the input signal CPN at the input terminal is low, the NMOS transistor NM2 and the NMOS transistor NM7 are turned off, and then the states of the NMOS transistor NM1 and the NMOS transistor NM6 will not affect the first half cycle; because the enable signal is converted from high level to low level, the voltage of the point A of the output end in the logic A110 is converted from low level to high level, the PMOS tube PM2 is switched off, the NMOS tube NM5 is switched on, the voltage of the drain electrode of the PMOS tube PM2, namely the voltage of the output end B, is pulled to low level, the NMOS tube NM4 is switched off, the PMOS tube PM1 is switched on, the voltage of the drain electrode of the PMOS tube PM1, namely the output end A, namely the voltage of the drain electrode of the PMOS tube PM1, is high level, the level conversion of the first half period of the input signal is completed, and the first 90-degree phase shift is generated.

For the logic B120, at this time, the input signal CP is at a high level, the NMOS transistor NM9 and the NMOS transistor NM14 are turned on, the output terminal B is connected to the gate of the NMOS transistor NM8, and the output is at a low level, then the NMOS transistor NM8 is turned off, and the output terminal C will not be affected by the NMOS transistor NM8 and the NMOS transistor NM 9; the output end A is connected with the grid electrode of the NMOS tube NM13 and the output is high level, then the NMOS tube NM13 is conducted, the output end D is influenced by the NMOS tube NM13 and the NMOS tube NM14, the potential of the output end D is low level, the grid electrode of the NMOS tube NM11 and the grid electrode of the PMOS tube PM3 are low level, then the NMOS tube NM11 is turned off, and the PMOS tube PM3 is conducted; at this time, the output terminal C is at a high level, the gate of the PMOS transistor PM4 and the gate of the NMOS transistor NM12 are connected to the output terminal C, so that the PMOS transistor PM4 is turned off, the NMOS transistor NM12 is turned on, the level of the input signal is shifted in the second half cycle, and a second 90 ° phase shift is generated.

The output end C and the output end D of the logic B120 are output ends QN and Q; meanwhile, the output terminal C and the output terminal D feed back the output signals to the NMOS transistor NM1 and the NMOS transistor NM6 of the logic a110, so as to form a complete loop.

The trigger provided by the invention has a frequency division function, the whole period of an input signal is a half period of an output signal, and therefore, the working principle is the first half period of the output signal; due to the consistent structure, i.e., the logic a110 and the logic B120 are in opposite states, the second half cycle of the output signal is realized.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.