阅读说明：本技术 显示基板和显示装置 (Display substrate and display device ) 是由 刘聪 黄耀 蔡建畅 程羽雕 吴超 于 2020-06-30 设计创作，主要内容包括：一种显示基板和显示装置,该显示基板包括：具有用于显示的第一侧和第二侧,包括：衬底基板；显示区,包括第一显示区和第二显示区,第一显示区包括多个像素单元组,多个像素单元组每个包括多个第一像素单元,多个第一像素单元的每个包括像素区和开口区；多条第一电源线,位于像素区；遮挡层,包括镂空区和遮挡区；对于一个像素单元组,各个第一像素单元的开口区与遮挡层的遮挡区至少部分重叠,至少一个第一像素单元的开口区包括第一遮挡连接部,与遮挡层的遮挡区至少部分重叠,且遮挡层通过第一遮挡连接部和多条第一电源线中的至少一条第一电源线连接。该显示基板可以在不降低像素密度的前提下,给遮挡层连接直流信号,防止遮挡层处于浮接状态。(A display substrate and a display device, the display substrate comprising: having a first side and a second side for display, comprising: a substrate base plate; a display area including a first display area and a second display area, the first display area including a plurality of pixel cell groups each including a plurality of first pixel cells each including a pixel area and an opening area; a plurality of first power lines in the pixel region; the shielding layer comprises a hollow-out area and a shielding area; for one pixel unit group, the opening area of each first pixel unit is at least partially overlapped with the shielding area of the shielding layer, the opening area of at least one first pixel unit comprises a first shielding connecting part which is at least partially overlapped with the shielding area of the shielding layer, and the shielding layer is connected with at least one first power line in a plurality of first power lines through the first shielding connecting part. The display substrate can connect a direct current signal to the shielding layer on the premise of not reducing the pixel density, and the shielding layer is prevented from being in a floating state.)

1. A display substrate having a first side for display and a second side opposite the first side, comprising:

a substrate base plate;

a display region disposed on the substrate, including a first display region and a second display region at least partially surrounding the first display region, wherein the first display region allows light from a first side of the display substrate to be at least partially transmitted to a second side of the display substrate for sensing, the first display region including a plurality of pixel cell groups arranged at intervals, the plurality of pixel cell groups each including a plurality of first pixel cells each including a pixel region and an opening region;

a plurality of first power lines positioned at the pixel region and configured to be connected to the plurality of pixel cell groups to supply a first power voltage to the plurality of pixel cell groups;

the shielding layer is arranged on the substrate base plate, is positioned on one side of the first power line close to the substrate base plate and comprises a hollow area and a shielding area;

wherein, for one pixel unit group, the opening area of each first pixel unit at least partially overlaps with the shielding area of the shielding layer,

the opening area of the at least one first pixel unit comprises a first shielding connecting part which is at least partially overlapped with the shielding area of the shielding layer, and the shielding layer is connected with at least one first power line in the plurality of first power lines through the first shielding connecting part to receive the first power voltage;

the first power lines are located on one side, away from the substrate base plate, of the first shielding connecting portion, the shielding layer is located on one side, close to the substrate base plate, of the first shielding connecting portion, and the first shielding connecting portion is located between the shielding layer and the first power lines.

2. The display substrate of claim 1, wherein the shielding layer is connected to the first shielding connection portion through a first via, and the first shielding connection portion is connected to the at least one first power line through a second via.

3. The display substrate of claim 2, wherein the display substrate further comprises a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first insulating layer is between the blocking layer and the first blocking connection portion,

the second insulating layer is positioned between the first insulating layer and the first shielding layer connecting part, and the third insulating layer is positioned between the first shielding connecting part and the plurality of first power lines; or, the second insulating layer is located between the first shielding connection portion and the plurality of first power lines, the third insulating layer is located between the second insulating layer and the plurality of first power lines,

the shielding layer is connected with the first shielding connecting part through a first via hole penetrating through the first insulating layer, and the first shielding connecting part is connected with the at least one first power line through a second via hole penetrating through the second insulating layer and the third insulating layer; or, the shielding layer is connected with the first shielding connecting part through a first via hole penetrating through the first insulating layer and the second insulating layer, and the first shielding connecting part is connected with the at least one first power line through a second via hole penetrating through the third insulating layer.

4. The display substrate of claim 3, wherein orthographic projections of the first and second vias on the substrate do not overlap;

the first power line comprises a protruding portion, an orthographic projection of the second via hole on the substrate base plate is overlapped with an orthographic projection of the protruding portion on the substrate base plate, and an orthographic projection of the first via hole on the substrate base plate is overlapped with an orthographic projection of the first power line on the substrate base plate.

5. The display substrate according to any one of claims 1 to 4, wherein adjacent pixel cell groups are connected by a trace, and an orthogonal projection of the plurality of pixel cell groups and the trace on the substrate falls within an orthogonal projection of a shielding region of the shielding layer on the substrate.

6. The display substrate according to any one of claims 1 to 4, wherein the second display region includes a plurality of second pixel units and a plurality of second power lines arranged in an array, each of the plurality of second pixel units including a pixel region and an opening region;

the plurality of second power lines are configured to be connected with the plurality of second pixel cells to supply a second power voltage to the plurality of second pixel cells, the second power voltage being the same as the first power voltage;

wherein, for one second pixel unit, the opening area of each second pixel unit at least partially overlaps with the shielding area of the shielding layer,

the opening area of the at least one second pixel unit comprises a second shielding connecting part, and the second shielding connecting part is at least partially overlapped with the shielding area of the shielding layer.

7. A display substrate according to any one of claims 1 to 4, wherein an orthographic projection of the second display area on the substrate falls within an orthographic projection of the blocking area of the blocking layer on the substrate.

8. The display substrate according to any one of claims 1 to 4, wherein each of the plurality of first pixel units and the plurality of second pixel units includes a pixel driving circuit configured to drive the light emitting device to emit light and a light emitting device.

9. The display substrate according to claim 8, wherein the pixel driving circuit comprises a driving transistor, a data writing transistor, a compensation transistor, a first light emission control transistor, a second light emission control transistor, a first reset transistor, a second reset transistor, and a storage capacitor;

wherein the active layers of the first reset transistor, the compensation transistor, the second emission control transistor, and the second reset transistor are located at a first semiconductor layer extending in a first direction, the active layers of the data write transistor and the first emission control transistor are located at a second semiconductor layer extending in a second direction, the first semiconductor layer and the second semiconductor layer are connected through the active layer of the driving transistor and integrally formed,

the active layer of the driving transistor is located on an imaginary line of the active layer of the first reset transistor in the first direction,

the active layers of the compensation transistor and the data writing transistor are respectively positioned at two sides of the active layer of the driving transistor and at one side of the active layer of the driving transistor close to the active layer of the first reset transistor,

the active layers of the second light-emitting control transistor and the first light-emitting control transistor are respectively positioned at two sides of the active layer of the driving transistor and at one side of the active layer of the driving transistor far away from the active layer of the first reset transistor,

the active layer of the second reset transistor is located on a side of the active layer of the second emission control transistor away from the active layer of the compensation transistor,

the compensation transistor includes a first gate extending in the first direction, a second gate extending in the second direction,

the second gate electrode is arranged side by side with the gate electrode of the second emission control transistor and the gate electrode of the second reset transistor extending in the second direction in the first direction,

a gate of the data writing transistor and a gate of the first light emission control transistor extend in the second direction and are arranged side by side in the first direction,

a gate of the first reset transistor and a gate of the driving transistor extend in the second direction and are arranged side by side in the first direction,

the gate of the driving transistor is integrally formed with the first plate of the storage capacitor.

10. The display substrate according to claim 9, further comprising a gate line, a light emission control signal line, a first reset signal line, and a second reset signal line extending in the second direction,

wherein a gate of the first reset transistor and the first reset signal line are connected and integrally formed,

the second gate electrode of the compensation transistor and the gate electrode of the data writing transistor are connected to the gate line and integrally formed,

a gate of the second light emission control transistor and a gate of the first light emission control transistor are connected to and integrally formed with the light emission control signal line,

the gate of the second reset transistor is connected to and integrally formed with the second reset signal line.

11. The display substrate of claim 10, further comprising a data line, wherein the data line is connected to an active layer of the data write transistor and configured to provide a data signal,

an orthographic projection of the first power supply line on the substrate base plate at least partially overlaps with orthographic projections of the active layer of the first reset transistor and the active layer of the drive transistor on the substrate base plate,

the orthographic projection of the data line on the substrate base plate is positioned on one side, away from the orthographic projection of the first power line on the substrate base plate, of the orthographic projection of the second semiconductor layer on the substrate base plate.

12. The display substrate of claim 11, wherein the pixel driving circuit further comprises a first relay electrode connected with the active layer of the second light emission control transistor, the active layer of the second reset transistor, and the first electrode of the light emitting device through a via hole,

an orthographic projection of the first transfer electrode on the substrate base plate is positioned between an orthographic projection of the active layer of the second reset transistor and an orthographic projection of the active layer of the driving transistor on the substrate base plate.

13. The display substrate according to claim 12, wherein, for each of the plurality of second pixel cells, an orthogonal projection of the second shield connection portion on the substrate is located between an orthogonal projection of the active layer of the second reset transistor on the substrate and an orthogonal projection of the second power supply line on the substrate, and at least partially overlaps with an orthogonal projection of the second power supply line on the substrate.

14. The display substrate according to claim 13, wherein the first shield connection portion is located between two first pixel cells adjacent in the first direction in each pixel cell group for each pixel cell group.

15. The display substrate according to claim 12, wherein an orthographic projection of the first shielding connection portion on the substrate is located between an orthographic projection of the active layer of the second reset transistor on the substrate and an orthographic projection of the first power supply line on the substrate, and at least partially overlaps with the orthographic projection of the first power supply line on the substrate.

16. The display substrate according to any one of claims 1 to 4, wherein the first shielding connecting portions are respectively located at two ends of each pixel unit group, and are connected to at least one of the plurality of first power lines respectively corresponding to the pixel unit groups.

17. The display substrate according to any one of claims 1 to 4, wherein the first shielding connection portions are respectively located at one end of each pixel unit group, and are connected to at least one of the plurality of first power lines corresponding to the pixel unit groups.

18. The display substrate according to claim 12, further comprising a fourth insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer;

wherein the first conductive layer includes the gate line, the second conductive layer includes a second plate of the storage capacitor, the third conductive layer includes the first power line,

in a direction perpendicular to the substrate base plate,

the fourth insulation is located between the barrier layer and the active layer of the transistor,

the first insulating layer is located between the active layer and the first conductive layer,

the second insulating layer is between the gate line and the second conductive layer,

the third insulating layer is located between the second plate of the storage capacitor and the third conductive layer.

19. The display substrate of claim 18, wherein the first shielding connection is located at the first conductive layer or the second conductive layer.

20. A display device comprising the display substrate of any one of claims 1-19 and a sensor,

the sensor is disposed on the second side of the display substrate and configured to receive light from the first side of the display substrate;

the orthographic projection of the sensor on the substrate base plate at least partially overlaps with the first display area.

Technical Field

At least one embodiment of the present disclosure relates to a display substrate and a display device.

Background

Based on the design of the under-screen camera, the display panel usually includes a high pixel density (Pixels Per inc, PPI) region and a low PPI region, however, the light transmittance of the general display panel in the low PPI region is low, which is not favorable for improving the display effect of the camera in the imaging region.

Disclosure of Invention

At least one embodiment of the present disclosure provides a display substrate having a first side for displaying and a second side opposite to the first side, including: a substrate base plate; a display region disposed on the substrate, including a first display region allowing light from a first side of the display substrate to be at least partially transmitted to a second side of the display substrate for sensing, and a second display region at least partially surrounding the first display region, the first display region including a plurality of pixel cell groups arranged at intervals, each of the plurality of pixel cell groups including a plurality of first pixel cells each including a pixel region and an opening region; a plurality of first power lines positioned at the pixel region and configured to be connected to the plurality of pixel cell groups to supply a first power voltage to the plurality of pixel cell groups; the shielding layer is arranged on the substrate base plate, is positioned on one side of the first power line close to the substrate base plate and comprises a hollow area and a shielding area; for one pixel unit group, the opening area of each first pixel unit at least partially overlaps with the shielding area of the shielding layer, the opening area of at least one first pixel unit comprises a first shielding connecting part at least partially overlapping with the shielding area of the shielding layer, and the shielding layer is connected with at least one first power line of the plurality of first power lines through the first shielding connecting part to receive the first power voltage; the first power lines are located on one side, away from the substrate base plate, of the first shielding connecting portion, the shielding layer is located on one side, close to the substrate base plate, of the first shielding connecting portion, and the first shielding connecting portion is located between the shielding layer and the first power lines.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the shielding layer is connected to the first shielding connecting portion through a first via hole, and the first shielding connecting portion is connected to the at least one first power line through a second via hole.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the display substrate further includes a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first insulating layer is located between the shielding layer and the first shielding connection portion, the second insulating layer is located between the first insulating layer and the first shielding layer connection portion, and the third insulating layer is located between the first shielding connection portion and the plurality of first power lines; or, the second insulating layer is located between the first shielding connection portion and the plurality of first power lines, the third insulating layer is located between the second insulating layer and the plurality of first power lines, the shielding layer is connected to the first shielding connection portion through a first via hole penetrating through the first insulating layer, and the first shielding connection portion is connected to the at least one first power line through a second via hole penetrating through the second insulating layer and the third insulating layer; or, the shielding layer is connected with the first shielding connecting part through a first via hole penetrating through the first insulating layer and the second insulating layer, and the first shielding connecting part is connected with the at least one first power line through a second via hole penetrating through the third insulating layer.

For example, in a display substrate provided in at least one embodiment of the present disclosure, orthographic projections of the first via hole and the second via hole on the substrate do not overlap; the first power line comprises a protruding portion, an orthographic projection of the second via hole on the substrate base plate is overlapped with an orthographic projection of the protruding portion on the substrate base plate, and an orthographic projection of the first via hole on the substrate base plate is overlapped with an orthographic projection of the first power line on the substrate base plate.

For example, in the display substrate provided in at least one embodiment of the present disclosure, adjacent pixel unit groups are connected by a trace, and an orthogonal projection of the plurality of pixel unit groups and the trace on the substrate falls into an orthogonal projection of the shielding region of the shielding layer on the substrate.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the second display region includes a plurality of second pixel units and a plurality of second power lines arranged in an array, and each of the plurality of second pixel units includes a pixel region and an opening region; the plurality of second power lines are configured to be connected with the plurality of second pixel cells to supply a second power voltage to the plurality of second pixel cells, the second power voltage being the same as the first power voltage; for one second pixel unit, the opening area of each second pixel unit at least partially overlaps with the shielding area of the shielding layer, the opening area of at least one second pixel unit comprises a second shielding connecting part, and the second shielding connecting part at least partially overlaps with the shielding area of the shielding layer.

For example, in the display substrate provided in at least one embodiment of the present disclosure, an orthogonal projection of the second display area on the substrate falls within an orthogonal projection of the shielding area of the shielding layer on the substrate.

For example, in a display substrate provided in at least one embodiment of the present disclosure, each of the plurality of first pixel units and the plurality of second pixel units includes a pixel driving circuit configured to drive the light emitting device to emit light and a light emitting device.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, a data writing transistor, a compensation transistor, a first light emission control transistor, a second light emission control transistor, a first reset transistor, a second reset transistor, and a storage capacitor; the active layers of the first reset transistor, the compensation transistor, the second emission control transistor, and the second reset transistor are located on a first semiconductor layer extending in a first direction, the active layers of the data write transistor and the first emission control transistor are located on a second semiconductor layer extending in a second direction, the first semiconductor layer and the second semiconductor layer are connected through the active layer of the driving transistor and integrally formed, the active layer of the driving transistor is located on an imaginary line of the active layer of the first reset transistor in the first direction, the active layers of the compensation transistor and the data write transistor are respectively located on both sides of the active layer of the driving transistor and on a side of the active layer of the driving transistor close to the active layer of the first reset transistor, the active layers of the second emission control transistor and the first emission control transistor are respectively located on a side of the active layer of the driving transistor The active layer of the second reset transistor is located on one side of the active layer of the second light-emitting control transistor, which is far away from the active layer of the compensation transistor, the compensation transistor comprises a first gate extending along the first direction and a second gate extending along the second direction, the second gate, the gate of the second light-emitting control transistor extending along the second direction and the gate of the second reset transistor are arranged side by side in the first direction, the gate of the data write transistor and the gate of the first light-emitting control transistor extend along the second direction and are arranged side by side in the first direction, and the gate of the first reset transistor and the gate of the drive transistor extend along the second direction, and are arranged side by side in the first direction, and the gate of the driving transistor is integrally formed with the first plate of the storage capacitor.

For example, at least one embodiment of the present disclosure provides a display substrate, further including a gate line, a light emission control signal line, a first reset signal line, and a second reset signal line extending in the second direction, wherein a gate of the first reset transistor and a gate of the first reset signal line are connected and integrally formed, a second gate of the compensation transistor and a gate of the data writing transistor are connected and integrally formed with the gate line, a gate of the second light emission control transistor and a gate of the first light emission control transistor are connected and integrally formed with the light emission control signal line, and a gate of the second reset transistor and a gate of the second reset signal line are connected and integrally formed with the second reset signal line.

For example, the display substrate provided by at least one embodiment of the present disclosure further includes a data line, wherein the data line is connected to the active layer of the data writing transistor and configured to provide a data signal, an orthogonal projection of the first power line on the substrate at least partially overlaps an orthogonal projection of the active layer of the first reset transistor and the active layer of the driving transistor on the substrate, and an orthogonal projection of the data line on the substrate is located on a side of an orthogonal projection of the second semiconductor layer on the substrate away from an orthogonal projection of the first power line on the substrate.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the pixel driving circuit further includes a first relay electrode connected to the active layer of the second emission control transistor, the active layer of the second reset transistor, and the first electrode of the light emitting device through a via hole, and an orthographic projection of the first relay electrode on the substrate is located between an orthographic projection of the active layer of the second reset transistor and an orthographic projection of the active layer of the driving transistor on the substrate.

For example, in the display substrate provided in at least one embodiment of the present disclosure, for each of the plurality of second pixel units, an orthogonal projection of the second shielding connection portion on the substrate is located between an orthogonal projection of the active layer of the second reset transistor on the substrate and an orthogonal projection of the second power supply line on the substrate, and at least partially overlaps with an orthogonal projection of the second power supply line on the substrate.

For example, in a display substrate provided in at least one embodiment of the present disclosure, for each pixel unit group, the first shielding connection portion is located between two first pixel units adjacent to each other in the first direction in each pixel unit group.

For example, in the display substrate provided in at least one embodiment of the present disclosure, an orthogonal projection of the first shielding connection portion on the substrate is located between an orthogonal projection of the active layer of the second reset transistor on the substrate and an orthogonal projection of the first power line on the substrate, and at least partially overlaps an orthogonal projection of the first power line on the substrate.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the first shielding connection portions are respectively located at two ends of each pixel unit group, and are connected to at least one of the plurality of first power lines respectively corresponding to the pixel unit groups.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the first shielding connection portions are respectively located at one end of each pixel unit group, and are connected to at least one of the plurality of first power lines corresponding to the pixel unit group.

For example, the display substrate provided in at least one embodiment of the present disclosure further includes a fourth insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer; the first conductive layer includes the gate line, the second conductive layer includes the second plate of the storage capacitor, the third conductive layer includes the first power line, in a direction perpendicular to the substrate, the fourth insulation layer is located between the shielding layer and the active layer of the transistor, the first insulation layer is located between the active layer and the first conductive layer, the second insulation layer is located between the gate line and the second conductive layer, and the third insulation layer is located between the second plate of the storage capacitor and the third conductive layer.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the first shielding connection portion is located on the first conductive layer or the second conductive layer.

At least one embodiment of the present disclosure further provides a display device, including the display substrate provided in any of the embodiments of the present disclosure, and a sensor disposed on the second side of the display substrate, and configured to receive light from the first side of the display substrate; the orthographic projection of the sensor on the substrate base plate at least partially overlaps with the first display area.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1A is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure;

fig. 1B is a schematic partial enlarged view of a display substrate according to at least one embodiment of the present disclosure;

fig. 1C is a partially enlarged schematic view of a display substrate according to at least another embodiment of the disclosure;

FIG. 1D is a schematic cross-sectional view taken along line B1-B2 shown in FIG. 1A;

fig. 2 is a schematic layout view of a pixel unit in a second display area according to at least one embodiment of the present disclosure;

fig. 3 is a schematic diagram of a first display area of a display panel according to at least one embodiment of the present disclosure;

fig. 4 is a schematic view of a display substrate according to at least one embodiment of the present disclosure;

fig. 5 is a schematic diagram of a pixel driving circuit according to at least one embodiment of the present disclosure;

FIG. 6A is a schematic diagram of a stacked structure of the pixel driving circuit shown in FIG. 5;

FIG. 6B is a schematic diagram of another stacked structure of the pixel driving circuit shown in FIG. 5;

FIG. 7 is a schematic cross-sectional view taken along line A-A' provided in accordance with at least one embodiment of the present disclosure;

FIG. 8 is a plan view of a semiconductor pattern of the display substrate shown in FIG. 6A;

FIG. 9 is a plan view of the first conductive layer of the display substrate shown in FIG. 6A;

FIG. 10 is a plan view of a second conductive layer of the display substrate shown in FIG. 6A;

FIG. 11 is a plan view of a third conductive layer of the display substrate shown in FIG. 6A;

fig. 12A is a schematic view of an example of a display substrate according to at least one embodiment of the present disclosure;

FIG. 12B is a plan view of a shielding region LS1 of a shielding layer LS of the display substrate shown in FIG. 12A;

FIG. 12C is a plan view of a semiconductor pattern of the display substrate shown in FIG. 12A;

FIG. 12D is a plan view of the first conductive layer of the display substrate shown in FIG. 12A;

FIG. 12E is a plan view of a second conductive layer of the display substrate shown in FIG. 12A;

FIG. 12F is a plan view of a third conductive layer of the display substrate shown in FIG. 12A;

fig. 13A is a schematic view of an example of another display substrate provided in at least one embodiment of the present disclosure;

FIG. 13B is a plan view of a shielding region LS1 of a shielding layer LS of the display substrate shown in FIG. 13A;

FIG. 13C is a plan view of a semiconductor pattern of the display substrate shown in FIG. 13A;

FIG. 13D is a plan view of the first conductive layer of the display substrate shown in FIG. 13A;

FIG. 13E is a plan view of the second conductive layer of the display substrate shown in FIG. 13A;

FIG. 13F is a plan view of a third conductive layer of the display substrate shown in FIG. 13A;

fig. 14A is a schematic view of an example of yet another display substrate provided in at least one embodiment of the present disclosure;

FIG. 14B is a plan view of a shielding region LS1 of a shielding layer LS of the display substrate shown in FIG. 14A;

FIG. 14C is a plan view of a semiconductor pattern of the display substrate shown in FIG. 14A;

FIG. 14D is a plan view of the first conductive layer of the display substrate shown in FIG. 14A;

FIG. 14E is a plan view of the second conductive layer of the display substrate shown in FIG. 14A;

FIG. 14F is a plan view of a third conductive layer of the display substrate shown in FIG. 14A;

fig. 15A is a schematic view of an example of yet another display substrate provided in at least one embodiment of the present disclosure;

FIG. 15B is a plan view of a shielding region LS1 of a shielding layer LS of the display substrate shown in FIG. 15A;

FIG. 15C is a plan view of a semiconductor pattern of the display substrate shown in FIG. 15A;

FIG. 15D is a plan view of the first conductive layer of the display substrate shown in FIG. 15A;

FIG. 15E is a plan view of the second conductive layer of the display substrate shown in FIG. 15A;

FIG. 15F is a plan view of a third conductive layer of the display substrate shown in FIG. 15A;

fig. 16 is a schematic view of a display device according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The OLED (Organic light-emitting diode) display technology has strong competitiveness in a display due to advantages of wide viewing angle, high contrast, fast response, low power consumption, foldability, flexibility and the like. With the wide development and deep application of OLED technology, the demand for display screens with higher screen occupation ratio is more and more strong. The leading camera of camera technique under the screen is located the screen below, can eliminate the fluting (notch) district that sets up leading camera, improves the screen and accounts for the ratio, has more excellent vision experience.

In order to enable more light to reach the front camera through the display panel, the PPI of the light-transmitting display area of the screen needs to be reduced, that is, the pixel density is reduced, but a large number of slits exist between pixel circuit wirings and between signal line connections between pixels, when the light passes through the slits, diffraction and interference occur, so that the brightness of the light reaching the camera is uneven, a glare phenomenon (too high brightness occurs at a certain local part in a visual field or too large brightness change occurs at the front and back), the visibility of an object is reduced, the imaging quality of the camera is reduced, and visual fatigue is easily caused.

At present, one solution is: a metal layer is added as a shielding layer to shield the pixel circuit and the routing position and prevent light from interfering through the slits, but the metal layers can interfere with signals of the pixel circuit due to the Floating state, so that the display effect is influenced. Therefore, it is necessary to supply a dc signal to the metal layers to stabilize the voltage. However, if the pixel circuit is directly connected by punching holes, the connection holes need to be arranged in space, so that the pixel size is increased, and the resolution of the screen is reduced; if the connection is made only from the IC (Integrated chip) end, a large trace voltage drop will be caused, which affects the display quality.

At least one embodiment of the present disclosure provides a display substrate having a first side for displaying and a second side opposite to the first side, including: a substrate base plate; a display area disposed on the substrate, including a first display area and a second display area at least partially surrounding the first display area, the first display area allowing light from a first side of the display substrate to be at least partially transmitted to a second side of the display substrate for sensing, the first display area including a plurality of pixel cell groups arranged at intervals, the plurality of pixel cell groups each including a plurality of first pixel cells, each of the plurality of first pixel cells including a pixel area and an opening area; a plurality of first power lines positioned at the pixel region and configured to be connected with the plurality of pixel cell groups to supply a first power voltage to the plurality of pixel cell groups; the shielding layer is arranged on the substrate base plate, is positioned on one side of the first power line close to the substrate base plate and comprises a hollow area and a shielding area; for one pixel unit group, the opening area of each first pixel unit is at least partially overlapped with the shielding area of the shielding layer, the opening area of at least one first pixel unit comprises a first shielding connecting part which is at least partially overlapped with the shielding area of the shielding layer, and the shielding layer is connected with at least one first power line in a plurality of first power lines through the first shielding connecting part to receive a first power voltage; many first power cords are located the first one side of sheltering from the substrate base plate of connecting portion that shelters from, and the shielding layer is located the first one side of sheltering from the substrate base plate of connecting portion that shelters from, and first shelters from connecting portion and is located between shielding layer and many first power cords.

The display substrate provided by the embodiment of the disclosure can connect a direct current signal to the shielding layer on the premise of not reducing the pixel density, so as to prevent the shielding layer from being in a floating state, prevent the signal jump of the shielding layer from causing interference to the pixel driving circuit, reduce the voltage drop of the first power line, and improve the display quality of the display panel.

Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

Fig. 1A is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure; fig. 1B is a schematic partial enlarged view of a display substrate according to at least one embodiment of the present disclosure; fig. 1C is a partially enlarged schematic view of a display substrate according to at least another embodiment of the disclosure; FIG. 1D is a schematic cross-sectional view taken along line B1-B2 of FIG. 1A.

For example, as shown in fig. 1A, a display substrate 1 provided in at least one embodiment of the present disclosure includes a substrate 100 and a display area. The display region is disposed on the substrate 100, and the display region includes a first display region 10 (e.g., a light-transmissive display region) and a second display region 20 (e.g., a normal display region). The display substrate 1 may further include a peripheral region 30, and the peripheral region 30 surrounds (e.g., partially surrounds) the display region. The second display area 20 surrounds (e.g., partially surrounds) the first display area 10.

For example, the display substrate 1 provided in at least one embodiment of the present disclosure may be a display substrate such as an Organic Light Emitting Diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, and the embodiment of the present disclosure does not limit the specific type of the display substrate.

For example, as shown in fig. 1D, the first display region 10 is a light-transmissive display region, i.e. light from a first side S1 (e.g. the display side) of the display substrate 1 is allowed to be at least partially transmitted to a second side S2 (e.g. the non-display side) of the display substrate 1, i.e. incident light from the display side is transmitted through the first display region 10 to reach the non-display side of the display substrate 1. A sensor 192 may also be provided on the second side S2 of the display substrate 1 to receive the transmitted light to perform a corresponding function (e.g., imaging, infrared sensing, distance sensing, etc.). For example, the sensor 192 is disposed on the second side S2 of the display substrate 1, and the orthographic projection of the sensor 192 on the substrate 100 at least partially overlaps the first display area 10 and is configured to receive and process light from the first side S1 of the display substrate 1. The light from the first side S1 of the display substrate 1 may be collimated light in the normal direction of the display substrate 1 (e.g., the Z1 direction) or may be non-collimated light.

For example, the sensor 192 is an image sensor, an infrared sensor, a distance sensor, etc., and the sensor 192 may be implemented in the form of a chip, etc., for example. The sensor 192 is arranged on a second side S2 (the side facing away from the user) of the display substrate 1. The sensor 192 at least partially overlaps the first display area 10 in the normal direction of the display surface of the display substrate.

For example, the sensor 192 may be an image sensor and may be used to capture an image of the external environment to which the light collecting surface of the sensor 192 faces, such as a CMOS image sensor or a CCD image sensor; the sensor 192 may also be an infrared sensor, a distance sensor, or the like. The sensor 192 may be used to implement a camera of a mobile terminal such as a mobile phone, a notebook, etc., and may further include an optical device such as a lens, a mirror, or an optical waveguide, etc., as necessary, to modulate an optical path. Embodiments of the present disclosure are not limited as to the type, function, and manner of arrangement of the sensors 192.

The sensor 192 is disposed on the first side S2 of the display substrate by means of a double-sided tape or the like, and an orthogonal projection of the sensor 192 on the substrate 100 at least partially overlaps the first display area 10, configured to receive light from the first side S1. Thus, the first display area 10 facilitates the arrangement of the sensor 192 while realizing the display.

For example, as shown in fig. 1B and 1C, the first display area 10 includes a first sub-pixel array (composed of gray boxes in the first display area 10) including a plurality of pixel cell groups P1 (gray boxes in the first display area 10) arranged in a first direction Y1 and a second direction X1 intersecting the first direction Y1. Each of the plurality of pixel cell groups P1 includes at least one first pixel cell (e.g., a plurality of first pixel cells) (described in detail later). The first pixel unit includes a first light emitting device and a first pixel driving circuit directly connected to each other, the first pixel driving circuit being configured to drive the first light emitting device to emit light. The first light emitting device and the first pixel driving circuit are located in the same pixel region and are not separated from each other in position.

The first direction Y1 and the second direction X1 may or may not intersect perpendicularly, for example, an acute angle formed by the intersection of the first direction Y1 and the second direction X1 may be in a range of 10 ° or less and 45 ° or more. The drawings of the embodiments of the present disclosure illustrate that the first direction Y1 perpendicularly crosses the second direction X1.

The plurality of pixel cell groups P1 have gaps therebetween that allow light to pass, i.e., blank regions in the first display region 10, to allow incident light from the first side S1 to be transmitted through the gaps between the adjacent pixel cell groups P1 to ensure light transmissivity of the first display region 10.

For example, as shown in fig. 1B, the plurality of first pixel cell groups P1 are arranged in a staggered manner between two adjacent columns, that is, the pixel cell group P1 of the first column is staggered from the pixel cell group P1 of the second column in the second direction X1 and distributed in different rows. For example, the pixel cell groups P1 of adjacent columns are different rows.

For example, as shown in fig. 1C, the plurality of pixel cell groups P1 are arranged in a plurality of rows and columns, i.e., a pixel cell group P1 of a first column in the figure is spaced apart from and adjacent to a pixel cell group P1 of a second column in the second direction X1.

For example, as shown in fig. 1B and 1C, the second display area 20 includes a second sub-pixel array (composed of white boxes in the second display area 20) including a plurality of second pixel units C (white boxes in the second display area 20). Each of the plurality of second pixel units C includes a second light emitting device and a second pixel driving circuit directly connected to each other, the second pixel driving circuit being configured to drive the second light emitting device to emit light. The second light emitting device and the second pixel driving circuit are located in the same pixel region, and are not separated from each other in position. For example, the second pixel units in the second display region 20 are arranged as shown in FIG. 2,

for example, the pixel density of the second display region is greater than that of the first display region, and as shown in fig. 1B and 1C, the arrangement density of the pixel cell group P1 in the first display region 10 is less than that of the second pixel cell C in the second display region 20. That is, the resolution of the first display region 10 is set lower than that of the second display region 20 to allow light to pass through, i.e., the density of pixels arranged in the first display region 10 for display is smaller than that of the second display region 20.

Fig. 2 is a schematic layout view of a pixel unit in a second display area according to at least one embodiment of the present disclosure. Fig. 3 is a schematic diagram of a first display area of a display panel according to at least one embodiment of the present disclosure. As shown in fig. 2 and 3, the first display region 10 and the second display region 20 of the display substrate respectively include a plurality of pixel cell groups P1, for example, it is only schematically shown in fig. 2 and 3 that each pixel cell group P1 includes 4 pixel cells P0, for example, the 4 pixel cells P0 are the first sub-pixel cell 101, the second sub-pixel cell 102, the third sub-pixel cell 103, and the fourth sub-pixel cell 104, respectively, which is not limited by the embodiment of the present disclosure.

It should be noted that each pixel cell group P1 may further include 2 pixel cells P0 (as shown in fig. 14A to 14E) or 3 pixel cells P0 (as shown in fig. 15A to 15E), and the like, which is not limited in this embodiment of the disclosure.

For example, in the example shown in fig. 14A, one pixel group may further include two sub-pixels, for example, a first sub-pixel 101 and a second sub-pixel 102, for example, the first sub-pixel 101 is a red sub-pixel, and the second sub-pixel 102 is a green sub-pixel; for example, in the embodiment shown in fig. 15A, one first pixel group P1 may further include three sub-pixels, for example, a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103, for example, the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, and the third sub-pixel 103 is a blue sub-pixel, for example, the three sub-pixels are located in one row; for example, in the example shown in fig. 12A, one pixel group may further include four sub-pixels, for example, a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104, for example, the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, the third sub-pixel 103 is a blue sub-pixel, and the fourth sub-pixel 104 is a green sub-pixel, and in other embodiments, pixel units of other colors may be used in the pixel group. Of course, in other embodiments, the arrangement of the plurality of sub-pixels P0 in the display panel is not limited to that shown in fig. 2 and 3. Embodiments of the present disclosure are not limited in this regard.

For example, as shown in fig. 2, in the second display area 20, the pixel units P0 are uniformly and regularly arranged, and will not be described herein again.

For example, as shown in fig. 3, the display substrate further includes a gate line 113 and a data line 313. The gate line 113 and the data line 313 are insulated from each other. Each gate line 113 connects a row of sub-pixels and each data line 313 connects a column of sub-pixels. For example, the gate line 113 is configured to supply a scan signal to a row of subpixels. The data line 313 is configured to supply a data signal to a column of subpixels.

For example, as shown in fig. 3, the data line 313 includes a first data line DL 1. The first data line DL1 is located at least in the first display area 10. For example, the first data line DL1 extends from the first display area 10 to the second display area 20. For example, as shown in fig. 3, the gate line 113 includes a first gate line GL1, the first gate line GL1 extending from the second display region 20 to the first display region 10.

For clarity and simplicity of representation, fig. 3 only schematically illustrates a connection relationship between adjacent pixel groups P1 in the first display area 10, and does not constitute a limitation of the present disclosure. Fig. 4 is a schematic view of a display substrate according to at least one embodiment of the present disclosure. For example, as shown in fig. 4, the display substrate further includes a first power line VDD1 and is configured to be connected to the plurality of pixel cell groups P1 to supply a first power voltage to the plurality of pixel cell groups P1.

For example, as shown in fig. 4, the display substrate further includes a shielding layer LS disposed on the substrate 100 and located on a side of the first power line VDD1 close to the substrate 100, and includes a hollow area LS2 and a shielding area LS 1. For example, the hollowed-out area LS2 corresponds to the light transmission area R0 between the adjacent first pixel cell groups shown in fig. 3. As shown in fig. 3 and 4, the light-transmitting region R0 is surrounded by two adjacent first gate lines GL1 and two adjacent first data lines DL1, but is not limited thereto.

For example, the first display region 10 includes a plurality of light transmission regions R0; the light transmission region R0 is positioned between the adjacent first pixel groups P1. The light transmitting region R0 is transparent to ambient light. For example, the light-transmitting region R0 may include a substrate and a transparent insulating layer on the substrate, and the light-transmitting region R0 has no light-shielding structure, e.g., no metal traces. For example, the light-transmitting region R0 is located in an area surrounded by four adjacent pixel cell groups P1 and the trace connecting the pixel cell group P1, but is not limited thereto.

For example, as shown in fig. 4, adjacent pixel cell groups are connected by traces (e.g., the first data line DL1, the first power line 311, the gate line GL1, the first reset signal line 111, the second reset signal line 112, the light-emitting control signal line 110, and the initialization signal line 210), for example, an orthogonal projection of the plurality of pixel cell groups P0 and the traces on the substrate 100 falls within an orthogonal projection of the shielding region LS1 of the shielding layer LS on the substrate 100. That is, the shielding region LS1 shields a large number of slits between the traces connecting the first pixel cell groups and between the internal connections of the first pixel cell groups, so as to avoid diffraction and interference generated when light passes through the slits, and avoid glare phenomenon caused by uneven brightness when light reaches the camera.

For example, in the embodiment of the disclosure, as shown in fig. 6A, each of the plurality of first pixel units P0 includes a pixel region a11 (i.e., a region of transistors, capacitors and wirings in the first pixel unit, for example, the plurality of power lines 311 (e.g., for the first pixel unit P0, the power line 311 is the first power line VDD1, for the second pixel unit C, the power line 311 is the second power line VDD2, and the following embodiments are the same and are not described again) located in the pixel region a11 and the opening region a 12. for example, the opening region is a region obtained by reducing the size of the first pixel unit P0 shown in fig. 6B, for example, by appropriately reducing the line width of the pixel driving circuit shown in fig. 6B, the aspect ratio of each transistor, the size of the capacitor, the size of the wiring, the size of the connection hole, and placing them collectively, etc., so that the first pixel unit P0 has one opening region a12 (as shown in fig. 6A) in the same solid line frame, thereby, the light transmittance of the display panel can be improved. For example, in the embodiment of the present disclosure, the pixel area a11 is intensively placed at a position above the pixel cell group P0 (i.e., the solid-line rectangular frame) to reduce the space occupied by the driving circuit while keeping the pixel resolution unchanged, so that a part of the space (i.e., the opening area a12) can be left for placing the first shielding connection SP1 and the connection hole V1/V2 for connecting the shielding layer LS to the first power line 311, and specific contrast diagrams of the normal pixel cell and the reduced-size pixel cell are shown in fig. 6B and 6A.

For example, the size of the pixel driving circuit in fig. 6A (i.e., the size of the pixel driving circuit after the reduction) is one fourth of the size of the pixel driving circuit shown in fig. 6B (i.e., the size of the pixel driving circuit before the reduction), and may be, of course, one sixth, one half, and so on, as long as the corresponding functions can be achieved, which is not limited by the embodiment of the present disclosure. For example: in some examples, for an FHD resolution off-screen camera screen, the size of the pixel drive circuitry can be reduced to QHD level while keeping the FHD level pixel resolution unchanged, so some space can be left for placing the occlusion connector LS2 and the connection hole connecting the occlusion layer LS.

In the above embodiments of the present disclosure, the size of the pixel driving circuit of the first pixel unit is reduced to facilitate light transmission, and meanwhile, the shielding layer is connected to the first power line or other power lines on the premise of not changing the pixel resolution, so that a dc signal can be connected to the shielding layer on the premise of not reducing the pixel density, the signal interference caused by the shielding layer in a floating state to the pixel driving circuit is prevented, the voltage drop of the first power line is reduced, and the display quality of the display panel is improved.

In order to ensure the etching uniformity of the shielding layer, the shielding layer is arranged below the pixel circuit in the normal display area. For example, the orthographic projection of the second display area 20 on the substrate base plate 100 falls within the orthographic projection of the blocking area LS2 of the blocking layer LS on the substrate base plate 100. For example, since the second display region 20 does not include the light transmission region R0, a portion of the shielding layer LS corresponding to the second display region 20 may be full-faced, that is, have no hollow area, so that a gap in each pixel driving circuit in the second display region 20 and a gap generated between the traces connecting each pixel driving circuit may be shielded.

Since the normal pixel driving circuit (for example, the pixel driving circuit shown in fig. 6B) has a relatively compact wiring, the size occupied by the driving circuit wiring is the pixel density, and there is no remaining space for placing the shielding connecting portion and the connecting hole for connecting the shielding layer LS.

In this regard, in order to ensure that the pixel density does not change, the pixel driving circuit in the second display area 20 adopts the same structure as the pixel driving circuit in the first display area 10, that is, also adopts the structure and size shown in fig. 6A.

For example, as for the second display area 20, as shown in fig. 1B and 1C, the second display area 20 includes a plurality of second pixel cells C arranged in an array and a plurality of second power supply lines VDD2, and each of the plurality of second pixel cells C has a structure as shown in fig. 6A, for example, including a pixel area a11 and an opening area a 12.

For example, the plurality of second power lines VDD2 are configured to be connected to the plurality of second pixel cells C to supply the second power voltage to the plurality of second pixel cells C. For example, the second power supply voltage is the same as the first power supply voltage. For example, the second power line VDD2 extends along the second direction X1, and provides a second power voltage to a column of the second pixel cells C.

It should be noted that, in order to distinguish the different regions where the power line 311 is located, the power line 311 located in the first display region 10 is referred to as a first power line VDD1, and the power line 311 located in the second display region 20 is referred to as a second power line VDD2, which provide the same signal, i.e., the first power voltage is the same as the second power voltage, and there is no essential difference.

For example, for one second pixel unit C, the opening area a12 of each second pixel unit C at least partially overlaps the shielding area LS1 of the shielding layer LS, i.e. after the second pixel unit C adopts the pixel structure shown in fig. 6A after being reduced in size, the opening area is also left to facilitate the connection of the shielding layer LS and the second power line VDD2, so as to provide a dc signal for the shielding layer LS and avoid the floating of the shielding layer LS.

For example, the opening area a12 of the at least one second pixel cell C includes a second shield connection SP2, the second shield connection SP2 at least partially overlaps the shield area LS2 of the shield layer LS, and the shield layer LS is connected through the second shield connection SP2 and at least one power line of the plurality of second power lines VDD2 to receive a second power voltage, thereby providing a direct current signal to the shield layer LS to prevent floating of the shield layer LS.

FIG. 7 is a schematic cross-sectional view taken along line A-A' according to at least one embodiment of the present disclosure. The first pixel cell P0 is described as an example, and the embodiment of the disclosure is not limited thereto.

For example, as shown in fig. 6A and 7, the shielding layer LS (e.g., the shielding region LS1 thereof) is connected to the first shielding connection SP1 through the first via V1, and the first shielding connection SP1 is connected to the at least one first power line VDD1 through the second via V2.

For example, as shown in fig. 7, the display substrate further includes a first insulating layer G11, a second insulating layer G12, a third insulating layer ILD, and a fourth insulating layer G10. For example, the first insulating layer G11 is located between the shielding layer LS (e.g., its shielding region LS1) and the first shielding layer connection SP 1.

For example, as shown in fig. 7, the second insulating layer G12 is positioned between the first insulating layer G11 and the first shielding connection SP1, and the third insulating layer ILD is positioned between the first shielding connection SP1 and the plurality of first power lines VDD 1; alternatively, the second insulating layer G12 is positioned between the first shield connection part SP1 and the plurality of first power lines VDD1, and the third insulating layer ILD is positioned between the second insulating layer G12 and the plurality of first power lines VDD1. The position relationship of the second insulating layer G12 is not specifically shown in fig. 7, which may be determined according to practical situations, and the embodiment of the disclosure is not limited thereto.

For example, in some examples, the shielding layer LS is connected to the first shielding connection SP1 through a first via penetrating the first insulating layer G11, and the first shielding connection SP1 is connected to the at least one first power line VDD1 through a second via penetrating the second insulating layer G12 and the third insulating layer ILD; or, for example, in other examples, as shown in fig. 7, the blocking layer LS is connected to the first blocking connection SP1 through a first via V1 penetrating the first and second insulating layers G11 and G12, and the first blocking connection SP1 is connected to the at least one first power line VDD1 through a second via penetrating the third insulating layer ILD. That is, the first shield connection portion SP1 may be located on the first conductive layer or the second conductive layer. Fig. 7 illustrates a schematic diagram of the first shielding connection part SP1 being located on the second conductive layer, which is not limited by the embodiment of the present disclosure. The description about the first conductive layer and the second conductive layer will be described below, and will not be repeated here. For example, the first shielding connection portion is located on the first conductive layer as an example, and the embodiment of the disclosure is not limited thereto.

FIG. 8 is a plan view of a semiconductor pattern of the display substrate shown in FIG. 6A; FIG. 9 is a plan view of the first conductive layer of the display substrate shown in FIG. 6A; FIG. 10 is a plan view of a second conductive layer of the display substrate shown in FIG. 6A; fig. 11 is a plan view of a third conductive layer of the display substrate shown in fig. 6A.

As shown in fig. 7, the fourth insulating layer G10 is positioned between the blocking layer LS and an active layer of the transistor (e.g., the active layer a7 of the second reset transistor T1).

For example, as shown in fig. 8 to 11, the first conductive layer LY1 includes a gate line GL1, the second conductive layer LY2 includes a second plate C12 of the storage capacitor C1, and the third conductive layer LY3 includes a first power supply line vdd1-for example, in a direction perpendicular to the substrate 100, the first insulating layer G11 is positioned between the active layer a7 and the first conductive layer LY1, the second insulating layer G12 is positioned between the gate line and the second conductive layer LY2, and the third insulating layer ILD is positioned between the second plate C12 and the third conductive layer LY3 of the storage capacitor C1. For example, the first shielding connection part SP1 is located on the first conductive layer LY1 shown in fig. 9, which is not limited by the embodiment of the present disclosure.

For example, as shown in fig. 5, the pixel driving circuit includes a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a first light emission controlling transistor T4, a second light emission controlling transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor C1. For example, each transistor and each capacitor includes a first electrode and a second electrode, and the description of the connection relationship and the operation principle of the pixel driving circuit can be referred to in the art and will not be repeated herein.

For example, as shown in fig. 8, the active layers a6, A3, A5, a7 of the first reset transistor T6, the compensation transistor T3, the second light emission controlling transistor T5 and the second reset transistor T7 are located at the first semiconductor layer a01 extending in the first direction Y1, the active layers a2, a4 of the data write transistor T2 and the first light emission controlling transistor T4 are located at the second semiconductor layer a02 extending in the second direction X1, and the first semiconductor layer a01 and the second semiconductor layer a02 are connected and integrally formed by the active layer a1 of the driving transistor T1.

For example, as shown in fig. 6A and 8, the active layer a1 of the driving transistor T1 is located on an imaginary line of the active layer a1 of the first reset transistor T1 in the first direction Y1, the active layers a1, a1 of the compensation transistor T1 and the data writing transistor T1 are respectively located on both sides of the active layer a1 of the driving transistor T1, and are located on a side of the active layer a1 of the driving transistor T1 close to the active layer a1 of the first reset transistor T1, that is, in the second direction Y1, the active layers a1, a1 of the compensation transistor T1 and the data writing transistor T1 are located above the active layer a1 of the driving transistor T1, the active layers a1, a1 of the second emission control transistor T1 and the first emission control transistor T1 are respectively located on both sides of the active layer a1 of the driving transistor T1, and are located on a side of the driving transistor T1, for example, the first reset transistor T1, the active layer a1 is located on the second direction Y1, under the active layer a1 of the driving transistor T1.

For example, as shown in fig. 6A and 9, the active layer a7 of the second reset transistor T7 is positioned at a side of the active layer a5 of the second light emission controlling transistor T5) away from the active layer of the compensation transistor T3, the compensation transistor T3 includes a first gate G31 extending in the first direction Y1, a second gate G32 extending in the second direction X1, and the second gate G32 is arranged side by side with the gate G5 of the second light emission controlling transistor T5 extending in the second direction X2, and a gate (not shown in the figure) of the second reset transistor T7 in the first direction Y1; the gate G2 of the data write transistor T2 and the gate G4 of the first light emission control transistor T4 extend in the second direction X1, and are arranged side by side in the first direction Y1,

for example, the gate G6 of the first reset transistor T6 and the gate G1 of the driving transistor T1 extend in the second direction X1 and are arranged side by side in the first direction Y1, and the gate G1 of the driving transistor T1 is integrally formed with the first plate C11 of the storage capacitor C1.

For example, the display substrate further includes a gate line 113 extending in the second direction Y1, a light emission control signal line 110, a first reset signal line 111, and a second reset signal line (integrally formed with the gate electrode of the second reset transistor T7).

For example, the gate G6 of the first reset transistor T6 and the first reset signal line 111 are connected and integrally formed, the second gate G32 of the compensation transistor T3 and the gate G2 of the data write transistor T2 are connected and integrally formed with the gate line 113, the gate G6 of the second emission control transistor T6 and the gate G5 of the first emission control transistor T5 are connected and integrally formed with the emission control signal line 110, and the gate of the second reset transistor T7 is connected and integrally formed with the second reset signal line.

For example, the display substrate further includes a gate line 113, a light emission control signal line 110, a first reset signal line 111, and a second reset signal line 112 extending in the second direction Y1, for example, a gate electrode of the first reset transistor T6 and the first reset signal line 111 are connected and integrally formed, and a second gate electrode G32 of the compensation transistor T3 and a gate electrode G2 of the data write transistor T2 are connected and integrally formed with the gate line 113. The gate G5 of the second light emission controlling transistor T5 and the gate G4 of the first light emission controlling transistor T4 are connected to and integrally formed with the light emission control signal line 110, and the gate G7 of the second reset transistor T7 is connected to and integrally formed with the second reset signal line 112.

For example, the display substrate further includes a DATA line 313, the DATA line 313 is connected to the active layer a4 of the DATA write transistor T4 and configured to provide the DATA signal DATA, an orthogonal projection of the first power line VDD1 on the substrate 100 at least partially overlaps an orthogonal projection of the active layer a6 of the first reset transistor T6 and the active layer a1 of the drive transistor T1 on the substrate 100, and an orthogonal projection of the DATA line 313 on the substrate 100 is located on a side of an orthogonal projection of the second semiconductor layer a02 on the substrate 100 away from an orthogonal projection of the first power line VDD1 on the substrate 100.

For example, as shown in fig. 6A and 11, the pixel driving circuit further includes a first transfer electrode EC1, the first transfer electrode EC1 is connected with the active layer of the second light emission controlling transistor T5, the active layer a7 of the second first bit transistor T7, and the first electrode E1 of the light emitting device 20 through vias, and an orthogonal projection of the first transfer electrode EC1 on the substrate 100 is located between the orthogonal projections of the active layer a7 of the second reset transistor T7 and the active layer a1 of the driving transistor T1 on the substrate 100.

For example, for each of the plurality of second pixel cells C, the orthogonal projection of the second shield connection SP2 on the substrate base board 100 is located between the orthogonal projection of the active layer a7 of the second reset transistor T7 on the substrate base board 100 and the orthogonal projection of the second power supply line VDD2 on the substrate base board 100, and at least partially overlaps the orthogonal projection of the second power supply line VDD2 on the substrate base board 100, whereby the opening area a12 can be left.

For example, referring to fig. 5, the gate line 113 is configured to supply a SCAN signal SCAN to the pixel circuit 10. The emission control signal line 110 is configured to supply an emission control signal EM to the sub-pixel P0. The DATA line 313 is configured to supply the DATA signal DATA to the pixel circuit 10, the first power line 311 is configured to supply a constant first voltage signal ELVDD to the pixel circuit 10, the third power line 312 is configured to supply a constant second voltage signal ELVSS to the pixel circuit 10, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to supply an initialization signal Vinit to the pixel circuit 10. The initialization signal Vinit is a constant voltage signal, and the magnitude thereof may be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto, and for example, the initialization signal Vinit may be less than or equal to the second voltage signal ELVSS. For example, the pixel circuit outputs a driving current to drive the light emitting element 20 to emit light under the control of signals of the SCAN signal SCAN, the DATA signal DATA, the initialization signal Vinit, the first voltage signal ELVDD, the second voltage signal ELVSS, the light emission control signal EM, and the like. The light emitting element 20 emits red light, green light, blue light, or white light or the like under the drive of its corresponding pixel circuit 10.

As shown in fig. 5, the driving transistor T1 of the pixel circuit 10 is electrically connected to the light emitting element 20 and outputs a driving current to drive the light emitting element 20 to emit light under the control of signals such as a SCAN signal SCAN, a DATA signal DATA, a first voltage signal ELVDD, a second voltage signal ELVSS, and the like.

For example, the display panel provided by the embodiment of the present disclosure further includes: a data driving circuit and a scan driving circuit. The DATA driving circuit is configured to supply the DATA signal DATA to the sub-pixel P0 according to an instruction of the control circuit; the SCAN driving circuit is configured to supply signals such as a light emission control signal EM, a SCAN signal SCAN, and first and second reset control signals RST1 and RST2 to the subpixel P0 according to an instruction of the control circuit. For example, the control circuit includes an external Integrated Circuit (IC), but is not limited thereto. For example, the scan driving circuit is a goa (gate driver On array) structure mounted On the display panel, or a driving chip (IC) structure bound (bonded) with the display panel. For example, it is also possible to use different driving circuits to supply the emission control signal EM and the SCAN signal SCAN, respectively. For example, the display panel further includes a power supply (not shown in the figure) configured to supply the first voltage signal ELVDD, the second power supply voltage ELVSS, the initialization signal Vinit, and the like to the sub-pixel P0 through the first power supply line 311, the third power supply line 312, and the initialization signal line 210, respectively, to supply the above-described voltage signals, which may be a voltage source or a current source, as needed.

As shown in fig. 5, the second pole C12 of the storage capacitor C1 is electrically connected to the first power line 311, and the first pole C11 of the storage capacitor C1 is electrically connected to the second pole T12 of the threshold compensation transistor T1. The gate T20 of the data writing transistor T2 is electrically connected to the gate line 113, and the first electrode T21 and the second electrode T22 of the data writing transistor T2 are electrically connected to the data line 313 and the first electrode T11 of the driving transistor T1, respectively. The gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first pole T31 of the threshold compensation transistor T3 is electrically connected to the second pole T12 of the driving transistor T1, and the second pole T32 of the threshold compensation transistor T3 is electrically connected to the gate T10 of the driving transistor T1.

For example, as shown in fig. 5, the gate T40 of the first light emission controlling transistor T4 and the gate T50 of the second light emission controlling transistor T5 are both connected to the light emission control signal line 110.

For example, as shown in fig. 5, the first pole T41 and the second pole T42 of the first light emitting control transistor T4 are electrically connected to the first power line 311 and the first pole T11 of the driving transistor T1, respectively. The first electrode T51 and the second electrode T52 of the second light-emitting control transistor T5 are electrically connected to the second electrode T12 of the driving transistor T16 and the pixel electrode E1 (which may be an anode of an OLED) of the light-emitting element 20, respectively. The common electrode E2 (which may be a common electrode of an OLED, e.g., a cathode) of the light emitting element 20 is electrically connected to the third power line 312.

For example, as shown in fig. 5, the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111, the first pole T61 of the first reset transistor T6 is electrically connected to the initialization signal line 210 (first initialization signal line 211), and the second pole T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1. The gate T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112, the first pole T71 of the second reset transistor T7 is electrically connected to the initialization signal line 210 (second initialization signal line 212), and the second pole T72 of the second reset transistor T7 is electrically connected to the pixel electrode E1 of the light emitting element 20.

Fig. 8 shows the semiconductor pattern SCP, and fig. 9 shows the first conductive layer LY1 with the first insulating layer G11 disposed between the first conductive layer LY1 and the semiconductor pattern SCP. The semiconductor pattern SCP is doped with the first conductive layer LY1 as a mask so that a region of the semiconductor pattern SCP not covered with the first conductive layer LY1 retains semiconductor characteristics to form a channel of the thin film transistor, and a region of the semiconductor pattern SCP covered with the first conductive layer LY1 is silicided to form a source or a drain of the thin film transistor. An active layer formed after the semiconductor pattern SCP is partially conducted is shown in fig. 6A.

As shown in fig. 9, the first conductive layer LY1 includes a first reset control signal line 111, a second reset control signal line (not shown in the drawing), a light emission control signal line 110, a gate line 113, and a first electrode C11 of a storage capacitor C1.

Fig. 10 shows the second conductive layer LY2 with the second insulating layer G12 disposed between the second conductive layer LY2 and the first conductive pattern layer LY 1. The second conductive layer LY2 includes the initialization signal line 210 and the second pole C12 of the storage capacitor C1. The second pole C12 of the storage capacitor C1 has an opening. The interlayer insulating layer ILD is positioned between the second conductive layer LY2 and the third conductive layer LY 3. As for the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, the first conductive layer LY1, the second conductive layer LY2, and the third conductive layer LY3, reference may be made to those in the art, and detailed description thereof will be omitted.

Fig. 11 shows the third conductive layer LY3, and the third conductive layer LY3 includes the first power line 311, the data line 313, the first connection electrode EC1, the second connection electrode EC2, and the first pole E1 of the light emitting element 20.

For example, as shown in fig. 11, the first power line 311 includes a protrusion 3111, and an orthogonal projection of the second via V2 on the substrate overlaps an orthogonal projection of the protrusion 3111 on the substrate, that is, the first shield connection SP1 is connected to the protrusion 3111 of the first power line S11 through the second via V2. An orthogonal projection of the first via hole V1 on the substrate board overlaps an orthogonal projection of the first power supply line 311 on the substrate board. For example, as shown in fig. 6A and 7, the first via V1 and the second via V2 are disposed left and right, but may be disposed up and down in the first direction Y1, and the embodiment of the present disclosure is not limited thereto.

For example, in the embodiment of the present disclosure, the orthographic projections of the first via V1 and the second via V2 on the substrate do not overlap, that is, the first via V1 and the second via V2 are disposed up and down or left and right, which can simplify the process, and avoid the problems that the film layer is easily broken and the process is not easily implemented and the first power line 311 has a large gradient and is not flat due to the overlapping of the orthographic projections of the first via V1 and the second via V2 on the substrate.

It should be noted that the transistors used in some embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. In an embodiment of the present disclosure, in order to distinguish two poles of a transistor except for a gate, one of the poles is directly described as a first pole, and the other pole is directly described as a second pole, so that the first pole and the second pole of all or part of the transistors in the embodiment of the present disclosure can be interchanged as needed. For example, the first pole of the transistor according to the embodiment of the present disclosure may be a source, and the second pole may be a drain; alternatively, the first pole of the transistor is the drain and the second pole is the source.

Further, the transistors may be classified into N-type and P-type transistors according to their characteristics. The embodiments of the present disclosure are described by taking P-type transistors as examples of transistors. Based on the description and teaching of this implementation manner in the present disclosure, a person skilled in the art can easily think of an implementation manner in which at least some of the transistors in the pixel circuit of the embodiment of the present disclosure are N-type transistors, that is, N-type transistors or a combination of N-type transistors and P-type transistors, without making creative work, and therefore, these implementation manners are also within the protection scope of the present disclosure.

Fig. 6A illustrates a pixel circuit of 7T1C as an example, and embodiments of the disclosure include but are not limited thereto. In addition, the number of thin film transistors and the number of capacitors included in the pixel circuit are not limited in the embodiments of the present disclosure. For example, in some other embodiments, the pixel circuit of the display base panel may also have a structure including another number of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T3C structure, which is not limited by the embodiments of the present disclosure.

For example, the substrate 100 in at least one embodiment of the present disclosure may be a glass plate, a quartz plate, a metal plate, or a resin plate. For example, the material of the base substrate may include an organic material, and for example, the organic material may be a resin-based material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate; for example, the substrate base plate 100 may be a flexible base plate or a non-flexible base plate, and the embodiment of the present disclosure is not limited thereto.

For example, the materials of the first insulating layer G11, the second insulating layer G12, the third insulating layer ILD, and the fourth insulating layer BL may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, organic insulating materials such as organic resins, or other suitable materials, which is not limited in this disclosure.

For example, the material of the third conductive layer LY3 may include titanium, a titanium alloy, aluminum, an aluminum alloy, copper, a copper alloy, or any other suitable composite material, which is not limited in this disclosure. For example, the materials of the shielding layer LS, the first conductive layer LY1, and the second conductive layer LY2 may be the same as the material of the third conductive layer LY3, and thus, a detailed description thereof will not be repeated

For example, the material of the semiconductor layer 310 may include an oxide semiconductor, an organic semiconductor, amorphous silicon, polysilicon, and the like, for example, the oxide semiconductor includes a metal oxide semiconductor (e.g., Indium Gallium Zinc Oxide (IGZO)), and the polysilicon includes low-temperature polysilicon or high-temperature polysilicon, and the like, which is not limited in this respect by the embodiment of the present disclosure. It should be noted that the source region and the drain region may be regions doped with n-type impurities or p-type impurities, and embodiments of the present disclosure are not limited thereto.

The following shows schematic diagrams of several examples of the first shield connection portion. For example, the first blocking connection may be located in the middle, at both ends, or at one end of two rows of the first pixel units of the first display area, which is not limited in this embodiment of the disclosure.

Fig. 12A is a schematic view of an example of a display substrate according to at least one embodiment of the present disclosure; FIG. 12B is a plan view of a shielding region LS1 of a shielding layer LS of the display substrate shown in FIG. 12A; FIG. 12C is a plan view of a semiconductor pattern of the display substrate shown in FIG. 12A; FIG. 12D is a plan view of the first conductive layer of the display substrate shown in FIG. 12A; FIG. 12E is a plan view of a second conductive layer of the display substrate shown in FIG. 12A; fig. 12F is a plan view of the third conductive layer of the display substrate shown in fig. 12A.

For example, as shown in fig. 12A, one pixel cell group includes four first pixel cells 101, 102, 103, and 104. For example, as shown in fig. 12A, for each pixel cell group, the first shield connection part SP1 is located between two adjacent first pixel cells in the first direction Y1 in each pixel cell group. The description of fig. 8-11 may be referenced in connection with the description of fig. 12B-12F.

For example, in the example shown in fig. 12A, the orthographic projection of the first shield connection SP1 on the substrate 100 is located between the orthographic projection of the active layer a7 of the second reset transistor T7 on the substrate 100 and the orthographic projection of the first power supply line VDD1 on the substrate 100, and at least partially overlaps with the orthographic projection of the first power supply line VDD1 on the substrate 100 (for example, as shown in fig. 6A).

For example, as shown in fig. 12A, in the first direction Y1, the first power line 311 between adjacent two pixel cell groups is connected by one third conductive line L3, the first data line DL1 includes a first portion DL11 and a second portion DL12, the first portion DL11 of the first data line DL1 partially overlaps the third conductive line L3, the second portion DL12 of the first data line DL1 at least partially overlaps the third conductive line L3, and the first portion DL11 of the first data line DL1 and the second portion DL12 of the first data line DL1 are located at different layers, respectively. For example, the first portion DL11 of the first data line DL1 on the left side in fig. 12A is located at the second conductive layer LY2 shown in fig. 12E, and the second portion DL12 of the first data line DL1 on the right side is located at the first conductive layer LY1 shown in fig. 12D. For example, referring to fig. 12A, 12D, and 12E, the first and second portions DL11 and DL12 of the first data line DL1 and the third conductive line L3 are located between adjacent pixel cell groups.

For example, as shown in fig. 12F, the third conductive line L3 is formed integrally with the first power line 311, and a first power line 311 connecting adjacent two pixel cell groups is connected, so that adjacent pixel cell groups are connected by only one third conductive line, thereby reducing the wiring area and improving the transmittance of light.

For example, referring to fig. 12F, two first data lines DL1 are provided, and two first data lines DL1 are respectively connected to two adjacent columns of sub-pixels. For example, as shown in fig. 12F, the first portion DL11 and the second portion DL12 are respectively connected to the two first data lines DL1 and overlap with an orthographic projection portion of the same third conductive line L3 on the substrate base BS. The arrangement mode enables the data lines positioned between the pixel unit groups in the two adjacent columns of sub-pixels to be hidden under the third conducting wire, thereby reducing the wiring area and improving the light transmittance.

For example, as shown in fig. 12B, the blocking area LS1 includes a first portion LS11, a second portion LS12, a third portion LS13 and a fourth portion LS14, which overlap with the wirings connected to the pixel cell group shown in fig. 12A, respectively. For example, an orthogonal projection of the third portion LS13 of the blocking region LS1 on the substrate overlaps with the third conductive line L3 connected to the previous pixel cell group in fig. 12A, and the first portion DL11 and the second portion DL12 of the first data line DL1 overlap in an orthogonal projection on the substrate, so that the third conductive line L3, the first portion DL11 and the second portion DL12 of the first data line DL1, and a gap therebetween may be blocked. An orthogonal projection of the fourth portion LS14 of the blocking area LS1 on the substrate overlaps with the third conductive line L3 connected to the next pixel cell group, the first portion DL11 and the second portion DL12 of the first data line DL1 in an orthogonal projection on the substrate in fig. 12A. Orthographic projections of the first part LS11 and the second part LS12 of the shielding area LS1 on the substrate base plate are respectively overlapped with orthographic projections of the wiring lines connected with the left pixel unit group and the right pixel unit group on the substrate base plate.

As shown in fig. 12C, since the shielding connection part SP1 is located in the middle of the adjacent first pixel cells, in order to facilitate the disposition of the shielding connection part SP1, the active layer of the second reset transistor in the previous first pixel cell located in the same column of the same pixel cell group extends in the first direction Y1 and is connected to the active layer of the first reset transistor T6 of the next first pixel cell located in the same column. It should be noted that the embodiments of the present disclosure are not limited thereto.

Fig. 13A is a schematic view of an example of another display substrate provided in at least one embodiment of the present disclosure; FIG. 13B is a plan view of a shielding region LS1 of a shielding layer LS of the display substrate shown in FIG. 13A; FIG. 13C is a plan view of a semiconductor pattern of the display substrate shown in FIG. 13A; FIG. 13D is a plan view of the first conductive layer of the display substrate shown in FIG. 13A; FIG. 13E is a plan view of the second conductive layer of the display substrate shown in FIG. 13A; fig. 13F is a plan view of the third conductive layer of the display substrate shown in fig. 13A.

For example, the display substrate shown in fig. 13A is similar to the display substrate shown in fig. 12A except that: the first shielding connection parts SP1 are respectively located at two ends of each pixel cell group, and are connected to at least one of the plurality of first power lines VDD1 respectively corresponding to each pixel cell group. For example, the first shielding connection portions SP1 at two ends may be connected to the same first power line VDD1, or may be connected to two different first power lines VDD1 corresponding to the pixel unit group, that is, the two first shielding connection portions may be located in the same row or in different rows, which is not limited in this embodiment of the disclosure.

As shown in fig. 13B, the shielding region LS1 includes only portions LS21, LS22, LS23, and LS24 extending along the second direction X1, respectively shielding the traces connected to the left and right pixel cell groups. Since the third conductive line connecting the upper and lower pixel cell groups, the first portion and the second portion of the first data line DL1, respectively, in fig. 13A extend in the second direction X1, the blocking area LS1 shown in fig. 13B does not include a portion extending in the first direction Y1 direction, compared to the example in fig. 12B.

Note that when the shielding connection portions SP1 are located at two ends, as shown in fig. 13B, the semiconductor layers of the first pixel cells are the same, that is, the first pixel cells located in the same column are not connected, and the active layer of the second reset transistor is different from that in fig. 12C, and further includes a bending portion T74.

Fig. 14A is a schematic view of an example of yet another display substrate provided in at least one embodiment of the present disclosure; FIG. 14B is a plan view of a shielding region LS1 of a shielding layer LS of the display substrate shown in FIG. 14A; FIG. 14C is a plan view of a semiconductor pattern of the display substrate shown in FIG. 14A; FIG. 14D is a plan view of the first conductive layer of the display substrate shown in FIG. 14A; FIG. 14E is a plan view of the second conductive layer of the display substrate shown in FIG. 14A; fig. 14F is a plan view of the third conductive layer of the display substrate shown in fig. 14A. Fig. 15A is a schematic view of an example of yet another display substrate provided in at least one embodiment of the present disclosure; FIG. 15B is a plan view of a shielding region LS1 of a shielding layer LS of the display substrate shown in FIG. 15A; FIG. 15C is a plan view of a semiconductor pattern of the display substrate shown in FIG. 15A; FIG. 15D is a plan view of the first conductive layer of the display substrate shown in FIG. 15A; FIG. 15E is a plan view of the second conductive layer of the display substrate shown in FIG. 15A; fig. 15F is a plan view of the third conductive layer of the display substrate shown in fig. 15A.

For example, as shown in fig. 14A, one pixel cell group includes 2 first pixel cells 101 and 102. For example, as shown in fig. 15A, one pixel cell group includes 3 first pixel cells 101, 102, and 103.

The blocking region in fig. 15B is similar to the blocking region in fig. 12B, except that a protrusion is further included, and the same parts will not be described again.

For example, as shown in fig. 14A and 15A, the first shield connection parts SP1 are respectively located at one end of each pixel cell group, and are connected to at least one of the plurality of first power supply lines VDD1 corresponding to the pixel cell group. For example, the first shield connection part SP1 is connected to the first power line VDD1 connected to the first pixel unit 101, which is not limited by the embodiment of the present disclosure.

For example, as shown in fig. 14B, when the first shield connection SP1 is respectively located at one end, or both ends, of each pixel cell group, the shield region LS1 of the shield layer LS further includes a protrusion LS11 to overlap with the first shield connection SP1, so that diffraction of light, etc. may be prevented from occurring.

It should be noted that the above embodiments only schematically show the number and positions of the first shielding connection parts SP1, and of course, the number and positions of the first shielding connection parts SP1 corresponding to the display substrate of different embodiments may be more or less, and the embodiments of the present disclosure are not limited thereto.

It should be noted that the manner of connecting the shielding layer LS and the second power line VDD2 by the second shielding portion SP2 in the second display area 20 is substantially the same as the manner of connecting the first shielding portion SP2 in the first display area 10, and reference may be specifically made to the above description of fig. 7 and fig. 12A to fig. 15F, and details are not repeated here. For example, each second pixel unit C in the second display area 20 corresponds to one second shielding portion, so that the ELVDD signal is connected to the shielding layer LS in each pixel circuit, a stable dc signal is input to the shielding layer LD, and a large ELVDD signal network is formed in the entire display area, which is beneficial to reducing the trace voltage drop, increasing the display uniformity, and improving the display effect. Meanwhile, the light-shielding layers LS of the first display area 10 and the light-shielding layers LS of the second display area 20 are connected and integrally formed, so that an entire ELVDD signal network is formed, and the routing voltage drop of the power lines (i.e., the first power line VDD1 and the second power line VDD2) for supplying ELVDD signals is further reduced, thereby improving the display effect.

Fig. 16 is a schematic view of a display device according to at least one embodiment of the present disclosure. At least one embodiment of the present disclosure provides a display device 2, and the display device 2 may include the display substrate 1 of any of the above embodiments.

For example, as shown in fig. 16, the display device 2 may further include a flexible circuit board and a control chip. For example, a flexible circuit board is bonded to the bonding area of the display substrate 1, and a control chip is mounted on the flexible circuit board, thereby being electrically connected to the display area; alternatively, the control chip is directly bonded to the bonding area, thereby being electrically connected to the display area.

For example, the control chip may be a central processing unit, a digital signal processor, a system on a chip (SoC), and the like. For example, the control chip may further include a memory, a power module, and the like, and implement power supply and signal input and output functions through additionally provided wires, signal lines, and the like. For example, the control chip may also include hardware circuitry, computer executable code, and the like. The hardware circuits may include conventional Very Large Scale Integration (VLSI) circuits or gate arrays and off-the-shelf semiconductors such as logic chips, transistors, or other discrete components; the hardware circuitry may also include field programmable gate arrays, programmable array logic, programmable logic devices, or the like.

For example, the display device 2 provided in at least one embodiment of the present disclosure may be any product or component having a display function, such as an OLED panel, an OLED television, a QLED panel, a QLED television, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, and a navigator. The display device 2 may further include other components, such as a data driving circuit, a timing controller, and the like, which is not limited in this disclosure.

For example, as shown in fig. 16 and 1, the display device 2 further includes a sensor 192. The sensor 192 is disposed on the second side S2 (e.g., the non-display side) of the display substrate 1. The sensor 192 is configured to receive light (e.g., collimated light or collimated light) from a first side S1 of the display substrate 1 (e.g., the display side of the display substrate). The orthographic projection of the sensor 192 on the substrate base plate 100 at least partially overlaps the first display area 10.

For example, the sensor 192 is an image sensor, an infrared sensor, a distance sensor, etc., and the sensor 192 may be implemented in the form of a chip, etc., for example. The sensor 192 is disposed on the non-display side S2 (the side facing away from the user) of the display substrate.

For example, the sensor 192 and the first display area 10 at least partially overlap in a normal direction of the display surface of the display substrate.

For example, the sensor 192 may be an image sensor and may be used to capture an image of the external environment to which the light collecting surface of the sensor 192 faces, such as a CMOS image sensor or a CCD image sensor; the sensor 192 may also be an infrared sensor, a distance sensor, or the like. The sensor 192 may be used to implement a camera of a mobile terminal such as a mobile phone, a notebook, etc., and may further include an optical device such as a lens, a mirror, or an optical waveguide, etc., as necessary, to modulate an optical path. Embodiments of the present disclosure are not limited as to the type, function, and manner of arrangement of the sensors 192.

The sensor 192 is disposed on the non-display side S2 of the display panel by means of a double-sided tape or the like, and an orthogonal projection of the sensor 192 on the substrate base board 100 at least partially overlaps the first display area 10, and is configured to receive light from the first side S1. Thus, the first display area 10 facilitates the arrangement of the sensor 192 while realizing the display.

It should be noted that, for clarity and conciseness of representation, not all the constituent elements of the display device are given in the embodiments of the present disclosure. Other structures not shown may be provided and disposed according to specific needs by those skilled in the art to realize the substrate function of the display device, and the embodiment of the present disclosure is not limited thereto.

Regarding the technical effects of the display device provided by the above embodiments, reference may be made to the technical effects of the display substrate provided by the embodiments of the present disclosure, and details are not repeated here.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.