阅读说明：本技术 一种无线弱能量收集用量子阱沟道mosfet及其制备方法 (Quantum well channel MOSFET for wireless weak energy collection and preparation method thereof ) 是由 刘伟峰 张士琦 宋建军 于 2021-09-29 设计创作，主要内容包括：本发明公开了一种无线弱能量收集用量子阱沟道MOSFET及其制备方法,在n-MOSFET中引入具有高电子迁移率的应变量子阱沟道,同时通过近零阈值电压以及新的接线方式,使MOSFET在2.45G微波无线弱能量收集系统应用时,具有整流效率高、器件集成度高、工艺成本低的显著优势。(The invention discloses a quantum well channel MOSFET for wireless weak energy collection and a preparation method thereof.A strained quantum well channel with high electron mobility is introduced into an n-MOSFET, and meanwhile, the MOSFET has the remarkable advantages of high rectification efficiency, high device integration level and low process cost when applied to a 2.45G microwave wireless weak energy collection system through near-zero threshold voltage and a new wiring mode.)

1. A wireless quantum well channel MOSFET for weak energy collection, comprising: the grid electrode, the source region electrode, the drain region electrode and the substrate are connected together in a short-circuit mode to serve as input ends;

and a strain Si layer is arranged among the gate region electrode, the source region electrode and the drain region electrode and the substrate, and the strain Si layer forms a quantum well channel of the MOSFET.

2. The preparation method of the quantum well channel MOSFET for the wireless weak energy collection, which is applied to the claim 1, is characterized by comprising the following steps:

epitaxially forming a SiGe layer with gradually changed components on a single crystal Si substrate;

epitaxially forming a SiGe layer with fixed components on the SiGe layer with gradually changed components to serve as a virtual substrate;

pseudomorphically growing a strain Si layer on the virtual substrate;

depositing an intrinsic Si cap layer on the strained Si layer;

depositing a hafnium oxide layer on the intrinsic Si cap layer;

depositing a TaN layer on the hafnium oxide layer;

etching the TaN layer and the hafnium oxide layer to form a gate electrode;

performing P-type ion implantation in the SiGe layer, the virtual substrate, the strained Si layer and the intrinsic Si cap layer with gradually changed components on two sides of the gate region electrode to form a source drain region;

depositing a dielectric layer on the gate region electrode and the source and drain regions;

etching two contact holes on the dielectric layers on two sides of the grid electrode;

depositing metal in the two contact holes to respectively form a source region electrode and a drain region electrode;

and taking the source region electrode as an output end, and taking the grid region electrode, the drain region electrode and the substrate short circuit as input ends.

3. The method for preparing a quantum well channel MOSFET for wireless weak energy collection according to claim 2, wherein P-type ion implantation is performed in the SiGe layer, the virtual substrate, the strained Si layer and the intrinsic Si cap layer with gradually changed components at two sides of the gate electrode to form a source drain region, comprising:

depositing SiO on the gate electrode and the strained Si layer₂；

In the SiO₂Depositing a sacrificial protective layer;

etching the SiO outside the grid electrode₂A layer and a sacrificial protective layer;

coating photoresist on the sacrificial protection layer;

and performing P-type ion implantation in the SiGe layer, the virtual substrate, the strained Si layer and the intrinsic Si cap layer with gradually changed components on two sides of the photoresist to form the source and drain regions.

4. The method for preparing the quantum well channel MOSFET for the wireless weak energy collection, according to claim 3, wherein before depositing the dielectric layer on the gate electrode and the source and drain regions, the method further comprises:

removing the photoresist;

removing the sacrificial protective layer and the SiO covered on the gate electrode₂And (3) a layer.

5. The method as claimed in claim 2, wherein the step of depositing metal in the two contact holes to form a source region electrode and a drain region electrode respectively comprises:

depositing metal layers on the dielectric layer of the source drain region and in the two contact holes;

and etching the metal layers except the metal layers in the two contact holes, wherein the metal layers in the two contact holes form the source region electrode and the drain region electrode.

6. The method as claimed in claim 2, wherein after the metal is deposited in the two contact holes to form the source region electrode and the drain region electrode, respectively, the method further comprises:

and depositing a passivation dielectric layer on the dielectric layer, the source region electrode and the drain region electrode.

7. The method as claimed in claim 2, wherein the thickness of the SiGe layer with gradually changed composition is 200-300nm, the Ge composition ratio is gradually decreased along the direction close to the single crystal Si substrate, the Ge highest composition ratio is 15%, and the P-type doping concentration of SiGe is 1 x 10%¹⁶cm^-3～1×10¹⁷cm^-3。

8. The method of claim 2The preparation method of the quantum well channel MOSFET for wireless weak energy collection is characterized in that the component proportion of Ge in the SiGe layer with fixed component is 15%, the thickness of the SiGe layer with fixed component is 400-500nm, and the P-type doping concentration is 1 multiplied by 10¹⁶cm^-3～1×10¹⁷cm^-3。

9. The method of claim 2, wherein the strained Si layer has a thickness of 10nm and has a lattice constant identical to that of a fixed-composition SiGe layer.

Technical Field

The invention relates to the technical field of semiconductor integrated circuits, in particular to a quantum well channel MOSFET for wireless weak energy collection and a preparation method thereof.

Background

A microwave wireless energy transmission system is a system that converts radio frequency energy into direct current voltage, and can also transmit electric energy in a space without a transmission line. At present, batteries are the main energy sources for various electronic products, and the limited capacity and service life of the batteries are a technical bottleneck for restricting the further development and application of the products. The microwave wireless energy transmission system provides a good solution for various problems of battery power supply at present.

The energy conversion efficiency (i.e., rectification efficiency) marks the ability of a microwave wireless energy transmission system to convert rf energy into dc energy. In a living environment, a plurality of wireless terminals such as Wi-Fi routers, notebook computers and tablet computers exist, according to the evaluation of the distribution of Radio Frequency energy in the environment of China, Radio Frequency signals in a 2.38-2.45G Frequency band are main RF (Radio Frequency) signal sources in the environment, but the actual environment Radio Frequency power density is low and is generally lower than 0 dBm. The microwave wireless energy collection technology has low energy rectification efficiency on the part, thereby causing energy waste. As known in the prior art, the current domestic and foreign researches on microwave wireless energy transmission systems mostly aim at the improvement of rectification efficiency under medium-high energy density, and the improvement of rectification efficiency under the working condition of weaker energy density (-15 dBm-0 dBm) still has no substantial breakthrough. Therefore, research on a 2.45G frequency band wireless energy collection technology with weak energy density improves rectification efficiency under low power density, so that power supply of an internet of things sensor system with higher efficiency is realized, and the method becomes one of hot spots and key directions of research in the field.

At present, an n-type metal-oxide-semiconductor field effect transistor (n-MOSFET) connected in a diode form has the advantage of being compatible with a Si process, so that the performance of the n-type MOSFET is used as a core element in a rectification circuit of a 2.45G weak energy density wireless energy collection system, and the performance of the n-type MOSFET determines the upper limit of the rectification efficiency of the whole rectification system. Unfortunately, the rectification efficiency of the diode-connected n-MOSFET-based 2.45G weak energy density collection system is low, and the commercial application cannot be really realized. At present, engineers mainly develop an optimization research and development work based on a CMOS rectification circuit through the design and structure optimization of a peripheral circuit to improve the rectification efficiency of a 2.45G weak energy density wireless energy collection system, but the effect is very small. Therefore, in order to further improve the rectification efficiency of the existing 2.45G weak energy density Wi-Fi band wireless energy collection system, the design optimization of core n-MOSFET components is imperative.

Disclosure of Invention

The embodiment of the invention provides a quantum well channel MOSFET for wireless weak energy collection and a preparation method thereof, which are used for solving the problem of low rectification efficiency of an n-MOSFET 2.45G weak energy density wireless energy collection system in the prior art.

In one aspect, an embodiment of the present invention provides a quantum well trench MOSFET for wireless weak energy collection, including: the grid electrode, the source region electrode, the drain region electrode and the substrate are connected together in a short-circuit mode to serve as an input end;

and a strained Si layer is arranged among the gate electrode, the source electrode and the drain electrode and the substrate, and the strained Si layer forms a quantum well channel of the MOSFET.

On the other hand, the embodiment of the invention also provides a preparation method of the quantum well channel MOSFET for wireless weak energy collection, which comprises the following steps:

epitaxially forming a SiGe layer with gradually changed components on a single crystal Si substrate;

epitaxially forming a SiGe layer with fixed components on the SiGe layer with gradually changed components to be used as a virtual substrate;

pseudomorphic growth of a strained Si layer on a virtual substrate;

depositing an intrinsic Si cap layer on the strained Si layer;

depositing a hafnium oxide layer on the intrinsic Si cap layer;

depositing a TaN layer on the hafnium oxide layer;

etching the TaN layer and the hafnium oxide layer to form a gate electrode;

performing P-type ion implantation in the SiGe layer, the virtual substrate, the strained Si layer and the intrinsic Si cap layer with gradually changed components on two sides of the gate electrode to form a source drain region;

depositing a dielectric layer on the gate region electrode and the source and drain regions;

etching two contact holes on the dielectric layers on two sides of the grid electrode;

depositing metal in the two contact holes to respectively form a source region electrode and a drain region electrode;

and taking the source region electrode as an output end, and taking the grid region electrode, the drain region electrode and the substrate short circuit as input ends.

In one possible implementation, the components on both sides of the gate electrodeP-type ion implantation is carried out in the SiGe layer, the virtual substrate, the strain Si layer and the intrinsic Si cap layer which are gradually changed to form a source drain region, and the method comprises the following steps: deposition of SiO on gate electrodes and strained Si layers₂(ii) a In SiO₂Depositing a sacrificial protective layer; etching SiO except for gate electrode₂A layer and a sacrificial protective layer; coating photoresist on the sacrificial protective layer; and performing P-type ion implantation in the SiGe layer, the virtual substrate, the strained Si layer and the intrinsic Si cap layer with gradually changed components on two sides of the photoresist to form a source drain region.

In a possible implementation manner, before depositing a dielectric layer on the gate electrode and the source and drain regions, the method further includes: removing the photoresist; removing the sacrificial protective layer and SiO covered on the gate electrode₂And (3) a layer.

In one possible implementation, depositing metal in two contact holes to form a source region electrode and a drain region electrode, respectively, includes: depositing metal layers on the dielectric layer of the source drain region and in the two contact holes; and etching the metal layers except the metal layers in the two contact holes, wherein the metal layers in the two contact holes form a source region electrode and a drain region electrode.

In one possible implementation manner, after depositing metal in the two contact holes to form the source region electrode and the drain region electrode respectively, the method further includes: and depositing a passivation dielectric layer on the dielectric layer, the source region electrode and the drain region electrode.

In one possible implementation, the thickness of the SiGe layer with gradually changed composition is 200-300nm, the Ge composition ratio is gradually reduced along the direction close to the single crystal Si substrate, the highest composition ratio of Ge is 15%, and the P-type doping concentration of SiGe is 1 × 10¹⁶cm^-3～1×10¹⁷cm^-3。

In one possible implementation, the Ge component ratio in the fixed-component SiGe layer is 15%, the thickness of the fixed-component SiGe layer is 400-500nm, and the P-type doping concentration is 1 × 10¹⁶cm^-3～1×10¹⁷cm^-3。

In one possible implementation, the strained Si layer has a thickness of 10nm and has a lattice constant that is the same as the lattice constant of the fixed-composition SiGe layer.

The quantum well channel MOSFET for wireless weak energy collection and the preparation method thereof have the following advantages:

a high-electron-mobility strain quantum well channel is introduced into an n-MOSFET, and a near-zero threshold voltage and a new wiring mode are adopted, so that the n-MOSFET has the remarkable advantages of high rectification efficiency, high device integration level and low process cost when applied to a 2.45G microwave wireless weak energy collection system.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic diagram of forward bias currents of a wireless quantum well channel MOSFET for weak energy collection and a connection thereof according to an embodiment of the present invention;

fig. 2 is a schematic diagram of reverse leakage currents of a wireless quantum well channel MOSFET for weak energy collection and a connection thereof according to an embodiment of the present invention;

fig. 3 is a schematic flow chart of a method for manufacturing a MOSFET according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 and fig. 2 are schematic diagrams of a wireless weak energy collection quantum well trench MOSFET and a connection thereof according to an embodiment of the present invention. The embodiment of the invention provides a quantum well channel MOSFET for wireless weak energy collection, which comprises: the grid electrode, the source region electrode, the drain region electrode and the substrate are connected together in a short-circuit mode to serve as an input end;

and a strained Si layer is arranged among the gate electrode, the source electrode and the drain electrode and the substrate, and the strained Si layer forms a quantum well channel of the MOSFET.

Illustratively, under the n-MOSFET and the wiring mode thereof provided by the invention, the drain-substrate PN junction is shorted, and the source-substrate PN junction is in effect.

Furthermore, the wiring scheme proposed by the present invention changes the bulk connection of the n-MOSFET such that the bias voltage V between the source and drain is_SBNot zero and thus there is a substrate bias effect as shown in equation (1).

Where γ is the bulk coefficient depending on the channel doping, V_SBIs the source-substrate potential difference, phi_FIs the Fermi potential in the semiconductor, dependent on the doping concentration and temperature, V_THAnd V_TH0The actual threshold voltage of the MOS tube and the ideal threshold voltage under the condition of zero substrate bias are respectively.

Meanwhile, the current extracted according to the BSIM3 transistor model is shown in formula (2), and V is obtained when a forward voltage is applied under the wiring mode provided by the invention_SB<0, which effectively reduces the forward starting voltage and greatly improves the forward bias current; when reverse voltage is applied V_SB>0, thereby greatly reducing reverse leakage current, and the physical characteristics are very favorable for eliminating the problems of high reverse leakage current of a low-threshold voltage device and large sub-threshold current of a quantum well channel, thereby effectively improving the efficiency of the n-MOSFET rectifying circuit.

In the formula, V_TKT/q is called thermal voltage, V_dIs the input voltage applied to the drain-source of the MOS transistor, and λ is the channel length modulation factor, μ_nIs the electron mobility, ε_SiIs the dielectric constant of Si, N_chIs the concentration of the doping in the channel,is the surface potential.

In a 2.45G weak energy density RF signal collection system, the input power of the signal tends to be very low, with an equivalent input amplitude of only 100mV at 50 Ω impedance for a radio frequency input power of-10 dBm. Therefore, for 2.45G weak energy density Wi-Fi band wireless energy, the normal starting operation of the MOSFET device is guaranteed. Therefore, the invention obviously reduces the threshold voltage of the n-MOSFET and even reaches the near-zero threshold voltage by optimally designing the physical parameters, particularly the work function, of the layer structure materials of each part of the device, so as to be beneficial to the starting application of the device in 2.45G weak energy density collection.

Meanwhile, in order to realize high energy conversion efficiency, the I-V characteristic of an ideal rectifying device should simultaneously present a large forward bias current and a very small reverse leakage current. In order to improve the rectification forward current density, the strain quantum well channel is introduced during device design, and the common effects of no surface roughness scattering, ionized impurity scattering and strain-induced electron migration enhancement of the strain quantum well channel are utilized to obviously improve the forward bias current of the device during weak energy rectification application. Meanwhile, in order to avoid the problems that a low-threshold-voltage device is high in reverse leakage current and large in quantum well channel subthreshold current, the substrate is further introduced, and the substrate bias effect and a new wiring mode are utilized to overcome the problems.

The embodiment of the invention also provides a preparation method of the quantum well channel MOSFET for wireless weak energy collection, and as shown in FIG. 3, the method comprises the following steps:

s200, as in fig. 3 (a), selecting a single crystal Si substrate (001);

s201, as shown in FIG. 3 (b), using RPCVD (reduced pressure chemical vapor deposition) technique on a single crystal Si substrate (001)A SiGe layer (002) with gradually changed Ge components is extended, the thickness is 200-300nm, the Ge component proportion of the SiGe layer (002) with gradually changed components is gradually reduced along the direction close to the single crystal Si substrate (001), the Ge component of the topmost layer (namely the position with the highest Ge component proportion) is 15%, and the P-type doping concentration is 1 multiplied by 10¹⁶cm^-3～1×10¹⁷cm^-3；

S202, as shown in (c) of FIG. 3, a layer of Si with a constant 15% Ge composition is epitaxially grown on the compositionally graded SiGe layer (002) by using an RPCVD technique_0.85Ge_0.15The layer (003) is used as a dummy substrate with a thickness of 400-500nm and a P-type doping concentration of 1 × 10¹⁶cm^-3～1×10¹⁷cm^-3；

S203, as shown in (d) of FIG. 3, pseudomorphically growing a strained Si layer (004) with a thickness of 10nm on the surface of the virtual substrate formed in the step S502. Due to the difference of lattice constants of Si and SiGe, the lattice constant of a pseudomorphically grown strained Si layer (004) is kept consistent with the lattice constant of a SiGe layer (003) with fixed components below by controlling the process conditions, so that tensile strain is introduced into the strained Si layer (004), the effective quality of electrons is reduced by introducing the tensile strain, and the mobility of the electrons is improved; simultaneously, the forbidden bandwidth of Si is also reduced, so that the SiGe layer and the deep Delta E layer are formed_CThe conduction band offset heterojunction is beneficial to forming a quantum well channel;

s204, as shown in (E) of FIG. 3, depositing an intrinsic Si cap layer (005) with a thickness of 4-6 nm on the strained Si layer (004) by using an MBE process in a vacuum environment, and forming a deep delta E with the strained Si layer (004)_CA conduction band offset heterojunction;

s205, as shown in (f) of FIG. 3, depositing hafnium oxide (HfO) with a thickness of 3nm by atomic layer deposition at 250-300 deg.C₂) Layer (006) with the reaction precursor [ (CH)₃)(C₂H₅)N]₄Hf, the oxidant is H₂O；

S206, as shown in (g) of FIG. 3, depositing a tantalum nitride (TaN) layer (007) with the thickness of 110nm by using a reactive sputtering system;

s207, as shown in fig. 3 (h), selectively etching away the tantalum nitride (TaN) layer (007) and the hafnium oxide layer (006) in the designated region by using an etching process to form an NMOS gate electrode, specifically, etching away both side regions except the central region;

s208, as shown in (i) of FIG. 3, depositing a thin SiO2 layer (008) with a thickness of about 10nm on the gate electrode and the surface of the strained Si layer (004);

s209, as shown in (j) of FIG. 3, depositing Si with a thickness of 20-30 nm by CVD (chemical vapor deposition)₃N₄The layer is used as a sacrificial protective layer (009) which is used for protecting the gate region electrode from being damaged in the etching process of the source and drain regions and not influencing the self-alignment process of source and drain ion implantation;

s210, as shown in (k) of FIG. 3, etching the SiO except the gate electrode₂A layer (008) and a sacrificial protective layer (009);

s211, as shown in (l) of fig. 3, performing photolithography, applying glue, and selectively exposing regions. Reserving photoresist (010) in the area at the center, and etching away the photoresist at the periphery;

s212, as shown in a figure 3 (m), carrying out P-type ion implantation on the SiGe layer, the virtual substrate, the strained Si layer and the intrinsic Si cap layer with gradually changed components by adopting a self-alignment process, and rapidly annealing at the temperature of 250-300 ℃ in a nitrogen environment to form an NMOS source drain region (011);

s213, as shown in (n) of FIG. 3, removing the photoresist and removing the sacrificial protective layer and SiO covered by the gate electrode by wet etching₂A layer;

s214, as shown in (o) of FIG. 3, a dielectric layer (012) is deposited, BPSG (borophosphosilicate glass) with 20-30 nm is deposited by a CVD method, and a dielectric layer (PMD) is formed. BPSG can trap mobile ions to prevent them from diffusing to the gate electrode and compromising device performance;

s215, as shown in fig. 3 (p), the contact hole is etched. Etching BPSG by nitric acid and hydrofluoric acid to form a source drain contact hole;

s216, as shown in (q) of FIG. 3, metal is deposited. Depositing a metal nickel Ni layer (012) with the thickness of 10-20 nm by electron beam evaporation so as to form good ohmic contact;

s217, as shown in (r) of FIG. 3, selectively etching away the metal Ni layer outside the contact hole by using an etching process to form a source region electrode and a drain region electrode;

s218, as shown in (S) of FIG. 3, depositing SiN material (013) with the thickness of 20-30 nm on the dielectric layer, the source region electrode and the drain region electrode by using a CVD (chemical vapor deposition) process for passivating the dielectric to finally form the strained Si layer quantum well channel MOSFET.

S219, as shown in (t) and (u) of fig. 3, is a diode connection mode of the quantum well trench MOSFET for wireless weak energy collection, and the source-drain PN junction is turned on under a forward bias condition, and a trench current acts to be able to provide a forward conduction current. Under the reverse bias condition, the source-substrate PN junction is cut off, and the reverse saturation current is extremely low.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.