阅读说明：本技术 一种模拟频率比较器 (Analog frequency comparator ) 是由 方健 江秋亮 刘晨旭 许明明 刘颖 王腾磊 魏亚瑞 于 2021-09-29 设计创作，主要内容包括：本发明属于模拟电路技术领域,具体的说是涉及一种模拟频率比较器。该频率比较器包含有：占空比转换模块用来将输入占空比不固定的输入信号转换为占空比固定的二分频信号；频率电压转换模块用来产生峰值电压与输入信号频率成反比的三角波信号；参考电压基准用于产生电压基准信号；比较器用于比较三角波信号与参考电压基准信号的大小；D触发器用于输出三角波信号峰值电压与参考电压基准信号的比较结果,并依据该输出电压电平来决定第一信号频率与固定参考频率之间的频率关系。(The invention belongs to the technical field of analog circuits, and particularly relates to an analog frequency comparator. The frequency comparator comprises: the duty ratio conversion module is used for converting an input signal with an unfixed duty ratio into a two-frequency division signal with a fixed duty ratio; the frequency-voltage conversion module is used for generating a triangular wave signal of which the peak voltage is inversely proportional to the frequency of the input signal; a reference voltage reference for generating a voltage reference signal; the comparator is used for comparing the magnitude of the triangular wave signal with the reference voltage reference signal; the D flip-flop is used for outputting a comparison result of the peak voltage of the triangular wave signal and the reference voltage reference signal, and determining the frequency relation between the first signal frequency and the fixed reference frequency according to the output voltage level.)

1. An analog frequency comparator is characterized by comprising a duty ratio conversion module, a frequency-voltage conversion module, a comparator and a D trigger; the input end of the duty ratio conversion module inputs a PWM signal, and the output end of the duty ratio conversion module is connected with the input end of the frequency-voltage conversion module and the clock input end of the D trigger; the output end of the frequency-voltage conversion module is connected with the non-inverting input end of the comparator, the inverting input end of the comparator is connected with the reference voltage, and the output end of the comparator is connected with the signal input end of the D trigger; the Q output end of the D trigger outputs a logic signal for the output end of the analog frequency comparator;

the duty ratio conversion module is used for converting an input PWM square wave signal with a non-fixed duty ratio into a square wave signal with a fixed duty ratio;

the frequency-voltage conversion module is used for converting the square wave signal with the fixed duty ratio into a voltage signal with the magnitude inversely related to the frequency of the square wave signal with the fixed duty ratio.

Technical Field

The invention belongs to the technical field of analog circuits, and particularly relates to an analog frequency comparator.

Background

Frequency comparators are widely used in measurement and communication technologies, and are used to determine the magnitude relationship between an input signal frequency and a reference signal frequency and to provide a determination logic signal.

A known frequency comparator includes a frequency detection circuit, a first counting circuit, a second counting circuit and a logic judger.

Another known frequency comparator includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, and an and gate.

The first known frequency comparator needs to use two counting circuits and an internal clock signal, and the circuit is complex and needs to perform logical judgment of signal frequency through one internal clock cycle, i.e. multiple signal cycles. Another known frequency comparator requires the input of a reference frequency.

Disclosure of Invention

The invention provides an analog frequency comparator, which compares an input PWM signal with an internal reference frequency and outputs a judgment logic signal.

The invention provides an analog frequency comparator which comprises a duty ratio conversion module, a frequency voltage conversion module, a comparator, a reference voltage reference and a D trigger. The input end of the duty ratio conversion module is connected with an input PWM signal, and the output end of the duty ratio conversion module is connected with the input end of the frequency-voltage conversion module and the clock input end of the D trigger. And the output end of the frequency-voltage conversion module is connected with the positive input end of the comparator. And the negative input end of the comparator is connected with the reference voltage reference, and the output end of the comparator is connected with the signal input end of the D trigger.

In the frequency comparator, the duty ratio conversion module converts the input PWM square wave signal with unfixed duty ratio into the square wave signal with fixed duty ratio.

In the frequency comparator, the frequency-voltage conversion module converts the square wave signal with the fixed space ratio into a voltage signal with a magnitude inversely related to the frequency of the square wave signal with the fixed duty ratio.

In the frequency comparator, the comparator compares the voltage signal with a reference voltage reference and outputs a judgment logic signal.

The analog frequency comparator has the advantages that the analog frequency comparator is simple in structure and high in speed, and the judgment of input signal logic is delayed by only one input signal period.

Drawings

Fig. 1 is a schematic diagram of an embodiment of a frequency comparator of the present invention.

Fig. 2 is a schematic diagram of a duty cycle conversion module in an embodiment.

Fig. 3 is a schematic diagram of a frequency-to-voltage conversion module in an embodiment.

Fig. 4 is a timing diagram of the operation of the frequency comparator of the present invention.

Detailed Description

The frequency comparator of the present invention will be described in further detail with reference to the accompanying drawings and examples.

Examples

Referring to fig. 1, the frequency comparator of this example includes a duty ratio conversion module 1, a frequency-voltage conversion module 2, a comparator 3, a voltage reference module 4, and a D flip-flop 5. Wherein the duty ratio conversion module 1 converts the input PWM signal (external input signal) with variable duty ratio into the first signal S with 50% duty ratio₁. First signal S₁As an input signal to the frequency-to-voltage conversion module 2 and as a clock signal to the D flip-flop 5. The frequency-voltage conversion module 2 converts the first signal S into the second signal S₁Outputting a second signal S₂A second signal S₂Is a peak voltage and the first signal S₁Triangular wave signals with negative frequency correlation. The positive input end of the comparator 3 is connected with the second signal S₂The negative input end is connected with the voltage reference module 4(VREF) and outputs a third signal S of the judgment logic signal₃. The input end of the D trigger 5 is connected with the third signal S₃The clock input terminal is connected with the first signal S₁For outputting a second signal S₂The result of the comparison of the voltage peak value with the reference voltage signal VREF.

FIG. 2 is an embodiment of the duty cycle conversion module 1 shown in FIG. 1, which is triggered by a DThe hair styling device is composed of a hair styling device. The input PWM signal is connected with the clock input end of the D trigger, and the inverted output end of the D trigger is connected with the input end of the D trigger to form a two-frequency-dividing circuit. Outputs a first signal S₁Is one half of the frequency of the input signal, outputs a first signal S₁The duty cycle is a signal with a fixed 50% duty cycle.

FIG. 3 is a schematic diagram of an embodiment of the frequency-voltage conversion module 2 shown in FIG. 1, including a PMOS transistor M₁NMOS transistor M₂Two current sources I₁And I₂And a capacitor C. When the input signal is at low level, M₁Pipe conduction, M₂The tube is turned off and the circuit has a size of I₁The current of (2) charges a capacitor C, the voltage on the capacitor having a relation to the charging time ofWhen the input signal is high, M₂Pipe conduction, M₁The tube is turned off and the circuit has a size of I₂Is discharged to the capacitor C, usually by taking the discharge current I₂Greater than the charging current I₁To ensure that the voltage on the capacitor can reach ground level. When the input signal is the first signal S with the duty ratio of 50 percent and the frequency of half of the frequency of the input signal₁Then outputs a second signal S₂The relationship between the peak voltage of (a) and the input signal frequency f is:

if the input signal frequency f is compared with the reference frequency f1, the reference voltage of the voltage reference module 4 is requiredWhen the second signal S₂When the voltage is greater than the reference voltage VREF, the comparator outputs a third signal S₃At high level when the second signal S₂When the voltage of the reference voltage VREF is less than the first reference voltage, the comparator outputs a third signal S₃Is low. Third signal S₃Connected to the input of the D flip-flop, a first signal S₁And the D flip-flop is connected with a clock input end of the D flip-flop. When the first signal isS₁At low level, the current source I₁Charging the capacitor C when the first signal S₁At high level, the current source I₂Discharging the capacitor C at the first signal S₁The voltage at the two ends of the capacitor just reaches the peak voltage during the rising edgeD flip-flop triggered by rising edge, wherein the output signal is just the peak voltageAnd a reference voltageThe comparison outputs a logic signal. When the input signal frequency f is greater than the reference frequency f1, the output is at low level, and when the input signal frequency f is less than the reference frequency f1, the output signal is at high level.

FIG. 4 is a timing diagram of the waveforms when the frequency of the input signal is less than the reference frequency and the frequency of the input signal is greater than the reference frequency. The input signal passes through a space ratio conversion module 1 to output a first signal S of a halved frequency signal with a duty ratio of 50%₁First signal S₁As an input signal of the frequency-voltage conversion module 2 and a clock signal of the D flip-flop, the D flip-flop is controlled to output a peak voltageWith reference voltageThe comparison outputs a logic signal.