阅读说明：本技术 一种通讯干扰防御电路 (Communication interference defense circuit ) 是由 霍煜 魏斌 张建 苏兴龙 赵博 于 2021-10-25 设计创作，主要内容包括：本发明提供一种通讯干扰防御电路,包括两组结构相同的电路：第一组电路包括由输入端至输出端依次连接的第一差分放大电路、第一延时放大电路、第一比较电路和第一互锁电路；第二组电路包括由输入端至输出端依次连接的第二差分放大电路、第二延时放大电路、第二比较电路和第二互锁电路。第一差分放大电路的输入端连接第一通讯端口,输出端依次经由第一延时放大电路和第一比较电路后连接至第一互锁电路的第一输入端,第一互锁电路的第二输入端连接第二互锁电路的第二输出端,第一互锁电路的第一输出端连接第二通讯端口,第一互锁电路的第二输出端连接至第二互锁电路的第二输入端。能够解决双工通讯信号传输过程中的通讯抗干扰问题。(The invention provides a communication interference defense circuit, which comprises two groups of circuits with the same structure: the first group of circuits comprises a first differential amplifying circuit, a first delay amplifying circuit, a first comparison circuit and a first interlocking circuit which are sequentially connected from the input end to the output end; the second group of circuits comprises a second differential amplifying circuit, a second delay amplifying circuit, a second comparing circuit and a second interlocking circuit which are sequentially connected from the input end to the output end. The input end of the first differential amplifying circuit is connected with the first communication port, the output end of the first differential amplifying circuit is connected to the first input end of the first interlocking circuit after sequentially passing through the first delay amplifying circuit and the first comparison circuit, the second input end of the first interlocking circuit is connected with the second output end of the second interlocking circuit, the first output end of the first interlocking circuit is connected with the second communication port, and the second output end of the first interlocking circuit is connected to the second input end of the second interlocking circuit. The problem of communication anti-interference in the duplex communication signal transmission process can be solved.)

1. A communication interference defense circuit is characterized by comprising two groups of circuits with the same structure: a first set of circuits and a second set of circuits; the first group of circuits comprises a first differential amplifying circuit, a first delay amplifying circuit, a first comparison circuit and a first interlocking circuit which are sequentially connected from the input end to the output end; the second group of circuits comprises a second differential amplifying circuit, a second delay amplifying circuit, a second comparing circuit and a second interlocking circuit which are sequentially connected from the input end to the output end;

the input end of the first differential amplification circuit is connected with the first communication port, the output end of the first differential amplification circuit is connected to the first input end of the first interlocking circuit after sequentially passing through the first delay amplification circuit and the first comparison circuit, the second input end of the first interlocking circuit is connected with the second output end of the second interlocking circuit, the first output end of the first interlocking circuit is connected with the second communication port, and the second output end of the first interlocking circuit is connected to the second input end of the second interlocking circuit;

the input end of the second differential amplifying circuit is connected with the second communication port, the output end of the second differential amplifying circuit is connected to the first input end of the second interlocking circuit after sequentially passing through the second delay amplifying circuit and the second comparison circuit, the second input end of the second interlocking circuit is connected with the second output end of the first interlocking circuit, the first output end of the second interlocking circuit is connected with the first communication port, and the second output end of the second interlocking circuit is connected to the second input end of the first interlocking circuit.

2. The communication disturbance defense circuit according to claim 1, wherein the first differential amplifier circuit and the second differential amplifier circuit have the same structure and are low-pass differential amplifier circuits each formed by an operational amplifier.

3. The circuit of claim 1, wherein the first delay amplifying circuit and the second delay amplifying circuit have the same structure, and each of the first delay amplifying circuit and the second delay amplifying circuit includes a preceding RC delay circuit and a succeeding inverse proportional-integral amplifier formed by an operational amplifier.

4. The circuit of claim 1, wherein the first and second comparison circuits are identical in structure and are both comparison circuits comprising comparators.

5. The communication disturbance defense circuit according to claim 1, wherein the first interlock circuit and the second interlock circuit are identical in structure and each includes a nand gate and two inverters;

two input ends of a NAND gate of the first interlocking circuit are respectively connected with an output end of the first comparison circuit and a second output end of the second interlocking circuit, the output end of the NAND gate is divided into three paths, the first path is directly connected with a first differential end of the second communication port, the second path is connected with a second differential end of the second communication port after passing through a first phase inverter of the first interlocking circuit, and the two paths are the first output end of the first interlocking circuit and are connected with the second communication port; the third path is a second output end of the first interlocking circuit after passing through a second inverter of the first interlocking circuit and is connected to a second input end of the NAND gate of the second interlocking circuit;

two input ends of a NAND gate of the second interlocking circuit are respectively connected with the output end of the second comparison circuit and the second output end of the first interlocking circuit, the output end of the NAND gate is divided into three paths, the first path is directly connected with the first differential end of the first communication port, the second path is connected with the second differential end of the first communication port after passing through the first phase inverter of the second interlocking circuit, and the two paths are the first output ends of the second interlocking circuit and are connected with the first communication port; the third path is a second output end of the second interlocking circuit after passing through a second inverter of the second interlocking circuit and is connected to a second input end of the NAND gate of the first interlocking circuit.

Technical Field

The invention relates to the technical field of communication circuits, in particular to a communication interference defense circuit.

Background

In the era of rapid development of electronic products, communication transmission of electrical and electronic devices is also updated at different times. The protocol is more and more complex, the signal quantity is more and more large, and the communication range is more and more extensive. Especially, electrical products do not exchange signals with each other all the time.

Under the background, the correct and error-free transmission of communication signals and the reduction of the error rate are the key for ensuring whether the equipment can work normally. However, some methods, such as various checks, various communication modes CAN, 485, etc., have been developed, and it is not necessary to improve the accuracy of communication, the transmission amount, and the transmission distance.

The circuit is developed on the basis of communication square waves, has stronger filtering capacity on clutter signals, stronger reducing capacity on weaker signals and stronger range-extending capacity on insufficient communication distance, can form a plurality of repeaters, and can theoretically support infinite long-distance transmission signals.

Disclosure of Invention

In order to solve the technical problems in the background art, the invention provides a communication interference defense circuit which can solve the problem of communication interference resistance in the process of duplex communication signal transmission.

In order to achieve the purpose, the invention adopts the following technical scheme:

a communication interference defending circuit comprises two groups of circuits with the same structure: a first set of circuits and a second set of circuits; the first group of circuits comprises a first differential amplifying circuit, a first delay amplifying circuit, a first comparison circuit and a first interlocking circuit which are sequentially connected from the input end to the output end; the second group of circuits comprises a second differential amplifying circuit, a second delay amplifying circuit, a second comparing circuit and a second interlocking circuit which are sequentially connected from the input end to the output end.

The input end of the first differential amplifying circuit is connected with the first communication port, the output end of the first differential amplifying circuit is connected to the first input end of the first interlocking circuit after sequentially passing through the first delay amplifying circuit and the first comparison circuit, the second input end of the first interlocking circuit is connected with the second output end of the second interlocking circuit, the first output end of the first interlocking circuit is connected with the second communication port, and the second output end of the first interlocking circuit is connected to the second input end of the second interlocking circuit.

The input end of the second differential amplifying circuit is connected with the second communication port, the output end of the second differential amplifying circuit is connected to the first input end of the second interlocking circuit after sequentially passing through the second delay amplifying circuit and the second comparison circuit, the second input end of the second interlocking circuit is connected with the second output end of the first interlocking circuit, the first output end of the second interlocking circuit is connected with the first communication port, and the second output end of the second interlocking circuit is connected to the second input end of the first interlocking circuit.

Furthermore, the first differential amplifier circuit and the second differential amplifier circuit have the same structure and are both low-pass differential amplifier circuits formed by operational amplifiers.

Furthermore, the first delay amplifying circuit and the second delay amplifying circuit have the same structure and both comprise a front-stage RC delay circuit and a rear-stage inverse proportional-integral amplifier formed by an operational amplifier.

Furthermore, the first comparison circuit and the second comparison circuit have the same structure and are both comparison circuits formed by comparators.

Further, the first interlock circuit and the second interlock circuit have the same structure and both comprise a nand gate and two inverters. Two input ends of a NAND gate of the first interlocking circuit are respectively connected with an output end of the first comparison circuit and a second output end of the second interlocking circuit, the output end of the NAND gate is divided into three paths, the first path is directly connected with a first differential end of the second communication port, the second path is connected with a second differential end of the second communication port after passing through a first phase inverter of the first interlocking circuit, and the two paths are the first output end of the first interlocking circuit and are connected with the second communication port; the third path is a second output end of the first interlocking circuit after passing through the second inverter of the first interlocking circuit and is connected to a second input end of the NAND gate of the second interlocking circuit. Two input ends of a NAND gate of the second interlocking circuit are respectively connected with the output end of the second comparison circuit and the second output end of the first interlocking circuit, the output end of the NAND gate is divided into three paths, the first path is directly connected with the first differential end of the first communication port, the second path is connected with the second differential end of the first communication port after passing through the first phase inverter of the second interlocking circuit, and the two paths are the first output ends of the second interlocking circuit and are connected with the first communication port; the third path is a second output end of the second interlocking circuit after passing through a second inverter of the second interlocking circuit and is connected to a second input end of the NAND gate of the first interlocking circuit.

Compared with the prior art, the invention has the beneficial effects that:

the communication interference defense circuit is developed on the basis of communication square waves, has stronger filtering capacity on clutter signals, stronger restoring capacity on weaker signals and stronger range-extending capacity on insufficient communication distance, can form a plurality of repeaters, and theoretically can support infinite distance transmission signals; the effective filter circuit can realize the duplex transmission of digital signals; effective data can be intercepted from the middle of the digital signal, so that the interference of signal wave crests and wave troughs to the signal is avoided; removing invalid narrow pulse interference by using reliable time delay; the lower attenuation signal can be restored to a normal clean signal. Multiple combinations may enable relay transmission of signals.

Drawings

FIG. 1 is an overall circuit diagram of a communication interference defense circuit of the present invention;

FIG. 2 is a differential amplifier circuit diagram of the present invention;

FIG. 3 is a circuit diagram of the delay amplifier of the present invention;

FIG. 4 is a comparison circuit diagram of the present invention;

FIG. 5 is a first interlock circuit diagram of the present invention;

fig. 6 is a second interlock circuit diagram of the present invention.

In the figure, 1-a first RS485 communication port 2-a first differential amplification circuit 3-a first delay amplification circuit 4-a first comparison circuit 5-a first interlock circuit 6-a second RS485 communication port 7-a second differential amplification circuit 8-a second delay amplification circuit 9-a second comparison circuit 10-a second interlock circuit.

Detailed Description

The following detailed description of the present invention will be made with reference to the accompanying drawings.

As shown in fig. 1, a communication interference defense circuit includes two sets of circuits with the same structure: a first set of circuits and a second set of circuits; the first group of circuits comprises a first differential amplifying circuit 2, a first delay amplifying circuit 3, a first comparison circuit 4 and a first interlocking circuit 5 which are sequentially connected from an input end to an output end; the second group of circuits comprises a second differential amplifying circuit 7, a second delay amplifying circuit 8, a second comparing circuit 9 and a second interlocking circuit 10 which are sequentially connected from the input end to the output end.

The input end of the first differential amplifying circuit 2 is connected with the first RS485 communication port 1, the output end of the first differential amplifying circuit is connected to the first input end of the first interlocking circuit 5 after sequentially passing through the first delay amplifying circuit 3 and the first comparison circuit 4, the second input end of the first interlocking circuit 5 is connected with the second output end of the second interlocking circuit 10, the first output end of the first interlocking circuit 5 is connected with the second RS485 communication port 6, and the second output end of the first interlocking circuit 5 is connected with the second input end of the second interlocking circuit 10.

The input end of the second differential amplifying circuit 7 is connected with the second RS485 communication port 6, the output end of the second differential amplifying circuit is connected to the first input end of the second interlocking circuit 10 after sequentially passing through the second delay amplifying circuit 8 and the second comparison circuit 9, the second input end of the second interlocking circuit 10 is connected with the second output end of the first interlocking circuit 5, the first output end of the second interlocking circuit 10 is connected with the first RS485 communication port 1, and the second output end of the second interlocking circuit 10 is connected with the second input end of the first interlocking circuit 5.

The circuit of the invention has 2 communication ports (RS 485 communication ports in the embodiment, CAN and other communication ports) for duplex communication signals, wherein one of the 2 communication ports is an input port, the other is an output port, and each port is an input port and an output port. Each of the circuits in the overall circuit diagram of fig. 1 is shown in an enlarged and clear view in fig. 2-6.

The following is a detailed description of the specific structure and circuit principle of each circuit in the present invention:

1. differential amplifier circuit

The first differential amplifier circuit 2 and the second differential amplifier circuit 7 have the same structure, and are both low-pass differential amplifier circuits formed by operational amplifiers. Fig. 2 is an enlarged view of the first differential amplifier circuit 2, and is identical in structure to the second differential amplifier circuit 7, only one of which is shown here. The differential amplification circuit comprises a low-pass differential amplification circuit composed of an operational amplifier U5A and auxiliary devices thereof (including resistors R1 and R11 and capacitors C13 and C14), high-value parts of the differential signal except effective values can be removed by setting resistors R1 and R11 to be low-pass, the middle effective value of the signal is taken, the signal except the effective values is equivalent to a clutter signal with wave crests and wave troughs of the signal removed, and the signal after being sorted is sent to a next-stage circuit. In addition, a transient suppression diode of T1-T3 is arranged at the front stage of the differential amplification circuit and used for lightning protection amplitude limiting.

2. Time-delay amplifying circuit

The first delay amplifying circuit 3 and the second delay amplifying circuit 8 have the same circuit structure and both comprise a front-stage RC delay circuit and a rear-stage inverse proportional-integral amplifier formed by an operational amplifier. Fig. 3 is an enlarged view of the first delay amplifying circuit 3, and has the same structure as the second delay amplifying circuit 8, and only one is shown here. The delay amplifying circuit comprises an RC delay circuit consisting of a resistor R6 and a capacitor C2 and a backward-stage inverse proportional integral amplifier consisting of an operational amplifier U5B and auxiliary devices thereof (including resistors R4 and R9 and capacitors C1 and C3), wherein the RC delay circuit plays a role in signal delay, and narrow pulses can be removed by signal delay in order to filter narrow pulse interference signals smaller than normal waveforms so as to ensure the correctness of the signals. The reverse proportional-integral amplifier further amplifies the signal, and the input end of the reverse proportional-integral amplifier is the negative end of the No. 6 pin, so that the reverse proportional-integral amplifier plays a role of reversing the negative signal of the front stage (changing the negative signal into a positive signal).

3. Comparison circuit

The first comparison circuit 4 and the second comparison circuit 9 have the same structure, and are both comparison circuits formed by comparators. Fig. 4 is a diagram of a first comparison circuit 4, which has the same structure as the second comparison circuit 9, and only one of them is shown here. The comparison circuit is composed of a comparator U8 and its accessories, pin 2 is the input end of the signal, pin 3 is the set value end, the input signal can be compared with the set value and then output to intercept the waveform, and the positive half cycle waveform, or the negative half cycle waveform, or the zero crossing point waveform (according to the actual needs of the site) can be cut off.

4. Interlock circuit

The first interlock circuit 5 and the second interlock circuit 10 have the same structure and both comprise a nand gate and two inverters.

As shown in fig. 5, two input ends (pin No. 1 and pin No. 2) of the nand gate U13 of the first interlock circuit 5 are respectively connected to the output end of the first comparison circuit 4 and the second output end of the second interlock circuit 10, the output end of the nand gate U13 is divided into three paths, the first path directly serves as the first differential end 485B-2 of the second RS485 communication port 6 after passing through the diode D1 and the resistor R5, the second path serves as the second differential end 485A-2 of the second RS485 communication port 6 after passing through the first inverter U1 of the first interlock circuit 5 (and then through the diode D2 and the resistor R14), and the two paths serve as the first output end of the first interlock circuit 5 and are connected to the second RS485 communication port 6; the third path is the second output terminal of the first interlock circuit 5 after passing through the second inverter U9 of the first interlock circuit 5, and is connected to the second input terminal of the nand gate U3 of the second interlock circuit 10.

As shown in fig. 6, two input ends (pin No. 1 and pin No. 2) of the nand gate U3 of the second interlock circuit 10 are respectively connected to the output end of the second comparator circuit 9 and the second output end of the first interlock circuit 5, the output end of the nand gate U3 is divided into three paths, the first path directly serves as the first differential end 485B-1 of the first RS485 communication port 1 after passing through the diode D3 and the resistor R18, the second path serves as the second differential end 485A-1 of the first RS485 communication port 1 after passing through the first inverter U6 (and then through the diode D5 and the resistor R31) of the second interlock circuit 10, and the two paths serve as the first output end of the second interlock circuit 10 and are connected to the first RS485 communication port 1; the third path is the second output terminal of the second interlock circuit 10 after passing through the second inverter U4 of the second interlock circuit 10, and is connected to the second input terminal of the nand gate U13 of the first interlock circuit 5.

The circuit principle of the interlock circuit is as follows: the operating principle of the nand gate is that when one input end is at low level, the output is at low level, that is, when the signal of the second input end of the nand gate is at low level, the signal (high level signal) from the first input end cannot be output, and the second output end of the nand gate is the signal passing through the inverters (U9 and U4), that is, when the first group of circuits normally output, the second output end of the nand gate is at low level signal passing through the inverter and is input to the second input end of the nand gate of the second group of circuits, the interlock circuit of the second group of circuits can be locked, so that the interlock circuit cannot be output. The interlock circuit functions as: the interlocking mode can ensure that only the single direction of the charging signal can be allowed to pass through in a certain time period. Because the signals used for communication are duplex, the signals can be from one side to the other side, or vice versa, but only one direction of the signals can be allowed to pass in the same time period. The two groups of circuits are mutually reversed and form a transmitting-receiving channel respectively so as to fulfill the aim of duplex.

The other inverter (U1 and U6) in the interlock circuit is used for inverting the output signal in the forward direction to realize differential output action, and the RS485 communication signal is a differential signal.

The above embodiment takes 485 communication as an example; the 485 communication is a differential signal of double square waves, one is from 0-5V, and the other is from 5-0V, the invention also supports the communication signal type of single-ended signals, when the two-way transmission of the single-ended signals is carried out, only one end of an operational amplifier of the differential amplification circuit needs to be connected with GND, and the first-stage transformation ratio is adjusted to be 1: 1; and meanwhile, the reference value VREF is properly adjusted.

The above embodiments are implemented on the premise of the technical solution of the present invention, and detailed embodiments and specific operation procedures are given, but the scope of the present invention is not limited to the above embodiments. The methods used in the above examples are conventional methods unless otherwise specified.