阅读说明：本技术 嵌入式fpga ip核顶层电路图自动生成方法、装置及存储介质 (Method and device for automatically generating top-level circuit diagram of embedded FPGA IP core and storage medium ) 是由 陈柱佳 其他发明人请求不公开姓名 于 2021-08-30 设计创作，主要内容包括：本发明涉及一种嵌入式FPGA IP核顶层电路图自动生成方法、装置及存储介质,其中,生成方法包括：根据资源排布信息,创建包含有若干格点单元的资源格点阵列；选取一格点单元,读取资源子模块库和资源排布图,以在选定的格点单元中布置资源子模块；获取资源子模块的一功能端口并创建对应该功能端口的线网,并根据功能端口的方向属性创建线名；遍历资源子模块的所有功能端口及所有格点单元后,建立顶层电路端口,输出FPGA IP核顶层电路图。通过合理利用FPGA内部资源的重复性和规律性,配合资源子模块库和资源排布图,从而实现了IP核顶层电路图的自动生成,极大的缩短了IP核顶层电路的生成时间,提高了FPGA IP核的开发效率。(The invention relates to an automatic generation method, a device and a storage medium for a top-level circuit diagram of an embedded FPGA IP core, wherein the generation method comprises the following steps: creating a resource grid point array comprising a plurality of grid point units according to the resource arrangement information; selecting a grid point unit, reading the resource sub-module library and the resource arrangement layout to arrange the resource sub-modules in the selected grid point unit; acquiring a functional port of the resource sub-module, creating a line network corresponding to the functional port, and creating a line name according to the direction attribute of the functional port; and after traversing all functional ports and all lattice point units of the resource sub-module, establishing a top circuit port and outputting a top circuit diagram of the FPGA IP core. By reasonably utilizing the repeatability and regularity of internal resources of the FPGA and matching with the resource sub-module library and the resource arrangement diagram, the automatic generation of the top-layer circuit diagram of the IP core is realized, the generation time of the top-layer circuit of the IP core is greatly shortened, and the development efficiency of the FPGA IP core is improved.)

1. An automatic generation method of a top-level circuit diagram of an IP core of an embedded FPGA is characterized by comprising the following steps:

after the IP resource arrangement is finished, a resource lattice point array comprising a plurality of lattice point units is created according to the resource arrangement information;

selecting a grid point unit, reading a resource sub-module library and a resource arrangement diagram, and arranging resource sub-modules in the selected grid point unit;

acquiring a functional port of a resource sub-module, creating a line network corresponding to the functional port, and creating a line name according to the direction attribute of the functional port;

and after traversing all functional ports and all lattice point units of the resource sub-module, establishing a top circuit port and outputting a top circuit diagram of the FPGA IP core.

2. The method for automatically generating the top-level circuit diagram of the IP core of the embedded FPGA according to claim 1, wherein the selecting a grid point unit, reading the resource sub-module library and the resource arrangement diagram to arrange the resource sub-modules in the selected grid point unit specifically comprises:

establishing a coordinate system covering the resource grid point array according to a resource layout diagram;

selecting a grid point unit according to a preset coordinate sequence, and recording the coordinate as (X, Y);

reading a resource sub-module library and a resource layout chart;

and arranging resource sub-modules in the selected grid point unit according to the resource arrangement diagram and the information of each resource sub-module in the resource sub-module library.

3. The method according to claim 2, wherein the obtaining a functional port of the resource sub-module and creating a net corresponding to the functional port specifically comprises:

acquiring a functional port of the resource sub-module according to a preset creating sequence and creating a network corresponding to the functional port;

and creating a line name corresponding to the functional port according to the attribute of the functional port.

4. The method according to claim 3, wherein the creating a line name according to the direction attribute of the functional port specifically comprises:

acquiring and judging the direction attribute of the functional port;

if the functional port is the output attribute, creating a line name according to the coordinates of the grid point unit where the resource sub-module is located and the name of the functional port;

and if the functional port is the input attribute, creating a line name according to the coordinate and the name of the connecting port corresponding to the functional port.

5. The method for automatically generating the top-level circuit diagram of the IP core of the embedded FPGA according to claim 4, wherein the step of creating a line name according to the coordinates and the name of the connection port corresponding to the functional port specifically comprises the steps of:

obtaining the coordinates of the grid point unit where the current resource sub-module is located from the resource layout diagram;

acquiring a connection port corresponding to the functional port and relative coordinates thereof from an interconnection information base among the resource modules, and recording the connection port and the relative coordinates as (delta X, delta Y);

calculating coordinates of the connection port according to the relative coordinates, and recording the coordinates as (X1, Y1);

and creating a line name according to the coordinates of the connecting port and the name of the connecting port.

6. The method according to claim 5, wherein the step of traversing all functional ports and all lattice units of the resource sub-module, establishing a top circuit port, and outputting the top circuit diagram of the FPGA IP core specifically includes:

after the line name is established, judging whether all functional ports of the resource sub-module are traversed or not;

if not, acquiring a next functional port of the resource sub-module according to a preset creating sequence;

if yes, continuously judging whether all the lattice point units are traversed or not;

if not, selecting a next grid point unit according to a preset coordinate sequence, and rearranging the resource sub-modules;

if yes, establishing a top layer circuit port according to the established wire network and the wire name, and outputting a top layer circuit diagram of the FPGA IP core.

7. The method for automatically generating the top-level circuit diagram of the IP core of the embedded FPGA according to claim 1, wherein the resource sub-module library comprises names of the resource sub-modules and information of functional ports in the resource sub-modules.

8. The method according to claim 5, wherein the interconnection information base among the resource modules includes connection relationships among the functional ports in the resource sub-modules.

9. The utility model provides an automatic device that generates of embedded FPGA IP core top layer circuit diagram which characterized in that includes:

the first establishing unit is used for establishing a resource grid point array comprising a plurality of grid point units according to the resource arrangement information after the IP resource arrangement is finished;

the resource arrangement unit is used for selecting a grid point unit, reading the resource sub-module library and the resource arrangement diagram, and arranging the resource sub-modules in the selected grid point unit;

the second establishing unit is used for acquiring a functional port of the resource sub-module, establishing a line network corresponding to the functional port and establishing a line name according to the direction attribute of the functional port;

and the generation execution unit is used for establishing a top circuit port after traversing all the functional ports and all the lattice point units of the resource sub-module and outputting a top circuit diagram of the FPGA IP core.

10. A storage medium storing computer readable instructions which, when executed by one or more processors, cause the one or more processors to perform the steps of the generation method of any one of claims 1 to 8.

Technical Field

The invention relates to the technical field of digital integrated circuits, in particular to an automatic generation method and device of an embedded FPGA IP core top layer circuit diagram and a storage medium.

Background

A Field-Programmable Gate Array (FPGA) is a general-purpose Programmable device, and has the characteristics of high flexibility and high parallelism, and generally includes a Programmable Logic module (CLB), a Programmable interconnect resource (CR), an Input Output module (IOB), and other IP resources (such as a Block memory, a digital signal processor, etc.), which provide a system Programmable or reconfigurable capability for a user.

An embedded FPGA (embedded FPGA) embeds an FPGA core array in an IP core form into chips such as asics (application Specific integrated circuits), assps (application Specific Standard parts), or System on Chip (SoC). Embedding FPGAs in IP form into a system on a chip can overcome the disadvantages of limited bandwidth of individual FPGAs and fixed ASIC functionality, as well as the problem of passing data between them. The FPGA IP embedded in the ASIC provides the SoC system with the ability to dynamically adjust, and the embedded FPGA has the advantage that the functionality of the SoC or ASIC can be reconfigured.

The design of the FPGA IP core is started after the resources required by the user circuit are determined, and the process comprises the following steps: determining the type, scale, arrangement and other parameters of basic elements of an FPGA IP core; step two, establishing IP resource arrangement; step three, designing a circuit; step four, generating IP core information; and step five, integrating the FPGA IP core by the user. The circuit design in the third step is divided into the design of the resource sub-modules and the design of the top-level circuit, and in the design of the top-level circuit of the FPGA IP core, the design period is very long due to the fact that the number of ports of the resource sub-modules is large and the interconnection complexity among the resource sub-modules is high, and the development efficiency of the FPGA IP core is limited.

Disclosure of Invention

In order to solve the technical problems, the invention provides an automatic generation method, device and storage medium for a top-level circuit diagram of an embedded FPGA IP core, and the method, device and storage medium have the advantages of automatically generating a top-level circuit and improving development efficiency.

In order to achieve the purpose, the technical scheme of the invention is as follows:

an automatic generation method of a top-level circuit diagram of an IP core of an embedded FPGA comprises the following steps:

after the IP resource arrangement is finished, a resource lattice point array comprising a plurality of lattice point units is created according to the resource arrangement information;

selecting a grid point unit, reading a resource sub-module library and a resource arrangement diagram, and arranging resource sub-modules in the selected grid point unit;

acquiring a functional port of a resource sub-module, creating a line network corresponding to the functional port, and creating a line name according to the direction attribute of the functional port;

and after traversing all functional ports and all lattice point units of the resource sub-module, establishing a top circuit port and outputting a top circuit diagram of the FPGA IP core.

As a preferred scheme of the present invention, the selecting a grid cell, reading the resource sub-module library and the resource arrangement diagram to arrange the resource sub-modules in the selected grid cell specifically includes:

establishing a coordinate system covering the resource grid point array according to a resource layout diagram;

selecting a grid point unit according to a preset coordinate sequence, and recording the coordinate as (X, Y);

reading a resource sub-module library and a resource layout chart;

and arranging resource sub-modules in the selected grid point unit according to the resource arrangement diagram and the information of each resource sub-module in the resource sub-module library.

As a preferred embodiment of the present invention, the acquiring a functional port of a resource sub-module and creating a net corresponding to the functional port specifically includes:

acquiring a functional port of the resource sub-module according to a preset creating sequence and creating a network corresponding to the functional port;

and creating a line name corresponding to the functional port according to the attribute of the functional port.

As a preferred embodiment of the present invention, the creating a line name according to the direction attribute of the functional port specifically includes:

acquiring and judging the direction attribute of the functional port;

if the functional port is the output attribute, creating a line name according to the coordinates of the grid point unit where the resource sub-module is located and the name of the functional port;

and if the functional port is the input attribute, creating a line name according to the coordinate and the name of the connecting port corresponding to the functional port.

As a preferred aspect of the present invention, the creating a line name according to the coordinate and the name of the connection port corresponding to the functional port specifically includes:

obtaining the coordinates of the grid point unit where the current resource sub-module is located from the resource layout diagram;

acquiring a connection port corresponding to the functional port and relative coordinates thereof from an interconnection information base among the resource modules, and recording the connection port and the relative coordinates as (delta X, delta Y);

calculating coordinates of the connection port according to the relative coordinates, and recording the coordinates as (X1, Y1);

and creating a line name according to the coordinates of the connecting port and the name of the connecting port.

As a preferred solution of the present invention, after traversing all functional ports and all lattice units of the resource sub-module, establishing a top-level circuit port, and outputting a top-level circuit diagram of an FPGA IP core specifically includes:

after the line name is established, judging whether all functional ports of the resource sub-module are traversed or not;

if not, acquiring a next functional port of the resource sub-module according to a preset creating sequence;

if yes, continuously judging whether all the lattice point units are traversed or not;

if not, selecting a next grid point unit according to a preset coordinate sequence, and rearranging the resource sub-modules;

if yes, establishing a top layer circuit port according to the established wire network and the wire name, and outputting a top layer circuit diagram of the FPGA IP core.

As a preferred scheme of the present invention, the resource sub-module library includes names of the resource sub-modules and information of the functional ports in the resource sub-modules.

As a preferred scheme of the present invention, the interconnection information base between the resource modules includes a connection relationship between the function ports in each resource sub-module.

In order to solve the above technical problem, an embodiment of the present invention further provides an apparatus for automatically generating a top-level circuit diagram of an IP core of an embedded FPGA, including:

the first establishing unit is used for establishing a resource grid point array comprising a plurality of grid point units according to the resource arrangement information after the IP resource arrangement is finished;

the resource arrangement unit is used for selecting a grid point unit, reading the resource sub-module library and the resource arrangement diagram, and arranging the resource sub-modules in the selected grid point unit;

the second establishing unit is used for acquiring a functional port of the resource sub-module, establishing a line network corresponding to the functional port and establishing a line name according to the direction attribute of the functional port;

and the generation execution unit is used for establishing a top circuit port after traversing all the functional ports and all the lattice point units of the resource sub-module and outputting a top circuit diagram of the FPGA IP core.

To solve the above technical problem, an embodiment of the present invention further provides a storage medium storing computer-readable instructions, where the computer-readable instructions, when executed by one or more processors, cause the one or more processors to perform the steps of the generation method according to any one of the above technical solutions.

The embodiment of the invention has the beneficial effects that:

the invention provides an automatic generation method, a device and a storage medium for an embedded FPGA IP core top-layer circuit diagram, which realize the automatic generation of the IP core top-layer circuit diagram by reasonably utilizing the repeatability and regularity of internal resources of the FPGA and matching with a resource sub-module library and a resource arrangement diagram, greatly shorten the generation time of the IP core top-layer circuit, improve the development efficiency of the FPGA IP core, can be integrated into the translation process of the IP core, and can be handed to a user to generate a proper IP core circuit and a netlist, so that the applicability is stronger.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a basic flow diagram of a generating method according to an embodiment of the present invention.

Fig. 2 is a schematic flow chart of arranging resource sub-modules in a grid cell according to an embodiment of the present invention.

Fig. 3 is a schematic flow chart of creating a line name according to an embodiment of the present invention.

Fig. 4 is a schematic flowchart illustrating a process of creating a line name according to coordinates and a name of a connection port corresponding to a functional port in an embodiment of the present invention.

Fig. 5 is a schematic flow chart of the top-level circuit diagram of the output FPGA IP core in the embodiment of the present invention.

Fig. 6 is a flowchart illustrating an embodiment of automatically generating an IP core top-level circuit diagram according to the present invention.

Fig. 7 is a top level circuit structure diagram generated by the embodiment of the invention.

Fig. 8 is a schematic diagram of a basic structure of an automatic generation apparatus in an embodiment of the present invention.

Fig. 9 is a block diagram showing a basic configuration of a computer device according to an embodiment of the present invention.

The corresponding part names indicated by the numbers and letters in the drawings:

601. an array of resource grid points; 602. a top layer circuit port; 603. a resource submodule; 604. a wire mesh; 701. a first creation module; 702. a resource arrangement module; 703. a second creation module; 704. and generating an execution module.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.

In some of the flows described in the present specification and claims and in the above figures, a number of operations are included that occur in a particular order, but it should be clearly understood that these operations may be performed out of order or in parallel as they occur herein, with the order of the operations being indicated as 101, 102, etc. merely to distinguish between the various operations, and the order of the operations by themselves does not represent any order of performance. Additionally, the flows may include more or fewer operations, and the operations may be performed sequentially or in parallel. It should be noted that, the descriptions of "first", "second", etc. in this document are used for distinguishing different messages, devices, modules, etc., and do not represent a sequential order, nor limit the types of "first" and "second" to be different.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic diagram of a basic flow of the generation method of the present embodiment.

As shown in fig. 1, an automatic generation method of a top-level circuit diagram of an IP core of an embedded FPGA includes:

s100, after the IP resource arrangement is finished, a resource grid point array comprising a plurality of grid point units is created according to the resource arrangement information.

The IP resource configuration is carried out after determining the basic element type, scale, configuration and other parameters of the FPGA IP, and the resource configuration information includes the basic element type, scale, configuration and other parameters of the IP.

S200, selecting a grid point unit, reading the resource sub-module library and the resource arrangement diagram, and arranging the resource sub-modules in the selected grid point unit.

As shown in fig. 2, S200 specifically includes:

s201, establishing a coordinate system covering the resource grid point array according to a resource layout diagram, wherein each grid point unit corresponds to a coordinate value;

s202, selecting a grid point unit according to a preset coordinate sequence, wherein the coordinate is (X, Y), and the preset coordinate sequence can be used for sequentially selecting the grid point units according to the sequence along the X axis or the sequence along the Y axis;

s203, reading a resource submodule library and a resource arrangement layout, wherein the resource submodule library comprises names of all resource submodules and information of all functional ports in the resource submodules, the resource submodules comprise functional modules such as a programmable logic block, a block memory, an input/output module and the like, the resource submodule library also comprises information such as design diagrams, symbolic diagrams and the like of all the resource submodules, the resource arrangement layout virtualizes array coordinates of an FPGA IP core, and defines resource types under each coordinate;

s204, according to the resource arrangement diagram and the information of each resource sub-module in the resource sub-module library, arranging the resource sub-modules in the selected grid point unit, and according to the correspondingly defined resource types in the resource arrangement diagram, selecting the resource sub-modules of the corresponding types from the resource module library to arrange.

S300, acquiring a functional port of the resource sub-module, creating a line network corresponding to the functional port, and creating a line name according to the direction attribute of the functional port.

S300 specifically comprises:

s301, acquiring a functional port of the resource sub-module according to a preset creating sequence and creating a wire network corresponding to the functional port;

s302, establishing a line name corresponding to the functional port according to the attribute of the functional port.

As shown in fig. 3, S302 specifically includes:

s3021, acquiring and judging the direction attribute of the functional port;

s3022, if the functional port is an output attribute, creating a line name according to the coordinate of the grid point unit where the resource sub-module is located and the name of the functional port;

and S3023, if the functional port is the input attribute, creating a line name according to the coordinate and the name of the connection port corresponding to the functional port.

As shown in fig. 4, creating a line name according to the coordinates and the name of the connection port corresponding to the functional port specifically includes:

s30231, obtaining the coordinates of the grid point unit where the current resource sub-module is located from the resource layout diagram;

s30232, obtaining a connection port corresponding to the functional port and a relative coordinate thereof from an interconnection information base between the resource modules, and recording the connection port and the relative coordinate as (Δ X, Δ Y), where the interconnection information base between the resource modules includes a connection relationship between the functional ports in the resource sub-modules, such as a connection relationship between the functional ports in each resource sub-module or a connection relationship between the functional ports and the functional modules in other resource sub-modules, which is specifically: the first port of the programmable logic module is connected with the second port of the storage module, the second port of the programmable logic module is connected with the seventh port of the programmable logic module and the like, and the connection port is a port for inputting data and signals to the functional port correspondingly;

s30233, calculating coordinates of the connection port according to the relative coordinates, and recording the coordinates as (X1, Y1);

s30234, creating a line name according to the coordinates of the connection port and the name of the connection port.

S400, after traversing all functional ports and all grid point units of the resource sub-modules, establishing a top circuit port, and outputting a top circuit diagram of the FPGA IP core.

As shown in fig. 5, S400 specifically includes:

s401, after the line name is established, judging whether all functional ports of the resource sub-module are traversed or not;

s402, if not, acquiring a next functional port of the resource sub-module according to a preset creating sequence;

s403, if yes, continuously judging whether all the lattice point units are traversed;

s404, if not, selecting a next grid point unit according to a preset coordinate sequence, and rearranging the resource sub-modules;

and S405, if so, establishing a top-layer circuit port according to the established wire network and the wire name, and outputting a top-layer circuit diagram of the FPGA IP core.

The invention has the following beneficial effects: by reasonably utilizing the repeatability and regularity of internal resources of the FPGA and matching with the resource sub-module library and the resource arrangement diagram, the automatic generation of the top-layer circuit diagram of the IP core is realized, the generation time of the top-layer circuit of the IP core is greatly shortened, the development efficiency of the FPGA IP core is improved, the FPGA IP core can be integrated into the translation process of the IP core, and a user generates a proper IP core circuit and a netlist, so that the applicability is stronger.

For convenience of understanding, a specific embodiment is described below, and as shown in fig. 6, the method for automatically generating the top-level circuit diagram of the IP core of the embedded FPGA of the specific embodiment includes:

s501, after the IP resource arrangement is finished, a resource grid point array 601 is established according to the resource arrangement information, and comprises a plurality of grid point units;

s502, selecting a grid point unit, defining the coordinate of the grid point unit as (X, Y), reading a resource sub-module library and a resource arrangement layout, and arranging resource sub-modules 603 in the selected grid point unit;

s503, acquiring a function port Pn in the resource sub-module;

s504, a wire net 604 corresponding to the functional unit is established;

s505, determining the direction attribute of the functional port, if the attribute is output, executing step S506, and if the attribute is input, executing step S507;

s506, creating a line name according to the coordinates (X, Y) of the resource in the module and the name of the functional port Pn;

s507, after the coordinates of the current resource sub-module are obtained from the resource layout diagram, the connection port Qn corresponding to the function port Pn and the relative coordinates (delta X, delta Y) thereof are obtained from the interconnection information base among the resource modules, and new coordinates (X1, Y1) are calculated;

s508, creating a line name according to the new coordinates (X1, Y1) and the name of the connection port Qn;

s509, judging whether all ports of the resource sub-module are traversed, if so, executing the step S510, and if not, repeatedly executing the step S503;

s510, judging whether all grid point units in the resource grid point array are traversed, if so, executing the step S511, and if not, repeatedly executing the step S502;

s511, establishing a top circuit port 602, outputting a top circuit diagram of the FPGA IP core, and outputting the top circuit diagram finally as shown in fig. 7.

In order to solve the above technical problem, an embodiment of the present invention further provides an apparatus for automatically generating a top-level circuit diagram of an IP core of an embedded FPGA, as shown in fig. 8, including:

a first creating unit 701, configured to create a resource grid point array including a plurality of grid point units according to resource arrangement information after the IP resource arrangement is completed;

a resource arrangement unit 702, configured to select a grid cell, read the resource sub-module library and the resource arrangement layout, and arrange resource sub-modules in the selected grid cell;

a second creating unit 703, configured to obtain a functional port of the resource sub-module, create a line network corresponding to the functional port, and create a line name according to a direction attribute of the functional port;

and the generation execution unit 704 is used for establishing a top circuit port after traversing all the functional ports and all the lattice point units of the resource sub-module and outputting a top circuit diagram of the FPGA IP core.

In order to solve the above technical problem, an embodiment of the present invention further provides a computer device. Referring to fig. 9, fig. 9 is a block diagram of a basic structure of a computer device according to the present embodiment.

As shown in fig. 9, the internal structure of the computer device is schematically illustrated. The computer device includes a processor, a non-volatile storage medium, a memory, and a network interface connected by a system bus. The non-volatile storage medium of the computer device stores an operating system, a database and computer readable instructions, the database can store control information sequences, and the computer readable instructions, when executed by the processor, can enable the processor to realize a top-level circuit diagram automatic generation method. The processor of the computer device is used for providing calculation and control capability and supporting the operation of the whole computer device. The memory of the computer device may have stored therein computer readable instructions that, when executed by the processor, cause the processor to perform a top level circuit diagram auto-generation method. The network interface of the computer device is used for connecting and communicating with the terminal. Those skilled in the art will appreciate that the architecture shown in fig. 9 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

The processor in this embodiment is configured to execute specific functions of the first creating module 701, the resource arranging module 702, the second creating module 703 and the generating and executing module 704 in fig. 8, and the memory stores program codes and various types of data required for executing the modules. The network interface is used for data transmission to and from a user terminal or a server.

When the computer equipment generates the IP core top circuit diagram, the repeatability and regularity of internal resources of the FPGA are reasonably utilized, and the resource sub-module library and the resource arrangement diagram are matched, so that the automatic generation of the IP core top circuit diagram is realized, the generation time of the IP core top circuit is greatly shortened, the development efficiency of the FPGA IP core is improved, the FPGA top circuit can be integrated into the translation process of the IP core, a user can generate a proper IP core circuit and a netlist, and the applicability is stronger.

To solve the above technical problem, an embodiment of the present invention further provides a storage medium storing computer-readable instructions, where the computer-readable instructions, when executed by one or more processors, cause the one or more processors to perform the steps of the generation method according to any one of the above technical solutions.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and can include the processes of the embodiments of the methods described above when the computer program is executed. The storage medium may be a non-volatile storage medium such as a magnetic disk, an optical disk, a Read-Only Memory (ROM), or a Random Access Memory (RAM).

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.