阅读说明：本技术 高可靠性电流频率转换电路 (High-reliability current frequency conversion circuit ) 是由 漆星宇 郑宗源 张琛 王新安 于 2021-03-10 设计创作，主要内容包括：本发明涉及一种高可靠性电流频率转换电路。其包括与待转换电流源CS适配的运算放大器AMP,还包括电荷积累与释放模块、积分状态判断模块以及状态切换控制模块,所述电荷积累与释放模块内至少包括一条充放电支路,在任一充放电支路内至少包括两个串接的充放电单元,利用所述充放电支路能形成所需的积分电容支路,所述积分电容支路内包括部分单元充放电容或全部单元充放电容；电荷积累与释放模块内所有的积分电容支路与运算放大器AMP适配连接后能形成所需的电流积分电路；本发明消除电容切换过程中的电荷损失,保证电流频率转换的线性度。(The invention relates to a high-reliability current frequency conversion circuit. The circuit comprises an operational amplifier AMP adaptive to a current source CS to be converted, a charge accumulation and release module, an integral state judgment module and a state switching control module, wherein the charge accumulation and release module at least comprises one charge-discharge branch, any charge-discharge branch at least comprises two charge-discharge units connected in series, the charge-discharge branch can be used for forming a required integral capacitor branch, and the integral capacitor branch comprises partial unit charge-discharge capacity or all unit charge-discharge capacity; all the integrating capacitor branches in the charge accumulation and release module are in adaptive connection with an operational amplifier AMP to form a required current integrating circuit; the invention eliminates the charge loss in the process of capacitance switching and ensures the linearity of current frequency conversion.)

1. A high-reliability current frequency conversion circuit comprises an operational amplifier AMP which is adaptive to a current source CS to be converted, wherein the output end of the current source CS is connected with the first end of the operational amplifier AMP; the method is characterized in that:

the device comprises an operational amplifier AMP, a charge accumulation and release module (3) which is in adaptive connection with a first end of the operational amplifier AMP and an output end of the operational amplifier AMP, an integration state judgment module (1) which is connected with the output end of the operational amplifier AMP, and a state switching control module (2) which is in adaptive connection with the output end of the integration state judgment module (1), wherein a conversion frequency signal Fout can be output through the state switching control module (2), and a charge and discharge control signal can be loaded to the charge accumulation and release module (3);

the charge accumulation and release module (3) at least comprises a charge and discharge branch circuit, any charge and discharge branch circuit at least comprises two charge and discharge units connected in series, each charge and discharge unit comprises a unit charge and discharge capacitor and a charge and discharge control switch connected with the unit charge and discharge capacitor in parallel, the charge and discharge control switch can be in an open state or a closed state according to a received charge and discharge control signal, a required integral capacitor branch circuit can be formed by using the charge and discharge branch circuit according to the on-off state of the charge and discharge control switch in the charge and discharge branch circuit, and the integral capacitor branch circuit comprises part of the unit charge and discharge capacitors or all the unit charge and discharge capacitors; all integrating capacitor branches in the charge accumulation and release module (3) are in adaptive connection with an operational amplifier AMP to form a required current integrating circuit;

in a conversion period of the current source CS frequency conversion, the integral state judgment module (1) can output a state switching control signal to the state switching control module (2) according to the integral voltage output by the current integral circuit, and the state switching control module (2) can adjust the state of the charging and discharging control signal according to the state switching control signal and can control the output state of the conversion frequency signal Fout so as to obtain a frequency value corresponding to the current of the current source CS according to the output conversion frequency signal Fout.

2. The high reliability current-to-frequency conversion circuit of claim 1, wherein: the charging and discharging control signals output by the state switching control module (2) comprise control signals phi 1 and control signals phi 2, wherein the control signals phi 1 and the control signals phi 2 output by the state switching control module (2) are simultaneously loaded into each charging and discharging branch, and the switching state of a charging and discharging control switch in the charging and discharging unit is only controlled by the control signals phi 1 or only by the control signals phi 2;

when a charge-discharge branch circuit exists in the charge accumulation and release module (3), when a charge-discharge control switch controlled by a control signal phi 1 is closed and a charge-discharge control switch corresponding to a control signal phi 2 is opened, a single-branch first equivalent capacitor can be obtained through the charge-discharge branch circuit; when the charge and discharge control switch controlled by the control signal phi 2 is closed and the charge and discharge control switch corresponding to the control signal phi 1 is opened, the single-branch second equivalent capacitor can be obtained through the charge and discharge branch, and the capacity value of the single-branch second equivalent capacitor is equal to that of the single-branch first equivalent capacitor.

3. The high reliability current-to-frequency conversion circuit of claim 1, wherein: when a plurality of charge and discharge branches are included in the charge accumulation and release module (3), all the charge and discharge branches are connected in parallel, the charge and discharge control signals output by the switching control module (2) comprise control signals phi 1 and phi 2, the control signals phi 1 and phi 2 output by the state switching control module (2) are simultaneously loaded into each charge and discharge branch, and the switching state of a charge and discharge control switch in the charge and discharge unit is only controlled by the control signals phi 1 or only by the control signals phi 2;

when the charge-discharge control switch controlled by the control signal phi 1 is closed and the charge-discharge control switch corresponding to the control signal phi 2 is opened, the multi-branch first equivalent capacitor can be obtained according to all charge-discharge branches in the charge accumulation and release module (3); when the charge and discharge control switch controlled by the control signal phi 2 is closed and the charge and discharge control switch corresponding to the control signal phi 1 is opened, a multi-branch second equivalent capacitor can be obtained according to all charge and discharge branches in the charge accumulation and release module (3), and the capacity value of the multi-branch second equivalent capacitor is equal to that of the multi-branch first equivalent capacitor.

4. A high reliability current-to-frequency conversion circuit as claimed in claim 2 or3, wherein: the integration state judgment module (1) can compare the integration voltage VA1 output by the operational amplifier AMP with a comparison reference voltage VT1 and a comparison reference voltage VT2 respectively, and the state switching control signal output by the integration state judgment module (1) comprises a state switching control signal V1 and a state switching control signal V2;

according to the comparison result of the integrated voltage VA1 and the comparison reference voltages VT1 and VT2, the state switching control module (2) can adjust the level states corresponding to the state switching control signals V1 and V2.

5. The high reliability current-to-frequency conversion circuit of claim 4, wherein: the integral state judging module (1) comprises a voltage comparator COMP1 and a voltage comparator COMP2, wherein the output end of an operational amplifier AMP is connected with one input end of a voltage comparator COMP1 and one input end of a voltage comparator COMP2, the other input end of the voltage comparator COMP1 receives a comparison reference voltage VT1, the other input end of the voltage comparator COMP2 receives a comparison reference voltage VT2, the comparison reference voltage VT2 is larger than the comparison reference voltage VT1, a state switching control signal V1 can be output through the output end of the voltage comparator COMP1, and a state switching control signal V2 can be output through the output end of the voltage comparator COMP 2.

6. The high reliability current-to-frequency conversion circuit of claim 4, wherein: the state switching control module (2) comprises a D flip-flop DFF, a LATCH LATCH1 and a LATCH LARCH2, wherein a clock terminal of the D flip-flop DFF is connected with a state switching control signal V1, and the state switching control signal V1 is also connected with a falling edge modulation module (6) and a LATCH LATCH1Terminal and LATCH of LATCH2End connection;

d terminal of D flip-flop DFF and D flip-flop DFFTerminal-connected and through said D flip-flop DFFEnd output frequency conversion inverted signalOutputting a conversion frequency signal Fout through a Q end of a D trigger DFF; of latches LATCH1Having terminals connected to the output of OR gate OR1, of LATCH LATCH2One terminal of the OR gate is connected with the output terminal of the OR gate OR2, one input terminal of the OR gate OR1 and one input terminal of the OR gate OR2 both receive the state switching control signal V2, and the other input terminal of the OR gate OR1 receives the frequency conversion inverted signalThe other input terminal of the OR gate OR2 receives the switching frequency signal Fout;

the output of LATCH1 outputs a control signal Φ 1 and the output of LATCH2 outputs a control signal Φ 2.

7. The high reliability current-to-frequency conversion circuit of claim 6, wherein: the falling edge modulation module (6) comprises an inverter INV and an OR gate OR3, wherein an input end of the inverter INV and an input end of the OR gate OR3 both receive a state switching control signal V1, an output end of the inverter INV is connected with one end of a capacitor C100 and the other input end of the OR gate OR3, the other end of the capacitor C100 is grounded, and an output end of the OR gate OR3 and an output end of a LATCH LATCH1Terminal and LATCH of LATCH2And end connection.

8. The high reliability current-to-frequency conversion circuit of claim 4, wherein: the first transition state, the first single integration state, the second transition state and the second single integration state are included in sequence in one conversion period of the frequency conversion of the current source CS.

9. The high reliability current-to-frequency conversion circuit of claim 8, wherein: during initial transition, the method also comprises an initial state before the first transition state;

in an initial state, the control signal Φ 1 is in a first level state, the control signal Φ 2 is in a second level state, the charge-discharge control switch controlled by the control signal Φ 2 is in a closed state, the integrating capacitor branch only includes a cell charge-discharge capacitor corresponding to the control signal Φ 1, when the integrated voltage VA1 output by the operational amplifier AMP reaches the comparison reference voltage VT1, the integrating state judgment module (1) inverts the state of the output state switching control signal V1, and the state switching control module (2) inverts the level state of the output switching frequency signal Fout according to the state switching control signal V1, and enables the control signal Φ 2 to be in the first level state.

10. The high reliability current-to-frequency conversion circuit of claim 9, wherein: in a first transition state, the charge and discharge control switches controlled by the control signal phi 1 and the control signal phi 2 are in a disconnected state, and the charge and discharge capacitors of the units in the charge and discharge branch circuit are connected in series to form an integral capacitor branch circuit; when the integrated voltage output by the operational amplifier AMP reaches the comparison reference voltage VT2, the integrated state judgment module (1) reverses the state of the output state switching control signal V2, and the state switching control module (2) enables the control signal phi 1 to be in a second level state according to the state of the state switching control signal V2;

in a first single integration state, a charge and discharge control switch controlled by a control signal phi 1 is in a closed state, an integration circuit branch only comprises a unit charge and discharge capacitor corresponding to a control signal phi 2, the unit charge and discharge capacitor corresponding to the control signal phi 1 releases accumulated charges, an integration voltage VA1 output by an operational amplifier AMP drops to (VT2-VT1)/2, an integration state judgment module (1) inverts the state of a state switching control signal V1, when the integration voltage VA1 output by the operational amplifier AMP reaches a comparison reference voltage VT1, the integration state judgment module (1) inverts the state of an output state switching control signal V1 again, and a state switching control module (2) inverts the level state of an output switching frequency signal Fout according to the state switching control signal V1;

in a second transition state, the charge and discharge control switches controlled by the control signal phi 1 and the control signal phi 2 are in a disconnected state, and the charge and discharge capacitors of the units in the charge and discharge branch circuit are connected in series to form an integral capacitor branch circuit; when the integrated voltage output by the operational amplifier AMP reaches the comparison reference voltage VT2, the integrated state judgment module (1) reverses the state of the output state switching control signal V2, and the state switching control module (2) enables the control signal phi 2 to be in a second level state according to the state of the state switching control signal V2;

in the second single integration state, the charge-discharge control switch controlled by the control signal Φ 2 is in a closed state, the branch of the integration circuit only comprises a cell charge-discharge capacitor corresponding to the control signal Φ 1, the cell charge-discharge capacitor corresponding to the control signal Φ 2 releases accumulated charges, the integration voltage VA1 output by the operational amplifier AMP drops to (VT2-VT1)/2, the integration state judgment module (1) inverts the state of the state switching control signal V1, when the integration voltage VA1 output by the operational amplifier AMP reaches the comparison reference voltage VT1, the integration state judgment module (1) inverts the state of the state switching control signal V1 again, and the state switching control module (2) inverts the level state of the output switching frequency signal Fout according to the state switching control signal V1.

Technical Field

The invention relates to a conversion circuit, in particular to a high-reliability current frequency conversion circuit.

Background

The current signal output is a common signal output method such as a sensor, and the current-voltage conversion or the current-frequency conversion is usually adopted for processing the output current signal. The current-voltage conversion is realized by introducing a resistor, and the converted output signal is a voltage signal.

The current-frequency conversion is realized by introducing an integrating capacitor and periodically charging and discharging the integrating capacitor through current, and the converted frequency signal is a square wave signal with the same amplitude as the power supply voltage and can be directly processed by a counter or a timer of a processor.

The publication No. CN106289333A discloses a current frequency conversion circuit, which includes a capacitor charge and discharge control module, where the capacitor charge and discharge control module includes an access control unit and a discharge control unit; during operation, the control of the charging and discharging process can be realized through the first control signal and the second control signal. For controlling the first switching capacitor, the access control unit comprises a first switch subunit and a second switch subunit, and the discharge control unit comprises a third switch subunit and a fourth switch subunit. Therefore, in the document, at least two switches are matched with a switching capacitor, and those skilled in the art can know that the non-ideal factors of the switches can cause the non-linear output of the whole conversion circuit.

As can be seen from the disclosure, the first switching capacitor, the second switching capacitor and the integrating capacitor are connected in parallel, and it is considered that the first control signal and the second control signal may not be completely ideal inverted logic signals. Therefore, there are the following problems in operation: 1) if a time interval that the first switching capacitor and the second switching capacitor are simultaneously accessed exists during switching, the newly accessed empty capacitor distributes charges on the capacitor to be removed, so that the actually removed charge amount is less; 2) if a time interval in which the first switching capacitor and the second switching capacitor are not switched in simultaneously exists during switching, the circuit needs to have a constantly switched-in integrating capacitor C0 to store the charges to be integrated in the time interval, otherwise, the operational amplifier enters an open-loop working state to generate an abnormality, and the charges to be integrated in the time interval are lost.

In summary, the current-frequency conversion circuit disclosed in publication No. CN106289333A has a complicated structure and poor operation stability when performing current-frequency conversion, and cannot effectively ensure the linearity of the current-frequency conversion.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provide a high-reliability current frequency conversion circuit which is compact in structure, eliminates charge loss in the process of capacitance switching and ensures the linearity of current frequency conversion.

According to the technical scheme provided by the invention, the high-reliability current frequency conversion circuit comprises an operational amplifier AMP adaptive to a current source CS to be converted, wherein the output end of the current source CS is connected with the first end of the operational amplifier AMP;

the device comprises an operational amplifier AMP, a charge accumulation and release module, an integral state judgment module and a state switching control module, wherein the charge accumulation and release module is adaptively connected with a first end of the operational amplifier AMP and an output end of the operational amplifier AMP;

the charge accumulation and release module at least comprises a charge and discharge branch circuit, any charge and discharge branch circuit at least comprises two charge and discharge units connected in series, each charge and discharge unit comprises a unit charge and discharge capacitor and a charge and discharge control switch connected with the unit charge and discharge capacitor in parallel, the charge and discharge control switch can be in an open state or a closed state according to a received charge and discharge control signal, a required integral capacitor branch circuit can be formed by using the charge and discharge branch circuit according to the on-off state of the charge and discharge control switch in the charge and discharge branch circuit, and the integral capacitor branch circuit comprises part of the unit charge and discharge capacitors or all the unit charge and discharge capacitors; all the integrating capacitor branches in the charge accumulation and release module are in adaptive connection with an operational amplifier AMP to form a required current integrating circuit;

in a conversion period of the current source CS frequency conversion, the integration state judgment module can output a state switching control signal to the state switching control module according to the integration voltage output by the current integration circuit, and the state switching control module can adjust the state of the charge and discharge control signal according to the state switching control signal and can control the output state of the conversion frequency signal Fout, so as to obtain a frequency value corresponding to the current of the current source CS according to the output conversion frequency signal Fout.

The charging and discharging control signals output by the state switching control module comprise control signals phi 1 and control signals phi 2, wherein the control signals phi 1 and the control signals phi 2 output by the state switching control module are simultaneously loaded into each charging and discharging branch, and the switching state of a charging and discharging control switch in the charging and discharging unit is only controlled by the control signals phi 1 or only by the control signals phi 2;

when a charge-discharge branch circuit exists in the charge accumulation and release module, when a charge-discharge control switch controlled by a control signal phi 1 is closed and a charge-discharge control switch corresponding to a control signal phi 2 is opened, a single-branch first equivalent capacitor can be obtained through the charge-discharge branch circuit; when the charge and discharge control switch controlled by the control signal phi 2 is closed and the charge and discharge control switch corresponding to the control signal phi 1 is opened, the single-branch second equivalent capacitor can be obtained through the charge and discharge branch, and the capacity value of the single-branch second equivalent capacitor is equal to that of the single-branch first equivalent capacitor.

When a plurality of charge and discharge branches are included in the charge accumulation and release module, all the charge and discharge branches are connected in parallel, the charge and discharge control signals output by the switching control module comprise control signals phi 1 and phi 2, the control signals phi 1 and phi 2 output by the state switching control module are simultaneously loaded into each charge and discharge branch, and the switching state of a charge and discharge control switch in the charge and discharge unit is only controlled by the control signals phi 1 or only by the control signals phi 2;

when the charge-discharge control switch controlled by the control signal phi 1 is closed and the charge-discharge control switch corresponding to the control signal phi 2 is opened, a plurality of first equivalent capacitors can be obtained according to all charge-discharge branches in the charge accumulation and release module; when the charge and discharge control switch controlled by the control signal phi 2 is closed and the charge and discharge control switch corresponding to the control signal phi 1 is opened, a multi-branch second equivalent capacitor can be obtained according to all charge and discharge branches in the charge accumulation and release module, and the capacity value of the multi-branch second equivalent capacitor is equal to that of the multi-branch first equivalent capacitor.

The integral state judgment module can compare the integral voltage VA1 output by the operational amplifier AMP with a comparison reference voltage VT1 and a comparison reference voltage VT2 respectively, and the state switching control signal output by the integral state judgment module comprises a state switching control signal V1 and a state switching control signal V2;

according to the comparison result of the integrated voltage VA1 and the comparison reference voltages VT1 and VT2, the state switching control module can adjust the level states corresponding to the state switching control signals V1 and V2.

The integral state judgment module comprises a voltage comparator COMP1 and a voltage comparator COMP2, wherein the output end of an operational amplifier AMP is connected with one input end of a voltage comparator COMP1 and one input end of a voltage comparator COMP2, the other input end of the voltage comparator COMP1 receives a comparison reference voltage VT1, the other input end of the voltage comparator COMP2 receives a comparison reference voltage VT2, the comparison reference voltage VT2 is larger than the comparison reference voltage VT1, a state switching control signal V1 can be output through the output end of the voltage comparator COMP1, and a state switching control signal V2 can be output through the output end of the voltage comparator COMP 2.

The state switching control module comprises a D flip-flop DFF, a LATCH LATCH1 and a LATCH LARCH2, wherein a clock terminal of the D flip-flop DFF is connected with a state switching control signal V1, and the state switching control signal V1 is also connected with a LATCH LATCH1 through a falling edge modulation moduleTerminal and LATCH of LATCH2End connection;

d terminal of D flip-flop DFF and D flip-flop DFFTerminal-connected and through said D flip-flop DFFEnd output frequency conversion inverted signalOutputting a conversion frequency signal Fout through a Q end of a D trigger DFF; of latches LATCH1Having terminals connected to the output of OR gate OR1, of LATCH LATCH2One terminal of the OR gate is connected with the output terminal of the OR gate OR2, one input terminal of the OR gate OR1 and one input terminal of the OR gate OR2 both receive the state switching control signal V2, and the other input terminal of the OR gate OR1 receives the frequency conversion inverted signalThe other input terminal of the OR gate OR2 receives the switching frequency signal Fout;

the output of LATCH1 outputs a control signal Φ 1 and the output of LATCH2 outputs a control signal Φ 2.

The falling edge modulation module comprises an inverter INV and an OR gate OR3, wherein an input terminal of the inverter INV and an input terminal of the OR gate OR3 both receive the state switching control signal V1, an output terminal of the inverter INV is connected to one terminal of a capacitor C100 and the other input terminal of the OR gate OR3, the other terminal of the capacitor C100 is grounded, and an output terminal of the OR gate OR3 and the LATCH1Terminal and LATCH of LATCH2And end connection.

The first transition state, the first single integration state, the second transition state and the second single integration state are included in sequence in one conversion period of the frequency conversion of the current source CS.

During initial transition, the method also comprises an initial state before the first transition state;

in an initial state, the control signal Φ 1 is in a first level state, the control signal Φ 2 is in a second level state, the charge-discharge control switch controlled by the control signal Φ 2 is in a closed state, the integrating capacitor branch only comprises a cell charge-discharge capacitor corresponding to the control signal Φ 1, when an integrating voltage VA1 output by the operational amplifier AMP reaches a comparison reference voltage VT1, the integrating state judgment module inverts the state of the output state switching control signal V1, and the state switching control module inverts the level state of the output switching frequency signal Fout according to the state switching control signal V1, so that the control signal Φ 2 is in the first level state。

In a first transition state, the charge and discharge control switches controlled by the control signal phi 1 and the control signal phi 2 are in a disconnected state, and the charge and discharge capacitors of the units in the charge and discharge branch circuit are connected in series to form an integral capacitor branch circuit; when the integrated voltage output by the operational amplifier AMP reaches the comparison reference voltage VT2, the integrated state judgment module flips the state of the output state switching control signal V2, and the state switching control module enables the control signal phi 1 to be in a second level state according to the state of the state switching control signal V2;

in a first single integration state, a charge-discharge control switch controlled by a control signal phi 1 is in a closed state, an integration circuit branch only comprises a unit charge-discharge capacitor corresponding to a control signal phi 2, the unit charge-discharge capacitor corresponding to the control signal phi 1 releases accumulated charges, an integration voltage VA1 output by an operational amplifier AMP drops to (VT2-VT1)/2, an integration state judgment module overturns the state of a state switching control signal V1, when the integration voltage VA1 output by the operational amplifier AMP reaches a comparison reference voltage VT1, the integration state judgment module overturns the state of an output state switching control signal V1 again, and the state switching control module overturns the level state of an output switching frequency signal Fout according to the state switching control signal V1;

in a second transition state, the charge and discharge control switches controlled by the control signal phi 1 and the control signal phi 2 are in a disconnected state, and the charge and discharge capacitors of the units in the charge and discharge branch circuit are connected in series to form an integral capacitor branch circuit; when the integrated voltage output by the operational amplifier AMP reaches the comparison reference voltage VT2, the integrated state judgment module flips the state of the output state switching control signal V2, and the state switching control module enables the control signal phi 2 to be in a second level state according to the state of the state switching control signal V2;

in a second single integration state, the charge-discharge control switch controlled by the control signal Φ 2 is in a closed state, the branch of the integration circuit only comprises a cell charge-discharge capacitor corresponding to the control signal Φ 1, the cell charge-discharge capacitor corresponding to the control signal Φ 2 releases accumulated charges, the integration voltage VA1 output by the operational amplifier AMP drops to (VT2-VT1)/2, the integration state judgment module inverts the state of the state switching control signal V1, when the integration voltage VA1 output by the operational amplifier AMP reaches the comparison reference voltage VT1, the integration state judgment module inverts the state of the state switching control signal V1 again, and the state switching control module inverts the level state of the output switching frequency signal Fout according to the state switching control signal V1.

The invention has the advantages that: the charge accumulation and release module is in adaptive connection with the operational amplifier AMP, the charge accumulation and release module at least comprises a charge-discharge branch, the charge-discharge branch at least comprises two charge-discharge units, the charge-discharge units in the charge-discharge branch are connected in series, the charge-discharge units comprise unit charge-discharge capacitors and parallel charge-discharge control switches, the unit charge-discharge capacitors and the parallel charge-discharge control switches of the unit charge-discharge capacitors are in one-to-one correspondence, the number of switches in the charge-discharge process can be reduced, and the influence of non-ideal factors of the switches on linearity is reduced; the integral state judgment module compares the integral voltage of the current integration circuit with the comparison reference voltage VT1 and the comparison reference voltage VT2 respectively, so that in the current-frequency conversion process, the stable state switching can be ensured through the transition state, the charge loss in the capacitance switching process is eliminated, the linearity in the current-frequency conversion process is ensured, and the current-frequency conversion circuit is safe and reliable.

Drawings

FIG. 1 is a schematic diagram of the present invention.

FIG. 2 is a schematic circuit diagram of a charging and discharging branch in the charge accumulation and discharge module according to the present invention.

FIG. 3 is a schematic diagram of an embodiment of the present invention.

FIG. 4 is a timing diagram of the present invention.

FIG. 5 is a schematic diagram of a second embodiment of the present invention.

FIG. 6 is a schematic diagram of a third embodiment of the present invention.

FIG. 7 is a schematic diagram of a state switching control module according to the present invention.

Description of reference numerals: the charge accumulating and releasing device comprises a 1-integration state judging module, a 2-state switching control module, a 3-charge accumulating and releasing module, a 4-first charge and discharge unit, a 5-second charge and discharge unit and a 6-falling edge modulating module.

Detailed Description

The invention is further illustrated by the following specific figures and examples.

As shown in fig. 1: in order to eliminate the charge loss in the process of capacitance switching and ensure the linearity of current frequency conversion, the invention comprises an operational amplifier AMP which is adaptive to a current source CS to be converted, wherein the output end of the current source CS is connected with the first end of the operational amplifier AMP;

the device comprises an operational amplifier AMP, a charge accumulation and release module 3, an integral state judgment module 1 and a state switching control module 2, wherein the charge accumulation and release module 3 is in adaptive connection with a first end of the operational amplifier AMP and an output end of the operational amplifier AMP, the integral state judgment module 1 is connected with the output end of the operational amplifier AMP, the state switching control module 2 is in adaptive connection with the output end of the integral state judgment module 1, a conversion frequency signal Fout can be output through the state switching control module 2, and a charge and discharge control signal can be loaded to the charge accumulation and release module;

the charge accumulation and release module 3 at least comprises a charge and discharge branch circuit, any charge and discharge branch circuit at least comprises two charge and discharge units connected in series, each charge and discharge unit comprises a unit charge and discharge capacitor and a charge and discharge control switch connected with the unit charge and discharge capacitor in parallel, the charge and discharge control switch can be in an open state or a closed state according to a received charge and discharge control signal, a required integral capacitor branch circuit can be formed by using the charge and discharge branch circuit according to the on-off state of the charge and discharge control switch in the charge and discharge branch circuit, and the integral capacitor branch circuit comprises part of the unit charge and discharge capacitors or all the unit charge and discharge capacitors; all the integrating capacitor branches in the charge accumulation and release module 3 are in adaptive connection with an operational amplifier AMP to form a required current integrating circuit;

in a conversion period of the current source CS frequency conversion, the integration state judgment module 1 can output a state switching control signal to the state switching control module 2 according to the integrated voltage output by the current integration circuit, and the state switching control module 2 can adjust the state of the charge/discharge control signal according to the state switching control signal and can control the output state of the conversion frequency signal Fout, so as to obtain a frequency value corresponding to the current of the current source CS according to the output conversion frequency signal Fout.

Specifically, the current source CS is generally a signal output by the sensor, the specific condition of the current source CS may be selected as needed, the operational amplifier AMP may adopt a conventional device, an output end of the current source CS is connected to a first end of the operational amplifier AMP, a second end of the operational amplifier AMP is grounded or connected to a reference voltage source, a specific matching form between the current source CS and the operational amplifier AMP may adopt a conventional form, specifically, the disclosure of the publication No. CN106289333A may be referred to, which is well known to those skilled in the art and is not described herein again.

As can be known to those skilled in the art, when frequency conversion is performed on the current source CS, an integration process is usually required, the charge accumulation and release module 3 and the operational amplifier AMP cooperate to form an integration circuit, an output end of the operational amplifier AMP is connected to the integration state judgment module 1, the state switching control module 2 can output a conversion frequency signal Fout, and a current relationship between the converted frequency and the current source CS can be obtained according to the conversion frequency signal Fout.

In the embodiment of the present invention, the charge accumulation and release module 3 includes at least one charge-discharge branch, and when there are multiple charge-discharge branches, all the charge-discharge branches are connected in parallel. That is, for all the charge/discharge branches, one end is connected to the first end of the operational amplifier AMP and the output end of the current source CS, and the other end is connected to the output end of the operational amplifier AMP.

In specific implementation, any charge-discharge branch at least comprises two charge-discharge units connected in series; when the number of the charge and discharge units in the charge and discharge branch circuit is more than two, the number of the charge and discharge units in the charge and discharge branch circuit is preferably even, and the charge and discharge units can be selected according to actual needs. Each charge and discharge unit comprises a unit charge and discharge capacitor and a charge and discharge control switch connected with the unit charge and discharge capacitor in parallel, of course, the unit charge and discharge capacitor can be formed by one capacitor or a plurality of capacitors, and can be specifically selected as required, and the details are not repeated here.

As shown in fig. 2 and fig. 3, a case where a charging/discharging branch includes two charging/discharging units is shown, in fig. 2, the two charging/discharging units are a first charging/discharging unit 4 and a second charging/discharging unit 5, and the first charging/discharging unit 4 and the second charging/discharging unit 5 are connected in series, where the first charging/discharging unit 4 has a unit charging/discharging capacitor C1 and a charging/discharging control switch S1 connected in parallel with the unit charging/discharging capacitor C1, the second charging/discharging unit 5 has a unit charging/discharging capacitor C2 and a charging/discharging control switch S2 connected in parallel with the unit charging/discharging capacitor C2, and the charging/discharging control switch S1 and the charging/discharging control switch S2 may both adopt conventional common switch forms, such as MOSFET devices, and they may be specifically selected as needed, and will not be described herein again.

Further, the charge and discharge control signal output by the state switching control module 2 includes a control signal Φ 1 and a control signal Φ 2, wherein the control signal Φ 1 and the control signal Φ 2 output by the state switching control module 2 are simultaneously loaded into each charge and discharge branch, and the switching state of a charge and discharge control switch in the charge and discharge unit is only controlled by the control signal Φ 1 or only by the control signal Φ 2;

when a charge-discharge branch circuit exists in the charge accumulation and release module 3, when a charge-discharge control switch controlled by a control signal phi 1 is closed and a charge-discharge control switch corresponding to a control signal phi 2 is opened, a single-branch first equivalent capacitor can be obtained through the charge-discharge branch circuit; when the charge and discharge control switch controlled by the control signal phi 2 is closed and the charge and discharge control switch corresponding to the control signal phi 1 is opened, the single-branch second equivalent capacitor can be obtained through the charge and discharge branch, and the capacity value of the single-branch second equivalent capacitor is equal to that of the single-branch first equivalent capacitor.

In the embodiment of the invention, a certain charge and discharge control switch is only controlled by a control signal phi 1 or only controlled by a control signal phi 2. In fig. 2 and 3, the charge and discharge control switch S1 is controlled by the control signal Φ 1, the charge and discharge control switch S2 is controlled by the control signal Φ 2, and the specific forms of the control signal Φ 1 and the control signal Φ 2 are generally related to the specific forms of the charge and discharge control switch, so that the charge and discharge control switch can be turned on or off. If the charge and discharge control switch adopts an N-type MOSFET device, the charge and discharge control switch can be in a closed state when the control signal Φ 1 and the control signal Φ 2 are at a high level, and the charge and discharge control switch can be in an open state when the control signal Φ 1 and the control signal Φ 2 are at a low level.

As shown in fig. 2 and 3, when the charge and discharge control switch S1 and the charge and discharge control switch S2 are both in the off state, the cell charge and discharge capacitor C1 and the cell charge and discharge capacitor C2 are connected in series with each other. When the charging and discharging control switch S1 is in a closed state under the action of the control signal phi 1, the short circuit of the unit charging and discharging capacitor C1 can be realized, the charging control switch S2 is still in an open state under the action of the control signal phi 2, and the single-branch first equivalent capacitor is the unit charging and discharging capacitor C2; and when the charge and discharge control switch S2 is in a closed state by the control signal Φ 2, the short circuit of the cell charge and discharge capacitor C2 can be realized, and the charge control switch S1 is still in an open state by the control signal Φ 1, the single-branch second equivalent capacitor is the cell charge and discharge capacitor C1, at this time, the capacitance value of the cell charge and discharge capacitor C1 is equal to the capacitance value of the cell charge and discharge capacitor C2, that is, the capacitance value of the single-branch first equivalent capacitor is equal to the capacitance value of the single-branch second equivalent capacitor.

As shown in fig. 5, an implementation case of including four charge and discharge units in a charge and discharge branch is shown, wherein a charge and discharge unit is formed by connecting a unit charge and discharge capacitor C11 and a charge and discharge control switch S11 in parallel, a charge and discharge unit is formed by connecting a unit charge and discharge capacitor C12 and a charge and discharge control switch S12 in parallel, a charge and discharge unit is formed by connecting a unit charge and discharge capacitor C21 and a charge and discharge control switch S21 in parallel, and a charge and discharge unit is formed by connecting a unit charge and discharge capacitor C22 and a charge and discharge control switch S22 in parallel. The four formed charge and discharge units form a series connection relationship, in addition, the switch states corresponding to the charge and discharge control switch S11 and the charge and discharge control switch S12 are controlled by the control signal Φ 2, and the switch states corresponding to the charge and discharge control switch S21 and the charge and discharge control switch S22 are controlled by the control signal Φ 1, and of course, the specific corresponding coordination conditions with the control signal Φ 1 and the control signal Φ 2 can be selected as required, and are not described herein again.

In fig. 5, different integrating capacitor branches can be obtained according to the specific states of the control signal Φ 1 and the control signal Φ 2; if the charge and discharge control switch S21 and the charge and discharge control switch S22 are closed by the control signal Φ 1 and the charge and discharge control switch S11 and the charge and discharge control switch S12 are kept open by the control signal Φ 2, the capacitance value of the single-branch first equivalent capacitor is the equivalent capacitance value of the unit charge and discharge capacitor C11 and the unit charge and discharge capacitor C12 connected in series; when the charge and discharge control switch S11 and the charge and discharge control switch S12 are closed by the control signal Φ 2 and the charge and discharge control switch S21 and the charge and discharge control switch S22 are kept open by the control signal Φ 1, the capacitance value of the single-branch second equivalent capacitor is the equivalent capacitance value of the capacitor C21 and the cell charge and discharge capacitor C22 connected in series.

In specific implementation, according to specific conditions of the control signal Φ 1 and the control signal Φ 2, connection matching forms of the charging and discharging capacitors of the units of the charging and discharging branches can be adjusted, so that different integrating capacitor branches can be obtained, and forms of a single-branch first equivalent capacitor and a single-branch second equivalent capacitor formed by the different integrating capacitor branches are confirmed according to actual circuit states, which is known to those skilled in the art. The integrating capacitor branch can form a current integrating circuit for integrating the current source CS in cooperation with the operational amplifier AMP.

In addition, when a plurality of charge and discharge branches are included in the charge accumulation and release module 3, all the charge and discharge branches are connected in parallel, the charge and discharge control signal output by the switching control module 2 comprises a control signal Φ 1 and a control signal Φ 2, wherein the control signal Φ 1 and the control signal Φ 2 output by the state switching control module 2 are simultaneously loaded into each charge and discharge branch, and the switching state of a charge and discharge control switch in the charge and discharge unit is only controlled by the control signal Φ 1 or only by the control signal Φ 2;

when the charge-discharge control switch controlled by the control signal phi 1 is closed and the charge-discharge control switch corresponding to the control signal phi 2 is opened, the multi-branch first equivalent capacitor can be obtained according to all charge-discharge branches in the charge accumulation and release module 3; when the charge and discharge control switch controlled by the control signal phi 2 is closed and the charge and discharge control switch corresponding to the control signal phi 1 is opened, the multi-branch second equivalent capacitor can be obtained according to all the charge and discharge branches in the charge accumulation and release module 3, and the capacity value of the multi-branch second equivalent capacitor is equal to that of the multi-branch first equivalent capacitor.

As shown in fig. 6, in the case that the charge accumulation and release module 3 includes two charge and discharge branches, the two charge and discharge branches are connected in parallel, and when there are more than two charge and discharge branches, reference may be made to the parallel connection in fig. 6, which is not described herein again. Generally, all the charging and discharging branches may adopt the same circuit form. In fig. 6, the cell charging and discharging capacitor C23 and the cell charging and discharging capacitor C24 are located in the same charging and discharging branch, and the cell charging and discharging capacitor C25 and the cell charging and discharging capacitor C26 are located in the same charging and discharging branch. The unit charging and discharging capacitor C23 is connected with the charging and discharging control switch S23 in parallel, the unit charging and discharging capacitor C24 is connected with the charging and discharging control switch S24 in parallel, the unit charging and discharging capacitor C25 is connected with the charging and discharging control switch S25 in parallel, and the unit charging and discharging capacitor C26 is connected with the charging and discharging control switch S26 in parallel.

The switching states corresponding to the charge and discharge control switch S24 and the charge and discharge control switch S25 are controlled by the control signal Φ 1, the switching states corresponding to the charge and discharge control switch S23 and the charge and discharge control switch S26 are controlled by the control signal Φ 2, and the specific case of forming the integrating capacitor branch by specifically matching the control signal Φ 1 and the control signal Φ 2 with the charge and discharge branch can refer to the above description, which is not described herein again. As shown in fig. 6, when the charge and discharge control switch S24 and the charge and discharge control switch S25 are closed by the control signal Φ 1 and the charge and discharge control switch S23 and the charge and discharge control switch S24 are kept in an open state by the control signal Φ 2, the capacitance value of the multi-branch first equivalent capacitor is the equivalent capacitance value of the unit charge and discharge capacitor C23 and the unit charge and discharge capacitor C24 connected in parallel. When the charge and discharge control switch S23 and the charge and discharge control switch S24 are closed by the control signal Φ 2 and the charge and discharge control switch S24 and the charge and discharge control switch S25 are kept in an open state by the control signal Φ 1, the capacitance value of the multi-branch second equivalent capacitor is the equivalent capacitance value after the unit charge and discharge capacitor C24 and the unit charge and discharge capacitor C25 are connected in parallel.

When there are multiple charging and discharging branches, the above description may be specifically referred to, so that the multiple-branch first equivalent capacitors and the multiple-branch second equivalent capacitors can be obtained.

In summary, the number of the charging and discharging branches in the charge accumulation and release module 3 and the specific form of the charging and discharging branches can be selected according to actual needs, and for the case that there are more than two charging and discharging units in the charging and discharging branches or the implementation case that there are multiple parallel charging and discharging branches, the matching form in fig. 2 and fig. 3 can be equivalent according to the connection relationship between capacitors. No matter the number of the charging and discharging branches and the specific implementation conditions of the charging and discharging branches, in the embodiment of the invention, a unit charging and discharging capacitor and the charging and discharging control switches connected with the unit charging and discharging capacitor in parallel are in one-to-one correspondence, and compared with the prior art, the number of the switches can be reduced, and the influence of non-ideal factors of the switches on the linearity is reduced. In addition, the implementation options of the charge accumulation and release module 3 can be expanded to meet the requirements of adapting to different application scenes.

During specific work, the integral state judgment module 1 can compare and judge integral voltage output by the current integral circuit, and output a state switching control signal to the state switching control module 2 according to a comparison judgment result, so that the state switching control module can adjust the specific states of the control signal phi 1 and the control signal phi 2 and control the output state of the switching frequency signal Fout. After a switching period, a frequency value corresponding to the current of the current source CS can be obtained according to the output switching frequency signal Fout.

Further, the integration state judgment module 1 can compare the integration voltage VA1 output by the operational amplifier AMP with the comparison reference voltage VT1 and the comparison reference voltage VT2, respectively, and the state switching control signal output by the integration state judgment module 1 includes a state switching control signal V1 and a state switching control signal V2;

according to the comparison result of the integrated voltage VA1 and the comparison reference voltages VT1 and VT2, the state switching control module 2 can adjust the level states of the state switching control signals V1 and V2.

In the embodiment of the present invention, the integration state determining module 1 has a comparison reference voltage VT1 and a comparison reference voltage VT2, the comparison reference voltage VT2 is greater than the comparison reference voltage VT1, and the state switching control module 2 can adjust the level states corresponding to the state switching control signal V1 and the state switching control signal V2 according to the comparison result between the integration voltage VA1 and the comparison reference voltage VT1 and the comparison reference voltage VT 2.

In specific implementation, in the charging and discharging branch, the charging and discharging units are connected in series, and the integral state judgment module 1 adopts the comparison reference voltage VT1 and the comparison reference voltage VT2 as two comparison values of the integral output voltage VA1, so that the stability of the whole conversion process can be realized, the charge loss in the switching process is eliminated, and the linearity of the current-frequency conversion is ensured.

As shown in fig. 3, 5 and 6, the integration state determining module 1 includes a voltage comparator COMP1 and a voltage comparator COMP2, an output terminal of the operational amplifier AMP is connected to an input terminal of the voltage comparator COMP1 and an input terminal of the voltage comparator COMP2, another input terminal of the voltage comparator COMP1 receives a comparison reference voltage VT1, another input terminal of the voltage comparator COMP2 receives the comparison reference voltage VT2, the comparison reference voltage VT2 is greater than the comparison reference voltage VT1, a state switching control signal V1 can be output from the output terminal of the voltage comparator COMP1, and a state switching control signal V2 can be output from the output terminal of the voltage comparator COMP 2.

In the embodiment of the present invention, the voltage comparator COMP1 and the voltage comparator COMP2 may both adopt the existing and commonly used comparator form, and may be specifically selected according to the needs. Generally, when the voltage VA1 output by the current integration circuit reaches the comparison reference voltage VT1, the state of the control signal V1 can be switched by the voltage comparator COMP1, and when the voltage VA1 output by the current integration circuit reaches the comparison reference voltage VT2, the state of the control signal V2 can be switched by the voltage comparator COMP 2. In a specific implementation, the state of the state switching control signal V1 is inverted by the voltage comparator COMP1, which means that the level state of the state switching control signal V1 is changed, for example, before the state switching control signal V1 is turned to be low level, the state switching control signal V1 is turned to be high level after the state switching, and the specific inversion condition of the state switching control signal V2 can refer to the description of the state switching control signal V1, which is not described herein again.

As shown in FIG. 7, the state-switching control module 2 comprises a D flip-flop DFF, a LATCH LATCH1 and a LATCH LARCH2, the clock terminal of the D flip-flop DFF and the state-switching control signal V1, and the state-switching control signal V1 further passes through the falling edge modulation module 6 and the LATCH LATCH1Terminal and LATCH of LATCH2End connection; d terminal of D flip-flop DFF and D flip-flop DFFTerminal-connected and through said D flip-flop DFFEnd output frequency conversion inverted signalBy D flip-flop DFThe Q end of the F outputs a conversion frequency signal Fout; of latches LATCH1Having terminals connected to the output of OR gate OR1, of LATCH LATCH2One terminal of the OR gate is connected with the output terminal of the OR gate OR2, one input terminal of the OR gate OR1 and one input terminal of the OR gate OR2 both receive the state switching control signal V2, and the other input terminal of the OR gate OR1 receives the frequency conversion inverted signalThe other input terminal of the OR gate OR2 receives the switching frequency signal Fout;

the output of LATCH1 outputs a control signal Φ 1 and the output of LATCH2 outputs a control signal Φ 2.

In the embodiment of the invention, when the state switching control signal V1 generates the falling edge jump, the D flip-flop DFF can control the switching frequency signal Fout and the frequency switching inverted signalAnd the falling edge modulation module 6 can modulate the falling edge transition of the state switching control signal V1 into a negative pulse signal, and the output control signal Φ 1 of the LATCH1 and the output control signal Φ 2 of the LATCH2 can be reset to a low level according to the negative pulse signal output by the falling edge modulation module 6. The state switching control signal V2 is respectively connected with the frequency conversion inverted signalAfter the conversion of the frequency signal Fout, the output control signal Φ 1 of the LATCH1 can be set high in accordance with the output of the OR gate OR1, OR the output control signal Φ 2 of the LATCH2 can be set high in accordance with the output of the OR gate OR2

In the embodiment of the present invention, the falling edge modulation module 6 includes an inverter INV and an OR gate OR3, the inverter INVThe input terminal of the OR gate OR3 receives the state switching control signal V1, the output terminal of the inverter INV is connected to one terminal of the capacitor C100 and the other input terminal of the OR gate OR3, the other terminal of the capacitor C100 is grounded, and the output terminal of the OR gate OR3 is connected to the LATCH LATCH1Terminal and LATCH of LATCH2And end connection.

Specifically, when current-frequency conversion is performed on the current source CS, a first transition state, a first individual integration state, a second transition state, and a second individual integration state are included in sequence in one conversion period of the frequency conversion of the current source CS; wherein, during the initial transition, the initial state before the first transition state is also included;

in an initial state, the control signal Φ 1 is in a first level state, the control signal Φ 2 is in a second level state, the charge-discharge control switch controlled by the control signal Φ 2 is in a closed state, the integrating capacitor branch only includes a cell charge-discharge capacitor corresponding to the control signal Φ 1, when an integrating voltage VA1 output by the operational amplifier AMP reaches a comparison reference voltage VT1, the integrating state judgment module 1 inverts the state of the output state switching control signal V1, and the state switching control module 2 inverts the level state of the output switching frequency signal Fout according to the state switching control signal V1, and makes the control signal Φ 2 be in the first level state;

in a first transition state, the charge and discharge control switches controlled by the control signal phi 1 and the control signal phi 2 are in a disconnected state, and the charge and discharge capacitors of the units in the charge and discharge branch circuit are connected in series to form an integral capacitor branch circuit; when the integrated voltage output by the operational amplifier AMP reaches the comparison reference voltage VT2, the integrated state judgment module 1 flips the state of the output state switching control signal V2, and the state switching control module 2 switches the state of the control signal V2 so that the control signal Φ 1 is in the second level state;

in a first single integration state, a charge-discharge control switch controlled by a control signal phi 1 is in a closed state, an integration circuit branch only comprises a cell charge-discharge capacitor corresponding to a control signal phi 2, the cell charge-discharge capacitor corresponding to a control signal Q1 releases accumulated charges, an integration voltage VA1 output by an operational amplifier AMP falls to (VT2-VT1)/2, an integration state judgment module 1 inverts the state of a state switching control signal V1, when an integration voltage VA1 output by the operational amplifier AMP reaches a comparison reference voltage VT1, the integration state judgment module 1 inverts the state of an output state switching control signal V1 again, and the state switching control module 2 inverts the level state of an output switching frequency signal Fout according to the state switching control signal V1;

in a second transition state, the charge and discharge control switches controlled by the control signal phi 1 and the control signal phi 2 are in a disconnected state, and the charge and discharge capacitors of the units in the charge and discharge branch circuit are connected in series to form an integral capacitor branch circuit; when the integrated voltage output by the operational amplifier AMP reaches the comparison reference voltage VT2, the integrated state judgment module 1 flips the state of the output state switching control signal V2, and the state switching control module 2 switches the state of the control signal V2 so that the control signal Φ 2 is in the second level state;

in the second single integration state, the charge-discharge control switch controlled by the control signal Φ 2 is in a closed state, the branch of the integration circuit only includes a cell charge-discharge capacitor corresponding to the control signal Φ 1, the cell charge-discharge capacitor corresponding to the control signal Q2 releases accumulated charges, the integration voltage VA1 output by the operational amplifier AMP drops to (VT2-VT1)/2, the integration state judgment module 1 inverts the state of the state switching control signal V1, when the integration voltage VA1 output by the operational amplifier AMP reaches the comparison reference voltage VT1, the integration state judgment module 1 inverts the state of the state switching control signal V1 again, and the state switching control module 2 inverts the level state of the output switching frequency signal Fout according to the state switching control signal V1.

In an embodiment of the present invention, in one switching period, the switching process includes a first transition state, a first individual integration state, a second transition state, and a second individual integration state, and the switching process is repeated in different switching periods. Of course, in the initial state, the initial state before the first transition state is also included, and the above-mentioned conversion process is repeated in the subsequent period. After a period of switching, a frequency value related to the current of the current source CS can be obtained according to the switching frequency signal Fout.

The control signal Φ 1 is in a first level state, generally means that the control signal Φ 1 is in a low level state, the control signal Φ 1 is in a second level state, specifically means that the control signal Φ 1 is in a high level state, and the specific condition of the control signal Φ 2 is consistent with the control signal Φ 1. Of course, the specific situations of the first level state and the second level state can also be selected according to needs, and are not described herein again.

The specific operation of one switching cycle of the present invention and the obtaining of the switching frequency signal Fout will be described in detail with reference to fig. 3 and 4. In fig. 3, the cell charge-discharge capacitance C1 and the cell charge-discharge capacitance C2 have the same capacitance value C, the charge-discharge control switch S1 is in a closed state when the control signal Φ 1 is at a high level, and is in an open state when the control signal Φ 1 is at a low level, and the specific condition between the charge-discharge control switch S2 and the control signal Φ 2 is consistent with the matching condition between the charge-discharge control switch S1 and the control signal Φ 1. In fig. 4, Q1 is the charge on the cell charge-discharge capacitor C1, and Q2 is the charge on the cell charge-discharge capacitor C2.

When the power is powered on for the first time, the power supply enters an initial state: the control signal Φ 1 is in a low level state, the control signal Φ 2 is in a high level state, at this time, the charge and discharge control switch S1 is in an open state, and the charge and discharge control switch S2 is in a closed state, that is, only the cell charge and discharge capacitor C1 is connected in parallel to the first input terminal of the operational amplifier AMP and the output terminal of the operational amplifier AMP, and the cell charge and discharge capacitor C2 is short-circuited, that is, only the cell charge and discharge capacitor C1 is included in the charge integration branch. The current I of the current source CS causes the cell charge/discharge capacitor C1 to gradually accumulate charges with time, so that the voltage of the integrating voltage VA1 at the output terminal of the operational amplifier AMP gradually increases until VA1 becomes VT1, and the time required for the whole integration is t0 becomes C VT 1/I. The state switching control signal V1 output by the voltage comparator COMP1 is inverted from high level to low level, and the state switching control module 2 immediately inverts the state of the switching frequency signal Fout, and at the same time, the state switching control module 2 inverts the control signal Φ 2 to low level.

A first transition state: since the control signal Φ 1 remains unchanged, the charge/discharge control switch S1 and the charge/discharge control switch S2 are both in the off state. The cell charge-discharge capacitor C2 starts to be connected to the integrating capacitor branch, and at this time, the cell charge-discharge capacitor C1 and the cell charge-discharge capacitor C2 are in a series state, so that the integrated charges in the transition state can be stored simultaneously without mutual interference, and the stored charges are the same. When the rising rate of the integrated voltage VA1 output by the current integration circuit is greater than that of only one capacitor, after the time t1 is equal to C (VT2-VT 1)/(2I), the integrated voltage VA1 output by the current integration circuit rises to VT2, the voltage comparator COMP2 inverts the output state switching control signal V2, that is, the state switching control signal V2 is inverted from high level to low level, the state switching control module 2 inverts the control signal Φ 1 to high level, and the control signal Φ 2 keeps the low level unchanged.

The first single integration state, the cell charge and discharge capacitance C2 single integration state: the high-level control signal Φ 1 enables the charge and discharge control switch S1 to be in a closed state, the charge and discharge control switch S2 to be in an open state, only the unit charge and discharge capacitor C2 in the integrating capacitor branch is connected in parallel with the first end and the output end of the operational amplifier AMP, and the unit charge and discharge capacitor C1 is short-circuited and releases all charges accumulated in the first two stages. After the state switching, the charge quantity on both sides of the cell charging and discharging capacitor C2 is (I × t1) — (C/2) × (VT2-VT1), the integrated voltage VA1 drops to (VT2-VT1)/2, and the state switching control signal V1 output by the voltage comparator COMP1 is inverted to a high level. The current I of the current source CS causes the cell charge/discharge capacity C2 to gradually accumulate charges over time, and the integrated voltage VA1 increases to V1 ═ VT1, with the time t2 ═ C (1.5 × VT1-0.5VT 2)/I. The state switching control signal V1 output by the voltage comparator COMP1 is inverted from high level to low level, and the balance switching signal Fout output by the state switching control module 2 is immediately inverted. The time interval from the previous inversion of the frequency conversion signal Fout is t1+ t2 ═ C × VT 1/I.

The second transition state: when the frequency conversion signal Fout is inverted, the control signal Φ 1 is also inverted at the same time, at this time, the control signal Φ 1 and the control signal Φ 2 are both in a low level state, the charge and discharge control switch S1 and the charge and discharge control switch S2 are both in an off state, the cell charge and discharge capacitor C1 starts to be connected to the charge integration circuit, the cell charge and discharge capacitor C1 and the cell charge and discharge capacitor C2 are in a series connection state, the circuit enters a transition state to operate, after a time t1 is equal to C (VT2-VT 1)/(2I), the integration voltage VA1 is increased to the comparison reference voltage VT2, the state switching control signal V2 output by the voltage comparator COMP2 is inverted from a high level to a low level, the state switching control module 2 inverts the control signal Φ 2 to a high level, and the control signal Φ 1 maintains the low level unchanged.

The second single integration state, the cell charge and discharge capacity C1 single integration state: because the control signal phi 2 is at a high level, the charge and discharge control switch S2 is in a closed state, the control signal phi 1 is at a low level, the charge and discharge control switch S1 is in an open state, only the unit charge and discharge capacitor C1 in the integrating capacitor branch is connected in parallel with the first end and the output end of the operational amplifier AMP, and the unit charge and discharge capacitor C2 is short-circuited and releases all charges accumulated in the first two stages. After the state switching, the charge amount on both sides of the cell charge-discharge capacitor C1 is (I × t1) — (C/2) × (VT2-VT1), the integrated voltage VA1 drops to (1/2) × (VT2-VT1), and the state switching control signal V1 output by the voltage comparator COMP1 is inverted to a high level. The current I of the current source CS causes the cell charge/discharge capacity C1 to gradually accumulate charges over time, and the integrated voltage VA1 increases to V1 ═ VT1, with the time t2 ═ C (1.5 × VT1-0.5VT 2)/I. The state switching control signal V1 output by the voltage comparator COMP1 is inverted from high level to low level, and the state switching control module 2 immediately inverts the state of the frequency switching signal Fout. At this time, the time interval from the previous inversion of the frequency conversion signal Fout is t1+ t2 — C × VT 1/I.

In summary, after the circuit is powered on, it is necessary to enter a cyclic operation mode of "the first transition state, the cell charge and discharge capacitor C2 single integration state, the second transition state, and the cell charge and discharge capacitor C1 single integration state" through an initial state, that is, after the initial state, each conversion period includes a process of "the first transition state, the cell charge and discharge capacitor C2 single integration state, the second transition state, and the cell charge and discharge capacitor C1 single integration state". The frequency of the frequency conversion signal Fout is

f＝1/T＝/2*(t1+t2)＝I/(2*C*VT1)

Wherein f is a frequency value of the frequency conversion signal, T is a time of the conversion period, C is a capacitance value of the unit charging and discharging capacitor C1 or the unit charging and discharging capacitor C2 in the single integration state, and when the branch of the integrating capacitor is in another form, the capacitance value C in the frequency formula is an equivalent capacitance value of the branch of the integrating capacitor connected in parallel between the first end and the output end of the operational amplifier AMP in the unit charging and discharging capacitor C1 and the unit charging and discharging capacitor C2 in the single integration state, that is, a capacitance value corresponding to the single-branch first equivalent capacitance or the multi-branch first equivalent capacitance.