阅读说明：本技术 存储器、存储器的衬底结构及其制备方法 (Memory, substrate structure of memory and preparation method of substrate structure ) 是由 周震 于 2019-11-26 设计创作，主要内容包括：本公开提供一种存储器、存储器的衬底结构及存储器的衬底结构的制备方法。该制备方法包括：提供衬底；在衬底上形成包括多个间隔分布的条状图形的第一掩膜层,各条状图形均沿着同一方向延伸；形成覆盖第一掩膜层的第一介质层；在第一介质层上形成多个间隔分布的牺牲部,各牺牲部均覆盖于条状图形；向牺牲部之间的间隙填充第二介质；去除各牺牲部,并保留间隙内的第二介质,以形成第二掩膜层,第二掩膜层对应于各牺牲部的区域均形成暴露条状图形的通孔图形；以第一掩膜层和第二掩膜层为掩膜,逐层刻蚀至衬底内,以形成多个阵列排布的有源区。本公开能够方便地形成多个呈阵列排布的有源区。(The disclosure provides a memory, a substrate structure of the memory and a preparation method of the substrate structure of the memory. The preparation method comprises the following steps: providing a substrate; forming a first mask layer comprising a plurality of strip patterns distributed at intervals on a substrate, wherein each strip pattern extends along the same direction; forming a first dielectric layer covering the first mask layer; forming a plurality of sacrificial parts distributed at intervals on the first dielectric layer, wherein each sacrificial part covers the strip-shaped graph; filling a second medium into the gap between the sacrificial parts; removing each sacrificial part, and reserving the second medium in the gap to form a second mask layer, wherein through hole patterns exposing the strip patterns are formed in the areas of the second mask layer corresponding to the sacrificial parts; and etching the first mask layer and the second mask layer into the substrate layer by taking the first mask layer and the second mask layer as masks to form a plurality of active regions arranged in an array. The present disclosure can conveniently form a plurality of active regions arranged in an array.)

1. A method for preparing a substrate structure of a memory is characterized by comprising the following steps:

providing a substrate;

forming a first mask layer on the surface of the substrate, wherein a plurality of strip patterns distributed at intervals are formed in the first mask layer, and each strip pattern extends along the same direction;

forming a first dielectric layer covering the first mask layer;

patterning the first dielectric layer to form a plurality of sacrificial parts distributed at intervals, wherein each sacrificial part covers the strip-shaped patterns;

filling a second medium into the gap between the sacrificial parts;

removing the sacrificial parts, and reserving the second medium in the gaps to form a second mask layer, wherein through hole patterns exposing the strip patterns are formed in the areas of the second mask layer corresponding to the sacrificial parts;

and etching the first mask layer and the second mask layer into the substrate layer by taking the first mask layer and the second mask layer as masks, and transmitting the strip patterns and the through hole patterns into the substrate to form a plurality of active regions which are arranged in an array.

2. The method of claim 1, wherein patterning the first dielectric layer to form a plurality of spaced apart sacrificial portions comprises:

forming a plurality of first through holes on the first medium layer, wherein the first through holes are distributed in an array;

forming a plurality of second through holes on the first medium layer, wherein the second through holes are distributed in an array; the first through holes and the second through holes are arranged in a staggered mode in a first direction and a second direction perpendicular to the first direction, and in the first direction and the second direction, orthographic projections of any first through hole and the adjacent second through hole on the substrate are in contact or overlap;

in a third direction, a part of the first medium layer, which is located between any one first through hole and the adjacent first through hole, forms the sacrificial part, and the deviation angle of the third direction relative to the first direction is pi/4.

3. The method of claim 2, wherein the first via and the second via have the same cross-sectional shape.

4. The method of claim 3, wherein the first through-holes and the second through-holes are circular holes.

5. The method of claim 4, wherein the first via and the second via have the same diameter.

6. The method of claim 1, wherein removing each sacrificial portion and leaving the second medium in the gap comprises:

and etching the sacrificial parts to form a second mask layer, wherein through hole patterns exposing the strip patterns are formed in the areas of the second mask layer corresponding to the sacrificial parts.

7. The method for preparing the substrate structure of the memory according to claim 6, wherein the etching rate of the second medium is less than the etching rate of the sacrificial portion, and the etching the sacrificial portion comprises:

and etching the sacrificial parts and the second medium to form a second mask layer, wherein through hole patterns exposing the strip patterns are formed in the areas of the second mask layer corresponding to the sacrificial parts.

8. The method as claimed in claim 7, wherein the second dielectric is silicon oxide, and the sacrificial material is silicon nitride.

9. The method of claim 8, wherein etching the sacrificial portion and the second dielectric comprises:

and etching the sacrificial parts and the second medium by using phosphoric acid to form a second mask layer, wherein through hole patterns exposing the strip patterns are formed in the areas of the second mask layer corresponding to the sacrificial parts.

10. The method as claimed in claim 7, wherein the second dielectric is silicon nitride, and the sacrificial material is silicon oxide.

11. The method of claim 10, wherein etching the sacrificial portion and the second dielectric comprises:

and etching the sacrificial parts and the second medium by adopting hydrofluoric acid to form a second mask layer, wherein through hole patterns exposing the strip patterns are formed in the areas of the second mask layer corresponding to the sacrificial parts.

12. The method for preparing the substrate structure of the memory according to claim 1, wherein the step of etching the first mask layer and the second mask layer into the substrate layer by layer with the first mask layer and the second mask layer as masks comprises:

etching the first mask layer by taking the second mask layer as a mask, and transferring the through hole pattern to the first mask layer so as to break the strip pattern;

and etching the substrate by taking the first mask layer with the broken strip patterns as a mask, and transmitting the strip patterns and the through hole patterns into the substrate to form a plurality of active regions arranged in an array.

13. The method of claim 1, wherein a distance between any two adjacent sacrificial portions is greater than a maximum dimension of any one of the sacrificial portions in a direction parallel to the substrate.

14. The method of claim 1, wherein filling the gaps between the sacrificial portions with a second medium comprises:

forming a second dielectric layer covering the sacrificial part and the gap between the sacrificial parts;

and removing the part of the second dielectric layer, which is positioned outside the gap.

15. The method of claim 14, wherein removing the second dielectric layer outside the gap comprises:

and removing the part of the second dielectric layer outside the gap by a chemical mechanical polishing process.

16. A substrate structure for a memory, characterized by being prepared by the method for preparing a substrate structure for a memory according to any one of claims 1 to 15.

17. A memory comprising the substrate structure of the memory of claim 16.

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to a memory, a substrate structure of the memory, and a method for manufacturing the substrate structure of the memory.

Background

With the rapid development of integrated circuit technology, memory has attracted more and more attention.

The memory includes a substrate structure and a capacitor structure on the substrate structure. In the process of preparing a substrate structure of a memory, a plurality of strip patterns need to be formed on a substrate firstly, then the strip patterns need to be broken to form a mask layer, and the mask layer is used as a mask to etch the substrate to form an active region. However, the stripe pattern is often difficult to break, resulting in difficulty in forming an active region on the substrate.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to a memory, a substrate structure of the memory, and a method for fabricating the substrate structure of the memory, which can conveniently form a plurality of active regions arranged in an array.

According to an aspect of the present disclosure, there is provided a method for preparing a substrate structure of a memory, including:

providing a substrate;

forming a first mask layer on the surface of the substrate, wherein a plurality of strip patterns distributed at intervals are formed in the first mask layer, and each strip pattern extends along the same direction;

forming a first dielectric layer covering the first mask layer;

patterning the first dielectric layer to form a plurality of sacrificial parts distributed at intervals, wherein each sacrificial part covers the strip-shaped patterns;

filling a second medium into the gap between the sacrificial parts;

removing the sacrificial parts, and reserving the second medium in the gaps to form a second mask layer, wherein through hole patterns exposing the strip patterns are formed in the areas of the second mask layer corresponding to the sacrificial parts;

and etching the first mask layer and the second mask layer into the substrate layer by taking the first mask layer and the second mask layer as masks, and transmitting the strip patterns and the through hole patterns into the substrate to form a plurality of active regions which are arranged in an array.

In an exemplary embodiment of the present disclosure, patterning the first dielectric layer to form a plurality of spaced apart sacrificial portions includes:

forming a plurality of first through holes on the first medium layer, wherein the first through holes are distributed in an array;

forming a plurality of second through holes on the first medium layer, wherein the second through holes are distributed in an array; the first through holes and the second through holes are arranged in a staggered mode in a first direction and a second direction perpendicular to the first direction, and in the first direction and the second direction, orthographic projections of any first through hole and the adjacent second through hole on the substrate are in contact or overlap;

in a third direction, a part of the first medium layer, which is located between any one first through hole and the adjacent first through hole, forms the sacrificial part, and the deviation angle of the third direction relative to the first direction is pi/4.

In an exemplary embodiment of the present disclosure, the first through-hole and the second through-hole have the same shape in cross section.

In an exemplary embodiment of the present disclosure, the first through-hole and the second through-hole are each a circular hole.

In an exemplary embodiment of the present disclosure, the first through hole and the second through hole have the same diameter.

In an exemplary embodiment of the present disclosure, removing each of the sacrificial portions and leaving the second medium in the gap includes:

and etching the sacrificial parts to form a second mask layer, wherein through hole patterns exposing the strip patterns are formed in the areas of the second mask layer corresponding to the sacrificial parts.

In an exemplary embodiment of the present disclosure, an etching rate of the second medium is less than an etching rate of the sacrificial portion, and etching the sacrificial portion includes:

and etching the sacrificial parts and the second medium to form a second mask layer, wherein through hole patterns exposing the strip patterns are formed in the areas of the second mask layer corresponding to the sacrificial parts.

In an exemplary embodiment of the present disclosure, the second dielectric is silicon oxide, and the material of the sacrificial portion is silicon nitride.

In an exemplary embodiment of the present disclosure, etching the sacrificial portion and the second medium includes:

and etching the sacrificial parts and the second medium by using phosphoric acid to form a second mask layer, wherein through hole patterns exposing the strip patterns are formed in the areas of the second mask layer corresponding to the sacrificial parts.

In an exemplary embodiment of the present disclosure, the second dielectric is silicon nitride, and the material of the sacrificial portion is silicon oxide.

In an exemplary embodiment of the present disclosure, etching the sacrificial portion and the second medium includes:

and etching the sacrificial parts and the second medium by adopting hydrofluoric acid to form a second mask layer, wherein through hole patterns exposing the strip patterns are formed in the areas of the second mask layer corresponding to the sacrificial parts.

In an exemplary embodiment of the present disclosure, etching layer by layer into the substrate with the first mask layer and the second mask layer as masks includes:

etching the first mask layer by taking the second mask layer as a mask, and transferring the through hole pattern to the first mask layer so as to break the strip pattern;

and etching the substrate by taking the first mask layer with the broken strip patterns as a mask, and transmitting the strip patterns and the through hole patterns into the substrate to form a plurality of active regions arranged in an array.

In an exemplary embodiment of the present disclosure, a distance between any adjacent two of the sacrificial portions is larger than a maximum dimension of any one of the sacrificial portions in a direction parallel to the substrate.

In one exemplary embodiment of the present disclosure, filling the gap between the sacrificial parts with a second medium includes:

forming a second dielectric layer covering the sacrificial part and the gap between the sacrificial parts;

and removing the part of the second dielectric layer, which is positioned outside the gap.

In an exemplary embodiment of the present disclosure, removing a portion of the second dielectric layer outside the gap includes:

and removing the part of the second dielectric layer outside the gap by a chemical mechanical polishing process.

According to one aspect of the disclosure, a substrate structure of a memory is provided, which is prepared by the preparation method of the substrate structure of the memory.

According to an aspect of the present disclosure, there is provided a memory including the substrate structure of the memory described in any one of the above.

According to the memory, the substrate structure of the memory and the preparation method of the substrate structure of the memory, the second mask layer is formed by removing the sacrificial parts and reserving the second medium filled in the gap positions among the sacrificial parts. Because each sacrificial part covers the strip-shaped patterns, through holes exposing the strip-shaped patterns are formed in the areas, corresponding to the sacrificial parts, of the formed second mask layer, the first mask layer and the second mask layer are used as masks, the strip-shaped patterns and the through hole patterns can be conveniently transmitted into the substrate, and therefore a plurality of active areas arranged in an array mode can be conveniently formed.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a flow chart of a method of fabricating a substrate structure of a memory according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of the substrate structure of the memory according to the embodiment of the disclosure after step S110 is completed;

fig. 3 is a flowchart of step S130 in a method for manufacturing a substrate structure of a memory according to an embodiment of the disclosure;

fig. 4 is a schematic diagram of the substrate structure of the memory according to the embodiment of the disclosure after step S1301 is completed;

fig. 5 is a schematic diagram of the method for manufacturing a substrate structure of a memory according to the embodiment of the disclosure after step S1302 is completed;

fig. 6 is a schematic diagram of a first via, a second via, and a sacrificial portion in a method for fabricating a substrate structure of a memory according to an embodiment of the disclosure;

fig. 7 is a schematic diagram of the substrate structure of the memory according to the embodiment of the disclosure after step S140 is completed;

fig. 8 is a schematic diagram of the substrate structure of the memory according to the embodiment of the disclosure after step S150 is completed;

fig. 9 is a schematic diagram of the method for manufacturing a substrate structure of a memory according to the embodiment of the disclosure after step S160 is completed.

In the figure: 1. a substrate; 101. a strip pattern; 102. an active region; 2. a first dielectric layer; 201. a first through hole; 202. a second through hole; 203. a sacrificial portion; 3. a second medium.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, materials, devices, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. The terms "a" and "the" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.

The embodiment of the disclosure provides a preparation method of a substrate structure of a memory. As shown in fig. 1, the method for preparing a substrate structure of a memory may include steps S100 to S160, wherein:

step S100, providing a substrate.

Step S110 is to form a first mask layer on the surface of the substrate, where a plurality of strip patterns are formed in the first mask layer, and each strip pattern extends along the same direction.

Step S120, a first dielectric layer covering the first mask layer is formed.

Step S130, patterning the first dielectric layer to form a plurality of sacrificial portions distributed at intervals, wherein each sacrificial portion covers the strip pattern.

Step S140 fills the gap between the sacrifice parts with a second medium.

And step S150, removing the sacrificial parts, and reserving the second medium in the gaps to form a second mask layer, wherein through hole patterns exposing the strip patterns are formed in the areas of the second mask layer corresponding to the sacrificial parts.

And step S160, etching the substrate layer by taking the first mask layer and the second mask layer as masks, and transmitting the strip patterns and the through hole patterns into the substrate to form a plurality of active regions which are arranged in an array.

According to the preparation method of the substrate structure of the memory, the sacrifice parts are removed, and the second medium filled in the gap position between the sacrifice parts is reserved to form the second mask layer. Because each sacrificial part covers the strip-shaped patterns, through holes exposing the strip-shaped patterns are formed in the areas of the formed second mask layer corresponding to the sacrificial parts, and the strip-shaped patterns and the through hole patterns can be conveniently transferred into the substrate by taking the first mask layer and the second mask layer as masks, so that a plurality of active regions arranged in an array mode are formed.

The following describes in detail the steps of the disclosed embodiments:

in step S100, a substrate is provided.

The substrate may be a single crystal silicon substrate, a single crystal germanium substrate, or a silicon-on-insulator (SOI) substrate, but the embodiments of the present disclosure are not particularly limited thereto.

In step S110, a first mask layer is formed on the surface of the substrate, and a plurality of strip patterns are formed in the first mask layer and are distributed at intervals, and each strip pattern extends along the same direction.

As shown in fig. 2, the material of the first mask layer may be silicon oxide, but is not limited thereto. The distance between any two adjacent bar patterns 101 may be the same, but is not limited thereto, and may also be different. The bar patterns 101 are all convex structures. For example, forming the first mask layer on the surface of the substrate 1 may include: forming a first material layer on the surface of the substrate 1; and patterning the first material layer to form a first mask layer. The first material layer may be prepared by chemical vapor deposition, and of course, may also be prepared by atomic layer deposition, but is not limited thereto, and may also be prepared by other methods. The patterning process may be a self-aligned double patterning (SADP) technique, and certainly, may also be a self-aligned quartic patterning (SAQP) technique, but the embodiment of the present disclosure is not limited thereto.

In step S120, a first dielectric layer covering the first mask layer is formed.

The first dielectric layer may be prepared by chemical vapor deposition, and of course, may also be prepared by atomic layer deposition, but is not limited thereto, and may also be prepared by other methods. The material of the first dielectric layer may be silicon nitride, but may also be silicon oxynitride (SiON), silicon carbon nitride (SiCN), or the like, but is not limited thereto, and may also be silicon oxide. The thickness of the first dielectric layer is not particularly limited in the embodiments of the present disclosure.

In step S130, the first dielectric layer is patterned to form a plurality of sacrificial portions distributed at intervals, and each sacrificial portion covers the stripe pattern.

The present disclosure may utilize a photo-etch-photo-etch process to pattern the first dielectric layer. Specifically, as shown in fig. 3, patterning the first dielectric layer to form a plurality of sacrificial portions distributed at intervals may include steps S1301 and S1302, wherein:

step S1301, forming a plurality of first through holes on the first dielectric layer, where the first through holes are distributed in an array.

The present disclosure may form a plurality of first vias on the first medium through a photolithography process. Specifically, the photolithography process includes: forming a photoresist layer on the first dielectric layer; exposing and developing the photoresist layer to form a plurality of channels; and etching the first medium layer by taking the photoresist layer with the plurality of channels as a mask so as to form a first through hole in a region corresponding to the channels on the first medium layer. As shown in fig. 4, the first through hole 201 may be a circular hole, but may also be an elliptical hole, but is not limited thereto, and may also be a square hole, etc.

Step 1302, forming a plurality of second through holes on the first dielectric layer, wherein the plurality of second through holes are distributed in an array.

As shown in fig. 5, the second through hole 202 may be a circular hole, but may also be an elliptical hole, but is not limited thereto, and may also be a square hole, etc. Preferably, the cross-sectional shapes of the second through-hole 202 and the first through-hole 201 may be the same, for example, and both the second through-hole 202 and the first through-hole 201 are circular holes. The sizes of the first through hole 201 and the second through hole 202 may be equal, and of course, may also be different, and this disclosure does not specifically limit this.

As shown in fig. 5 and 6, the first through holes 201 and the second through holes 202 are staggered in the first direction, that is, in the first direction, any one of the first through holes 201 is adjacent to one of the second through holes 202. The first direction is the X direction. The first direction is parallel to the substrate 1. Further, in the first direction, an orthographic projection of any one first through hole 201 and an adjacent second through hole 202 on the substrate 1 are in contact or overlap. Taking the first through holes 201 and the second through holes 202 as circular holes as an example, in the first direction, orthographic projections of any one first through hole 201 and an adjacent second through hole 202 on the substrate 1 are in contact or overlap, that is, a distance between an axis of any one first through hole 201 and an axis of an adjacent second through hole 202 is smaller than or equal to a sum of a radius of the first through hole 201 and a radius of the second through hole 202. In addition, the first direction is different from the extending direction of the stripe patterns 101.

As shown in fig. 5 and 6, the first through holes 201 and the second through holes 202 are staggered in the second direction, that is, in the second direction, any one of the first through holes 201 is adjacent to one of the second through holes 202. The second direction is the Y direction. The second direction is parallel to the substrate 1 and perpendicular to the first direction. Further, in the second direction, an orthographic projection of any one first through hole 201 and an adjacent second through hole 202 on the substrate 1 are contacted or overlapped. Taking the first through holes 201 and the second through holes 202 as circular holes as an example, in the second direction, orthographic projections of any one first through hole 201 and an adjacent second through hole 202 on the substrate 1 are in contact or overlap, that is, a distance between an axis of any one first through hole 201 and an axis of an adjacent second through hole 202 is smaller than or equal to a sum of a radius of the first through hole 201 and a radius of the second through hole 202. In addition, the second direction is different from the extending direction of the stripe patterns 101.

As shown in fig. 5 and 6, in the third direction, a portion of the first dielectric layer 2 located between any first through hole 201 and an adjacent first through hole 201 constitutes the sacrificial portion 203. The third direction is the M direction. The third direction is parallel to the substrate 1, and the deviation angle of the third direction relative to the first direction is pi/4, that is, the included angle between the third direction and the first direction is pi/4. Further, taking the example that the first through hole 201 and the second through hole 202 are both circular holes, the diameters of the first through hole 201 and the second through hole 202 are both larger than the maximum dimension of the sacrifice part 203 in the direction parallel to the substrate 1. In addition, the third direction is different from the extending direction of the stripe patterns 101.

In step S140, a second medium is filled into the gap between the sacrifice parts.

As shown in fig. 6 and 7, the etching rate of the second dielectric 3 may be smaller than that of the sacrificial portion 203. The material of the second dielectric 3 may be silicon oxide, and of course, the material of the second dielectric 3 may also be BPSG (borophosphosilicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), etc., but is not limited thereto, and may also be silicon nitride. For example, filling the gaps between the sacrificial portions 203 with the second medium 3 may include: forming a second dielectric layer covering the sacrificial part 203 and the gap between the sacrificial parts 203; and removing the part of the second dielectric layer outside the gap. The second dielectric layer may be prepared by chemical vapor deposition, and of course, may also be prepared by atomic layer deposition, but is not limited thereto, and may also be prepared by other methods. The second medium layer can be removed from the gap through grinding. Wherein the polishing may be chemical mechanical polishing. Taking the case where the first dielectric layer 2 is located between any first via 201 and the adjacent first via 201 to form the sacrificial portion 203, the second dielectric layer 3 may fill the first vias 201 and the second vias 202.

In step S150, each sacrificial portion is removed, and the second dielectric in the gap is retained to form a second mask layer, where a through hole pattern exposing the stripe pattern is formed in a region of the second mask layer corresponding to each sacrificial portion.

As shown in fig. 8, the present disclosure may form the above-described second mask layer by etching the sacrificial portion 203. Further, the present disclosure may form the above-mentioned second mask layer by etching the sacrificial portion 203 and the second dielectric 3. The etching may be a dry etching process, or a wet etching process. In an embodiment, the second dielectric 3 is silicon oxide, the material of the sacrificial portion 203 is silicon nitride, and the present disclosure may use phosphoric acid to etch the sacrificial portion 203 and the second dielectric 3 to form a second mask layer, where a region of the second mask layer corresponding to each sacrificial portion 203 forms a via pattern exposing the stripe pattern 101. In another embodiment, the second dielectric 3 is silicon nitride, the material of the sacrificial portion 203 is silicon oxide, and the present disclosure may use hydrofluoric acid to etch the sacrificial portion 203 and the second dielectric 3 to form a second mask layer, where a region of the second mask layer corresponding to each sacrificial portion 203 forms a via pattern exposing the stripe pattern 101. Further, the dimension of the via pattern in a direction perpendicular to the extending direction of the stripe pattern 101 is larger than the width of the stripe pattern 101, i.e. the projection of the via pattern on the substrate 1 covers the projection of the stripe pattern 101 on the substrate 1.

In step S160, the first mask layer and the second mask layer are used as masks, and the first mask layer and the second mask layer are etched into the substrate layer by layer, and the stripe patterns and the via hole patterns are transferred into the substrate to form a plurality of active regions arranged in an array.

For example, etching layer by layer into the substrate with the first mask layer and the second mask layer as masks may include: etching the first mask layer by taking the second mask layer as a mask, and transferring the through hole pattern to the first mask layer so as to break the strip pattern; and etching the substrate by taking the first mask layer with the broken strip patterns as a mask, and transmitting the strip patterns and the through hole patterns into the substrate to form a plurality of active regions arranged in an array. The etching may be performed by a dry etching process, but is not limited thereto, and may also be performed by an etching process. In addition, as shown in fig. 9, a plurality of active regions 102 are spaced apart.

The embodiment of the disclosure also provides a substrate structure of the memory. The substrate structure of the memory can be prepared by the method for preparing the substrate structure of the memory according to any one of the above embodiments, and therefore, the substrate structure of the memory has the same beneficial effects, and further description is omitted.

The embodiment of the disclosure also provides a memory. The memory includes the substrate structure of the memory described in the above embodiments. Of course, the memory may also include a capacitor structure, etc., but the disclosure is not limited thereto. Since the substrate structure included in the memory according to the embodiment of the present disclosure is the same as that in the embodiment of the substrate structure of the memory, the substrate structure has the same beneficial effects, and thus, the description thereof is omitted.

Moreover, although the steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.