阅读说明：本技术 半导体结构及其制备方法 (Semiconductor structure and preparation method thereof ) 是由 鲍锡飞 于 2019-11-28 设计创作，主要内容包括：本发明涉及一种半导体结构,包括：基底；第一支撑层,电容接触结构,形成于基底内,第一支撑层内形成有电容孔,电容接触结构延伸至第一支撑层内的部分与第一支撑层之间具有间隙；下电极层,包括主体部及延伸部；延伸部填充于间隙内,不仅下电极层的主体部接触电容接触结构,同时下电极层的延伸部接触电容接触结构靠近第一支撑层的侧面,使得下电极层与电容接触结构之间的接触面积增大,因此降低了接触电阻,同时主体部与延伸部共同组成下电极层使得下电极层呈嵌入第一支撑层与电容接触结构之间的状态,增加了下电极层的稳定性,能够在一定程度上防止电容侧倾或产生剥落缺陷,有利于动态存储器进一步缩小半导体元件的尺寸大小。(The invention relates to a semiconductor structure, comprising: a substrate; the capacitor contact structure is formed in the substrate, a capacitor hole is formed in the first support layer, and a gap is formed between the part of the capacitor contact structure extending into the first support layer and the first support layer; a lower electrode layer including a main body portion and an extension portion; the extension part is filled in the gap, not only the main body part of the lower electrode layer contacts the capacitor contact structure, and simultaneously the extension part of the lower electrode layer contacts the side surface of the capacitor contact structure close to the first support layer, so that the contact area between the lower electrode layer and the capacitor contact structure is increased, therefore, the contact resistance is reduced, and simultaneously the main body part and the extension part jointly form the lower electrode layer so that the lower electrode layer is in a state of being embedded between the first support layer and the capacitor contact structure, thereby increasing the stability of the lower electrode layer, preventing the capacitor from tilting or generating the peeling defect to a certain extent, and being beneficial to further reducing the size of the semiconductor element of the.)

1. A semiconductor structure, comprising:

a substrate;

a first support layer formed on the substrate;

a capacitor contact structure formed in the substrate and partially extending into the first support layer; a capacitor hole is formed in the first supporting layer, and the capacitor hole exposes the part of the capacitor contact structure extending into the first supporting layer; a gap is arranged between the part of the capacitance contact structure extending into the first support layer and the first support layer;

a lower electrode layer including a main body portion and an extension portion; the bottom of the main body part covers the upper surface of the capacitor contact structure; the extending part is located below the main body part and is integrally connected with the main body part, and the extending part is filled in the gap and is in contact with the capacitor contact structure.

2. The semiconductor structure of claim 1, wherein the capacitive contact structure has a Z-shape in longitudinal cross-section.

3. The semiconductor structure of claim 1, further comprising:

the second supporting layer is positioned above the first supporting layer and has a distance with the first supporting layer;

the third supporting layer is positioned above the second supporting layer and has a distance with the second supporting layer;

the capacitor hole also penetrates through the third supporting layer and the second supporting layer and extends to the first supporting layer; the main body part of the lower electrode layer also at least covers the side wall of the capacitor hole.

4. The semiconductor structure of claim 3, further comprising:

the capacitor dielectric layer covers the surface of the lower electrode layer;

and the upper electrode layer covers the surface of the capacitance dielectric layer.

5. A method for manufacturing a semiconductor structure, comprising the steps of:

providing a substrate;

forming a capacitor contact structure in the substrate, wherein the capacitor contact structure partially extends to the substrate;

forming a groove sacrificial layer on the side surface of the part of the capacitance contact structure extending to the substrate;

forming a first supporting layer on the substrate, wherein the first supporting layer covers the part of the capacitor contact structure extending to the substrate and the groove sacrificial layer;

forming a capacitor hole in the first support layer, wherein the capacitor hole exposes a part of the capacitor contact structure extending to the substrate and the groove sacrificial layer;

removing the groove sacrificial layer to form a gap between the part of the capacitance contact structure extending to the substrate and the first support layer;

forming a lower electrode layer in the capacitor hole, wherein the lower electrode layer comprises a main body part and an extension part; the bottom of the main body part covers the upper surface of the capacitor contact structure; the extending part is located below the main body part and is integrally connected with the main body part, and the extending part is filled in the gap and is in contact with the capacitor contact structure.

6. The method of claim 5, wherein forming a capacitive contact structure in the substrate comprises:

forming a contact hole in the substrate;

forming a contact material layer in the contact hole and on the substrate;

and photoetching the contact material layer to obtain the capacitor contact structure.

7. The method for fabricating a semiconductor structure according to claim 5, wherein forming a trench sacrificial layer on a side surface of a portion of the capacitor contact structure extending to the substrate comprises:

depositing a groove sacrificial layer on the surface of the part of the capacitance contact structure extending to the substrate and the upper surface of the substrate;

and removing the groove sacrificial layers on the upper surface of the capacitor contact structure and the upper surface of the substrate, and only keeping the groove sacrificial layer on the side surface of the part of the capacitor contact structure extending to the substrate.

8. The method according to claim 1, wherein under the same etching conditions, the removal rate of the trench sacrificial layer is greater than the removal rate of the first supporting layer and the removal rate of the capacitor contact structure.

9. The method of claim 1, further comprising, after forming a first support layer on the substrate and before forming a capacitor hole in the first support layer:

forming a first sacrificial layer on the first support layer;

forming a second supporting layer on the first sacrificial layer;

forming a second sacrificial layer on the second support layer;

forming a third supporting layer on the second sacrificial layer;

the capacitor hole penetrates through the third support layer, the second sacrificial layer, the second support layer and the first sacrificial layer along the thickness direction and extends into the first support layer.

10. The method for fabricating a semiconductor structure according to claim 9, further comprising, after forming the lower electrode layer:

forming openings in the third support layer and the second support layer respectively;

removing the second sacrificial layer and the first sacrificial layer based on the opening;

forming a capacitance dielectric layer on the surface of the lower electrode layer;

and forming an upper electrode layer on the surface of the capacitance dielectric layer.

Technical Field

The invention relates to the field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.

Background

A Dynamic Random Access Memory (DRAM) cell includes a capacitor for storing charge and a transistor to access the capacitor. As the geometric dimensions continue to decrease according to moore's law, the density of semiconductor devices in an integrated circuit increases, and thus the spacing between the dimensions of the semiconductor devices decreases, and the contact resistance between the capacitor contact structure and the capacitor increases, which may affect the performance of the memory to some extent and limit the reduction of the memory size.

Disclosure of Invention

In view of the above, it is desirable to provide a semiconductor structure and a method for fabricating the same. Which has the effect of facilitating the dynamic access memory to further reduce the size of the semiconductor device.

A semiconductor structure, comprising:

a substrate;

a first support layer formed on the substrate;

a capacitor contact structure formed in the substrate and partially extending into the first support layer; a capacitor hole is formed in the first supporting layer, and the capacitor hole exposes the part of the capacitor contact structure extending into the first supporting layer; a gap is arranged between the part of the capacitance contact structure extending into the first support layer and the first support layer;

a lower electrode layer including a main body portion and an extension portion; the bottom of the main body part covers the upper surface of the capacitor contact structure; the extending part is located below the main body part and is integrally connected with the main body part, and the extending part is filled in the gap and is in contact with the capacitor contact structure.

Through the technical scheme, not only the main part contact capacitance contact structure of lower electrode layer, the extension contact capacitance contact structure of lower electrode layer is close to the side of first supporting layer simultaneously, make the area of contact increase between lower electrode layer and the capacitance contact structure, consequently, contact resistance has been reduced, the main part constitutes the lower electrode layer jointly with the extension simultaneously and makes the lower electrode layer be the state of embedding between first supporting layer and the capacitance contact structure, the stability of lower electrode layer has been increased, can prevent to a certain extent that the electric capacity from heeling or produce and peel off the defect, be favorable to dynamic memory further to reduce semiconductor element's size of a dimension.

In one embodiment, the longitudinal cross-sectional shape of the capacitive contact structure is a zigzag shape.

In one embodiment, the semiconductor structure further comprises:

the second supporting layer is positioned above the first supporting layer and has a distance with the first supporting layer;

the third supporting layer is positioned above the second supporting layer and has a distance with the second supporting layer;

the capacitor hole also penetrates through the third supporting layer and the second supporting layer and extends to the first supporting layer; the main body part of the lower electrode layer also at least covers the side wall of the capacitor hole.

In one embodiment, the semiconductor structure further comprises:

the capacitor dielectric layer covers the surface of the lower electrode layer;

and the upper electrode layer covers the surface of the capacitance dielectric layer.

The invention also provides a preparation method of the semiconductor structure, which comprises the following steps:

providing a substrate;

forming a capacitor contact structure in the substrate, wherein the capacitor contact structure partially extends to the substrate;

forming a groove sacrificial layer on the side surface of the part of the capacitance contact structure extending to the substrate;

forming a first supporting layer on the substrate, wherein the first supporting layer covers the part of the capacitor contact structure extending to the substrate and the groove sacrificial layer;

forming a capacitor hole in the first support layer, wherein the capacitor hole exposes a part of the capacitor contact structure extending to the substrate and the groove sacrificial layer;

removing the groove sacrificial layer to form a gap between the part of the capacitance contact structure extending to the substrate and the first support layer;

forming a lower electrode layer in the capacitor hole, wherein the lower electrode layer comprises a main body part and an extension part; the bottom of the main body part covers the upper surface of the capacitor contact structure; the extending part is located below the main body part and is integrally connected with the main body part, and the extending part is filled in the gap and is in contact with the capacitor contact structure.

The lower electrode layer formed by the technical scheme is in contact with the capacitor contact structure through the main body part, the extension part is also in contact with the side face of the capacitor contact structure close to the first support layer, so that the contact area between the lower electrode layer and the capacitor contact structure is increased, therefore, the contact resistance is reduced, meanwhile, the main body part and the extension part jointly form the lower electrode layer, so that the lower electrode layer is in a state of being embedded between the first support layer and the capacitor contact structure, the stability of the lower electrode layer is increased, the capacitor can be prevented from inclining or peeling off to a certain extent, and the size of a semiconductor element can be further reduced by the dynamic memory

In one embodiment, forming a capacitive contact structure in the substrate includes:

forming a contact hole in the substrate;

forming a contact material layer in the contact hole and on the substrate;

and photoetching the contact material layer to obtain the capacitor contact structure.

In one embodiment, the forming a trench sacrificial layer on a side surface of a portion of the capacitor contact structure extending to the substrate includes:

depositing a groove sacrificial layer on the surface of the part of the capacitance contact structure extending to the substrate and the upper surface of the substrate;

and removing the groove sacrificial layers on the upper surface of the capacitor contact structure and the upper surface of the substrate, and only keeping the groove sacrificial layer on the side surface of the part of the capacitor contact structure extending to the substrate.

In one embodiment, under the same etching condition, the removal rate of the trench sacrificial layer is greater than the removal rate of the first support layer and the removal rate of the capacitor contact structure.

In one embodiment, after forming the first supporting layer on the substrate and before forming the capacitor hole in the first supporting layer, the method further includes:

forming a first sacrificial layer on the first support layer;

forming a second supporting layer on the first sacrificial layer;

forming a second sacrificial layer on the second support layer;

forming a third supporting layer on the second sacrificial layer;

the capacitor hole penetrates through the third support layer, the second sacrificial layer, the second support layer and the first sacrificial layer along the thickness direction and extends into the first support layer.

In one embodiment, after forming the lower electrode layer, the method further includes:

forming openings in the third support layer and the second support layer respectively;

removing the second sacrificial layer and the first sacrificial layer based on the opening;

forming a capacitance dielectric layer on the surface of the lower electrode layer;

and forming an upper electrode layer on the surface of the capacitance dielectric layer.

Drawings

FIG. 1 is a flow chart illustrating a method for fabricating a semiconductor structure according to one embodiment of the present invention;

FIGS. 2-8 are schematic structural views showing steps of a method for fabricating a semiconductor structure according to one embodiment of the present invention;

FIGS. 9-11 are schematic structural views showing steps in a method of fabricating a semiconductor structure according to another embodiment of the present invention; fig. 9 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention; fig. 11 is a schematic structural diagram of a semiconductor structure according to another embodiment of the present invention.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on methods or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

As the pitch between the semiconductor device dimensions is reduced, the contact resistance between the capacitor contact structure and the capacitor is also continuously increased, which affects the performance of the memory to a certain extent and limits the reduction of the memory dimensions, therefore, the present invention provides a method for manufacturing a semiconductor structure, as shown in fig. 1, specifically comprising the following steps:

step S10: providing a substrate 10;

step S20: forming a capacitor contact structure 12 in the substrate 10, wherein the capacitor contact structure 12 partially extends to the substrate 10;

step S30: forming a trench sacrificial layer 22 on the side of the portion of the capacitor contact structure 12 extending to the substrate 10;

step S40: forming a first supporting layer 11 on the substrate 10, wherein the first supporting layer 11 covers a portion of the capacitor contact structure 12 extending to the substrate 10 and the trench sacrificial layer 22;

step S50: forming a capacitor hole 13 in the first supporting layer 11, wherein the capacitor hole 13 exposes a portion of the capacitor contact structure 12 extending to the substrate 10 and the trench sacrificial layer 22;

step S60: removing the trench sacrificial layer 22 to form a gap 14 between the portion of the capacitor contact structure 12 extending onto the substrate 10 and the first support layer 11;

step S70: forming a lower electrode layer 15 in the capacitor hole 13, wherein the lower electrode layer 15 includes a main body portion 151 and an extension portion 152; the bottom of the body 151 covers the upper surface of the capacitor contact structure 12; the extension portion 152 is located below the main body portion 151 and integrally connected to the main body portion 151, and the extension portion 152 is filled in the gap 14 and contacts with the capacitor contact structure.

For step S10, specifically, as shown in fig. 2, the substrate 10 may be a silicon nitride substrate or the like.

For step S20, in an alternative embodiment, the following steps are specifically included, as shown in fig. 2:

step S201: forming a contact hole in the substrate 10;

specifically, a photoresist material layer is spin-coated on the substrate 10, a patterned photoresist layer is formed on the substrate 10 after patterned exposure and development, the substrate 10 is etched according to a pattern defined by the position and shape of the hole on the photoresist layer, and a contact hole is formed on the substrate 10.

Step S202: forming a contact material layer in the contact hole and on the substrate 10;

specifically, a contact material layer is deposited on the substrate 10 with the contact hole formed thereon, and the contact material layer is a conductive material, and may be a conductive metal such as tungsten, aluminum alloy, and the like.

Step S203: photoetching the contact material layer to obtain a capacitor contact structure 12;

specifically, an isolation layer and a graphical material layer are sequentially deposited on the contact material layer, an amorphous silicon layer, a silicon oxynitride layer and an oxide material layer are sequentially deposited on the graphical material layer, a strip-shaped graph is defined on the oxide material layer in a first direction through a photoetching process, and the graphical material layer is etched according to the graph in the first direction after the first etching. And depositing the amorphous silicon layer, the silicon oxynitride layer and the oxide material layer on the patterned material layer for the first time, defining a strip-shaped pattern on the oxide material layer in the second direction through photoetching, etching the patterned material layer according to the pattern in the second direction after the second etching, and enabling the pattern lines transferred to the patterned material layer to be straighter by the amorphous silicon layer and the silicon oxynitride layer. The first direction intersects the second direction, so that the patterned material layer after twice etching forms a raised pattern in a matrix arrangement. The raised patterns arranged in the matrix are transferred to the contact material layer through etching, so that the capacitor contact structure 12 is formed, the positions of the raised patterns and the positions of the contact holes on the substrate 10 are staggered, and the longitudinal section of the capacitor contact structure 12 obtained through etching is Z-shaped.

For step S30, in an alternative embodiment, the method specifically includes the following steps:

step S301: depositing a trench sacrificial layer 22 on the surface of the portion of the capacitor contact structure 12 extending to the substrate 10 and the upper surface of the substrate 10, as shown in fig. 3;

specifically, the trench sacrificial layer 22 may be an oxide such as silicon dioxide, and under the same etching condition, the removal rate of the trench sacrificial layer 22 is much greater than that of the capacitor contact structure 12.

Step S302: the trench sacrificial layer 22 on the upper surface of the capacitor contact structure 12 and the upper surface of the substrate 10 is removed, and only the trench sacrificial layer 22 on the side surface of the portion of the capacitor contact structure 12 extending to the substrate 10 remains, as shown in fig. 4.

Specifically, the top of the capacitor contact structure 12 and the trench sacrificial layer 22 on the substrate 10 are removed by dry etching, so that a ring of trench sacrificial layer 22 on the sidewall of the capacitor contact structure 12 is remained.

For step S40, as shown in fig. 5, specifically, the material of the first support layer 11 may be silicon nitride, and under the same etching condition, the etching rate of the first support layer 11 is much smaller than that of the trench sacrificial layer 22.

In an alternative embodiment, step S41 is further included after step S40 and before step S50, and step S41 specifically includes the following steps:

step S411: forming a first sacrificial layer 20 on the first support layer 11;

step S412: forming a second support layer 16 on the first sacrificial layer 20;

step S413: forming a second sacrificial layer 21 on the second support layer 16;

step S411: a third support layer 17 is formed on the second sacrificial layer 21, as shown in fig. 6.

Specifically, the first sacrificial layer 20 and the second sacrificial layer 21 may be oxides such as silicon oxide, the second support layer 16 and the third support layer 17 may be silicon nitride, and under the same etching condition, the removal rates of the first sacrificial layer 20, the second sacrificial layer 21, the second support layer 16 and the third support layer 17 are different.

As for step S50, as shown in fig. 7, in an alternative embodiment, the method specifically includes the following steps:

step S501: forming a patterned mask layer on the third supporting layer 17, and etching the third supporting layer 17 according to a pattern defined by the patterned mask layer to expose the second sacrificial layer 21;

step S502: etching the second sacrificial layer 21 by using the third support layer 17 as a mask layer to expose the second support layer 16;

step S503: etching the exposed second support layer 16 to expose the first sacrificial layer 20;

step S504: etching the exposed first sacrificial layer 20 to expose the first support layer 11;

step S505 is to etch the exposed first supporting layer 11 to form a capacitor hole 13, and the capacitor hole 13 exposes the capacitor contact structure 12 and the trench sacrificial layer 22.

Specifically, the etching is performed by dry etching, so that a deeper capacitor hole 13 can be formed, and the inner wall of the capacitor hole 13 is close to a vertical state.

For step S60, as shown in fig. 7, specifically, the trench sacrificial layer 22 is etched through the capacitor hole 13, so that the capacitor hole 13 communicates with the gap 14 formed between the portion of the capacitor contact structure 12 extending onto the substrate 10 and the first support layer 11.

For step S70: as shown in fig. 8, specifically, the lower electrode layer 15 is deposited in the capacitor hole 13, the lower electrode layer 15 includes a main body portion 151 and an extension portion 152, the main body portion 151 is formed on an inner wall of the capacitor hole 13 and covers an upper surface of the capacitor contact structure 12, the capacitor hole 13 is communicated with the gap 14, so that the extension portion 152 fills the gap 14 and has one end integrally disposed with the main body portion 151, the extension portion 152 is in direct contact with the capacitor contact structure 12, and the lower electrode layer 15 may be a conductive compound formed by one or two of metal nitride and metal silicide, such as titanium nitride, titanium silicide, nickel silicide, and the like.

Because the main body 151 of the lower electrode layer 15 contacts the capacitor contact structure 12 and the extension portion 152 of the lower electrode layer 15 also directly contacts the capacitor contact structure 12, the contact area between the lower electrode layer 15 and the capacitor contact structure 12 is increased, so that the contact resistance is reduced, and meanwhile, the main body 151 and the extension portion 152 jointly form the lower electrode layer 15, so that the lower electrode layer 15 is embedded between the first support layer 11 and the capacitor contact structure 12, and the stability of the lower electrode layer 15 is increased.

Step S80 is further included after step S70, and step S80 specifically includes the following steps:

step S801: forming openings in the third support layer 17 and the second support layer 16, respectively, as shown in fig. 9;

specifically, the lower electrode layer 15 on the top of the third support layer 17 is removed, and a plurality of opening positions are selected to remove the third support layer 17 and the second support layer 16 at the positions, so as to form openings.

Step S802: removing the second sacrificial layer 21 and the first sacrificial layer 20 based on the opening, as shown in fig. 9;

specifically, the etching solution can etch the first sacrificial layer 20 and the second sacrificial layer 21 through the opening, and after the etching is finished, the first support layer 11, the second support layer 16, and the third support layer 17 still remain and support the lower electrode layer 15.

Step S803: forming a capacitance dielectric layer 18 on the surface of the lower electrode layer 15, as shown in fig. 10;

specifically, the capacitor dielectric layer 18 is deposited on the bottom electrode layer 15, and the capacitor dielectric layer 18 may be made of a high-K dielectric material to increase the capacitance of the single-area capacitor, and may be a laminate formed of one or more of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, and AlOx.

Step S804: forming an upper electrode layer 19 on the surface of the capacitor dielectric layer 18, as shown in fig. 11;

specifically, the upper electrode layer 19 is deposited on the capacitor dielectric layer 18, and the upper electrode layer 19 may be a conductive compound formed by one or both of metal nitride and metal silicide, such as titanium nitride, titanium silicide, nickel silicide, and the like.

In an alternative embodiment, the present invention also provides a semiconductor structure, as shown in FIG. 9, comprising

Substrate 10, in an alternative embodiment, substrate 10 may be a silicon nitride substrate.

The first support layer 11, which is formed on the substrate 10 through a deposition process, may be made of silicon nitride.

A capacitor contact structure 12 formed in the substrate 10 and partially extending into the first supporting layer 11, wherein in an alternative embodiment, the longitudinal cross-sectional shape of the capacitor contact structure 12 is a Z-shape; a capacitor hole 13 is formed in the first supporting layer 11, and the capacitor hole 13 exposes a part of the capacitor contact structure 12 extending into the first supporting layer 11; the portion of the capacitor contact structure 12 extending into the first support layer 11 has a gap 14 with the first support layer 11.

A lower electrode layer 15 including a main body portion 151 and an extension portion 152; in an alternative embodiment, the lower electrode layer 15 may be a conductive compound formed by one or both of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, and the like. The bottom of the body 151 covers the upper surface of the capacitor contact structure 12; the extension portion 152 is located below the main body portion 151 and integrally connected to the main body portion 151, and the extension portion 152 is filled in the gap 14 and contacts with the capacitor contact structure.

In other alternative embodiments, the semiconductor structure further includes a second support layer 16 and a third support layer 17, the capacitor hole 13 penetrates through the third support layer 17 and the second support layer 16 and extends to the first support layer 11, and the main body portion 151 of the lower electrode layer 15 completely covers the sidewall of the capacitor hole 13, so that the second support layer 16 and the third support layer 17 can be sufficiently in contact with the lower electrode layer 15, and thus the lower electrode layer 15 can be better supported, and the lower electrode layer 15 is not prone to toppling.

In other alternative embodiments, as shown in fig. 11, the semiconductor structure further includes a capacitor dielectric layer 18 and an upper electrode layer 19, and the capacitor dielectric layer 18 is located between the upper electrode layer 19 and the lower electrode layer 15. The capacitor dielectric layer 18 can be a high-K dielectric material to increase the capacitance of the single-area capacitor, and can be a stack of one or more of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, and AlOx. The upper electrode layer 19 may be a conductive compound formed of one or both of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, or the like.

In summary, not only the main portion 151 of the lower electrode layer 15 contacts the capacitor contact structure 12, but also the extension portion 152 of the lower electrode layer 15 contacts the side surface of the capacitor contact structure 12 close to the first supporting layer 11, so that the contact area between the lower electrode layer 15 and the capacitor contact structure 12 is increased, and therefore the contact resistance is reduced, and meanwhile, the main portion 151 and the extension portion 152 jointly form the lower electrode layer 15, so that the lower electrode layer 15 is embedded between the first supporting layer 11 and the capacitor contact structure 12, so that the stability of the lower electrode layer 15 is increased, the formed capacitor is not prone to peeling defects, and the dynamic memory is beneficial to further reducing the size of the semiconductor device.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.