阅读说明：本技术 形成半导体结构的方法 (Method for forming semiconductor structure ) 是由 张锦标 于 2020-02-03 设计创作，主要内容包括：本发明公开了一种形成半导体结构的方法,包括以下步骤：在底金属上形成介电堆叠。在介电堆叠上形成第一遮罩层,其中第一遮罩层具有第一通孔,其一部分位于第一遮罩层的中心部分。在第一遮罩层上及第一通孔中形成第二遮罩层。图案化第二遮罩层,以形成位于第二遮罩层的中心部分与周围部分之间的开口,使得开口下方的第一通孔中的第二遮罩层被移除,其中第二遮罩层的中心部分覆盖第一通孔的部分,且中心部分被周围部分围绕。蚀刻第一通孔下方的介电堆叠,以形成第二通孔,其中底金属经由第二通孔而暴露。在第二通孔中及介电堆叠的顶表面上形成导电层。通过使用上述的形成半导体结构的方法,可以改善半导体结构的效能。(The invention discloses a method for forming a semiconductor structure, which comprises the following steps: a dielectric stack is formed on the bottom metal. A first masking layer is formed over the dielectric stack, wherein the first masking layer has a first via, a portion of which is located in a central portion of the first masking layer. A second mask layer is formed on the first mask layer and in the first via hole. The second mask layer is patterned to form an opening between a central portion and a peripheral portion of the second mask layer such that the second mask layer in the first via hole under the opening is removed, wherein the central portion of the second mask layer covers a portion of the first via hole and the central portion is surrounded by the peripheral portion. The dielectric stack under the first via is etched to form a second via, wherein the bottom metal is exposed through the second via. A conductive layer is formed in the second via and on the top surface of the dielectric stack. By using the above method for forming a semiconductor structure, the performance of the semiconductor structure can be improved.)

1. A method of forming a semiconductor structure, comprising:

forming a dielectric stack on the bottom metal;

forming a first masking layer over the dielectric stack, wherein the first masking layer has a plurality of first through holes, and a portion of the plurality of first through holes is located in a central portion of the first masking layer;

forming a second mask layer on the first mask layer and in the plurality of first through holes;

patterning the second masking layer to form an opening between a central portion and a peripheral portion of the second masking layer such that the second masking layer of the plurality of first vias below the opening is removed, wherein the central portion of the second masking layer covers the portion of the plurality of first vias and the central portion is surrounded by the peripheral portion;

etching the dielectric stack under the plurality of first vias to form second vias, wherein the bottom metal is exposed through the second vias; and

a conductive layer is formed in the second via and on a top surface of the dielectric stack.

2. The method of forming a semiconductor structure of claim 1, further comprising:

forming a metal layer on sidewalls of the second via and on the top surface of the dielectric stack prior to forming the conductive layer.

3. The method of forming a semiconductor structure of claim 2, further comprising:

forming the metal layer on a bottom surface of the second via such that the metal layer contacts the bottom metal.

4. The method of forming a semiconductor structure of claim 2, further comprising:

etching the metal layer on the top surface of the dielectric stack to form a third via.

5. The method of forming a semiconductor structure of claim 4, wherein a portion of the metal layer is etched such that the third via is directly connected to the second via.

6. The method of forming a semiconductor structure of claim 4, further comprising:

forming a top electrode in the third via.

7. The method of forming a semiconductor structure of claim 6, wherein the top electrode is formed in the third via such that the top electrode is electrically connected to the conductive layer.

8. The method of forming a semiconductor structure of claim 2, further comprising:

a first isolation layer is formed on the dielectric stack prior to forming the first masking layer.

9. The method of forming a semiconductor structure of claim 8, further comprising:

forming the second isolation layer on the first isolation layer such that the metal layer is located between the first isolation layer and the second isolation layer.

10. The method of forming a semiconductor structure of claim 1, further comprising:

removing an oxide layer of the dielectric stack prior to forming the conductive layer.

11. The method of forming a semiconductor structure of claim 1, further comprising:

forming a dielectric structure in the second via prior to forming the conductive layer such that the conductive layer in the second via is surrounded by the dielectric structure.

12. The method of claim 1, wherein the peripheral portion and the central portion of the second masking layer are made of a photoresist material.

13. The method of forming a semiconductor structure of claim 1, wherein the second masking layer is patterned such that the opening of the second masking layer is directly connected to the first via of the first masking layer.

14. The method of claim 1, wherein the second masking layer is patterned such that a width of the via of the second masking layer is greater than a width of the first via of the first masking layer.

Technical Field

The invention relates to a method for forming a semiconductor structure.

Background

With the rapid development of the electronic industry, the development of semiconductor devices has achieved high performance and miniaturization. The circuit design of Dynamic Random Access Memory (DRAM) requires a decoupling capacitor (decoupling capacitor) with a small capacitance. In particular, decoupling capacitors may be built into the chip to prevent voltage spikes in the power supply, for example when the chip is initially powered or when components of the chip are activated. However, the smaller capacitor array may cause a risk of collapse of the structure because the smaller capacitor array is independent (stod-alone) in the existing manufacturing method.

Disclosure of Invention

An aspect of the present invention is to provide a method of forming a semiconductor structure, by which performance of the semiconductor structure may be improved.

According to one embodiment of the present invention, a method of forming a semiconductor structure includes the following steps. A dielectric stack is formed on the bottom metal. A first masking layer is formed over the dielectric stack, wherein the first masking layer has a first via, a portion of the first via being located in a central portion of the first masking layer. A second mask layer is formed on the first mask layer and in the first via hole. The second mask layer is patterned to form an opening between a central portion and a peripheral portion of the second mask layer such that the second mask layer in the first via hole under the opening is removed, wherein the central portion of the second mask layer covers a portion of the first via hole and the central portion is surrounded by the peripheral portion. The dielectric stack under the first via is etched to form a second via, wherein the bottom metal is exposed through the second via. A conductive layer is formed in the second via and on the top surface of the dielectric stack.

In some embodiments of the present invention, the method of forming a semiconductor structure further comprises forming a metal layer on sidewalls of the second via and on a top surface of the dielectric stack prior to forming the conductive layer.

In some embodiments of the present invention, the method of forming a semiconductor structure further comprises forming a metal layer on a bottom surface of the second via such that the metal layer contacts the bottom metal.

In some embodiments of the present invention, the method of forming a semiconductor structure further comprises etching the metal layer on the top surface of the dielectric stack to form a third via.

In some embodiments of the invention, a portion of the metal layer is etched such that the third via is directly connected to the second via.

In some embodiments of the present invention, the method of forming a semiconductor structure further comprises forming a top electrode in the third via.

In some embodiments of the present invention, a top electrode is formed in the third via hole such that the top electrode is electrically connected to the conductive layer.

In some embodiments of the present invention, the method of forming a semiconductor structure further comprises forming a first isolation layer on the dielectric stack prior to forming the first masking layer.

In some embodiments of the present invention, the method of forming a semiconductor structure further comprises forming a second isolation layer on the first isolation layer such that the metal layer is between the first isolation layer and the second isolation layer.

In some embodiments of the present invention, the method of forming a semiconductor structure further comprises removing an oxide layer of the dielectric stack prior to forming the conductive layer.

In some embodiments of the present invention, the method of forming a semiconductor structure further comprises forming a dielectric structure in the second via prior to forming the conductive layer, such that the conductive layer in the second via is surrounded by the dielectric structure.

According to an embodiment of the present invention, the outer peripheral portion and the central portion of the second mask layer are made of a photoresist material.

According to an embodiment of the present invention, the second mask layer is patterned such that the opening of the second mask layer is directly connected to the first via hole of the first mask layer.

In some embodiments of the present invention, the second mask layer is patterned such that a width of the through hole of the second mask layer is greater than a width of the first through hole of the first mask layer.

In the foregoing embodiments, since the second mask layer is patterned to form openings at the central portion and the peripheral portion of the second mask layer, a smaller capacitor array (small-sized capacitor) can be realized and the risk of collapse can be avoided. Therefore, the performance of the semiconductor structure can be improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as claimed.

Drawings

Aspects of the invention can be understood from the following detailed description of embodiments and the accompanying drawings.

Fig. 1A and 1B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention.

Fig. 2A and 2B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention.

Fig. 3A and 3B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention.

Fig. 4A and 4B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention.

Fig. 5A and 5B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention.

Fig. 6A and 6B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with an embodiment of the present invention.

Fig. 7A and 7B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention.

Fig. 8A and 8B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with an embodiment of the present invention.

Fig. 9A and 9B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention.

Fig. 10A and 10B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with an embodiment of the present invention.

Description of the main reference numerals:

100-bottom metal, 110-dielectric stack, 112-first nitride layer, 113-first oxide layer, 114-second nitride layer, 115-second oxide layer, 120-first isolation layer, 130-first masking layer, 132-first via, 140-second masking layer, 142-first opening, 144-center portion, 146-peripheral portion, 148-second via, 150-metal layer, 152-bottom, 160-second isolation layer, 170-third masking layer, 172-second opening, 174-third via, 180-dielectric structure, 190-first conductive layer, 200-top electrode, 210-second conductive layer, R-recess, W1-width, W2-width, W3-width, W4-width, 1B-1B-line, 2B-2B-line, 3B-3B-line, 4B-4B-line, 5B-5B-line, 6B-6B-line, 7B-7B-line, 8B-8B-line, 9B-9B-line, 10B-10B-line.

Detailed Description

Reference will now be made to embodiments of the invention, examples of which are illustrated in the accompanying drawings. The present invention is described with reference to the drawings and specification, in which like reference numerals are used to refer to the same or similar parts throughout the several views.

Fig. 1A and 1B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention. FIG. 1B is a cross-sectional view taken along line 1B-1B of FIG. 1A. Referring to fig. 1A and 1B, a dielectric stack 110 is formed on a bottom metal 100. The dielectric stack 110 may include a plurality of nitride layers and a plurality of oxide layers alternately formed on the bottom metal 100. In detail, a first nitride layer 112, a first oxide layer 113, a second nitride layer 114, and a second oxide layer 115 are sequentially formed on the bottom metal 100. In some embodiments, the first nitride layer 112 contacts the bottom metal 100. In some embodiments, the bottom metal 100 may be considered a bottom electrode (bottom electrode) of a semiconductor structure.

After forming the dielectric stack 110 on the bottom metal 100, a first isolation layer 120 is formed on the dielectric stack 110. The first isolation layer 120 may be made of a nitride material. For example, the first isolation layer 120 may be made of silicon nitride or other suitable dielectric material. In some embodiments, the first isolation layer 120 may be formed by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable processes. In some embodiments, the first isolation layer 120 may be made of the same material as the first nitride layer 112 and the second nitride layer 114.

In some embodiments, the substrate may be formed prior to forming the bottom metal 100, with the bottom metal 100 being formed on the substrate. The substrate may be a silicon substrate. The aforementioned substrate may include other semiconductor elements, such as: germanium (germanium), or semiconductor compounds such as: silicon carbide (silicon carbide), gallium arsenide (gallium arsenic), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenic), and/or indium antimonide (indium antimonide), or other semiconductor alloys, such as: silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), indium aluminum arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide (GaInAsP), and any combination thereof.

Fig. 2A and 2B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention. Fig. 2B is a cross-sectional view along line 2B-2B of fig. 2A. Referring to fig. 2A and 2B, a first masking layer 130 is formed over the dielectric stack 110. The first mask layer 130 has a plurality of first through holes 132, and a portion of the first through holes 132 is located at a central portion of the first mask layer 130. In other words, the first mask layer 130 contacts the first isolation layer 120. The first via 132 exposes the underlying first isolation layer 120.

In some embodiments, the first mask layer 130 is made of a photoresist material or a multi-layer dielectric (multilayered) material. For example, the first mask layer 130 may be made of a black photoresist material or a multi-layer dielectric material, such as oxide-nitride-oxide (ONO). In some embodiments, the method of forming the first mask layer 130 may include forming a photoresist layer on the first isolation layer 120, and then patterning the photoresist layer by a photolithography process.

Fig. 3A and 3B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention. Fig. 3B is a cross-sectional view taken along line 3B-3B of fig. 3A. Referring to fig. 2A, 2B, 3A, and 3B, after forming the first masking layer 130 over the dielectric stack 110, a second masking layer 140 is formed over the first masking layer 130 and in the first via 132. In other words, the second mask layer 140 covers the first mask layer 130 and fills the first through hole 132.

After the second mask layer 140 is formed on the first mask layer 130 and in the first via hole 132, patterning is performed on the second mask layer 140 to form a first opening 142 between a central portion 144 and a peripheral portion 146 of the second mask layer 140, so that the second mask layer 140 in the first via hole 132 under the first opening 142 is removed. Accordingly, the structure of the first and second mask layers 130 and 140 facilitates formation of a small-sized capacitor in a subsequent process. That is, since the second mask layer 140 is filled in the first through hole 132 of the first mask layer 130, no through hole is formed at the position (the position where the second mask layer 140 is filled in the first through hole 132) in the subsequent process, which is helpful for avoiding the risk of collapse in the subsequent formation of the capacitor. By adjusting the size of the capacitor, a desired semiconductor structure design can be achieved.

In detail, the central portion 144 of the second mask layer 140 covers a portion of the first through hole 132 in the central portion of the first mask layer 130, and is surrounded by the peripheral portion 146. The central portion 144 of the second mask layer 140 is correspondingly disposed at the central portion of the first mask layer 130. For example, the central portion 144 of the second masking layer 140 is at the same vertical height as the central portion of the first masking layer 130.

In some embodiments, the second mask layer 140 is patterned such that the first opening 142 of the second mask layer 140 is directly connected to the first via 132 of the first mask layer 130. The first via 132 exposes the underlying first isolation layer 120. In some embodiments, the second masking layer 140 is patterned such that the width W2 of the first opening 142 of the second masking layer 140 is greater than the width W1 of the first via 132 of the first masking layer 130.

In some embodiments, as shown in FIG. 3B, the second mask layer 140 and the first mask layer 130 have a stepped profile. As shown in fig. 3A, the second mask layer 140 has a hollow-shaped (doughnut-shaped) pattern or a donut-shaped (donut-shaped) pattern. In some embodiments, the second mask layer 140 has a mesh-shaped pattern.

In some embodiments, central portion 144 and peripheral portion 146 of second masking layer 140 are light shielding (light shielding) portions. In some embodiments, the central portion 144 and the peripheral portion 146 of the second masking layer 140 may be made of a photoresist material or a multi-layer dielectric material. For example, the central portion 144 and the peripheral portion 146 of the second mask layer 140 may be made of a black photoresist material or a multi-layer dielectric material, such as oxide-nitride-oxide (ONO).

Fig. 4A and 4B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention. Fig. 4B is a cross-sectional view taken along line 4B-4B of fig. 4A. Referring to fig. 3A, 3B, 4A, and 4B, after patterning the second mask layer 140, the dielectric stack 110 under the first via 132 is etched to form a second via 148. In detail, the first isolation layer 120 and the dielectric stack 110 are etched using the first and second mask layers 130 and 140 as etching masks. The etching process deepens the first via 132 until the bottom metal 100 is reached to form a second via 148. The bottom metal 100 is exposed through the second via hole 148.

In some embodiments, the first and second masking layers 130, 140 are removed after etching the first isolation layer 120 and the dielectric stack 110.

In some embodiments, as shown in fig. 3B and 4B, the depth of the second via 148 is greater than the depth of the first via 132. In some embodiments, as shown in fig. 3B and 4B, the width W3 of the second via 148 is substantially the same as the width W1 of the first via 132.

Fig. 5A and 5B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention. Fig. 5B is a cross-sectional view taken along line 5B-5B of fig. 5A. Referring to fig. 5A and 5B, after forming the second via 148, a metal layer 150 is formed on the sidewalls and bottom surface of the second via 148 and the top surface of the dielectric stack 110. In other words, the metal layer 150 covers the bottom metal 100 and the first isolation layer 120. In some embodiments, the metal layer 150 contacts the bottom metal 100, the dielectric stack 110, and the first isolation layer 120.

Fig. 6A and 6B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with an embodiment of the present invention. Fig. 6B is a cross-sectional view taken along line 6B-6B of fig. 6A. Referring to fig. 6A and 6B, after the metal layer 150 is formed, a second isolation layer 160 is formed on the first isolation layer 120, such that the metal layer 150 is located between the first isolation layer 120 and the second isolation layer 160. In other words, the second isolation layer 160 covers the metal layer 150. The second isolation layer 160 contacts the metal layer 150 on the top surface of the dielectric stack 110.

In some embodiments, the second isolation layer 160 may be made of a nitride material. For example, the second isolation layer 160 may be made of silicon nitride or other suitable dielectric material. In some embodiments, the second isolation layer 160 can be formed by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable processes. In some embodiments, the second isolation layer 160 may be made of the same material as the first isolation layer 120.

Fig. 7A and 7B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention. Fig. 7B is a cross-sectional view taken along line 7B-7B of fig. 7A. Referring to fig. 7A and 7B, after forming the second isolation layer 160, a third mask layer 170 is formed on the second isolation layer 160. The third masking layer 170 has a second opening 172, and the second opening 172 exposes the underlying second isolation layer 160.

In some embodiments, the second opening 172 is aligned with the second through hole 148. The second opening 172 and the second via 148 are separated by a second isolation layer 160. In some embodiments, the width of the second opening 172 is greater than the width of the second through hole 148.

In some embodiments, the third mask layer 170 has a lattice-shaped pattern. In some embodiments, the third mask layer 170 is made of a photoresist material or a multi-layer dielectric material. For example, the third mask layer 170 is made of a black photoresist material or a multi-layer dielectric material, such as oxide-nitride-oxide (ONO). In some embodiments, the third mask layer 170 may be formed by a method including forming a photoresist layer and then patterning the photoresist layer by a photolithography process.

Fig. 8A and 8B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with an embodiment of the present invention. Fig. 8B is a cross-sectional view taken along line 8B-8B of fig. 8A. Referring to fig. 7A, 7B, 8A, and 8B, after forming the third masking layer 170, the metal layer 150 on the top surface of the dielectric stack 110 is etched to form a third via 174. In detail, the metal layer 150 and the second isolation layer 160 are etched using the third mask layer 170 as an etching mask. The etching process removes a portion of the metal layer 150 and a portion of the second isolation layer 160 such that the third via 174 is directly connected to the second via 148. The bottom 152 of the metal layer 150 is exposed through the second via 148.

In some embodiments, the third masking layer 170 is removed after etching the metal layer 150 and the second isolation layer 160.

In some embodiments, the width W4 of the third through-hole 174 is greater than the width W3 of the second through-hole 148. In some embodiments, the depth of the third through-hole 174 is less than the depth of the second through-hole 148.

Fig. 9A and 9B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with one embodiment of the present invention. Fig. 9B is a cross-sectional view taken along line 9B-9B of fig. 9A. Referring to fig. 8A, 8B, 9A and 9B, after the third via 174 is formed, the first oxide layer 113 and the second oxide layer 115 of the dielectric stack 110 are removed to form a recess R. In some embodiments, the recess R is directly connected to the third through-hole 174. The recess R is separated from the second via 148 by a metal layer 150.

Fig. 10A and 10B are top and cross-sectional views, respectively, of a semiconductor structure at a stage in accordance with an embodiment of the present invention. Fig. 10B is a cross-sectional view taken along line 10B-10B of fig. 10A. Referring to fig. 9A, 9B, 10A and 10B, after removing the first oxide layer 113 and the second oxide layer 115 of the dielectric stack 110, a dielectric structure 180 is formed in the recess R. In detail, the dielectric structure 180 is also formed on the top surface of the second isolation layer 160. The dielectric structure 180 contacts the first nitride layer 112, the second nitride layer 114, the first isolation layer 120, the metal layer 150, and the second isolation layer 160. In some embodiments, a dielectric structure 180 is formed in the second via 148. In some embodiments, the dielectric structure 180 may comprise a high-k dielectric material and titanium nitride (TiN).

After forming the dielectric structure 180, a first conductive layer 190 is formed in the second via 148 and on the top surface of the dielectric stack 110. A first conductive layer 190 is also formed on the top surface of the dielectric structure 180. In some embodiments, the first conductive layer 190 in the second via 148 is surrounded by the dielectric structure 180 in the second via 148. The metal layer 150, the dielectric structure 180 and the first conductive layer 190 in the second via 148 can be regarded as a capacitor.

In some embodiments, the first conductive layer 190 may be made of metal. In some embodiments, the first conductive layer 190 and the metal layer 150 may be made of the same material.

After the first conductive layer 190 is formed, the top electrode 200 is formed in the third via hole 174. In other words, the top electrode 200 is formed on the first conductive layer 190. In other words, the top electrode 200 is electrically connected to the first conductive layer 190. In some embodiments, the bottom surface of the top electrode 200 is lower than the bottom surface of the metal layer 150. In some embodiments, the top electrode 200 may be made of a polysilicon material.

After the top electrode 200 is formed, a second conductive layer 210 is formed on the top electrode 200. In some embodiments, the second conductive layer 210 contacts the top electrode 200. In some embodiments, the second conductive layer 210 may be made of a metal, such as tungsten (W).

As described above, since the second mask layer is patterned to form openings at the central portion and the peripheral portion of the second mask layer, a smaller capacitor array (small-sized capacitor) can be realized and the risk of collapse can be avoided. Therefore, the performance of the semiconductor structure can be improved.

Although the present invention has been described in detail with reference to the embodiments, other embodiments are possible and are not intended to limit the present invention. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

Various changes and substitutions may be made by one skilled in the art without departing from the spirit and scope of the invention, and it is intended that all such changes and substitutions be covered by the scope of the claims of the invention.