阅读说明：本技术 具有氧化中介层的半导体元件及其制备方法 (Semiconductor device with oxidation intermediate layer and preparation method thereof ) 是由 黄至伟 于 2020-11-10 设计创作，主要内容包括：本公开提供一种具有一氧化中介层的半导体元件及该半导体元件的制备方法。该半导体元件具有一基底、一存储单元以及一控制单元。该存储单元具有一存储单元导电层以及一横向氧化中介层,该存储单元导电层位于该基底上,该横向氧化中介层位于该存储单元导电层下。该控制单元位于该基底中,并位于该横向氧化中介层下。该横向氧化中介层具有一侧壁部以及一中心部,而相较于该中心部,该侧壁部具有一较高的氧浓度。(The present disclosure provides a semiconductor device having an oxidation interposer and a method for fabricating the semiconductor device. The semiconductor device has a substrate, a memory cell and a control unit. The memory cell has a memory cell conductive layer on the substrate and a lateral oxidation intermediate layer under the memory cell conductive layer. The control unit is located in the substrate and under the transverse oxidation intermediate layer. The lateral oxidation medium layer has a sidewall portion and a central portion, and the sidewall portion has a higher oxygen concentration than the central portion.)

1. A semiconductor component, comprising:

a substrate;

a memory cell comprising a memory cell conductive layer and a lateral oxidation interposer, the memory cell conductive layer being disposed on the substrate, the lateral oxidation interposer being disposed under the memory cell conductive layer; and

a control unit located in the substrate and under the transverse oxidation medium layer;

the lateral oxidation medium layer comprises a side wall part and a central part, and the side wall part has higher oxygen concentration relative to the central part.

2. The semiconductor device as claimed in claim 1, wherein the memory cell comprises a handle portion and a fork portion, the handle portion is disposed on the substrate, the fork portion is connected to the handle portion, the fork portion comprises the transverse oxidation medium layer and the memory cell conductive layer, and the control unit is disposed under the fork portion.

3. The semiconductor device as defined in claim 2, wherein the handle portion comprises the memory cell conductive layer and a tunnel isolation layer between the memory cell conductive layer and the substrate.

4. The semiconductor device as defined in claim 3, wherein the substrate comprises a first region and a second region, the second region being adjacent to the first region, the handle portion being located on the first region, and the fork portion being located on the second region.

5. The semiconductor device as claimed in claim 4, further comprising a plurality of doped regions in the first region of the substrate and disposed adjacent to sides of the tunneling isolation layer.

6. The semiconductor device as claimed in claim 5, further comprising a plurality of lightly doped regions in the second region of the substrate and disposed adjacent to sides of the lateral oxidation interposer.

7. The semiconductor device as claimed in claim 6, further comprising a plurality of diffusion regions in the second region of the substrate and between an adjacent pair of the lightly doped regions.

8. The semiconductor device as defined in claim 7, further comprising a first well region in the first region of the substrate, wherein the plurality of doped regions are in the first well region.

9. The semiconductor device as defined in claim 8, further comprising a second well region in the second region of the substrate and spaced apart from the first well region, wherein the control unit, the lightly doped regions and the diffusion regions are in the second well region.

10. The semiconductor device as claimed in claim 9, wherein the memory cell comprises a plurality of cell spacers bonded to the sidewall portion of the lateral oxidation interposer.

11. The semiconductor device of claim 10, further comprising a memory cell cap layer on said memory cell conductive layer.

12. The semiconductor device as claimed in claim 10, wherein the lateral oxidation interposer has a thickness betweenToIn the meantime.

13. The semiconductor device according to claim 10, wherein the tunnel isolation layer has a thickness different from a thickness of the lateral oxidation intermediate layer, and a material forming the tunnel isolation layer is different from a material forming the lateral oxidation intermediate layer.

14. The semiconductor device as claimed in claim 10, wherein the lateral oxidation interposer comprises a lower lateral oxidation interposer, a middle lateral oxidation interposer, and an upper lateral oxidation interposer, the lower lateral oxidation interposer being on the control unit, the middle lateral oxidation interposer being on the lower lateral oxidation interposer, and the upper lateral oxidation interposer being on the middle lateral oxidation interposer.

15. The semiconductor device as defined in claim 10, further comprising a selection unit on the substrate and adjacent to the memory cell.

16. The semiconductor device as defined in claim 15, wherein the select cell comprises a select cell isolation layer and a select cell conductive layer, the select cell isolation layer being located adjacent to the memory cell conductive layer, the select cell conductive layer being located on the select cell isolation layer.

17. A semiconductor component, comprising:

a substrate;

a memory cell comprising a memory cell conductive layer and a lateral oxidation interposer, the memory cell conductive layer being on the substrate, the lateral oxidation interposer being on the memory cell conductive layer; and

a control unit located on the transverse oxidation medium layer;

the lateral oxidation medium layer comprises a side wall part and a central part, and the side wall part has higher oxygen concentration relative to the central part.

18. The semiconductor device according to claim 17, further comprising a memory upper conductive layer on the control unit.

19. A method for manufacturing a semiconductor device includes:

providing a substrate;

forming a control unit in the substrate;

forming a memory cell comprising a lateral oxidation interposer and a memory cell conductive layer, the lateral oxidation interposer being on the control unit, the memory cell conductive layer being on the lateral oxidation interposer; and

performing a lateral oxidation process on the substrate, wherein a process temperature of the lateral oxidation process is between 300 ℃ and 600 ℃.

20. The method of claim 19, wherein a portion of the pressure of the oxygen in the lateral oxidation process is between 100mTorr and 20 atm.

Technical Field

The present disclosure claims priority and benefit of us official application No. 16/696,504, filed on 26.11.2019, the contents of which are incorporated herein by reference in their entirety.

Background

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually becoming smaller to meet the increasing demand for computing power. However, during the process of becoming smaller in size, there is a problem that the frequency is different from the increase in influence. Thus, there is a continuing challenge to achieve improved quality, yield, and reliability.

The above description of "prior art" is merely provided as background, and it is not an admission that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and that any description of "prior art" above should not be taken as an admission that it is any part of the present disclosure.

Disclosure of Invention

An embodiment of the present disclosure provides a semiconductor device, including a substrate; a memory cell comprising a memory cell conductive layer and a lateral oxidation interposer, the memory cell conductive layer being disposed on the substrate, the lateral oxidation interposer being disposed under the memory cell conductive layer; and a control unit in the substrate and under the transverse oxidation medium layer. The lateral oxidation medium layer includes a sidewall portion and a central portion, and the sidewall portion has a higher oxygen concentration relative to the central portion.

In some embodiments of the present disclosure, the memory cell includes a handle on the substrate and a fork connected to the handle, the fork including the transverse oxidation interposer and the memory cell conductive layer, and the control unit is under the fork.

In some embodiments of the present disclosure, the handle includes the memory cell conductive layer and a tunnel isolation layer between the memory cell conductive layer and the substrate.

In some embodiments of the present disclosure, the base includes a first region and a second region, the second region being adjacent to the first region, the handle being located on the first region, and the fork being located on the second region.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of doped regions in the first region of the substrate and disposed adjacent to sides of the tunneling isolation layer.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of lightly doped regions in the second region of the substrate and disposed adjacent to a side of the lateral oxidation interposer.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of diffusion regions in the second region of the substrate and between an adjacent pair of the lightly doped regions.

In some embodiments of the present disclosure, the semiconductor device further includes a first well region in the first region of the substrate, wherein the plurality of doped regions are in the first well region.

In some embodiments of the present disclosure, the semiconductor device further includes a second well region in the second region of the substrate and spaced apart from the first well region, wherein the control unit, the lightly doped regions and the diffusion regions are in the second well region.

In some embodiments of the present disclosure, the memory cell includes a plurality of memory cell spacers attached to the sidewall portion of the lateral oxidation interposer.

In some embodiments of the present disclosure, the semiconductor device further includes a memory cell cap layer on the memory cell conductive layer.

In some embodiments of the present disclosure, the lateral oxidation interposer has a thickness betweenToIn the meantime.

In some embodiments of the present disclosure, the tunnel isolation layer has a thickness different from a thickness of the lateral oxidation intermediate layer, and a material forming the tunnel isolation layer is different from a material forming the lateral oxidation intermediate layer.

In some embodiments of the present disclosure, the lateral oxidation interposer includes a lower lateral oxidation interposer located on the control unit, a middle lateral oxidation interposer located on the lower lateral oxidation interposer, and an upper lateral oxidation interposer located on the middle lateral oxidation interposer.

In some embodiments of the present disclosure, the semiconductor device further includes a selection unit located on the substrate and adjacent to the memory cell.

In some embodiments of the present disclosure, the select cell includes a select cell isolation layer located adjacent to the memory cell conductive layer and a select cell conductive layer located on the select cell isolation layer.

Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate; a memory cell comprising a memory cell conductive layer and a lateral oxidation interposer, the memory cell conductive layer being on the substrate, the lateral oxidation interposer being on the memory cell conductive layer; and a control unit located on the transverse oxidation medium layer. The lateral oxidation medium layer includes a sidewall portion and a central portion, and the sidewall portion has a higher oxygen concentration relative to the central portion.

In some embodiments of the present disclosure, the semiconductor device further includes a storage upper conductive layer on the control unit.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The preparation method comprises the following steps: providing a substrate; forming a control unit in the substrate; forming a memory cell comprising a lateral oxidation interposer and a memory cell conductive layer, the lateral oxidation interposer being on the control unit, the memory cell conductive layer being on the lateral oxidation interposer; and performing a lateral oxidation process on the substrate, wherein a process temperature of the lateral oxidation process is between 300 ℃ and 600 ℃.

In some embodiments of the present disclosure, a portion of the pressure of the oxygen of the lateral oxidation process is between 100mTorr to 20 atm.

Due to the design of the semiconductor device of the present disclosure, the dielectric constant of the lateral oxidation interposer may be increased. As a result, capacitive coupling between the control unit and the memory unit may be more effective. Therefore, the performance of the semiconductor device can be improved.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure will become more fully understood from the consideration of the following description and the appended claims, taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like elements.

Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1.

FIG. 3 is a schematic cross-sectional view taken along line B-B' of FIG. 1.

FIG. 4 is a cross-sectional view of a semiconductor device taken along line A-A' of FIG. 1 according to another embodiment of the present disclosure.

Fig. 5 to 7 are schematic cross-sectional views of semiconductor devices along the cross-sectional line B-B' of fig. 1 according to other embodiments of the present disclosure.

Fig. 8 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure.

Fig. 9 is a schematic cross-sectional view taken along line a-a' of fig. 8.

Fig. 10 is a schematic cross-sectional view taken along line B-B' of fig. 8.

Fig. 11 and 12 are schematic cross-sectional views of semiconductor devices along the cross-sectional line a-a' of fig. 8 according to other embodiments of the present disclosure.

Fig. 13 is a top view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 14 is a schematic cross-sectional view taken along line A-A' of FIG. 13.

Fig. 15 is a flow chart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 16 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure.

Fig. 17 is a schematic cross-sectional view taken along line a-a' of fig. 16.

FIG. 18 is a schematic cross-sectional view taken along section line B-B' of FIG. 16.

Fig. 19 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure.

FIG. 20 is a schematic cross-sectional view taken along line A-A' of FIG. 19.

FIG. 21 is a schematic cross-sectional view taken along section line B-B' of FIG. 19.

Fig. 22 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure.

FIG. 23 is a schematic cross-sectional view taken along line A-A' of FIG. 22.

FIG. 24 is a schematic cross-sectional view taken along section line B-B' of FIG. 22.

Fig. 25 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure.

FIG. 26 is a schematic cross-sectional view taken along line A-A' of FIG. 25.

FIG. 27 is a schematic cross-sectional view taken along section line B-B' of FIG. 25.

Fig. 28 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure.

FIG. 29 is a schematic cross-sectional view taken along section line A-A' of FIG. 28.

FIG. 30 is a schematic cross-sectional view taken along section line B-B' of FIG. 28.

Fig. 31 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure.

FIG. 32 is a schematic cross-sectional view taken along section line A-A' of FIG. 31.

FIG. 33 is a schematic cross-sectional view taken along section line B-B' of FIG. 31.

Fig. 34 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure.

FIG. 35 is a schematic cross-sectional view taken along line A-A' of FIG. 34.

FIG. 36 is a schematic cross-sectional view taken along section line B-B' of FIG. 34.

Description of reference numerals:

10: first region

10J: first region

20: second region

20J: second region

30: preparation method

100A: semiconductor device with a plurality of semiconductor chips

100B: semiconductor device with a plurality of semiconductor chips

100C: semiconductor device with a plurality of semiconductor chips

100D: semiconductor device with a plurality of semiconductor chips

100E: semiconductor device with a plurality of semiconductor chips

100F: semiconductor device with a plurality of semiconductor chips

100G: semiconductor device with a plurality of semiconductor chips

100H: semiconductor device with a plurality of semiconductor chips

100I: semiconductor device with a plurality of semiconductor chips

100J: semiconductor device with a plurality of semiconductor chips

101: substrate

101J: substrate

103: insulation structure

103J: insulation structure

105: passivation barrier layer

105J: passivation barrier layer

107: the first well region

107D: the first well region

107J: the first well region

109: second well region

109J: second well region

201: memory cell

201F: memory cell

201I: memory cell

201J: memory cell

203: handle part

203F: handle part

203I: handle part

203J: handle part

205: fork part

205F: fork part

205I-1: oar part

205J: fork part

207: tunneling isolation layer

207J: tunneling isolation layer

209: transverse oxidation interposer

209D: transverse oxidation interposer

209E: transverse oxidation interposer

209E-1: lower intervening barrier layer

209E-2: middle interposed isolation layer

209E-3: upper intervening isolation layer

209F: transverse oxidation interposer

209G: transverse oxidation interposer

209G-1: lower intervening barrier layer

209G-2: middle interposed isolation layer

209G-3: upper intervening isolation layer

209J: transverse oxidation interposer

211: memory cell conductive layer

211J: memory cell conductive layer

213 memory cell spacer

213C: memory cell spacer

213F: memory cell spacer

213J: memory cell spacer

215: memory cell capping layer

217: conductive layer on memory

219: side wall part

219D: side wall part

221: center part

221D: center part

301: first doped region

301J: first doped region

303: second doped region

303J: second doped region

305: a third doped region

305J: a third doped region

307: a fourth doped region

307H: a fourth doped region

401: selection unit

401J: selection unit

403: select cell isolation layer

403J: select cell isolation layer

405: selecting cell conductive layer

405J: selecting cell conductive layer

407: conductive layer on selection unit

407J: conductive layer on selection unit

409: selecting cell spacer

409J: selecting cell spacer

501: control unit

501F: control unit

501G: control unit

501J: control unit

503: lightly doped region

503J: lightly doped region

505: diffusion region

505J: diffusion region

507: adjusting layer

601: control contact

601J: control contact

603: doped region contact

603J: doped region contact

701: a first mask layer

703: lower isolation layer

705: lower conductive layer

707: a second mask layer

709: a third mask layer

711: a fourth mask layer

S11: step (ii) of

S13: step (ii) of

S15: step (ii) of

S17: step (ii) of

S19: step (ii) of

X: direction of rotation

Y: direction of rotation

Z: direction of rotation

Detailed Description

Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these examples are merely illustrative and are not intended to limit the scope of the present disclosure. For example, the formation of a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed intermediate the first and second features such that the first and second features may not be in direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. These repetitions are for simplicity and clarity and do not, in themselves, represent a particular relationship between the various embodiments and/or configurations discussed, unless specifically stated in the context.

Furthermore, for ease of description, spatially relative terms such as "below", "lower", "above", "upper", and the like may be used herein to describe one element or feature's relationship to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

It will be understood that forming one element over (on), connecting to (connecting to), and/or coupling to (connecting to) another element may include embodiments in which the elements are formed in direct contact, and may also include embodiments in which additional elements are formed between the elements such that the elements are not in direct contact.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

Unless otherwise indicated in the context, when representing orientation (orientation), layout (layout), location (location), shape (shapes), size (sizes), quantity (amounts), or other measurements (measures), then terms (terms), such as "same", "equal", "flat", or "coplanar", as used herein, do not necessarily mean an exactly identical orientation, layout, location, shape, size, quantity, or other measurement, but mean that within an acceptable difference, including, by way of example, an almost identical orientation, layout, location, shape, size, quantity, or other measurement, the acceptable difference may occur as a result of manufacturing processes. The term "substantially" may be used herein to convey this meaning. Such as, for example, substantially identical (substitionally the same), substantially equal (substitionally equivalent), or substantially flat (substitional planar), exactly identical, equal, or flat, or they may be identical, equal, or flat within acceptable differences that may occur, for example, as a result of a manufacturing process.

In the present disclosure, a semiconductor device generally means a device that can operate by utilizing semiconductor characteristics (semiconductor characteristics), and an electro-optical device (electro-optical device), a light-emitting display device (light-emitting display device), a semiconductor circuit (semiconductor circuit), and an electronic device (electronic device) are included in the scope of the semiconductor device.

It should be understood that in the description of the present disclosure, the upper (above) is the direction corresponding to the Z-direction arrow, and the lower (below) is the opposite direction corresponding to the Z-direction arrow.

Fig. 1 is a schematic top view of a semiconductor device 100A according to an embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1. FIG. 3 is a schematic cross-sectional view taken along line B-B' of FIG. 1.

Referring to fig. 1 to fig. 3, in the embodiment, the semiconductor device 100A may include a substrate 101, an insulating structure 103, a passivation isolation layer 105, a plurality of doped regions, a selection unit 401, a control unit 501, a plurality of lightly doped regions 503, a plurality of diffusion regions 505, a plurality of control contacts 601, and a plurality of doped region contacts 603.

Referring to fig. 1 to 3, in the embodiment, the substrate 101 may include a first region 10 and a second region 20. The second zone 20 may be disposed adjacent to the first zone 10. For example, the substrate 101 may be formed of the following materials: silicon, doped silicon, germanium, silicon germanium (silicon carbide), silicon carbide (silicon carbon), silicon germanium carbide (silicon germanium carbon), gallium arsenide (gallium arsenide), indium arsenide (indium arsenide), indium phosphide (indium phosphide), or other group IV, group III, or group II-VI semiconductor materials. In the present embodiment, the substrate 101 may be formed of doped silicon and has a first electrical type (electrical type). The substrate 101 may be doped with a dopant, such as boron (boron).

It should be understood that the first region 10 may include a portion of the substrate 101 and a space on the portion of the substrate 101. Describing a feature disposed on the first region 10 means that the feature is disposed on a top surface of the portion of the substrate 101. It is described that a component is provided in the first region 10, meaning that the component is provided in the portion of the substrate 101; however, a top surface of the feature may be flush with the top surface of the portion of the substrate 101. Describing a feature disposed over the first region 10 means that the feature is disposed over the top surface of the portion of the substrate 101. Accordingly, the second region 20 may include other portions of the substrate 101 and a space on the other portions of the substrate 101.

Referring to fig. 1 to 3, in the illustrated embodiment, the first well region 107 may be disposed in the first region 10 of the substrate 101. The first well region 107 may be doped with a dopant, such as phosphorus, arsenic or antimony, and have a second electrical type. The second well region 109 may be spaced apart from the first well region 107 and may be disposed in the second region 20 of the substrate 101. The second well 109 may be doped with a dopant, such as phosphorus, arsenic or antimony, and has a second electrical type.

Referring to fig. 1 to 3, in the embodiment, the insulating structure 103 may be disposed in the first region 10 and the second region 20 of the substrate 101. The insulating structure 103 may confine a portion of the second well region 109, and the portion of the second well region 109 may be considered as the control unit 501. In other words, the control unit 501 may be defined by the insulating structure 103, and the insulating structure 103 is located in the second region 20 of the substrate 101. For example, the insulating structure 103 may be made of an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluorine-doped silicon (fluorine-doped silicon).

It should be understood that in the present disclosure, silicon oxynitride refers to a material that contains silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon oxynitride refers to a material that contains silicon, nitrogen, and oxygen, where the proportion of nitrogen is greater than the proportion of oxygen.

Referring to fig. 1 to 3, in the embodiment, the memory cell 201 may be disposed in the first region 10 and the second region 20 of the substrate 101. The memory cell 201 may have a stem 203, a fork 205, a tunnel isolation layer 207, a lateral oxidation interposer 209, a memory cell conductive layer 211, and a plurality of memory cell spacers 213.

Referring to fig. 1 to 3, in the embodiment, the handle 203 may be disposed on the first region 10 of the substrate 101. The handle 203 may have a tunneling isolation layer 207 and a memory cell conductive layer 211. In particular, a portion of the memory cell conductive layer 211 disposed on the first region 10 and the tunneling isolation layer 207 together form the handle 203 of the memory cell 201.

Referring to fig. 1 to 3, in the embodiment, the fork 205 may be disposed on the second region 20 of the substrate 101. From a top view, one end of the fork 205 may be connected to the handle 203. An opposite end of the fork 205 may be split into four segments (segments) that extend in a direction relative to the handle 203 and along a first direction Y. Accordingly, four corresponding sections of the fork 205 are shown in the cross-sectional view of fig. 3. The fork 205 may include a lateral oxidation interposer 209 and a memory cell conductive layer 211. In particular, a portion of the memory cell conductive layer 211 disposed on the second region 20 forms a fork 205 with the lateral oxidation interposer 209.

Referring to fig. 1 to 3, in the embodiment, the tunneling isolation layer 207 may be disposed on the first region 10 of the substrate 101. The tunnel isolation layer 207 may have a thickness betweenToIn the meantime. For example, the tunnel isolation layer 207 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof. In the present embodiment, the oxygen concentration at the sidewalls of the tunnel isolation layer 207 may be equal to the oxygen concentration at the center of the tunnel isolation layer 207. Alternatively, in another embodiment, the oxygen concentration at the sidewalls of the tunnel isolation layer 207 may be greater than the oxygen concentration at the center of the tunnel isolation layer 207.

Referring to fig. 1 to 3, in the embodiment, the lateral oxidation interposer 209 may be disposed on the second region 20 of the substrate 101. The lateral oxidation interposer 209 may have a thickness different from the thickness of the tunnel isolation layer 207. The lateral oxidation interposer 209 may have a thickness betweenToIn the meantime. The lateral oxidation interposer 209 is formed of a material different from the material forming the tunnel isolation layer 207. For example, the lateral oxidation interposer 209 may be made of an isolation material having a dielectric constant of about 4.0 or greater. (unless otherwise indicated, all dielectric constants mentioned herein are relative to a vacuum.) the barrier material having a dielectric constant of about 4.0 or greater can be hafnium oxide (hafnium oxide), zirconium oxide (zirconia oxide), aluminum oxide (aluminum oxide), titanium oxide (titanium oxide), lanthanum oxide (lanthanum oxide), titanium strontium titanate (strontium titanate), lanthanum aluminate (lanthanum aluminate), yttrium oxide (yttrium oxide), germanium oxide (gallium (iii) trioxide), gadolinium gallium oxide (gadolinium gallium titanate), lead zirconate titanate (lead zirconate titanate), barium strontium titanate (barium titanate), or mixtures thereof. The oxygen concentration at the sidewall portions 219 of the lateral oxidation interposer 209 may be higher than the oxygen concentration at the center portion 221 of the lateral oxidation interposer 209.

Alternatively, in another embodiment, the lateral oxidation interposer 209 may have the same thickness as the tunneling isolation layer 207. The lateral oxidation interposer 209 may be made of the same material as the tunneling isolation layer 207. The tunnel isolation layer 207 and the lateral oxidation interposer 209 may have been formed in the same semiconductor process at the same time.

Referring to fig. 1 to 3, in the embodiment, the memory cell conductive layer 211 may be disposed over the first region 10 and the second region 20 of the substrate 101. The memory cell conductive layer 211 may be disposed on the tunnel isolation layer 207 and the lateral oxidation interposer 209, respectively. For example, the memory cell conductive layer 211 may be made of polysilicon or polycrystalline silicon-germanium (polysilicon-germanium).

Referring to fig. 1 to 3, in the embodiment, a plurality of memory cell spacers 213 may be disposed on the first region 10 and the second region 20 of the substrate 101. A plurality of memory cell spacers 213 may be attached to the sidewalls of the tunnel isolation layer 207, the sidewalls of the lateral oxidation interposer 209, and the sidewalls of the memory cell conductive layer 211. For example, the plurality of memory cell spacers 213 may be made of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide.

Referring to fig. 1 to 3, in the embodiment, the selection unit 401 may be disposed on the first region 10 and the second region 20 of the substrate 101. The selection unit 401 may be spaced apart from the memory cell 201 along a second direction X, which is perpendicular to the first direction Y. The select cell 401 may have a select cell isolation layer 403, a select cell conductive layer 405, a select cell top conductive layer 407, and a plurality of select cell spacers 409.

Referring to fig. 1 to 3, in the embodiment, the select cell isolation layer 403 may be disposed on the first region 10 and the second region 20 of the substrate 101. The select cell isolation layer 403 may have a well betweenToIn the meantime. It should be understood that the thickness of the select cell isolation layer 403 may be set within an arbitrary range depending on the circumstances. For example, the select cell isolation layer 403 may be made of an isolation material having a dielectric constant of 4.0 or more. Alternatively, in another embodiment, the isolation material may be silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. The select cell conductive layer 405 may be disposed over the first and second regions 10 and 20 of the substrate 101. A select cell conductive layer 405 may be disposed on the select cell isolation layer 403. The select cell conductive layer 405 may have a thickness between 150nm to 300 nm. For example, the select cell conductive layer 405 may be made of doped polysilicon.

Referring to fig. 1 to 3, in the embodiment, the conductive layer 407 on the selection unit may be disposed above the first region 10 and the second region 20 of the substrate 101. A select cell upper conductive layer 407 may be disposed on the select cell conductive layer 405. For example, the select cell upper conductive layer 407 may be made of a metal silicide. The metal silicide may be nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. A plurality of select cell spacers 409 may be attached to sidewalls of the select cell isolation layers 403 and sidewalls of the select cell conductive layers 405. For example, the plurality of select cell spacers 409 may be made of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide.

Referring to FIGS. 1 to 3, in the illustrated embodiment, a plurality of doped regions may be disposed in the first well region 107. The doped regions may be doped with a dopant (dopant), such as phosphorus, and have a first electrical type. The plurality of doped regions may include a first doped region 301, a second doped region 303, and a third doped region 305.

Referring to fig. 1 to 3, in the illustrated embodiment, the first doped region 301 may be disposed in the first well region 107 and adjacent to one side of the tunneling isolation layer 207. A portion of a top surface of the first doped region 301 may contact a bottom of the tunneling isolation layer 207. A second doped region 303 may be disposed in the first well region 107 and adjacent to an opposite side of the tunneling isolation layer 207. One side of the second doped region 303 may contact the bottom of the tunneling isolation layer 207. An opposite side of the second doped region 303 may be disposed adjacent to one side of the selection cell isolation layer 403. A third doped region 305 may be disposed in the first well region 107 and adjacent to an opposite side of the select cell isolation layer 403.

Referring to fig. 1 to fig. 3, in the embodiment, the control unit 501 may be disposed in the second well 109. The control unit 501 may be disposed apart from the plurality of doped regions with the insulating structure 103 and the substrate 101 having the first electrical type interposed therebetween. The control unit 501, which is disposed in a well different from the doped regions, can prevent the leakage current from affecting the doped regions when an external voltage source is applied. The control unit 501 may be disposed under the lateral oxidation interposer 209. In other words, the control unit 501 may be disposed at the opposite memory cell conductive layer 211 with the lateral oxidation interposer 209 interposed therebetween. From a top view, a ratio of an area of the fork 205 overlapping the control unit 501 to a surface area of the control unit 501 may be between 20% and 60%. Due to the presence of the lateral oxidation interposer 209, although the control unit 501 only partially overlaps the memory cell 201, the control unit 501 can still generate effective capacitive coupling with the memory cell 211 when an external voltage source is provided.

Referring to fig. 1 to 3, in the embodiment, a plurality of lightly doped regions 503 may be disposed in the second region 20 of the substrate 101. A plurality of lightly doped regions 503 may be disposed in the second well region 109 and adjacent to the sides of the lateral oxidation interposer 209. In particular, from a cross-sectional view, a plurality of lightly doped regions 503 may be respectively disposed between adjacent pairs (pairs) of four sections of the fork 205. The top surfaces of the lightly doped regions 503 may contact portions of a bottom portion of the lateral oxidation interposer 209. The lightly doped regions 503 may be doped with a dopant, such as phosphorus, arsenic, or antimony, and have a second electrical type. The lightly doped regions 503 may have a doping concentration greater than that of the second well 109 or the control unit 501. The lightly doped regions 503 may be electrically connected to the control unit 501.

Referring to fig. 1 to 3, in the embodiment, a plurality of diffusion regions 505 may be disposed in the second region 20 of the substrate 101. A plurality of diffusion regions 505 may be disposed in the second well region 109 between adjacent pairs (pairs) of four segments of the fork 205. In particular, a plurality of diffusion regions 505 may be disposed between adjacent pairs (pairs) of the plurality of lightly doped regions 503. Portions of the top surfaces of the plurality of diffusion regions 505 may contact portions of the bottoms of the plurality of memory cell spacers 213. The plurality of diffusion regions 505 may be doped with a dopant, such as phosphorus, arsenic, or antimony, and have a second electrical type. The plurality of diffusion regions 505 may have a doping concentration greater than the doping concentration of the plurality of lightly doped regions 503. The plurality of diffusion regions 505 may be electrically coupled to the plurality of lightly doped regions 503 and the control unit 501.

Referring to fig. 1 to 3, in the embodiment, a passivation isolation layer 105 may be disposed on the substrate 101. The passivation isolation layer 105 may cover the memory cell 201 and the selection cell 401. For example, the passivation isolation layer 105 may be made of the following materials: silicon nitride, silicon oxide, silicon oxynitride, flowable oxide (flowable oxide), a fire-resistant silazane (silicone tile), undoped silicate glass (undoped silicate glass), borosilicate glass (borosilicate glass), phosphosilicate glass (phosphosilicate glass), borophosphosilicate glass (borophosphosilicate glass), plasma-enhanced tetraethoxysilane (plasma enhanced tetra ethyl silicate), fluorosilicate glass (fluoride silicate), carbon-doped silicon oxide (carbon-doped silicon oxide), xerogel (xerogel), aerogel (aerogel), amorphous fluorinated carbon (amorphous fluorinated carbon), organic silicate glass (organic silicate glass), parylene (para-xylene), bis-benzocyclobutene (benzocyclobutene-styrene), polyimide (polyimide), polymeric materials or combinations thereof.

Referring to fig. 1 to 3, in the embodiment, a plurality of control contacts 601 may be disposed on the second region 20 of the substrate 101. The plurality of control contacts 601 may pass through the plurality of control contacts 601 and may be electrically coupled to the plurality of diffusion regions 505. For example, the plurality of control contacts 601 may be made of doped polysilicon, metal nitride, or metal silicide. The metal may be aluminum, copper, tungsten, or cobalt. A voltage may be applied to the control unit 501 via a plurality of control contacts 505, a plurality of diffusion regions 505, and a plurality of lightly doped regions 503. A plurality of doped region contacts 603 may be disposed on the first region 10 of the substrate 101. The plurality of doped region contacts 603 may pass through the passivation isolation layer 105 and may be electrically coupled to the plurality of doped regions. For example, the plurality of doped region contacts 603 may be made of doped polysilicon, metal nitride, or metal silicide.

In the semiconductor device 100A, electrons (electrons) can be transported to the memory cell conductive layer 211 through the tunneling isolation layer 207 by hot electron injection (hot electron injection) or Fowler-Nordheim tunneling (Fowler-Nordheim tunneling). In other electron transfer mechanisms, a voltage potential may be applied to the memory cell conductive layer 211 by capacitive coupling of the control unit 501. When a voltage source providing a voltage potential is applied to the control unit 501, the control unit 501 may be capacitively coupled to the memory cell conductive layer 211 through the lateral oxidation interposer 209. Due to the presence of the lateral oxidation interposer 209, and the higher oxygen concentration at the sidewall portion of the lateral oxidation interposer 209, the capacitive coupling between the control unit 501 and the memory cell conductive layer 211 can be more efficient. As a result, electron transfer (electron transfer) of the semiconductor element 100A can be improved. In other words, the performance of the semiconductor device 100A may be improved.

Fig. 4 is a schematic cross-sectional view of a semiconductor device 100B along the line a-a' of fig. 1 according to another embodiment of the present disclosure. Fig. 5 to 7 are schematic cross-sectional views of semiconductor devices 100C, 100D, 100E along the cross-sectional line B-B' of fig. 1 according to other embodiments of the present disclosure.

Referring to fig. 4, the semiconductor device 100B may have a fourth doped region 307. The fourth doped region 307 may be disposed in the second doped region 303. The fourth doped region 307 may be doped with a dopant, such as boron. The fourth doping region 307 may have a doping concentration greater than that of the second doping region 303.

Referring to fig. 5, the semiconductor device 100C may have a memory cell cap layer 215. A memory cell capping layer 215 may be disposed on the memory cell conductive layer 211. For example, the memory cell cap layer 215 may be made of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. A plurality of memory cell spacers 213C may be attached to sidewalls of the memory cell cap layer 215.

Referring to fig. 6, in the semiconductor device 100D, oxygen (oxygen) at the sidewall 219D of the lateral oxidation interposer 209D may diffuse to the center of the lateral oxidation interposer 209D. The lateral oxidation interposer 209D may be fully oxidized. The oxygen concentration at the sidewall portions 219D of the lateral oxidation interposer 209D and the oxygen concentration at the center portion 221D of the lateral oxidation interposer 209D may be approximately the same. The lateral oxidation interposer 209D in FIG. 6 may have a dielectric constant that is greater than the dielectric constant of the lateral oxidation interposer 209 in FIG. 3.

Referring to FIG. 7, in the semiconductor device 100E, the lateral oxidation interposer 209E may have a lower intervening isolation layer 209E-1, an intervening isolation layer 209E-2, and an upper intervening isolation layer 209E-3. A lower intervening isolation layer 209E-1 may be provided on the control unit 501. An intermediate intervening isolation layer 209E-2 may be disposed on the lower intervening isolation layer 209E-1 and an upper intervening isolation layer 209E-3 may be disposed on the intermediate intervening isolation layer 209E-2. For example, the lower intervening isolation layer 209E-1 and the upper intervening isolation layer 209E-3 may be made of silicon nitride. The oxygen concentration at the sidewall portions of the lower intervening spacer 209E-1 and the upper intervening spacer 209E-3 is greater than the oxygen concentration at the center portions of the lower intervening spacer 209E-1 and the upper intervening spacer 209E-3. For example, the oxide layer may be made of silicon oxide, aluminum oxide, hafnium oxide (hafnium oxide), zirconium oxide (zirconia oxide), or a combination thereof.

Fig. 8 is a schematic top view of a semiconductor device 100F according to an embodiment of the present disclosure. Fig. 9 is a schematic cross-sectional view taken along line a-a' of fig. 8. Fig. 10 is a schematic cross-sectional view taken along line B-B' of fig. 8.

Referring to FIGS. 8-10, the first well region 107F may be disposed in the first region 10 and the second region 20 of the substrate 101. The lateral oxidation interposer 209F may be disposed over the first region 10 and the second region 20 of the substrate 101. A lateral oxidation interposer 209F may be disposed on the memory cell conductive layer 211. The control unit 501F may be disposed over the first and second regions 10 and 20 of the substrate 101. The control unit 501F may be disposed on the lateral oxidation interposer 209F. For example, the control unit 501F may be made of polysilicon or polycrystalline silicon germanium. A storage upper conductive layer 217 may be disposed over the first region 10 and the second region 20 of the substrate 101. The storage upper conductive layer 217 may be disposed on the control unit 501F. For example, the storage upper conductive layer 217 may be made of a metal silicide.

Referring to fig. 8 to 10, a plurality of memory cell spacers 213F may be attached to the sidewalls of the control unit 501F, the sidewall of the lateral oxidation interposer 209F, the sidewalls of the memory cell conductive layers 211, and the sidewalls of the tunneling isolation layer 207. The tunneling isolation layer 207, the memory cell conductive layer 211, the lateral oxidation interposer 209F, the control unit 501F, the plurality of memory cell spacers 213F, and the memory top conductive layer 217 together form the stem 203F and the fork 205F of the memory cell 201F.

Fig. 11 and 12 are schematic cross-sectional views of semiconductor devices 100G and 100H along the line a-a' of fig. 8 according to other embodiments of the present disclosure.

Referring to fig. 11, in the semiconductor device 100G, the lateral oxidation interposer 209G may have a lower intervening isolation layer 209G-1, an intervening isolation layer 209G-2, and an upper intervening isolation layer 209G-3. A lower intervening isolation layer 209G-1 may be disposed on the memory cell conductive layer 211. An intervening isolation layer 209G-2 may be disposed on the lower intervening isolation layer 209G-1. An upper intervening isolation layer 209G-3 may be disposed on the intervening isolation layer 209G-2. The control unit 501G is disposed on the upper intervening isolation layer 209G-3.

Referring to fig. 12, the semiconductor device 100H may have a fourth doped region 307H. The fourth doped region 307H may be disposed in the second doped region 303. The fourth doped region 307H may be doped with a dopant, such as boron. The doping concentration of the fourth doping region 307H may be higher than the doping concentration of the second doping region 303.

Fig. 13 is a schematic top view of a semiconductor device 100I according to an embodiment of the present disclosure. FIG. 14 is a schematic cross-sectional view taken along line A-A' of FIG. 13.

Referring to fig. 13 and 14, in the semiconductor device 100I, the memory cell 201I may have a handle portion 203I and a paddle portion 205I-1. The paddle portion 205I-1 may be disposed on the second region 20 of the substrate 101. The paddle portion 205I-1 may have a rectangular shape in a top view. The control unit 501I is disposed in the second well 109 and may be surrounded by the isolation structure 103. A tuning layer 507 may be disposed in the second well 109 and under the control unit 501I. The adjustment layer 507 may be doped with a dopant, such as phosphorus, arsenic or antimony, and may have a second electrical type. The adjusting layer 507 may assist in adjusting a threshold voltage (threshold voltage) of the control unit 501. From a top view, the ratio of a surface area of the control unit 501I to a surface area of the paddle 205I-1 may be greater than or equal to 90%.

Fig. 15 is a flow chart illustrating a method 30 for fabricating a semiconductor device 100J according to an embodiment of the present disclosure. Fig. 16 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure. Fig. 17 is a schematic cross-sectional view taken along line a-a' of fig. 16. FIG. 18 is a schematic cross-sectional view taken along section line B-B' of FIG. 16.

Referring to FIGS. 15-18, in step S11, in the illustrated embodiment, a substrate 101J may be provided, a first well region 107J, a second well region 109J, and an isolation structure 103J may be formed in the substrate 101J, and a control unit 501J may be defined in the second well region 109J by the isolation structure 103J. The substrate 101J may have a first region 10J and a second region 20J, the second region 20J being disposed adjacent to the first region 10J. The first well region 107J and the second well region 109J may be formed in the first region 10J and the second region 20J, respectively, by a single step implantation (implantation) process or a multi-step implantation process. The insulating structure 103J may be formed in the first region 10J and the second region 20J, and may constrain a portion of the second well region 109J to form the control unit 501J.

Fig. 19 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure. FIG. 20 is a schematic cross-sectional view taken along line A-A' of FIG. 19. FIG. 21 is a schematic cross-sectional view taken along section line B-B' of FIG. 19. Fig. 22 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure. FIG. 23 is a schematic cross-sectional view taken along line A-A' of FIG. 22. FIG. 24 is a schematic cross-sectional view taken along section line B-B' of FIG. 22. Fig. 25 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure. FIG. 26 is a schematic cross-sectional view taken along line A-A' of FIG. 25. FIG. 27 is a schematic cross-sectional view taken along section line B-B' of FIG. 25.

Referring to fig. 15 and 19 through 27, in step S13, in the embodiment, a memory cell 201J and a select cell 401J may be formed on a substrate 101J, and a plurality of doped regions, a plurality of lightly doped regions 503J and a plurality of diffusion regions 505J may be formed in the substrate 101J. Referring to fig. 19 to 21, a lower isolation layer 703 and a lower conductive layer 705 may be sequentially deposited on the substrate 101. For example, the lower isolation layer 703 may be made of an isolation material having a dielectric constant of about 4.0 or greater. Alternatively, in other embodiments, the isolation material may be silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. For example, the lower conductive layer 705 may be made of polysilicon or polycrystalline silicon germanium. A photolithography process may be performed and a first mask layer 701 may be used to define the locations of the memory cell 201J and the select cell 401J.

Referring to fig. 22 to 24, after the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to remove portions of the lower conductive layer 705 and the lower isolation layer 703, thereby forming a stem portion 203J and a fork portion 205J of the memory cell 201J and the selection unit 401J. After the etching process, the lower isolation layer 703 can be transformed into a tunnel isolation layer 207J on the first region 10J, a lateral oxidation interposer 209J on the second region 20J, and a select cell isolation layer 403J on the first region 10J and the second region 20J. The bottom conductive layer 705 can be transformed into a memory cell conductive layer 211J on the tunnel isolation layer 207J and on the lateral oxidation interposer 209J; while other portions of the lower conductive layer 705 may be converted into a selected cell conductive layer 405J over the selected cell isolation layer 403J. The tunneling isolation layer 207J forms the stem 203J together with the memory cell conductive layer 211J. The lateral oxidation interposer 209J forms a fork 205J together with the memory cell conductive layer 211J. The selection cell isolation layer 403J forms a selection cell 401J together with a selection cell conductive layer 405J.

Referring to fig. 22 to 24, a second mask layer 707 may be patterned to mask the first region 10J. An angled implantation process may be performed to form a plurality of lightly doped regions 503J in the second well 109J. Next, an implantation process may be performed to form a plurality of diffusion regions 505J in the second well 109J and between adjacent pairs (pairs) of the plurality of lightly doped regions 503J. After the plurality of diffusion layers 505J are formed, the second masking layer 707 may be removed.

Referring to fig. 25 to 27, a third masking layer 709 may be patterned to mask the second region 20J. An implantation process may be performed to form a plurality of doped regions in the first well region 107J. The doped regions may have a first doped region 301J, a second doped region 303J, and a third doped region 305J. The first doped region 301J and the second doped region 303J may be formed adjacent to the sidewall of the tunneling isolation layer 207J, respectively. The second doped region 303J may be formed between the tunnel isolation layer 207J and the select cell isolation layer 403J. A third doped region 305J may be formed at a sidewall opposite to the second doped region 303J and adjacent to the selection cell isolation layer 403J. After the implantation process, the third masking layer 709 may be removed.

Fig. 28 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure. FIG. 29 is a schematic cross-sectional view taken along section line A-A' of FIG. 28. FIG. 30 is a schematic cross-sectional view taken along section line B-B' of FIG. 28.

Referring to fig. 15 and 28 to 30, in step S15, in the embodiment, a lateral oxidation process may be performed on the substrate 101J to oxidize the lateral oxidation interposer 209J and the tunnel isolation layer 207J. During the lateral oxidation process, the intermediate semiconductor element may be placed in an oxidizing ambient having a plurality of oxidizing species (shown as small circles in fig. 29 and 30). The oxide species may diffuse from the sidewalls thereof into the tunnel isolation layer 207J and the lateral oxidation interposer 209J and fill oxygen vacancies (oxygen vacancies) in the tunnel isolation layer 207J and the lateral oxidation interposer 209J. A process temperature of the lateral oxidation process may be between 300 ℃ and 600 ℃. Preferably, the process temperature of the lateral oxidation process may be between 400 ℃ and 500 ℃. A portion of the pressure of the oxygen of the lateral oxidation process may be between 100mTorr to 20 atm. Preferably, a portion of the pressure of oxygen of the lateral oxidation process may be between 0.1atm and 1.0 atm. A period of the lateral oxidation process may be between 10 minutes and 6 hours. After the lateral oxidation process, the threshold voltage of the tunnel isolation layer 207J and the lateral oxidation interposer 209J may be increased. The oxidizing species may be an oxygen-containing molecule, such as molecular oxygen, water vapor (water vapor), nitric oxide (nitrooxide), or nitrous oxide (nitrous oxide). The process temperature of the lateral oxidation process, the partial pressure of oxygen of the lateral oxidation process, and the duration of the lateral oxidation process may together determine the oxidation degree (extension) of the tunnel isolation layer 207J and the lateral oxidation interposer 209J.

After the lateral oxidation process, the oxygen concentration at the sidewall portions of the lateral oxidation interposer 209J and the tunnel isolation layer 207J may be greater than the oxygen concentration at the center portions of the lateral oxidation interposer 209J and the tunnel isolation layer 207J. It should be understood that other partial pressures of oxygen for the lateral oxidation process may be applied, and that other partial pressures of oxygen for the lateral oxidation process may be greater or less than the partial pressure of oxygen for the lateral oxidation process described previously. Other periods of the lateral oxidation process may be applied, which may be greater or less than the preceding periods of the lateral oxidation process. Generally, the duration of the lateral oxidation process may decrease as one of a process temperature of the lateral oxidation process or a partial pressure of the lateral oxidation process increases. Alternatively, in other embodiments, the oxygen concentration may be increased at both the sidewall and center portions of the tunnel isolation layer 207J and at both the sidewall and center portions of the lateral oxidation interposer 209J when a longer duration of the lateral oxidation process is provided. The oxygen concentration at the sidewall portion of the lateral oxidation interposer 209J may be equal to the oxygen concentration at the center portion of the lateral oxidation interposer 209J.

Fig. 31 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure. FIG. 32 is a schematic cross-sectional view taken along section line A-A' of FIG. 31. FIG. 33 is a schematic cross-sectional view taken along section line B-B' of FIG. 31.

Referring to fig. 15 and 31-33, in step S17, in the illustrated embodiment, a plurality of memory cell spacers 213J, a plurality of select cell spacers 409J, and a select cell upper conductive layer 407J may be formed over the substrate 101J. A gap sub-layer may be formed over the substrate 101J. The gap sub-layer may cover the top surfaces of the memory cell conductive layer 211J and the select cell conductive layer 405J; and may cover sidewalls of the memory cell conductive layer 211J, the tunneling isolation layer 207J, the lateral oxidation interposer 209J, the select cell conductive layer 405J, and the select cell isolation layer 403J. An etching process, such as an anisotropic dry etching process, may be performed on a portion of the spacer layer and may simultaneously form a plurality of memory cell spacers 213J and a plurality of select cell spacers 409J. A fourth masking layer 711 may be patterned to mask the memory cell 201. A self-aligned silicide process may be performed to form the select cell upper conductive layer 407J over the select cell conductive layer 405J. After the salicidation process, the fourth masking layer 711 may be removed.

Fig. 34 is a schematic top view of a semiconductor device in a process for fabricating the semiconductor device according to an embodiment of the present disclosure. FIG. 35 is a schematic cross-sectional view taken along line A-A' of FIG. 34. FIG. 36 is a schematic cross-sectional view taken along section line B-B' of FIG. 34.

Referring to fig. 15 and 34 to 36, in step S19, in the embodiment, a passivation isolation layer 105J may be formed on the substrate 101J, and a plurality of control contacts 601J and a plurality of doped region contacts 603J may be formed in the passivation isolation layer 105J. A passivation isolation layer 105J may be formed to cover the memory cell 201 and the selection cell 401. A planarization process, such as chemical mechanical polishing, may be performed on the passivation isolation layer 105J to provide a substantially planar surface for subsequent processing steps. Through a damascene process, a plurality of control contacts 601J may be formed on the control unit 501J and in the passivation isolation layer 105J, and a plurality of doped region contacts 603J may be formed on the doped regions and in the passivation isolation layer 105J.

Due to the design of the semiconductor device 100A of the present disclosure, the dielectric constant of the lateral oxidation interposer 209 may be increased. As a result, the capacitive coupling between the control unit 501 and the memory cell conductive layer 211 can become more efficient. Therefore, the performance of the semiconductor device 100A may be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of this disclosure.