阅读说明：本技术 数模转换器建模方法及系统、数模转换器 (Digital-to-analog converter modeling method and system and digital-to-analog converter ) 是由 刘杰 班郁 李苗 叶雨农 王皓岩 李嵬 于 2021-04-09 设计创作，主要内容包括：本公开提供一种数模转换器建模方法及系统、数模转换器,所述方法包括：建立基于行为级语言VerilogA的行为级模型；建立基于Spice的端口模型；将所述基于行为级语言VerilogA的行为级模型和所述基于Spice的端口模型相结合,构建从数字信号输入到模拟信号输出的信号通路,获得数模转换器模型。本公开的数模转换器建模方法,设计了基于行为级语言VerilogA的行为级模型和基于Spice的端口模型相融合的模型架构,在保障数模转换器集成仿真需求和精度的同时,有效提升模型的仿真效率,增加了模型的可用性,增加了模型的可共享性,该数模转换器模型建模方法可有效支撑基于模型的IP共享。(The present disclosure provides a modeling method and system for a digital-to-analog converter, and a digital-to-analog converter, wherein the method comprises the following steps: establishing a behavior level model based on a behavior level language Veriloga; establishing a port model based on Spice; and combining the behavioral level model based on the behavioral level language Veriloga and the port model based on Spice to construct a signal path from digital signal input to analog signal output so as to obtain a digital-to-analog converter model. According to the modeling method of the digital-to-analog converter, a model architecture in which a behavioral level model based on a behavioral level language Veriloga and a port model based on Spice are fused is designed, the simulation efficiency of the model is effectively improved while the integrated simulation requirement and precision of the digital-to-analog converter are guaranteed, the usability of the model is increased, and the sharability of the model is increased.)

1. A method of modeling a digital-to-analog converter, the method comprising:

establishing a behavior level model based on a behavior level language Veriloga;

establishing a port model based on Spice;

and combining the behavioral level model based on the behavioral level language Veriloga and the port model based on Spice to construct a signal path from digital signal input to analog signal output so as to obtain a digital-to-analog converter model.

2. The method of claim 1, wherein the building a behavioral-level model based on the behavioral-level language verilog a comprises:

and (3) model architecture: establishing a behavioral model basic structure by combining a digital-to-analog converter circuit design framework, and hiding the core circuit design while keeping the whole circuit structure;

parameter configuration: setting model configurable parameters by combining the configurability requirements of the whole digital-to-analog converter;

functional modeling: the digital-to-analog converter is combined with the integral function, the conversion function from a digital signal to an analog signal is completed through a behavioral level language Veriloga, and the signal behavior simulation is completed according to the parameter requirement;

noise simulation: and combining the performance simulation and test results of the digital-to-analog converter circuit, and finishing the introduction of noise through the behavioral level language Veriloga to finish the performance simulation of the analog signal.

3. The method of claim 2, wherein the establishing a Spice-based port model comprises:

port function: combining the functions of an output port part in the design of a digital-to-analog converter circuit, and constructing a port Spice circuit based on the currently selected process basic transistor;

parameter configuration: setting configurable parameters of an output port by combining configurable requirements of the whole digital-to-analog converter;

port performance: and adjusting the parameters of the process basic transistor by combining the performance simulation and test results of the digital-to-analog converter circuit to finish the performance simulation of the output port.

4. The method according to claim 3, wherein said combining said behavioral-level model based on the behavioral-level language Veriloga and said Spice-based port model to construct a signal path from a digital signal input to an analog signal output to obtain a digital-to-analog converter model comprises:

parameter configuration: combining the behavioral level model based on the behavioral level language Veriloga and the parameter configuration of the port model based on Spice to form a parameter configuration requirement of a digital-to-analog converter model;

combining models: and combining the behavioral level model based on the behavioral level language Veriloga and the port model based on Spice by combining the integral function of the digital-to-analog converter, and constructing a signal path from digital signal input to analog signal output to obtain the digital-to-analog converter model.

5. A digital to analog converter modeling system, the system comprising:

the first establishing module is used for establishing a behavior level model based on a behavior level language Veriloga;

the second establishing module is used for establishing a port model based on Spice;

and the combination module is used for combining the behavioral level model based on the behavioral level language Veriloga and the port model based on Spice, constructing a signal path from digital signal input to analog signal output, and obtaining a digital-to-analog converter model.

6. The system of claim 5, wherein the first building module is configured to build a behavioral-level model based on a behavioral-level language Veriloga, and comprises:

the first establishing module is specifically configured to:

and (3) model architecture: establishing a behavioral model basic structure by combining a digital-to-analog converter circuit design framework, and hiding the core circuit design while keeping the whole circuit structure;

parameter configuration: setting model configurable parameters by combining the configurability requirements of the whole digital-to-analog converter;

functional modeling: the digital-to-analog converter is combined with the integral function, the conversion function from a digital signal to an analog signal is completed through a behavioral level language Veriloga, and the signal behavior simulation is completed according to the parameter requirement;

noise simulation: and combining the performance simulation and test results of the digital-to-analog converter circuit, and finishing the introduction of noise through the behavioral level language Veriloga to finish the performance simulation of the analog signal.

7. The system of claim 6, wherein the second establishing module is configured to establish a Spice-based port model, and comprises:

the second establishing module is specifically configured to:

port function: combining the functions of an output port part in the design of a digital-to-analog converter circuit, and constructing a port Spice circuit based on the currently selected process basic transistor;

parameter configuration: setting configurable parameters of an output port by combining configurable requirements of the whole digital-to-analog converter;

port performance: and adjusting the parameters of the basic transistor by combining the performance simulation and test results of the digital-to-analog converter circuit to finish the performance simulation of the output port.

8. The system according to claim 7, wherein the combining module is configured to combine the behavioral-level model based on the behavioral-level language verilog a and the Spice-based port model to construct a signal path from a digital signal input to an analog signal output, and obtain the digital-to-analog converter model, and includes:

the binding module is specifically configured to:

parameter configuration: combining the behavioral level model based on the behavioral level language Veriloga and the parameter configuration of the port model based on Spice to form a parameter configuration requirement of a digital-to-analog converter model;

combining models: and combining the behavioral level model based on the behavioral level language Veriloga and the port model based on Spice by combining the integral function of the digital-to-analog converter, and constructing a signal path from digital signal input to analog signal output to obtain the digital-to-analog converter model.

9. A digital-to-analog converter, characterized by being built using the modeling method of any one of claims 1 to 4.

Technical Field

The disclosure belongs to the technical field of modeling, and particularly relates to a modeling method and system for a digital-to-analog converter and the digital-to-analog converter.

Background

The digital-to-analog converter has extremely wide application in the current electronic equipment of information, communication and the like, can meet the requirement of high-efficiency conversion from a digital domain to an analog domain, and the model of the digital-to-analog converter is mainly used for realizing the function and performance simulation of the digital-to-analog converter when being integrated in a system. In the current prior art, the model of the digital-to-analog converter can be mainly modeled by a Spice-based circuit modeling and an IBIS model based on port behaviors, and different modeling methods are different in modeling process and simulation application.

A digital-to-analog converter model formed based on Spice circuit modeling can accurately represent the design details of a digital-to-analog converter, but the modeling process is high in requirement, the model scale is large, the efficiency is low in system simulation, the design of the digital-to-analog converter can be disclosed to a certain degree, and the intellectual property protection is insufficient. The IBIS model based on the port behaviors is mainly used for representing the current and voltage behaviors of the signal port, is mainly used for cascade simulation of an interconnection part in integrated design, cannot represent the function and performance of a digital-to-analog converter, and is insufficient in system function evaluation.

Disclosure of Invention

The present disclosure is directed to at least one of the technical problems in the prior art, and provides a modeling method and system for a digital-to-analog converter, and a digital-to-analog converter.

In one aspect of the present disclosure, there is provided a digital-to-analog converter modeling method, the method including:

establishing a behavior level model based on a behavior level language Veriloga;

establishing a port model based on Spice;

and combining the behavioral level model based on the behavioral level language Veriloga and the port model based on Spice to construct a signal path from digital signal input to analog signal output so as to obtain a digital-to-analog converter model.

In some embodiments, the creating a behavior-level model based on a behavior-level language verilog a includes:

and (3) model architecture: establishing a behavioral model basic structure by combining a digital-to-analog converter circuit design framework, and hiding the core circuit design while keeping the whole circuit structure;

parameter configuration: setting model configurable parameters by combining the configurability requirements of the whole digital-to-analog converter;

functional modeling: the digital-to-analog converter is combined with the integral function, the conversion function from a digital signal to an analog signal is completed through a behavioral level language Veriloga, and the signal behavior simulation is completed according to the parameter requirement;

noise simulation: and combining the performance simulation and test results of the digital-to-analog converter circuit, and finishing the introduction of noise through the behavioral level language Veriloga to finish the performance simulation of the analog signal.

In some embodiments, the establishing the Spice-based port model includes:

port function: combining the functions of an output port part in the design of a digital-to-analog converter circuit, and constructing a port Spice circuit based on the currently selected process basic transistor;

parameter configuration: setting configurable parameters of an output port by combining configurable requirements of the whole digital-to-analog converter;

port performance: and adjusting the parameters of the basic transistor by combining the performance simulation and test results of the digital-to-analog converter circuit to finish the performance simulation of the output port.

In some embodiments, the combining the behavioral level model based on the behavioral level language verilog a and the Spice-based port model to construct a signal path from a digital signal input to an analog signal output to obtain a digital-to-analog converter model includes:

parameter configuration: combining the behavioral level model based on the behavioral level language Veriloga and the parameter configuration of the port model based on Spice to form a parameter configuration requirement of a digital-to-analog converter model;

combining models: and combining the behavioral level model based on the behavioral level language Veriloga and the port model based on Spice by combining the integral function of the digital-to-analog converter, and constructing a signal path from digital signal input to analog signal output to obtain the digital-to-analog converter model.

In another aspect of the present disclosure, there is provided a digital-to-analog converter modeling system, the system including:

the first establishing module is used for establishing a behavior level model based on a behavior level language Veriloga;

the second establishing module is used for establishing a port model based on Spice;

and the combination module is used for combining the behavioral level model based on the behavioral level language Veriloga and the port model based on Spice, constructing a signal path from digital signal input to analog signal output, and obtaining a digital-to-analog converter model.

In some embodiments, the first building module is configured to build a behavioral level model based on a behavioral level language verilog a, and includes:

the first establishing module is specifically configured to:

and (3) model architecture: establishing a behavioral model basic structure by combining a digital-to-analog converter circuit design framework, and hiding the core circuit design while keeping the whole circuit structure;

parameter configuration: setting model configurable parameters by combining the configurability requirements of the whole digital-to-analog converter;

functional modeling: the digital-to-analog converter is combined with the integral function, the conversion function from a digital signal to an analog signal is completed through a behavioral level language Veriloga, and the signal behavior simulation is completed according to the parameter requirement;

noise simulation: and combining the performance simulation and test results of the digital-to-analog converter circuit, and finishing the introduction of noise through the behavioral level language Veriloga to finish the performance simulation of the analog signal.

In some embodiments, the second establishing module is configured to establish a Spice-based port model, and includes:

the second establishing module is specifically configured to:

port function: combining the functions of an output port part in the design of a digital-to-analog converter circuit, and constructing a port Spice circuit based on the currently selected process basic transistor;

parameter configuration: setting configurable parameters of an output port by combining configurable requirements of the whole digital-to-analog converter;

port performance: and adjusting the parameters of the basic transistor by combining the performance simulation and test results of the digital-to-analog converter circuit to finish the performance simulation of the output port.

In some embodiments, the combining module is configured to combine the behavioral-level model based on the behavioral-level language verilog a and the Spice-based port model to construct a signal path from a digital signal input to an analog signal output, and obtain a digital-to-analog converter model, and includes:

the binding module is specifically configured to:

parameter configuration: combining the behavioral level model based on the behavioral level language Veriloga and the parameter configuration of the port model based on Spice to form a parameter configuration requirement of a digital-to-analog converter model;

combining models: and combining the behavioral level model based on the behavioral level language Veriloga and the port model based on Spice by combining the integral function of the digital-to-analog converter, and constructing a signal path from digital signal input to analog signal output to obtain the digital-to-analog converter model.

In another aspect of the present disclosure, a digital-to-analog converter is provided, which is built by the modeling method described above.

According to the modeling method and system for the digital-to-analog converter and the digital-to-analog converter, a model architecture in which a behavioral level model based on a behavioral level language Veriloga and a port model based on Spice are fused is designed, the simulation efficiency of the model is effectively improved while the integrated simulation requirement and precision of the digital-to-analog converter are guaranteed, the usability of the model is increased, and the sharability of the model is increased.

Drawings

FIG. 1 is a flow chart of a digital to analog converter modeling method according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a digital-to-analog converter according to another embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a digital-to-analog converter for system integration simulation according to another embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a digital-to-analog converter modeling system according to another embodiment of the present disclosure.

Detailed Description

For a better understanding of the technical aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

One aspect of the present embodiment, as shown in fig. 1, relates to a digital-to-analog converter modeling method S100, where the method S100 includes:

and S110, establishing a behavior level model based on a behavior level language Veriloga.

Specifically, in this step, modeling of the function of the digital-to-analog converter is completed through the behavioral level language verilog a, conversion from a digital signal to an analog signal is completed, and the model is consistent with the relevant function and performance of the digital-to-analog converter circuit design.

And S120, establishing a port model based on Spice.

Specifically, in this step, the performance characterization of the analog port output on the digital-to-analog converter circuit, which mainly includes the voltage, current, etc. on the analog port, can be completed through the selected basic gate circuit in the process PDK, so as to obtain the same performance as the digital-to-analog converter circuit port.

S130, combining the behavioral level model based on the behavioral level language Veriloga and the port model based on Spice, and constructing a signal path from digital signal input to analog signal output to obtain a digital-to-analog converter model.

Specifically, in this step, the behavioral level model based on the behavioral level language verilog a and the Spice-based port model are combined to construct a signal path from a digital signal input to an analog signal output, and obtain a digital-to-analog converter model, as shown in fig. 2.

According to the modeling method of the digital-to-analog converter, a model architecture in which a behavioral level model based on a behavioral level language Veriloga and a port model based on Spice are fused is designed, the simulation efficiency of the model is effectively improved while the integrated simulation requirement and precision of the digital-to-analog converter are guaranteed, the usability of the model is increased, and the sharability of the model is increased.

In some embodiments, the creating a behavior-level model based on a behavior-level language verilog a includes:

and (3) model architecture: establishing a behavioral model basic structure by combining a digital-to-analog converter circuit design framework, and hiding the core circuit design while keeping the whole circuit structure;

parameter configuration: setting model configurable parameters by combining the configurability requirements of the whole digital-to-analog converter;

functional modeling: the digital-to-analog converter is combined with the integral function, the conversion function from a digital signal to an analog signal is completed through a behavioral level language Veriloga, and the signal behavior simulation is completed according to the parameter requirement;

noise simulation: and combining the performance simulation and test results of the digital-to-analog converter circuit, and finishing the introduction of noise through the behavioral level language Veriloga to finish the performance simulation of the analog signal.

It should be noted that the core circuit is an architecture circuit that performs digital-to-analog conversion performance index analysis, and for example, the core circuit may be used to perform processing such as noise reduction and filtering on an input digital signal, and may also analyze a ratio weight of each bit of the digital signal, so as to ensure that an obtained analog signal can accurately reflect the digital signal.

In some embodiments, the establishing the Spice-based port model includes:

port function: combining the functions of an output port part in the design of a digital-to-analog converter circuit, and constructing a port Spice circuit based on the currently selected process basic transistor;

parameter configuration: setting configurable parameters of an output port by combining configurable requirements of the whole digital-to-analog converter;

port performance: and adjusting the parameters of the basic transistor by combining the performance simulation and test results of the digital-to-analog converter circuit to finish the performance simulation of the output port.

In some embodiments, the combining the behavioral level model based on the behavioral level language verilog a and the Spice-based port model to construct a signal path from a digital signal input to an analog signal output to obtain a digital-to-analog converter model includes:

parameter configuration: combining the behavioral level model based on the behavioral level language Veriloga and the parameter configuration of the port model based on Spice to form a parameter configuration requirement of a digital-to-analog converter model;

combining models: and combining the behavioral level model based on the behavioral level language Veriloga and the port model based on Spice by combining the integral function of the digital-to-analog converter, and constructing a signal path from digital signal input to analog signal output to obtain the digital-to-analog converter model.

The following describes the application of the digital-to-analog converter model formed by the digital-to-analog converter modeling method of the present disclosure.

As shown in fig. 3, the digital-to-analog converter model formed by the digital-to-analog converter modeling method of the present disclosure may be used for system integration simulation to complete system integration function evaluation. The system integration simulation comprises A-input control, B-output detection and C-digital-to-analog converter model.

The A-input control consists of a signal source and an ideal analog-to-digital converter, and can be replaced by a specific system front-end digital signal functional circuit and a model, and mainly provides a digital signal source.

The B-output detection is composed of signal analysis, and mainly completes the correlation performance analysis of the analog signal, which may include signal-to-distortion-noise ratio (SNDR), significance (ENOB), etc., and may also be replaced by the subsequent analog signal processing, mainly completing the analog signal analysis.

The C-digital-to-analog converter model is a digital-to-analog converter model completed by the modeling method provided by the disclosure, and the model parameter configuration can be completed according to relevant requirements needed actually.

In another aspect of the present disclosure, as shown in fig. 4, a digital-to-analog converter modeling system 100 is provided, and the system 100 may be applied to the above-mentioned digital-to-analog converter modeling method, and the related contents may refer to the above description and will not be described herein again. The system 100 includes:

the first building module 110 is used for building a behavior-level model based on a behavior-level language verilog a.

And a second establishing module 120, configured to establish a Spice-based port model.

A combining module 130, configured to combine the behavioral level model based on the behavioral level language verilog a with the Spice-based port model, and construct a signal path from a digital signal input to an analog signal output, so as to obtain a digital-to-analog converter model.

The modeling system of the digital-to-analog converter of the embodiment designs a model architecture in which a behavioral level model based on a behavioral level language Veriloga and a port model based on Spice are fused, so that the simulation efficiency of the model is effectively improved, the usability of the model is increased, and the sharability of the model is increased while the integrated simulation requirement and precision of the digital-to-analog converter are guaranteed.

In some embodiments, the first establishing module 110 is configured to establish a behavior-level model based on a behavior-level language verilog a, and includes:

the first establishing module 110 is specifically configured to:

and (3) model architecture: establishing a behavioral model basic structure by combining a digital-to-analog converter circuit design framework, and hiding the core circuit design while keeping the whole circuit structure;

parameter configuration: setting model configurable parameters by combining the configurability requirements of the whole digital-to-analog converter;

functional modeling: the digital-to-analog converter is combined with the integral function, the conversion function from a digital signal to an analog signal is completed through a behavioral level language Veriloga, and the signal behavior simulation is completed according to the parameter requirement;

noise simulation: and combining the performance simulation and test results of the digital-to-analog converter circuit, and finishing the introduction of noise through the behavioral level language Veriloga to finish the performance simulation of the analog signal.

In some embodiments, the second establishing module 120 is configured to establish a Spice-based port model, and includes:

the second establishing module is specifically configured to:

port function: combining the functions of an output port part in the design of a digital-to-analog converter circuit, and constructing a port Spice circuit based on the currently selected process basic transistor;

parameter configuration: setting configurable parameters of an output port by combining configurable requirements of the whole digital-to-analog converter;

port performance: and adjusting the parameters of the basic transistor by combining the performance simulation and test results of the digital-to-analog converter circuit to finish the performance simulation of the output port.

In some embodiments, the combining module 130 is configured to combine the behavioral-level model based on the behavioral-level language verilog a and the Spice-based port model to construct a signal path from a digital signal input to an analog signal output, and obtain a digital-to-analog converter model, and includes:

the combining module 130 is specifically configured to:

parameter configuration: combining the behavioral level model based on the behavioral level language Veriloga and the parameter configuration of the port model based on Spice to form a parameter configuration requirement of a digital-to-analog converter model;

combining models: and combining the behavioral level model based on the behavioral level language Veriloga and the port model based on Spice by combining the integral function of the digital-to-analog converter, and constructing a signal path from digital signal input to analog signal output to obtain the digital-to-analog converter model.

In another aspect of the present disclosure, a digital-to-analog converter is provided, which is built by the modeling method described above.

The digital-to-analog converter of the embodiment is built by the modeling method described above, and a model architecture in which a behavioral level model based on a behavioral level language verilog a and a port model based on Spice are fused is designed, so that the simulation efficiency of the model is effectively improved, the usability of the model is increased, and the sharability of the model is increased while the integrated simulation requirement and precision of the digital-to-analog converter are guaranteed.

It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.