阅读说明：本技术 存储控制器以及存储装置初始化方法 (Storage controller and storage device initialization method ) 是由 陈俊明 于 2019-11-13 设计创作，主要内容包括：本发明提供一种存储控制器以及存储装置初始化方法。所述方法包括抹除可复写式非易失性存储器模块的多个实体区块；写满预定数据至所述多个实体区块；对所述多个实体页面执行读取操作以获得多个页面错误比特数；根据所述多个页面错误比特数来识别所述多个实体区块各自的物理状况,并且根据多个物理状况来排序所述多个实体区块以获得区块序列；反应于判定所述区块序列中的所有实体区块的所述总空间不等于所述第一预定空间,从所述区块序列中移除排序于最前方的实体区块；以及反应于判定所述总空间等于所述第一预定空间,完成所述初始化操作,选择所述区块序列中的多个第一实体区块中的多个第二实体区块的总空间来作为具有预定大小的第二预定空间。(The invention provides a storage controller and a storage device initialization method. The method comprises the steps of erasing a plurality of entity blocks of the rewritable nonvolatile memory module; writing predetermined data to the plurality of physical blocks; performing a read operation on the plurality of entity pages to obtain a plurality of page error bit numbers; identifying respective physical conditions of the plurality of physical blocks according to the plurality of page error bit numbers, and sorting the plurality of physical blocks according to a plurality of physical conditions to obtain a block sequence; removing a front-most physical block from the block sequence in response to determining that the total space of all physical blocks in the block sequence is not equal to the first predetermined space; and in response to determining that the total space is equal to the first predetermined space, completing the initialization operation, selecting a total space of a plurality of second physical blocks of the plurality of first physical blocks in the block sequence as a second predetermined space having a predetermined size.)

1. A memory controller for controlling a memory device configured with a rewritable non-volatile memory module, the memory controller comprising:

a connection interface circuit for coupling to a host system;

a memory interface control circuit for coupling to the rewritable nonvolatile memory module; and

a processor coupled to the connection interface circuit and the memory interface control circuit,

wherein the processor is to begin performing initialization operations,

wherein the processor is further configured to erase a plurality of physical blocks of the rewritable non-volatile memory module, wherein none of the plurality of physical blocks is mapped to a plurality of logical blocks of the host system, wherein the plurality of physical blocks are grouped into a plurality of physical pages of the rewritable non-volatile memory module,

wherein the processor is further configured to write predetermined data to the plurality of physical blocks so that the plurality of physical blocks are full of the predetermined data,

wherein the processor is further configured to perform a read operation on the plurality of physical pages to obtain a number of page error bits for each of the plurality of physical pages,

wherein the processor is further configured to obtain a number of block error bits for each of the plurality of physical blocks according to the number of page error bits for each of the plurality of physical pages,

wherein the processor is further configured to identify a physical condition of each of the plurality of physical blocks according to the number of page error bits of each of the plurality of physical pages and the number of block error bits of each of the plurality of physical blocks, and sort the plurality of physical blocks according to a plurality of physical conditions to obtain a block sequence, wherein a front-most physical block in the block sequence has a worst physical condition and a rear-most physical block in the block sequence has a worst physical condition,

wherein the processor is further configured to determine whether a total space of all physical blocks in the sequence of blocks is equal to a first predetermined space,

wherein in response to determining that the total space of all physical blocks in the block sequence is not equal to the first predetermined space, the processor is further configured to remove a head-most physical block from the block sequence and update the block sequence, wherein all physical blocks in the block sequence are each a first physical block,

wherein in response to determining that the total space of all physical blocks in the block sequence is equal to the first predetermined space, the processor is further configured to complete the initialization operation, and select a total space of a plurality of second physical blocks in a plurality of first physical blocks in the block sequence as a second predetermined space, wherein a size of the second predetermined spaces is a predetermined size.

2. The memory controller according to claim 1, wherein in said operation of identifying the physical condition of each of the plurality of physical blocks according to the number of page error bits of each of the plurality of physical pages and the number of block error bits of each of the plurality of physical blocks, and sorting the plurality of physical blocks according to the plurality of physical conditions to obtain the block sequence,

the processor marks one or more target physical pages of the plurality of physical pages having the number of page error bits greater than a threshold number of page error bits as bad physical pages,

wherein the processor sums the number of the bad physical pages that each of the plurality of physical blocks has as a total number of bad physical pages,

wherein the processor performs a first ordering on the plurality of physical blocks according to a total number of the bad physical pages of each of the plurality of physical blocks from large to small to obtain a first block sequence,

in response to that the total number of the bad entity pages of each of the target entity blocks is equal, the processor performs a second sorting on the target entity blocks according to the number of block error bits of each of the target entity blocks from large to small, so as to update the first block sequence to be the block sequence.

3. The storage controller of claim 1, wherein the second physical blocks are configured to be mapped to the logical blocks of the host system.

4. The storage controller of claim 3, wherein the predetermined size is a predetermined capacity that can be used by the host system.

5. The memory controller of claim 1, wherein the processor further records the removed one or more physical blocks in a bad physical block table.

6. A storage device initialization method is suitable for a storage device configured with a rewritable nonvolatile memory module, and is characterized by comprising the following steps:

starting to execute an initialization operation, and erasing a plurality of physical blocks of the rewritable non-volatile memory module, wherein none of the physical blocks is mapped to a plurality of logical blocks of a host system, and the physical blocks are grouped by a plurality of physical pages of the rewritable non-volatile memory module;

writing predetermined data into the plurality of physical blocks so that the plurality of physical blocks are full of the predetermined data;

performing a reading operation on the plurality of entity pages to obtain respective page error bit numbers of the plurality of entity pages;

obtaining the block error bit number of each entity block according to the page error bit number of each entity page;

identifying respective physical conditions of the plurality of physical blocks according to the number of page error bits of each of the plurality of physical pages and the number of block error bits of each of the plurality of physical blocks, and sorting the plurality of physical blocks according to a plurality of physical conditions to obtain a block sequence, wherein a front-most physical block in the block sequence has a worst physical condition and a rear-most physical block in the block sequence has a worst physical condition;

judging whether the total space of all the entity blocks in the block sequence is equal to a first preset space or not;

in response to determining that the total space of all physical blocks in the block sequence is not equal to the first predetermined space, removing a head-ranked physical block from the block sequence and updating the block sequence, wherein all physical blocks in the block sequence are each a first physical block; and

in response to determining that the total space of all physical blocks in the block sequence is equal to the first predetermined space, the initialization operation is completed, and a total space of a plurality of second physical blocks in a plurality of first physical blocks in the block sequence is selected as a second predetermined space, wherein the size of the second predetermined spaces is a predetermined size.

7. The method according to claim 6, wherein said identifying the physical condition of each of the plurality of physical blocks according to the number of page error bits of each of the plurality of physical pages and the number of block error bits of each of the plurality of physical blocks, and said sorting the plurality of physical blocks according to the physical conditions to obtain the block sequence comprises:

marking one or more target entity pages of the plurality of entity pages having the page fault bit number greater than a page fault bit number threshold as bad entity pages;

summing the number of the bad entity pages of each of the plurality of entity blocks to be the total number of the bad entity pages;

performing a first ordering on the plurality of physical blocks according to the total number of the bad physical pages of each of the plurality of physical blocks from large to small to obtain a first block sequence; and

and performing second sorting on the target entity blocks according to the block error bit numbers of the target entity blocks from large to small in response to the fact that the total number of the bad entity pages of each of the target entity blocks is equal, so as to update the first block sequence to be the block sequence.

8. The method of claim 6, wherein the second physical blocks are configured to be mapped to the logical blocks of the host system.

9. The storage device initialization method of claim 8, wherein the predetermined size is a predetermined capacity that can be used by the host system.

10. The storage device initialization method of claim 6, the method further comprising:

recording the removed one or more physical blocks in the bad physical block table.

Technical Field

The present invention relates to a memory controller and a memory device initialization method used by the memory controller.

Background

Generally, before the storage device is used or when the storage device is connected to the host system for the first time, the storage device performs an initialization operation (also referred to as a card opening operation) to determine that the storage device can allocate a predetermined amount of storage space to the host system. However, in the conventional initialization operation, only a plurality of physical blocks with a total space equal to a predetermined size are simply selected to be allocated to the host system for use.

Disclosure of Invention

The present invention is directed to a memory controller for controlling a memory device configured with a rewritable non-volatile memory module and a memory device initialization method used by the memory controller.

Embodiments of the present invention provide a memory controller for controlling a memory device configured with a rewritable non-volatile memory module. The storage controller includes: the interface circuit, the memory interface control circuit and the processor are connected. The connection interface circuit is used for being coupled to a host system. The memory interface control circuit is used for being coupled to the rewritable nonvolatile memory module. The processor is coupled to the connection interface circuit and the memory interface control circuit. The processor is configured to start performing an initialization operation, wherein the processor is further configured to erase a plurality of physical blocks of the rewritable non-volatile memory module, wherein none of the physical blocks is mapped to a plurality of logical blocks of the host system, wherein the physical blocks are grouped into a plurality of physical pages of the rewritable non-volatile memory module, wherein the processor is further configured to write predetermined data into the physical blocks so that the physical blocks are full of the predetermined data, wherein the processor is further configured to perform a read operation on the physical pages to obtain respective numbers of page error bits of the physical pages, wherein the processor is further configured to obtain the respective numbers of block error bits of the physical blocks according to the respective numbers of page error bits of the physical pages, the processor is further configured to identify a physical condition of each of the plurality of physical blocks according to the number of page error bits of each of the plurality of physical pages and the number of block error bits of each of the plurality of physical blocks, and sort the plurality of physical blocks according to a plurality of physical conditions to obtain a block sequence, wherein a front-most physical block in the block sequence has a worst physical condition, and a rear-most physical block in the block sequence has a worst physical condition. In addition, the processor is further configured to determine whether a total space of all physical blocks in the block sequence is equal to a first predetermined space, wherein in response to determining that the total space of all physical blocks in the sequence of blocks is not equal to the first predetermined space, the processor is further configured to remove a head-most physical block from the sequence of blocks and update the sequence of blocks, wherein all physical blocks in the sequence of blocks are each a first physical block, wherein in response to determining that the total space of all physical blocks in the sequence of blocks is equal to the first predetermined space, the processor is further configured to complete the initialization operation, and select a total space of a plurality of second physical blocks in a plurality of first physical blocks in the block sequence as a second predetermined space, where a size of the second predetermined spaces is a predetermined size.

In an embodiment of the present invention, in the operation of identifying the physical status of each of the plurality of physical pages according to the number of page error bits of each of the plurality of physical pages and the number of block error bits of each of the plurality of physical blocks and sorting the plurality of physical blocks according to the physical statuses to obtain the block sequence, the processor marks one or more target physical pages of the plurality of physical pages having the number of page error bits larger than a threshold value of the number of page error bits as bad physical pages, wherein the processor sums up the number of the bad physical pages of each of the plurality of physical blocks to be a total number of the bad physical pages, wherein the processor performs a first sorting on the plurality of physical blocks according to the total number of the bad physical pages of each of the plurality of physical blocks from large to small, and in response to that the total number of the bad entity pages of each of the target entity blocks is equal, the processor performs a second sorting on the target entity blocks from a greater size to a smaller size according to the number of block error bits of each of the target entity blocks, so as to update the first block sequence to be the block sequence.

In an embodiment of the invention, the second physical blocks are configured to be mapped to the logical blocks of the host system.

In an embodiment of the invention, the predetermined size is a predetermined capacity that can be used by the host system.

In an embodiment of the invention, the processor further records the removed one or more physical blocks in the bad physical block table

The embodiment of the invention provides a storage device initialization method, which is suitable for a storage device configured with a rewritable nonvolatile memory module. The method comprises the following steps: starting to execute an initialization operation, and erasing a plurality of physical blocks of the rewritable non-volatile memory module, wherein none of the physical blocks is mapped to a plurality of logical blocks of a host system, and the physical blocks are grouped by a plurality of physical pages of the rewritable non-volatile memory module; writing predetermined data into the plurality of physical blocks so that the plurality of physical blocks are full of the predetermined data; performing a reading operation on the plurality of entity pages to obtain respective page error bit numbers of the plurality of entity pages; obtaining the block error bit number of each entity block according to the page error bit number of each entity page; identifying respective physical conditions of the plurality of physical blocks according to the number of page error bits of each of the plurality of physical pages and the number of block error bits of each of the plurality of physical blocks, and sorting the plurality of physical blocks according to a plurality of physical conditions to obtain a block sequence, wherein a front-most physical block in the block sequence has a worst physical condition and a rear-most physical block in the block sequence has a worst physical condition; judging whether the total space of all the entity blocks in the block sequence is equal to a first preset space or not; in response to determining that the total space of all physical blocks in the block sequence is not equal to the first predetermined space, removing a head-ranked physical block from the block sequence and updating the block sequence, wherein all physical blocks in the block sequence are each a first physical block; and in response to determining that the total space of all physical blocks in the block sequence is equal to the first predetermined space, completing the initialization operation, and selecting a total space of a plurality of second physical blocks in a plurality of first physical blocks in the block sequence as a second predetermined space, wherein the size of the second predetermined spaces is a predetermined size.

Based on the above, the memory controller and the method for initializing a memory device according to the embodiments of the present invention can obtain the number of error bits corresponding to each physical page by performing an erase operation, a write operation, and a read operation on all the physical blocks and the physical pages in an initialization operation performed on the memory device, so that one or more physical blocks with poor physical conditions can be removed according to the number of error bits corresponding to each physical page in a case of meeting a predetermined size of the memory device, so that the host system can only use the physical blocks with better physical conditions. Therefore, after the initialization operation is completed, the host system can be prevented from using the removed entity blocks with poor physical conditions, and the reliability of the storage data of the storage device is improved.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 is a block diagram illustrating a host system and a storage device according to an embodiment of the invention.

FIG. 2 is a flowchart illustrating a method for initializing a memory device according to an embodiment of the invention.

Fig. 3 is a flowchart illustrating step S25 in fig. 2 according to an embodiment of the present invention.

Fig. 4 is a schematic diagram illustrating marking a bad entity page according to an embodiment of the present invention.

Fig. 5 is a diagram illustrating obtaining a block sequence and removing a physical block from the block sequence according to an embodiment of the invention.

Description of the reference numerals

10: host system

110. 211: processor with a memory having a plurality of memory cells

120: host memory

130: data transmission interface circuit

210: storage controller

212: data management circuit

213: memory interface control circuit

214: error checking and correcting circuit

216: buffer memory

217: power management circuit

220: rewritable nonvolatile memory module

230: connection interface circuit

S21, S22, S23, S24, S25, S26, S27, S28: flow steps of test data generation method

S251, S252, S253, S254: step of step S25

400(1) - (400 (8)): entity page

400-407: physical block

A41, A51-A53: arrow head

501(1) - (501 (2)): frame line

500-502: sequence of

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a block diagram illustrating a host system and a storage device according to an embodiment of the invention. Referring to fig. 1, a host system 10 is, for example, a personal computer, a notebook computer, or a server. The Host System (Host System)10 includes a Processor (Processor)110, a Host Memory (Host Memory)120, a Data Transfer Interface Circuit (Data Interface Circuit)130, and a storage device 140. In the present embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120, the data transmission interface circuit 130 and the storage device. In another embodiment, the Processor (Processor)110, the host memory 120, the data transmission interface circuit 130 and the storage device 140 are coupled to each other by a System Bus (System Bus). In the present embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 may be disposed on a motherboard of the host system 10.

The Memory device 20 includes a Memory Controller (Storage Controller)210, a Rewritable Non-Volatile Memory Module (Rewritable Non-Volatile Memory Module)220, and a Connection Interface Circuit (Connection Interface Circuit) 230. The Memory controller 210 includes a processor 211, a Data Management Circuit (Data Management Circuit)212, and a Memory Interface Control Circuit (Memory Interface Control Circuit) 213.

In the present embodiment, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operation. For example, the host system 10 may store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.

In this embodiment, the number of the data transmission interface circuits 130 may be one or more. The motherboard can be coupled to the memory device 20 via a wired or wireless connection via the data transmission interface circuit 130. The storage device 20 may be, for example, a usb disk, a memory card, a Solid State Drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon), which are based on various wireless Communication technologies. In addition, the motherboard may also be coupled to various I/O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, and the like through a System bus.

In the present embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the PCI Express (Peripheral Component Interconnect Express) standard. The data transmission interface circuit 130 and the connection interface circuit 230 transmit data by using a Non-Volatile Memory interface (NVMe) protocol.

However, it should be understood that the present invention is not limited thereto, and the data transmission interface circuit 130 and the connection interface circuit 230 may also conform to Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Serial Advanced Technology Attachment (SATA) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed (UHS-eMI) interface standard, Ultra High Speed (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, Multi-Chip Package (Multi-P Package) interface standard, multimedia Memory Card (Multi-Media) interface, Flash Memory standard (MMC) interface, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In addition, in another embodiment, the connection interface circuit 230 may be packaged with the memory controller 210 in a chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210.

In the present embodiment, the host memory 120 is used for temporarily storing instructions or data executed by the processor 110. For example, in the present embodiment, the host Memory 120 may be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), and the like. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may be other suitable memories.

The memory controller 210 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 220 according to commands of the host system 10.

More specifically, the processor 211 in the memory controller 210 is computing hardware for controlling the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control commands/program codes, and the control commands/program codes are executed to perform data writing, reading and erasing operations during the operation of the memory device 20. In addition, in the embodiment, the control instructions/program codes may also be executed to perform a test data generation operation, so as to implement the test data generation method provided by the present invention.

It should be noted that, in the embodiment, the Processor 110 and the Processor 211 are, for example, a Central Processing Unit (CPU), a Microprocessor (micro-Processor), or other Programmable Processing Unit (Microprocessor), a Digital Signal Processor (DSP), a Programmable controller, an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), or other similar circuit elements, and the invention is not limited thereto.

In one embodiment, the memory controller 210 further has a read only memory (not shown) and a random access memory (not shown). In particular, the rom has a boot code (bootstrap code), and when the memory controller 210 is enabled, the processor 211 executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 220 into the ram of the memory controller 210. Then, the processor 211 operates the control commands to perform data writing, reading, and erasing operations. In another embodiment, the control instructions of the processor 211 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 220, for example, in a physical storage unit of the rewritable nonvolatile memory module 220 dedicated for storing system data.

In the present embodiment, as described above, the memory controller 210 further includes the data management circuit 212 and the memory interface control circuit 213. It should be noted that the operations performed by the components of the storage controller 210 may also be referred to as operations performed by the storage controller 210.

The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used for receiving an instruction from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written into the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation is performed according to a write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more memory cells of the one or more physical units), and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read command from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

The memory interface control circuit 213 is used to receive an instruction from the processor 211, and cooperate with the data management circuit 212 to perform a writing (also called Programming) operation, a reading operation or an erasing operation on the rewritable nonvolatile memory module 220.

For example, the processor 211 can execute a write command sequence to instruct the memory interface control circuit 213 to write data into the rewritable nonvolatile memory module 220; the processor 211 can execute a read instruction sequence to instruct the memory interface control circuit 213 to read data from one or more physical units of the rewritable nonvolatile memory module 220 corresponding to the read instruction; the processor 211 can execute an erase command sequence to instruct the memory interface control circuit 213 to perform an erase operation on the rewritable nonvolatile memory module 220. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 220 to perform corresponding operations of writing, reading, and erasing. In one embodiment, the processor 211 may also issue other types of instruction sequences to the memory interface control circuit 213 to perform corresponding operations on the rewritable nonvolatile memory module 220.

In addition, the data to be written into the rewritable nonvolatile memory module 220 is converted into a format accepted by the rewritable nonvolatile memory module 220 through the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable nonvolatile memory module 220, the processor 211 transmits a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, the command sequences may include a write command sequence for instructing writing data, a test data write command sequence for instructing writing test data, a read command sequence for instructing reading data, an erase command sequence for instructing erasing data, and corresponding command sequences for instructing various memory operations. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

In addition, the memory controller 210 establishes a Logical To Physical address mapping table (Logical To Physical address mapping table) and a Physical To Logical address mapping table (Physical To Logical address mapping table) To record an address mapping relationship between a Logical unit (e.g., a Logical block, a Logical page, or a Logical sector) and a Physical unit (e.g., a Physical erase unit/a Physical block, a Physical page, a Physical sector) configured To the rewritable nonvolatile memory module 220. In other words, the memory controller 210 may look up an entity unit mapped by a logic unit (e.g., look up an entity page mapped by a logic page; look up an entity address mapped by a logic address) through the logical-to-entity address mapping table, and the memory controller 210 may look up a logic unit mapped by an entity unit (e.g., look up a logic page mapped by an entity page; look up a logic address mapped by an entity address) through the entity-to-logic address mapping table. However, the technical concepts related to the mapping of the logical units and the physical units are conventional and not intended to be described in the present invention, and are not described herein again

In the present embodiment, the error checking and correcting circuit 214 is coupled to the processor 211 and is used for performing an error checking and correcting procedure to ensure the correctness of the data. Specifically, when the processor 211 receives a write command from the host system 10, the ECC and ECC circuit 214 generates an Error Correction Code (ECC) and/or an EDC (EDC) for data corresponding to the write command, and the processor 211 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 220. Thereafter, when the processor 211 reads data from the rewritable nonvolatile memory module 220, the corresponding error correction code and/or error check code is simultaneously read, and the error checking and correcting circuit 214 performs an error checking and correcting process on the read data according to the error correction code and/or error check code. In addition, after the Error checking and correcting process, if the read data is successfully decoded, the Error checking and correcting circuit 214 may return an Error bit value to the processor 211. If the number of error bits corresponding to a piece of data is higher, the processor 211 may determine that the physical state of the physical unit (e.g., physical sector/physical page/physical block) for storing the data is worse.

In one embodiment, the memory controller 210 further includes a buffer memory 216 and a power management circuit 217. The buffer memory is coupled to the processor 211 and is used for temporarily storing data and instructions from the host system 10, data from the rewritable nonvolatile memory module 220, or other system data for managing the storage device 20, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 216. The power management circuit 217 is coupled to the processor 211 and is used to control the power of the memory device 20.

The rewritable nonvolatile memory module 220 is coupled to the memory controller 210 (the memory interface control circuit 213) and is used for storing data written by the host system 10. The rewritable nonvolatile memory module 220 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 Bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module capable of storing 4 bits in one memory Cell), a three-dimensional NAND flash memory module (3D NAND flash memory module), or a Vertical flash memory module (Vertical flash memory module) or other same flash memory modules having the same memory module A memory module of a nature. The Memory cells (also called Memory cells) in the rewritable nonvolatile Memory module 220 are arranged in an array.

In the embodiment, the rewritable nonvolatile memory module 220 has a plurality of word lines, wherein each of the word lines is coupled to a plurality of memory cells. A plurality of memory cells on the same word line constitute a physical program cell (also called a physical page). In addition, a plurality of physical pages may constitute one physical block (also called physical erase unit).

In the present embodiment, the minimum unit of the data size of the write data written into the rewritable non-volatile memory module 220 at a time is a Cluster (Cluster). The operating system executed by the host system 10 accesses/manages data written to the logical pages using the cluster as a minimum unit, and the operating system can grasp/manage the logical address and size of each data. The size of one cluster may be smaller than or equal to the size of one physical page. One cluster may have a plurality of sectors (sectors). The size of one cluster may be less than or equal to one logical page.

For convenience of explanation, in the following embodiments, the size of one cluster is equal to the size of one physical page, and the size of one physical page is also equal to the size of one logical page. Further, assume that the size of each physical page of the rewritable non-volatile memory module 220 is 1024 Bytes (Bytes). However, it should be noted that the present invention is not limited to the size of each physical page, logical page, cluster.

In the present embodiment, the processor 211 may also perform an initialization operation (which may also be referred to as a card-opening operation) by accessing and executing a card-opening program (which is stored in the rewritable non-volatile memory module 220 or the read-only memory in the form of software or firmware). Generally, when the storage device is first connected to the host system 10, the processor 211 performs the initialization operation according to the storage device initialization method provided by the present invention. The storage device initialization method provided by the present invention will be described below with reference to fig. 2.

FIG. 2 is a flowchart illustrating a method for generating test data according to an embodiment of the invention. Referring to fig. 2, in step S21, the processor 211 starts to perform an initialization operation to erase the physical blocks of the rewritable nonvolatile memory module 220, wherein none of the physical blocks is mapped to the logical blocks of the host system, and the physical blocks are grouped into physical pages of the rewritable nonvolatile memory module. Specifically, when the initialization operation is started, the processor 211 first issues an erase command for all the physical blocks of the rewritable nonvolatile memory module to apply an erase voltage to all the physical blocks, thereby ensuring that all the physical blocks can be written with data.

Next, in step S22, the processor 211 writes predetermined data into the physical blocks so that the physical blocks are full of the predetermined data. Specifically, the processor 211 may continue to write the predetermined data into all of the physical blocks until all of the physical blocks are full of the predetermined data (i.e., do not have any remaining available space).

Next, in step S23, the processor 211 performs a read operation on the plurality of physical pages to obtain the number of page error bits of each of the plurality of physical pages. Specifically, when the processor 211 reads the original data stored in an entity page from the entity page, the processor 211 may instruct the error checking and correcting circuit 214 to perform a decoding operation on the original data according to the corresponding error checking and correcting code to obtain the decoded data and the corresponding number of error bits (i.e., the number of page error bits).

In another embodiment, the processor 211 may not perform a decoding operation on the read original data, and directly compare the differences between the bit values of the predetermined data and the bit values of the original data to obtain the number of error bits. For example, the bit values of a piece of original data stored in a physical page are all equal to the bit values of the predetermined data, and the processor 211 can identify that the number of error bits (page error bits) of the original data read from the physical page is zero.

Next, in step S24, the processor 211 obtains a block error bit number of each of the plurality of physical blocks according to the page error bit number of each of the plurality of physical pages. Specifically, after obtaining the number of Error Bits of each physical page, the processor 211 may sum the number of Error Bits of all the physical pages in each physical Block to obtain a sum as the number of Block Error Bits (BEB) of each physical Block.

Next, in step S25, the processor 211 identifies physical conditions of each of the plurality of physical blocks according to the number of page error bits of each of the plurality of physical pages and the number of block error bits of each of the plurality of physical blocks, and sorts the plurality of physical blocks according to the physical conditions to obtain a block sequence, wherein a front-most physical block in the block sequence has a worst physical condition and a rear-most physical block in the block sequence has a worst physical condition. Details of step S25 will be described below with reference to fig. 3.

Fig. 3 is a flowchart illustrating step S25 in fig. 2 according to an embodiment of the present invention. Referring to fig. 3, in step S251, the processor 211 marks one or more target physical pages of the plurality of physical pages having the page error bit number greater than the page error bit number threshold as bad physical pages. Specifically, the processor 211 may compare the page error bit number of each entity page with a preset threshold value of the page error bit number, and identify the entity page to which the page error bit number greater than the threshold value of the page error bit number belongs as a bad entity page.

Next, in step S252, the processor 211 sums the number of the Bad entity pages that each of the plurality of entity blocks has as a total number of Bad entity pages (BPA). The following describes the process of steps S251 to S252 in detail with reference to fig. 4.

Fig. 4 is a schematic diagram illustrating marking a bad entity page according to an embodiment of the present invention. Referring to fig. 4, for example, for convenience of illustration, it is assumed that one physical block 400 has 8 physical pages 400(1) to 400(8), and the processor 211 has obtained error bits corresponding to the 8 physical pages 400(1) to 400(8), which are "342", "718", "54", "1039", "72", "3", "457" and "361", respectively. Further, it is assumed that the threshold value of the number of page error bits is set to 500 in advance.

In the example of fig. 4, processor 211 compares the threshold number of bits error of page "500" with the number of bits error "342", "718", "54", "1039", "72", "3", "457", "361" of physical pages 400(1) to 400(8) one by one to identify the bad physical pages as physical page 400(2) and physical page 400(4) (as indicated by arrow a 41). Next, the processor 211 sums the number of bad entity pages in the entity block 400, and obtains a total number "2" of bad entity pages (the entity block 400 has 2 bad entity pages in total).

On the other hand, it is noted that, according to the error bit numbers "342", "718", "54", "1039", "72", "3", "457" and "361" of the entity pages 400(1) to 400(8), the processor 211 may calculate the block error bit number 3046 of the entity block 400 (i.e., 342+718+54+1039+72+3+457+361 ═ 3046).

Referring back to fig. 3, in step S253, the processor 211 performs a first sorting on the plurality of physical blocks according to the total number of bad physical pages of each of the plurality of physical blocks from large to small, so as to obtain a first block sequence. Specifically, after obtaining the total number of bad physical pages of each of the plurality of physical blocks, the processor 211 may perform a first sorting with the total number of bad physical pages as a reference to preliminarily sort the plurality of physical blocks into a first block sequence. In a first sorting operation, the processor 211 determines the physical condition of each physical block using the total number of bad physical pages as a reference (the physical condition of the physical block with the larger total number of bad physical pages is worse).

It should be noted that, in this step, for a plurality of physical blocks (also referred to as target physical blocks) having the same number of bad physical pages, the processor 211 does not care about the ordering of the target physical blocks (the processor 211 processes the ordering among the target physical blocks in step S254).

In step S254, in response to that the total number of the bad entity pages of each of the target entity blocks is equal, the processor 211 performs a second sorting on the target entity blocks according to the block error bit number of each of the target entity blocks from large to small, so as to update the first block sequence to be the block sequence. Specifically, in order to further distinguish the physical conditions among a plurality of target physical blocks having the same total number of bad physical pages, the processor 211 further compares the physical conditions of the plurality of physical blocks by using the block error bits of the plurality of target physical blocks as a reference. The following describes the process of steps S253 to S254 in detail with reference to fig. 5.

Fig. 5 is a diagram illustrating obtaining a block sequence and removing a physical block from the block sequence according to an embodiment of the invention. Referring to FIG. 5, for example, for convenience of illustration, it is assumed that the rewritable nonvolatile memory module has 8 physical blocks 400-407, and the physical blocks 400-407 are sorted into an original sequence 500 according to their respective physical addresses. It should be noted that the original sequence 500, the first block sequence 501, and the second block sequence/block sequence 502 described below are only sequences formed by conceptually/abstractly sorting a plurality of physical blocks, and are not physical/physical sorting of the physical blocks.

The processor 211 obtains the total number of bad physical pages and the number of block error bits (which can be identified as information representing the physical condition of the physical blocks 400-407) of each of the 8 physical blocks 400-407 through the above-described manner. As shown in fig. 5, the total number of bad entity pages of the corresponding entity block 400 is "2", and the number of block error bits is "3046"; the total number of bad entity pages corresponding to the entity block 401 is "5", and the number of block error bits is "2645"; the total number of bad entity pages corresponding to the entity block 402 is "2", and the number of block error bits is "3752"; the total number of bad entity pages corresponding to the entity block 403 is "1", and the number of block error bits is "942"; the total number of bad entity pages corresponding to the entity block 404 is "3", and the number of block error bits is "3339"; the total number of bad entity pages corresponding to the entity block 405 is "3", and the number of block error bits is "1834"; the total number of bad entity pages corresponding to the entity block 406 is "7", and the number of block error bits is "6123"; the total number of bad entity pages of the corresponding entity block 407 is "3", and the number of block error bits is "2346".

Then, as shown by arrow a51, the processor 211 performs a first sorting, sorting the physical blocks 400-407 according to the total number of bad physical pages of each physical block from small to large, and obtaining a first block sequence 501. For example, through the original sequence 500 and the first block sequence 501 in fig. 5, it can be seen that the entity blocks 400, 401, 402, 403, 404, 405, 406, 407 of the corresponding original sequence have been sorted into the entity blocks 400, 401, 402, 403, 404, 405, 406, 407 in the first block sequence 501, wherein the total number of bad entity pages of each entity block 400, 401, 402, 403, 404, 405, 406, 407 is "7", "5", "3", "2", "1".

As shown by the lines 501(1) and 501(2), the total number of bad physical pages of the physical blocks 404, 405, 407 is equal (all 3); the total number of bad physical pages in each of the physical blocks 400, 402 is equal (both are 2). The processor 211 may identify the physical blocks 404, 405, 407 as target physical blocks 404, 405, 407, identify the physical blocks 400, 402 as target physical blocks 400, 402, and perform a further sorting (i.e., a second sorting) on the target physical blocks of the different groups, respectively.

For example, as shown by arrow a52, for the group of target physical blocks 404, 405, 407 in the block line 501(1), the processor 211 performs a further second sorting on the target physical blocks 404, 405, 407 by using the block error bits numbers "3339", "1834", "2345", respectively, of the target physical blocks 404, 405, 407 from large to small; for the group of target blocks 400, 402 in the frame lines 501(2), the processor 211 further performs a second sorting of the target blocks 404, 405, 407 by using the respective numbers of block error bits "3046", "3752" of the target blocks 400, 402 from large to small.

That is, the target physical blocks 404, 405, 407 are reordered into the target physical blocks 404, 407, 405 based on the block error bits numbers "3339", "1834", "2345" of the target physical blocks 404, 405, 407; based on the respective block error bits "3046" and "3752" of the target entity blocks 400 and 402, the target entity blocks 400 and 402 are reordered into the target entity blocks 402 and 400.

After the target physical blocks of the groups are reordered, the first block sequence 501 is updated to a second block sequence 502, and the processor 211 may use the second block sequence 502 as the block sequence to be obtained (i.e., the block sequence described in step S254).

Referring back to fig. 2, after the block sequence is processed through the first sorting and the second sorting, in step S26, the processor 211 determines whether the total space of all the physical blocks in the block sequence is equal to the first predetermined space. Specifically, the size of all physical blocks (also referred to as the original space (corresponding to the original sequence)) of the rewritable nonvolatile memory module 220 is larger than the expected space of the storage device 20 (e.g., the size of the space marked on the tag of the storage device on the device/the predetermined size) when the initialization operation is just started. The processor 211 may preset a size of the first predetermined space to be larger than a size of the desired space and smaller than a size of the original space.

In response to determining that the total space of all the physical blocks in the block sequence is not equal to the first predetermined space, performing step S27(S27 → no); in response to determining that the total space of all physical blocks in the block sequence is equal to the first predetermined space (S27 → Yes), step S28 is performed.

In step S27, the processor 211 removes the first-ordered physical block from the block sequence, and updates the block sequence, wherein all physical blocks in the block sequence are the first physical block. Specifically, if step S27 is executed, it indicates that the processor 211 considers that the total size of all physical blocks in the current block sequence has not yet decreased to the size of the first predetermined space, and can remove/remove the physical block with the worst physical condition from all the first physical blocks in the block sequence. As indicated by arrow a53 of fig. 5, the processor 211 selects the physical block ordered at the top of the block sequence 502 for removal (i.e., deletes the physical block 406 from the block sequence 502).

In step S28, the processor 211 completes the initialization operation, and selects a total space of a plurality of second physical blocks in a plurality of first physical blocks in the block sequence as a second predetermined space, wherein the size of the second predetermined spaces is a predetermined size. Specifically, if step S27 is executed, it indicates that the processor 211 considers that the total size of all physical blocks in the current block sequence has decreased to the size of the first predetermined space, and does not need to continuously remove the physical block with the worst physical condition in the block sequence. That is, the process of eliminating one or more physical blocks with poor physical conditions is completed, and the processor 211 may select a plurality of second physical blocks with a total space size equal to the second predetermined space size from a plurality of first physical blocks (the total space is equal to the first predetermined space) in the current block sequence, so that the plurality of second physical blocks may be mapped to a plurality of logical blocks of the host system 10.

It should be noted that the second predetermined space may also be referred to as a desired space. The predetermined size is a predetermined capacity that can be used by the host system 10.

It should be noted that the processor 211 records the physical address of the physical block removed in step S27 in the bad physical block table. The Bad Block Table is also called Bad Block Table (Bad Block Table). The processor 2111 may identify one or more bad physical blocks in the bad block table that will not be used. In this way, one or more bad blocks in the bad block table that have been determined to be physically bad are prevented from being used by the host system 10 or the storage device 20. In other words, the storage device initialization method provided by the present embodiment can ensure that the physical condition of other physical blocks (the first physical blocks in the finally obtained block sequence) that are not recorded in the bad physical block table is better, so as to ensure that data can be stored in the other physical blocks with better physical condition later, thereby achieving higher data storage reliability (the stored data is less prone to errors).

Based on the above, the memory controller and the method for initializing a memory device according to the embodiments of the present invention can obtain the number of error bits corresponding to each physical page by performing an erase operation, a write operation, and a read operation on all the physical blocks and the physical pages in an initialization operation performed on the memory device, so that one or more physical blocks with poor physical conditions can be removed according to the number of error bits corresponding to each physical page in a case of meeting a predetermined size of the memory device, so that the host system can only use the physical blocks with better physical conditions. Therefore, after the initialization operation is completed, the host system can be prevented from using the removed entity blocks with poor physical conditions, and the reliability of the storage data of the storage device is improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.