阅读说明：本技术 一种集成esd结构的高压平面vdmos器件及制造方法 (High-voltage plane VDMOS device integrated with ESD structure and manufacturing method ) 是由 刘秀梅 周祥瑞 刘锋 于 2021-02-04 设计创作，主要内容包括：本发明涉及一种集成ESD结构的高压平面VDMOS器件及制造方法,包括有源区、终端保护区及过渡区,过渡区包括ESD静电保护区,其包括第一导电类型漂移区、第一导电类型衬底及场氧化层,在场氧化层上设有多个串联的环形多晶硅二极管单元,环形多晶硅二极管单元包括两个背靠背设置的二极管,在靠近有源区一端的二极管的正极穿过绝缘介质层与位于其上方的源极金属欧姆接触,在靠近终端保护区一端的二极管的正极穿过绝缘介质层与位于其上方的栅极金属欧姆接触。本发明在栅极和源极间设置多个多晶硅二极管单元,多个多晶硅二极管单元以环形的形式设置在过渡区,不暂用有源区和终端保护区的面积,既不影响器件的性能,又提升了器件的ESD静电防护能力。(The invention relates to a high-voltage plane VDMOS device of an integrated ESD structure and a manufacturing method thereof, and the device comprises an active region, a terminal protection region and a transition region, wherein the transition region comprises an ESD electrostatic protection region which comprises a first conduction type drift region, a first conduction type substrate and a field oxide layer, a plurality of serially connected annular polycrystalline silicon diode units are arranged on the field oxide layer, each annular polycrystalline silicon diode unit comprises two diodes which are arranged back to back, the anode of the diode close to one end of the active region penetrates through an insulating medium layer to be in ohmic contact with a source electrode metal positioned above the diode, and the anode of the diode close to one end of the terminal protection region penetrates through the insulating medium layer to be in ohmic contact with a grid electrode metal positioned above the diode. According to the invention, the plurality of polysilicon diode units are arranged between the grid electrode and the source electrode, and are arranged in the transition region in an annular form, so that the areas of the active region and the terminal protection region are not used temporarily, the performance of the device is not influenced, and the ESD electrostatic protection capability of the device is improved.)

1. A high-voltage planar VDMOS device with an integrated ESD structure, comprising an active region (100), a termination protection region (102) surrounding said active region (100), and a transition region (101) between said termination protection region (102) and said active region (100), characterized in that: the transition region (101) comprises an ESD electrostatic protection region (1011); on a cross section of the VDMOS device, the ESD electrostatic protection (1011) region comprises a first conductive type drift region (2), a first conductive type substrate (1) which is positioned below and adjacent to the first conductive type drift region (2), and a field oxide layer (4) which is positioned above the first conductive type drift region (2), a plurality of annular polysilicon diode units (5) are arranged on the field oxide layer (4), the annular polycrystalline silicon diode units (5) are connected in series, the annular polycrystalline silicon diode units (5) comprise two diodes which are arranged back to back, the anode of the diode close to one end of the active region (100) is in ohmic contact with the source metal (10) positioned above the anode through the insulating medium layer (7), and the anode of the diode close to one end of the terminal protection region (102) is in ohmic contact with the gate metal (8) positioned above the diode through the insulating medium layer (7).

2. The ESD structure integrated high-voltage planar VDMOS device of claim 1, wherein: the terminal protection area (102) comprises a partial voltage protection area and a cut-off area, the cut-off area is located on the outer circle of the terminal protection area (102), and the partial voltage protection area is located between the ESD electrostatic protection area (1011) and the cut-off area.

3. A high-voltage planar VDMOS device integrated with an ESD structure according to claim 2, wherein: on the cross section of the VDMOS device, at least one field limiting ring (3) is included in the partial pressure protection region, and the field limiting ring (3) is positioned in the first conduction type drift region (2); the utility model discloses a solar energy field limiting device, including field limiting ring (3), field oxide (4) top covers has field oxide (4), field oxide (4) top is equipped with superficial empty conductive polysilicon (6), superficial empty conductive polysilicon (6) top is equipped with superficial empty metal (9), it separates through insulating medium layer (7) to float empty conductive polysilicon (6) and superficial empty metal (9) within a definite time.

4. A high-voltage planar VDMOS device integrated with an ESD structure according to claim 2, wherein: on the cross section of the VDMOS device, the cut-off region comprises a second conduction type cut-off well region (14) located in the first conduction type drift region (2) and a first conduction type cut-off source region (15) located in the second conduction type cut-off well region (14), a cut-off ring metal (12) and a cut-off conductive polysilicon (13) are arranged above the first conduction type cut-off source region (15), and the cut-off ring metal (12) penetrates through an insulating medium layer (7) to be in ohmic contact with the first conduction type cut-off source region (15) and the cut-off conductive polysilicon (13) respectively.

5. The ESD structure integrated high-voltage planar VDMOS device of claim 1, wherein: on the cross section of the VDMOS device, the active region (100) comprises a plurality of cell units which are arranged in parallel, each cell unit comprises a second conduction type well region (16) located in the first conduction type drift region (2), a first conduction type source region (17) located in the second conduction type well region (16), a gate oxide layer (18) covering the first conduction type drift region (2), gate conduction polycrystalline silicon (19) covering the gate oxide layer (18), an insulating medium layer (7) covering the gate conduction polycrystalline silicon (19), and a source metal (10) covering the insulating medium layer (7), wherein the source metal (10) penetrates through the insulating medium layer (7) to be in ohmic contact with the second conduction type well region (16) and the first conduction type source region (17).

6. A manufacturing method of a high-voltage plane VDMOS device integrated with an ESD structure comprises the following steps:

a. providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type drift region (2) and a first conduction type substrate (1) positioned below the first conduction type drift region (2), the upper surface of the first conduction type drift region (2) is a first main surface (001) of the semiconductor substrate, and the lower surface of the first conduction type substrate (1) is a second main surface (002) of the semiconductor substrate;

b. depositing a hard mask layer on the first main surface (001) of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned first hard mask window (20);

c. implanting ions of a second conductivity type into the first main face (001) under the masking of the first hard mask window (20) and trapping to obtain a plurality of field limiting rings (3) located in the drift region (2) of the first conductivity type, and removing the first hard mask window (20);

d. growing a thick oxide layer on the first main surface (001) of the semiconductor substrate, and etching the thick oxide layer to obtain a field oxide layer (4) on the first main surface (001);

e. growing an oxide layer and depositing conductive polysilicon on the field oxide layer (4) and the first main surface (001) of the semiconductor substrate, and etching the oxide layer and the conductive polysilicon in turn to obtain gate conductive polysilicon (19) positioned in the cell region (100), a gate oxide layer (18) positioned below the gate conductive polysilicon (19), conductive polysilicon positioned on the field oxide layer (4) of the transition region (101), floating conductive polysilicon (6) positioned on the field oxide layer (4) of the terminal protection region (102), and cut-off conductive polysilicon (13);

f. implanting second conductivity type ions into the first main surface (001) of the semiconductor substrate, and annealing to obtain a second conductivity type well region (16) located in the active region (100) and the transition region (101) and a second conductivity type cut-off well region (14) located in the cut-off region (102);

g. selectively implanting first conductivity type ions into a first main surface (001) of the semiconductor substrate to obtain a first conductivity type source region (17) located in a second conductivity type well region (16) of the active region (100) and a first conductivity type stop source region (15) located in a second conductivity type stop well region (14) of the stop region (102);

h. depositing a hard mask layer on the first main surface (001) of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned second hard mask window (21);

i. implanting second conductivity type ions into the conductive polysilicon under the masking of the second hard mask window (21), annealing to obtain a plurality of annular polysilicon diode units (5) on the field oxide layer (4) of the transition region (101), and removing the second hard mask window (21);

j. depositing an insulating medium layer (7) on the first main surface (001), and etching the insulating medium layer (7) to obtain a plurality of metal contact holes;

k. depositing metal in the metal contact hole and on the insulating medium layer (7), and etching the metal to obtain source metal (10), grid metal (8), floating metal (9) and stop ring metal (12);

and l, thinning the second main surface (002) of the semiconductor, and then depositing metal to obtain drain metal (11) positioned on the lower surface of the first conduction type substrate (1).

7. The method of claim 6, wherein the method comprises the steps of: and in the h and the i, selectively masking and etching the hard mask layer to obtain a second hard mask window (21) for second conductive type ion implantation on the conductive polycrystalline silicon layer, and implanting second conductive type impurity ions under the masking of the second hard mask window (21) to obtain a plurality of annular polycrystalline silicon diode units (5), wherein the annular polycrystalline silicon diode units (5) comprise a second conductive area, a first conductive area and a second conductive area which are sequentially connected, and the second conductive area, the first conductive area and the second conductive area which are sequentially connected form back-to-back diode units.

8. The method of claim 6, wherein the method comprises the steps of: in the k, in the cell region (100), the source metal (10) is in ohmic contact with the second conductivity type body region (16) and the first conductivity type source region (17), respectively; in the transition region (101), the source metal (10) is in ohmic contact with the anode of the annular polycrystalline silicon diode unit (5) close to one end of the active region (100), and the gate metal (8) is in ohmic contact with the anode of the annular polycrystalline silicon diode unit (5) close to one end of the terminal protection region (102); in the terminal protection region (102), the stop ring metal (12) is in ohmic contact with the first conduction type stop source region (15) and the stop conductive polysilicon (13) respectively.

9. The integrated ESD structure high-voltage planar VDMOS device and method of fabrication according to claim 1 or 6, wherein: for an N-type MOSFET device structure, the first conductivity type is N-type conductivity, the second conductivity type is P-type conductivity, the first conductivity region is an N-conductivity region, and the second conductivity region is a P-conductivity region; for a P-type MOSFET device structure, the first conductivity type is P-type conductivity, the second conductivity type is N-type conductivity, the first conductivity region is a P-conductivity region, and the second conductivity region is an N-conductivity region.

Technical Field

The invention relates to a power semiconductor device, in particular to a high-voltage plane VDMOS device integrated with an ESD structure and a manufacturing method thereof, belonging to the technical field of power semiconductor devices.

Background

Power MOSFET devices are susceptible to electrostatic discharge (ESD) during packaging, shipping, assembly and use, which can comprise hundreds of nanojoules of energy and generates about 3000V, which can damage almost all semiconductor devices and semiconductor integrated circuits. Since ESD is common in many operating environments, more and more semiconductor devices are equipped with independent ESD protection designs in pursuit of higher yield and device reliability.

In the common design method in the prior art design, Zener diodes with different groups are connected between a grid electrode and a source electrode, and when static electricity occurs, the Zener diodes can be broken down before a grid electrode oxide layer, so that voltage and current are discharged instantly, and the MOSFET is protected from being damaged.

The existing design of the planar VDMOS with the ESD protection structure has several forms:

1) the ESD protection structure is arranged in the active region, but the area of the active region is often temporarily used, so that the characteristic resistance of the device is seriously influenced, the on-resistance is increased, and the on-loss is further increased;

2) the ESD protection structure is arranged in the terminal protection area, so that the terminal area can be temporarily used, the voltage-resistant characteristic of the terminal of the device is influenced, the voltage-resistant performance of the device is reduced, and the reliability is reduced.

Disclosure of Invention

The invention aims to overcome the defects in the prior power MOSFET device technology and provide a high-voltage planar VDMOS device integrated with an ESD structure and a manufacturing method thereof.

In order to achieve the technical purpose, the technical scheme of the invention is as follows: a high-voltage plane VDMOS device of an integrated ESD structure comprises an active region, a terminal protection region surrounding the active region and a transition region located between the terminal protection region and the active region, and is characterized in that: the transition region comprises an ESD electrostatic protection region; on the cross-section of VDMOS device, ESD electrostatic protection district includes first conductivity type drift region, is located first conductivity type drift region below and the first conductivity type substrate that borders on and be located the field oxide layer of first conductivity type drift region top be equipped with a plurality of annular polycrystalline silicon diode units on the field oxide layer, establish ties between a plurality of annular polycrystalline silicon diode units, annular polycrystalline silicon diode unit includes two diodes that set up back to back, is being close to the positive pole of the diode of active area one end passes insulating medium layer and the source electrode metal ohmic contact who is located its top, is being close to the positive pole of the diode of terminal protection district one end passes insulating medium layer and the grid metal ohmic contact who is located its top.

Further, the terminal protection area comprises a partial pressure protection area and a cut-off area, the cut-off area is located on the outer ring of the terminal protection area, and the partial pressure protection area is located between the ESD electrostatic protection area and the cut-off area.

Further, on the cross section of the VDMOS device, at least one field limiting ring is included in the partial pressure protection region, and the field limiting ring is located in the first conduction type drift region; the field limiting ring is covered with a field oxide layer, a floating conductive polysilicon layer is arranged above the field oxide layer, a floating metal is arranged above the floating conductive polysilicon layer, and the floating conductive polysilicon layer and the floating metal are separated by an insulating medium layer.

Further, on the cross section of the VDMOS device, the cut-off region includes a second conductivity type cut-off well region located in the first conductivity type drift region, and a first conductivity type cut-off source region located in the second conductivity type cut-off well region, a cut-off ring metal and a cut-off conductive polysilicon are disposed above the first conductivity type cut-off source region, and the cut-off ring metal passes through the insulating medium layer and is in ohmic contact with the first conductivity type cut-off source region and the cut-off conductive polysilicon, respectively.

Further, on the cross section of the VDMOS device, the active region includes a plurality of cell units arranged in parallel, each cell unit includes a second conductive type well region located in the first conductive type drift region, a first conductive type source region located in the second conductive type well region, a gate oxide layer covering the first conductive type drift region, a gate conductive polysilicon covering the gate oxide layer, an insulating dielectric layer covering the gate conductive polysilicon, and a source metal covering the insulating dielectric layer, and the source metal passes through the insulating dielectric layer and is in ohmic contact with the second conductive type well region and the first conductive type source region respectively.

In order to further achieve the above technical object, the present invention further provides a method for manufacturing a high voltage planar VDMOS device integrated with an ESD structure, including the following steps:

a. providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type drift region and a first conduction type substrate positioned below the first conduction type drift region, the upper surface of the first conduction type drift region is a first main surface of the semiconductor substrate, and the lower surface of the first conduction type substrate is a second main surface of the semiconductor substrate;

b. depositing a hard mask layer on the first main surface of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned first hard mask window;

c. under the shielding of the first hard mask window, injecting second conductive type ions into the first main surface, carrying out trap pushing to obtain a plurality of field limiting rings positioned in the first conductive type drift region, and removing the first hard mask window;

d. growing a thick oxide layer on the first main surface of the semiconductor substrate, and etching the thick oxide layer to obtain a field oxide layer on the first main surface;

e. growing an oxide layer and depositing conductive polycrystalline silicon on the field oxide layer and the first main surface of the semiconductor substrate, and etching the oxide layer and the conductive polycrystalline silicon in turn to obtain gate conductive polycrystalline silicon positioned in a cell region, a gate oxide layer positioned below the gate conductive polycrystalline silicon, conductive polycrystalline silicon positioned on the field oxide layer of a transition region, floating conductive polycrystalline silicon positioned on the field oxide layer of a terminal protection region and cut-off conductive polycrystalline silicon;

f. implanting second conductivity type ions into the first main surface 001 of the semiconductor substrate, and annealing to obtain a second conductivity type well region 16 located in the active region 100 and the transition region 101 and a second conductivity type stop well region 14 located in the cut-off region 102;

g. selectively implanting first conductivity type ions into the first main surface 001 of the semiconductor substrate to obtain a first conductivity type source region 17 located in the second conductivity type well region 16 of the active region 100 and a first conductivity type stop source region 15 located in the second conductivity type stop well region 14 of the stop region 102;

h. depositing a hard mask layer on the conductive polysilicon, and selectively etching the hard mask layer to obtain a patterned second hard mask window;

i. under the masking of the second hard mask window, injecting second conductive type ions into the conductive polysilicon, annealing to obtain a plurality of annular polysilicon diode units on the field oxide layer of the transition region, and removing the second hard mask window;

j. depositing an insulating medium layer on the first main surface, and etching the insulating medium layer to obtain a plurality of metal contact holes;

k. depositing metal in the metal contact hole and on the insulating medium layer, and etching the metal to obtain source metal, grid metal, floating metal and stop ring metal;

and l, thinning the second main surface of the semiconductor, and then depositing metal to obtain drain metal positioned on the lower surface of the first conduction type substrate.

Further, in the h and i, a second hard mask window for second conductive type ion implantation is obtained on the conductive polycrystalline silicon layer by selectively masking and etching the hard mask layer, and second conductive type impurity ion implantation is performed under the masking of the second hard mask window to obtain a plurality of annular polycrystalline silicon diode units, wherein each annular polycrystalline silicon diode unit comprises a P conductive region, an N conductive region and a P conductive region which are sequentially connected, and the P conductive region, the N conductive region and the P conductive region which are sequentially connected form a back-to-back diode unit.

Further, in the k, in the cell region, the source metal is in ohmic contact with the second conductive type body region and the first conductive type source region respectively; in the transition region, the source metal is in ohmic contact with the anode of the annular polycrystalline silicon diode unit close to one end of the active region, and the gate metal is in ohmic contact with the anode of the annular polycrystalline silicon diode unit close to one end of the terminal protection region; in the terminal protection region, the cut-off ring metal is in ohmic contact with the first conductive type cut-off source region and the cut-off conductive polysilicon respectively.

Further, for an N-type MOSFET device structure, the first conductivity type is N-type conductivity, the second conductivity type is P-type conductivity, the first conductivity region is an N-conductivity region, and the second conductivity region is a P-conductivity region; for a P-type MOSFET device structure, the first conductivity type is P-type conductivity, the second conductivity type is N-type conductivity, the first conductivity region is a P-conductivity region, and the second conductivity region is an N-conductivity region.

Compared with the prior art, the invention has the following advantages:

1) the ESD electrostatic protection area is arranged in the transition area between the active area and the terminal protection area in an annular form, so that the area of the transition area is effectively utilized, the area of the terminal is not occupied, and the area of the active area is not occupied, so that the parameter performance of the device is not influenced;

2) the field oxide layer is provided with a plurality of field limiting rings in the first conduction type drift region, the field limiting rings are used for bearing the withstand voltage, and the polysilicon diode unit on the field oxide layer of the transition region is arranged between the grid metal and the source metal without bearing the withstand voltage, so that the withstand voltage performance of the device is not influenced;

3) the ESD electrostatic protection area effectively utilizes the area of the transition area of the device, has compact structure, is compatible with the prior process steps, and is safe and reliable.

Drawings

Fig. 1 is a schematic top view of the structure in embodiment 1 of the present invention.

FIG. 2 is a schematic sectional view showing A-A' in FIG. 1 in example 1 of the present invention.

Fig. 3 is an enlarged structural schematic diagram of the ESD protection region in fig. 2 in embodiment 1 of the present invention.

Fig. 4 is a schematic cross-sectional view of a semiconductor substrate in embodiment 1 of the present invention.

Fig. 5 is a schematic cross-sectional structure diagram of forming a first hard mask window in embodiment 1 of the present invention.

Fig. 6 is a schematic sectional view showing a structure of forming a field limiting ring in embodiment 1 of the present invention.

Fig. 7 is a schematic cross-sectional view of forming a field oxide layer in embodiment 1 of the present invention.

Fig. 8 is a schematic cross-sectional view of the gate oxide layer, the floating conductive polysilicon, the cut conductive polysilicon, and the gate conductive polysilicon formed in embodiment 1 of the present invention.

Fig. 9 is a schematic cross-sectional view of forming a P-type stop well region, an N-type stop source region, a P-type well region, and an N-type source region in embodiment 1 of the present invention.

Fig. 10 is a schematic cross-sectional structure diagram of forming a second hard mask window in embodiment 1 of the present invention.

Fig. 11 is a schematic cross-sectional structure diagram of forming a ring-shaped polysilicon diode cell in embodiment 1 of the present invention.

Fig. 12 is a schematic cross-sectional view of an insulating dielectric layer formed in embodiment 1 of the present invention.

Description of reference numerals: 100-an active region; 101-a transition region; 102-terminal protection zone; 1-a first conductivity type substrate; 2-a first conductivity type drift region; 3-field limiting ring; 4-field oxide layer; 5-ring-shaped polysilicon diode unit; 6-floating conductive polysilicon; 7-insulating dielectric layer; 8-gate metal; 9-floating metal; 10-source metal; 11-drain metal; 12-stop ring metal; 13-cutting off the conductive polysilicon; 14-a second conductivity type off well region; 15-first conductivity type off source region; 16-a second conductivity type well region; 17-a first conductivity type source region; 18-a gate oxide layer; 19-gate conductive polysilicon; 20 — a first hard mask window; 21-a second hard mask window; 001-first major face; 002-second major face; 1011-ESD electrostatic protection area.

Detailed Description

The present invention will be further described with reference to the following specific examples.

In the high-voltage planar VDMOS device integrated with the ESD structure in embodiment 1, taking an N-type planar VDMOS as an example, the first conductivity type is an N-type, the second conductivity type is a P-type, the first conductivity region is an N-conductivity region, and the second conductivity region is a P-conductivity region;

as shown in fig. 1 and fig. 2, a high-voltage planar VDMOS device with an integrated ESD structure includes an active region 100, a terminal protection region 102 surrounding the active region 100, and a transition region 101 located between the terminal protection region 102 and the active region 100, where the transition region 101 includes an ESD electrostatic protection region 1011, and the ESD electrostatic protection region 1011 is disposed in the transition region 101 in an annular form;

in the active region 100, on the cross section of the VDMOS device, the active region 100 includes a plurality of cell units arranged in parallel, each cell unit includes a P-type well region 16 located in the N-type drift region 2, an N-type source region 17 located in the P-type well region 16, a gate oxide layer 18 covering the N-type drift region 2, a gate conductive polysilicon 19 covering the gate oxide layer 18, an insulating medium layer 7 covering the gate conductive polysilicon 19, and a source metal 10 covering the insulating medium layer 7, and the source metal 10 penetrates through the insulating medium layer 7 and is in ohmic contact with the P-type well region 16 and the N-type source region 17 respectively.

The terminal protection region 102 comprises a voltage division protection region and a cut-off region, the cut-off region is located at the outer ring of the terminal protection region 102, and the voltage division protection region is located between the ESD electrostatic protection region 1011 and the cut-off region; on the cross section of the VDMOS device, at least one field limiting ring 3 is included in the partial pressure protection region, and the field limiting ring 3 is positioned in the N-type drift region 2; a field oxide layer 4 covers the field limiting ring 3, floating conductive polysilicon 6 is arranged above the field oxide layer 4, floating metal 9 is arranged above the floating conductive polysilicon 6, and the floating conductive polysilicon 6 and the floating metal 9 are separated by an insulating medium layer 7; the cut-off region comprises a P-type cut-off well region 14 located in the N-type drift region 2 and an N-type cut-off source region 15 located in the P-type cut-off well region 14, a cut-off ring metal 12 and a cut-off conductive polysilicon 13 are arranged above the N-type cut-off source region 15, and the cut-off ring metal 12 penetrates through the insulating medium layer 7 to be in ohmic contact with the N-type cut-off source region 15 and the cut-off conductive polysilicon 13 respectively.

In the transition region 101, a P-well 16 located in the N-drift region 2 and a source metal 10 in ohmic contact with the P-well 16 are included between the active region 100 and the ESD protection region 1011;

as shown in fig. 3, in the transition region 101, on the cross section of the VDMOS device, the ESD electrostatic protection region 1011 includes an N-type drift region 2, an N-type substrate 1 located below and adjacent to the N-type drift region 2, and a field oxide layer 4 located above the N-type drift region 2, a plurality of annular polysilicon diode units 5 are disposed on the field oxide layer 4, the annular polysilicon diode units 5 are connected in series, the annular polysilicon diode units 5 include two diodes disposed back to back, the anode of the diode near one end of the active region 100 passes through the insulating medium layer 7 and is in ohmic contact with the source metal 10 located above the insulating medium layer, and the anode of the diode near one end of the terminal protection region 102 passes through the insulating medium layer 7 and is in ohmic contact with the gate metal 8 located above the insulating medium layer.

The method for manufacturing the high-voltage planar VDMOS device integrated with the ESD structure in embodiment 1 includes the following steps:

as shown in fig. 4, a, providing a semiconductor substrate, where the semiconductor substrate includes an N-type drift region 2 and an N-type substrate 1 located below the N-type drift region 2, an upper surface of the N-type drift region 2 is a first main surface 001 of the semiconductor substrate, and a lower surface of the N-type substrate 1 is a second main surface 002 of the semiconductor substrate;

as shown in fig. 5, b, depositing a hard mask layer on the first main surface 001 of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned first hard mask window 20;

as shown in fig. 6, c, under the masking of the first hard mask window 20, implanting P-type ions into the first main surface 001, and trapping to obtain a plurality of field limiting rings 3 located in the N-type drift region 2, and removing the first hard mask window 20;

the patterned first hard mask window 20 is used as a masking layer for implantation of the field limiting ring 3;

as shown in fig. 7, d, growing a thick oxide layer on the first main surface 001 of the semiconductor substrate, and etching the thick oxide layer to obtain a field oxide layer 4 on the first main surface 001;

as shown in fig. 8, e, growing an oxide layer and depositing conductive polysilicon on the field oxide layer 4 and the first main surface 001 of the semiconductor substrate, and etching the oxide layer and the conductive polysilicon in turn to obtain a gate conductive polysilicon 19 located in the cell region 100, a gate oxide layer 18 located below the gate conductive polysilicon 19, conductive polysilicon located on the field oxide layer 4 of the transition region 101, floating conductive polysilicon 6 located on the field oxide layer 4 of the terminal protection region 102, and cut-off conductive polysilicon 13;

as shown in fig. 9, f, implanting P-type ions into the first main surface 001 of the semiconductor substrate, and annealing to obtain P-type well regions 16 located in the active region 100 and the transition region 101 and P-type cut-off well regions 14 located in the cut-off region 102;

g. selectively implanting N-type ions into the first main surface 001 of the semiconductor substrate to obtain an N-type source region 17 located in the P-type well region 16 of the active region 100 and an N-type cut-off source region 15 located in the P-type cut-off well region 14 of the cut-off region;

as shown in fig. 10, h, depositing a hard mask layer on the conductive polysilicon, and selectively etching the hard mask layer to obtain a patterned second hard mask window 21;

as shown in fig. 11, i, under the masking of the second hard mask window 21, implanting P-type ions into the conductive polysilicon, and annealing to obtain a plurality of annular polysilicon diode units 5 located on the field oxide layer 4 of the transition region 101, and removing the second hard mask window 21;

in this embodiment 1, by selectively masking and etching the hard mask layer, a second hard mask window 21 for P-type ion implantation is obtained on the conductive polysilicon layer in the transition region 101, and P-type impurity ion implantation is performed under the masking of the second hard mask window 21, so as to obtain 2 annular polysilicon diode units 5, where each annular polysilicon diode unit 5 includes a P conductive region, an N conductive region, and a P conductive region that are sequentially connected, and the P conductive region, the N conductive region, and the P conductive region that are sequentially connected constitute back-to-back diode units;

the present embodiment 1 includes two back-to-back diode units (i.e. two annular polysilicon diode units 5);

as shown in fig. 12, j, depositing an insulating dielectric layer 7 on the first main surface 001, and etching the insulating dielectric layer 7 to obtain a plurality of metal contact holes;

as shown in fig. 2, k, depositing metal in the metal contact hole and on the insulating dielectric layer 7, and etching the metal to obtain a source metal 10, a gate metal 8, a floating metal 9 and a stop ring metal 12;

in the cell area 100, the source metal 10 is in ohmic contact with the P-type body area 16 and the N-type source area 17 respectively; in the transition region 101, the source metal 10 is in ohmic contact with the anode of the annular polysilicon diode unit 5 close to one end of the active region 100, and the gate metal 8 is in ohmic contact with the anode of the annular polysilicon diode unit 5 close to one end of the terminal protection region 102, so that an ESD electrostatic protection region 1011 is formed; in the terminal protection region 102, the cut-off ring metal 12 is in ohmic contact with the N-type cut-off source region 15 and the cut-off conductive polysilicon 13 respectively;

l, thinning the second main surface 002 of the semiconductor, depositing metal to obtain drain metal 11 positioned on the lower surface of the N-type substrate 1, wherein the drain metal 11 is in ohmic contact with the lower surface of the N-type substrate 1, and manufacturing a planar VDMOS device with an integrated ESD structure is completed;

the invention can change the ESD protection capability of the annular polysilicon diode unit 5 by changing the implantation concentration of the P-type ions in the step i, or can change the number of the annular polysilicon diode units 5 by changing the windowing number of the second hard mask windows 21, thereby changing the electrostatic protection capability of the whole ESD electrostatic protection area 1011.

When the device is voltage-resistant, namely a forward bias voltage is applied to the drain end of the device, the source end and the gate end are grounded, and the breakdown position of the device is positioned at the bottom of the P-type well region 16 in the active region 100; at this time, in the active region 100, a PN junction formed by the N-type drift region 2 and the P-type well region 16 in the active region 100 is reverse biased, and the depletion layer expands toward the N-type drift region 2; in the transition region 101, similarly, a PN junction formed by the N-type drift region 2 and the P-type well region 16 is reversely biased, the depletion layer expands towards the N-type drift region 2 and does not affect the ESD electrostatic protection region 1011, and the field limiting ring 3 below the field oxide layer 4 expands and depletes towards the N-type drift region 2 and is used for bearing voltage resistance and does not affect the ESD electrostatic protection region 1011; in the termination protection region 102, the field limiting ring 3 under the field oxide layer 4 is expanded and exhausted toward the N-type drift region 2, so as to bear the withstand voltage without affecting the ESD electrostatic protection region 1011.

The electrostatic protection capability of the ESD electrostatic protection region 1011 can be adjusted by the number of the annular polysilicon diode units 5 and the concentration of the P conductive region in the annular polysilicon diode units 5;

the ESD electrostatic protection region 1011 is arranged in the transition region 101 between the active region 100 and the terminal protection region 102 in an annular form, so that the area of the transition region 101 is effectively utilized, and the area of the terminal protection region 102 and the area of the active region 100 are not occupied, so that the parameter performance of the device is not influenced; the ESD electrostatic protection structure effectively utilizes the area of the transition region 101 of the device, has a compact structure, is compatible with the prior process steps, and is safe and reliable.

The present invention and its embodiments have been described above, and the description is not intended to be limiting, and the embodiments shown in the drawings are only one embodiment of the present invention, and the actual structure is not limited thereto. In summary, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.