阅读说明：本技术 一种efuse阵列结构及其编程方法和读方法 (EFUSE array structure and programming method and reading method thereof ) 是由 任永旭 蒋宇 沈灵 严慧婕 王新杰 于 2020-12-30 设计创作，主要内容包括：本发明提供了一种EFUSE阵列结构及其编程方法和读方法。EFUSE阵列结构包括列译码电路和行译码电路、以及多个按阵列方式排列的存储单元；每一列上的各EFUSE共用一条编程电源线；每一行上的各编程晶体管共用一条编程字线；每一行上的各读晶体管共用一条读字线；每一列上的各读晶体管共用一条位线；列译码电路将选中的编程电源线设置为高电平,将未选中的编程电源线设置为低电平；行译码电路将选中的编程字线设置为高电平,将未选中的编程字线设置为低电平,将选中的读字线设置为高电平,将未选中的读字线设置为低电平。本方案可以降低读模式下的非读取存储单元的漏电,获得更低的读功耗以及更快的读取速度,节省整个芯片的功耗浪费。(The invention provides an EFUSE array structure and a programming method and a reading method thereof. The EFUSE array structure comprises a column decoding circuit, a row decoding circuit and a plurality of storage units which are arranged in an array mode; each EFUSE on each column shares a programming power line; the programming transistors on each row share a programming word line; the reading transistors on each row share one reading word line; each read transistor on each column shares a bit line; the column decoding circuit sets the selected programming power line to high level and sets the unselected programming power line to low level; the row decoding circuit sets a selected program word line to a high level, sets unselected program word lines to a low level, sets a selected read word line to a high level, and sets unselected read word lines to a low level. The scheme can reduce the electric leakage of the non-read memory unit in the read mode, obtain lower read power consumption and higher read speed, and save the power consumption waste of the whole chip.)

1. An EFUSE array structure is characterized by comprising a column decoding circuit, a row decoding circuit and a plurality of storage units which are arranged in an array mode;

each of the memory cells includes an EFUSE, a program transistor, and a read transistor; one end of the EFUSE is connected with a programming power line, and the other end of the EFUSE is respectively connected with one of a source electrode and a drain electrode of the programming transistor and one of a source electrode and a drain electrode of the reading transistor; the grid electrode of the programming transistor is connected with a programming word line; the grid electrode of the reading transistor is connected with a reading word line, and the other electrode of the source electrode and the drain electrode of the reading transistor is connected with a bit line;

the programming power line is connected with one output end of the column decoding circuit; the programming word line and the reading word line are respectively connected with one output end of the row decoding circuit; the bit line is connected with one input end of the sensitive amplifier, and the other input end of the sensitive amplifier is connected with the reference circuit;

each EFUSE on each column shares a programming power line; each programming transistor on each row shares a programming word line; each reading transistor on each row shares one reading word line; each of the read transistors on each column shares a bit line;

the column decoding circuit sets a selected programming power line to be at a high level and sets unselected programming power lines to be at a low level according to a preset column address, a preset programming signal and a preset reading signal; the row decoding circuit sets a selected programming word line to a high level, sets an unselected programming word line to a low level, sets a selected read word line to a high level, and sets an unselected read word line to a low level according to a preset row address, the programming signal, and the preset read signal.

2. An EFUSE array structure as claimed in claim 1 wherein the program transistor and the read transistor are NMOS transistors.

3. An EFUSE array architecture as claimed in claim 2 wherein said column decode circuit includes a plurality of column decode modules, each of said column decode modules for controlling one of said programming power lines;

each column decoding module comprises a column decoder, a fuse power switch and a first grounding switch, wherein the column decoder comprises a plurality of input ends and an output end, the fuse power switch comprises two input ends and an output end, and the first grounding switch comprises two input ends and an output end;

a plurality of input ends of the column decoder are respectively used for inputting a fuse power supply, the preset column address and the programming signal, and an output end of the column decoder is connected with one input end of the fuse power supply switch and one input end of the first grounding switch;

and the other input end of the fuse wire power switch is used for inputting the fuse wire power supply, and the output end of the fuse wire power switch is connected with the output end of the first grounding switch and then connected with one programming power line.

4. An EFUSE array architecture as claimed in claim 3 wherein said row decode circuit includes a plurality of row decode modules, each said row decode module for controlling one said program wordline and one said read wordline;

each row decoding module comprises a row decoder, a read word line switch, a second grounding switch, a programming word line switch and a third grounding switch, the row decoder comprises a plurality of input ends and two output ends, the read word line switch comprises two input ends and one output end, the second grounding switch comprises two input ends and one output end, the programming word line switch comprises two input ends and one output end, and the third grounding switch comprises two input ends and one output end;

the row decoder is used for inputting a row address, the programming signal and the reading signal, one output end of the row decoder is respectively connected with one input end of the reading word line switch and one input end of the second grounding switch, and the other output end of the row decoder is respectively connected with one input end of the programming word line switch and one input end of the third grounding switch;

the other input end of the read word line switch is connected with VDD, the other input end of the second grounding switch is connected with a ground wire, and the output end of the read word line switch is connected with one read word line after being connected with the output end of the second grounding switch;

the other input end of the programming word line switch is connected with VDDQ, the other input end of the third grounding switch is connected with the ground wire, and the output end of the programming word line switch is connected with one programming word line after being connected with the output end of the third grounding switch.

5. An EFUSE array architecture as claimed in claim 4 wherein the other input of each of said sense amplifiers shares one of said reference circuits.

6. A programming method of an EFUSE array structure, wherein the programming method performs a programming operation using the EFUSE array structure of claim 5, the programming method comprising:

when the programming signal is at high level and the reading signal is at low level, in the column decoding circuit, a low level enable signal decoded by a column decoder to a column address closes a programming power supply switch in the column and opens a first grounding switch in the column, and a programming voltage is transmitted to a programming power supply line of the column, so that the memory cell of the column is selected; opening a programming power supply switch in the column and closing a first grounding switch in the column by using a high-level enabling signal decoded by a column decoder from a column address, and pulling down a programming power supply line of the column to the ground, wherein the column is an unselected memory cell;

in the row decoding circuit, a low level enabling signal decoded by a row decoder from a row address is used for closing a programming word line switch in the row and opening a third grounding switch in the row, and a programming auxiliary voltage is transmitted to a programming word line of the row, so that a memory cell in the row is selected; utilizing a high-level enabling signal decoded by a row decoder from a row address to open a programming word line switch in the row and close a third grounding switch in the row, and pulling down the programming word line of the row to the ground, wherein the row is a non-selected memory cell; and respectively utilizing a high-level enabling signal decoded by the row decoder to the row address to open the read word line switch in the row and close the second grounding switch in the row, and pulling down the read word line of the row to the ground so as to enable all the read word lines to be at a low level.

7. A method for reading an EFUSE array structure, the method for reading an EFUSE array structure according to claim 5, the method comprising:

when the programming signal is at a low level and the reading signal is at a high level, in the column decoding circuit, respectively opening a programming power supply switch in the column and closing a first grounding switch in the column by using a high-level enabling signal decoded by a decoder from a column address, and pulling down a programming power supply line of the column to the ground so as to enable each programming power supply line to be at a low level;

in the row decoding circuit, a high-level enabling signal decoded by a row decoder from a row address is used for opening a programming word line switch in the row and closing a third grounding switch in the row respectively, and the programming word lines in the row are pulled down to the ground so that all the programming word lines are at a low level; and closing the read word line switch in the row and opening the second grounding switch in the row by using a low-level enabling signal decoded by the row decoder from the row address, and transmitting the read voltage to the read word line of the row.

Technical Field

The present invention relates to the field of semiconductor integrated circuits, and more particularly, to an EFUSE (electrically programmable fuse) array structure, and a programming method and a reading method thereof.

Background

The main functions of the EFUSE memory chip are to store the version number, production date, trimming code (trimming code) and other information of the chip. With the development of 5G and the internet of things, the types of chips are more and more, which puts higher demands on the capacity of the EFUSE memory chip, and meanwhile, the battery endurance limits the development of the EFUSE memory chip, so that the design of the EFUSE memory chip with high capacity and low power consumption becomes more and more important.

Fig. 1 and 2 show a conventional EFUSE memory cell array structure, where the EFUSE array structure shown in fig. 1 includes EFUSE memory cells, a row address decoding selection circuit (i.e., WL Driver in fig. 1), and a column address decoding selection circuit (i.e., BL Programming Select in fig. 1). The EFUSE storage unit is composed of an EFUSE and a programming drive NMOS tube, in order to ensure that two ends of the EFUSE can conduct larger current in a programming mode, the size selection of the programming drive NMOS tube is usually larger, the selection of the storage unit has the leakage of a non-read storage unit in a reading mode under the existing storage array architecture, so that the waste of non-read row read power consumption exists in the reading mode, and particularly in a large-capacity EFUSE storage chip, the waste of read power consumption is more obvious.

The EFUSE array structure shown in FIG. 2 consists of EFUSE memory cells and row address decode select circuits (i.e. WL driver in FIG. 2) and column address decode select circuits (not shown in FIG. 2). In order to obtain an ideal programming current at two ends of the EFUSE, an anode end of the EFUSE is directly connected with a programming voltage fs, and meanwhile, in order to ensure that a programming operation mode is single-bit operation, a NOR logic gate control consisting of 2 PMOS transistors and 2 NMOS transistors (not shown in fig. 2) is required to be added to a gate end of each programming driving transistor, so that the area of an EFUSE storage unit is increased undoubtedly, the area overhead of control of an address decoding selection circuit is increased, and particularly in the design of a large-capacity EFUSE storage chip, the area of the chip is greatly increased. In the read mode, each group of Sense Amplifier circuits is connected with a reference circuit, and with the increase of the capacity of the EFUSE memory chip, the number of SA (Sense Amplifier) and the number of reference circuits are increased, so that the waste of power consumption in the read mode is increased.

Disclosure of Invention

The invention provides an EFUSE array structure, a programming method and a reading method thereof, which aim to solve the technical problems of high power consumption waste and large area of the conventional EFUSE array structure.

In order to solve the above technical problem, the present invention provides an EFUSE array structure, where the EFUSE array structure includes a column decoding circuit, a row decoding circuit, and a plurality of memory cells arranged in an array manner;

each of the memory cells includes an EFUSE, a program transistor, and a read transistor; one end of the EFUSE is connected with a programming power line, and the other end of the EFUSE is respectively connected with one of a source electrode and a drain electrode of the programming transistor and one of a source electrode and a drain electrode of the reading transistor; the grid electrode of the programming transistor is connected with a programming word line; the grid electrode of the reading transistor is connected with a reading word line, and the other electrode of the source electrode and the drain electrode of the reading transistor is connected with a bit line;

the programming power line is connected with one output end of the column decoding circuit; the programming word line and the reading word line are respectively connected with one output end of the row decoding circuit; the bit line is connected with one input end of the sensitive amplifier, and the other input end of the sensitive amplifier is connected with the reference circuit;

each EFUSE on each column shares a programming power line; each programming transistor on each row shares a programming word line; each reading transistor on each row shares one reading word line; each of the read transistors on each column shares a bit line;

the column decoding circuit sets a selected programming power line to be at a high level and sets unselected programming power lines to be at a low level according to a preset column address, a preset programming signal and a preset reading signal; the row decoding circuit sets a selected programming word line to a high level, sets an unselected programming word line to a low level, sets a selected read word line to a high level, and sets an unselected read word line to a low level according to a preset row address, the programming signal, and the preset read signal.

Optionally, the programming transistor and the reading transistor are both NMOS transistors.

Optionally, the column decoding circuit includes a plurality of column decoding modules, and each column decoding module is configured to control one of the programming power lines;

each column decoding module comprises a column decoder, a fuse power switch and a first grounding switch, wherein the column decoder comprises a plurality of input ends and an output end, the fuse power switch comprises two input ends and an output end, and the first grounding switch comprises two input ends and an output end;

a plurality of input ends of the column decoder are respectively used for inputting a fuse power supply, the preset column address and the programming signal, and an output end of the column decoder is connected with one input end of the fuse power supply switch and one input end of the first grounding switch;

and the other input end of the fuse wire power switch is used for inputting the fuse wire power supply, and the output end of the fuse wire power switch is connected with the output end of the first grounding switch and then connected with one programming power line.

Optionally, the row decoding circuit includes a plurality of row decoding modules, and each row decoding module is configured to control one of the programming word lines and one of the reading word lines;

each row decoding module comprises a row decoder, a read word line switch, a second grounding switch, a programming word line switch and a third grounding switch, the row decoder comprises a plurality of input ends and two output ends, the read word line switch comprises two input ends and one output end, the second grounding switch comprises two input ends and one output end, the programming word line switch comprises two input ends and one output end, and the third grounding switch comprises two input ends and one output end;

the row decoder is used for inputting a row address, the programming signal and the reading signal, one output end of the row decoder is respectively connected with one input end of the reading word line switch and one input end of the second grounding switch, and the other output end of the row decoder is respectively connected with one input end of the programming word line switch and one input end of the third grounding switch;

the other input end of the read word line switch is connected with VDD, the other input end of the second grounding switch is connected with a ground wire, and the output end of the read word line switch is connected with one read word line after being connected with the output end of the second grounding switch;

the other input end of the programming word line switch is connected with VDDQ, the other input end of the third grounding switch is connected with the ground wire, and the output end of the programming word line switch is connected with one programming word line after being connected with the output end of the third grounding switch.

Optionally, another input terminal of each of the sense amplifiers shares one of the reference circuits.

The invention also provides a programming method of the EFUSE array structure, which utilizes the EFUSE array structure to carry out programming operation and comprises the following steps:

when the programming signal is at high level and the reading signal is at low level, in the column decoding circuit, a low level enable signal decoded by a column decoder to a column address closes a programming power supply switch in the column and opens a first grounding switch in the column, and a programming voltage is transmitted to a programming power supply line of the column, so that the memory cell of the column is selected; opening a programming power supply switch in the column and closing a first grounding switch in the column by using a high-level enabling signal decoded by a column decoder from a column address, and pulling down a programming power supply line of the column to the ground, wherein the column is an unselected memory cell;

in the row decoding circuit, a low level enabling signal decoded by a row decoder from a row address is used for closing a programming word line switch in the row and opening a third grounding switch in the row, and a programming auxiliary voltage is transmitted to a programming word line of the row, so that a memory cell in the row is selected; utilizing a high-level enabling signal decoded by a row decoder from a row address to open a programming word line switch in the row and close a third grounding switch in the row, and pulling down the programming word line of the row to the ground, wherein the row is a non-selected memory cell; and respectively utilizing a high-level enabling signal decoded by the row decoder to the row address to open the read word line switch in the row and close the second grounding switch in the row, and pulling down the read word line of the row to the ground so as to enable all the read word lines to be at a low level.

The invention also provides a reading method of the EFUSE array structure, which utilizes the EFUSE array structure to carry out reading operation and comprises the following steps:

when the programming signal is at a low level and the reading signal is at a high level, in the column decoding circuit, respectively opening a programming power supply switch in the column and closing a first grounding switch in the column by using a high-level enabling signal decoded by a decoder from a column address, and pulling down a programming power supply line of the column to the ground so as to enable each programming power supply line to be at a low level;

in the row decoding circuit, a high-level enabling signal decoded by a row decoder from a row address is used for opening a programming word line switch in the row and closing a third grounding switch in the row respectively, and the programming word lines in the row are pulled down to the ground so that all the programming word lines are at a low level; and closing the read word line switch in the row and opening the second grounding switch in the row by using a low-level enabling signal decoded by the row decoder from the row address, and transmitting the read voltage to the read word line of the row.

According to the EFUSE array structure, the programming method and the reading method thereof, the electric leakage of a non-read storage unit in a reading mode is reduced through the array structure which is small in area and can separate a writing path from a reading path, meanwhile, the parasitic capacitance of a reading bit line can be reduced, so that lower reading power consumption and higher reading speed are obtained, and meanwhile, the complexity of a peripheral circuit can be obviously reduced due to the separation of the writing path and the reading path, so that the power consumption waste of the whole chip is saved.

Drawings

Fig. 1 is a schematic structural diagram of an EFUSE array structure in the prior art.

Fig. 2 is a schematic structural diagram of an EFUSE array structure in the prior art.

Fig. 3 is a schematic structural diagram of an EFUSE array structure according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of an EFUSE memory cell according to an embodiment of the present invention.

Detailed Description

To make the objects, advantages and features of the present invention more apparent, an EFUSE array structure, a programming method and a reading method thereof according to the present invention are further described in detail with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

As shown in fig. 3, the present embodiment provides an EFUSE array structure, which includes a column decoding circuit, a row decoding circuit, and a plurality of memory cells arranged in an array; each of the memory cells includes an EFUSE, a program transistor, and a read transistor; one end of the EFUSE is connected with a programming power line SL, and the other end of the EFUSE is respectively connected with one of a source electrode and a drain electrode of the programming transistor and one of a source electrode and a drain electrode of the reading transistor; the gate of the programming transistor is connected with a programming word line PGM _ WL; the grid electrode of the reading transistor is connected with a reading word line RD _ WL, and the other electrode of the source electrode and the drain electrode of the reading transistor is connected with a bit line BL; the programming power line SL is connected with one output end of the column decoding circuit; the program word line PGM _ WL and the read word line RD _ WL are respectively connected to an output terminal of the row decoding circuit; the bit line BL is connected with one input end of a sense amplifier, and the other input end of the sense amplifier is connected with a reference circuit; each EFUSE on each column shares one programming power line SL; each programming transistor on each row shares one programming word line PGM _ WL; the reading transistors on each row share one reading word line RD _ WL; the reading transistors on each column share one bit line BL; the column decoding circuit sets a selected programming power line SL to be at a high level and sets unselected programming power lines SL to be at a low level according to a preset column address Coladd, a preset programming signal PGM and a preset READ signal READ; the Row decoding circuit sets a selected program word line PGM _ WL to a high level, sets an unselected program word line PGM _ WL to a low level, sets a selected READ word line RD _ WL to a high level, and sets an unselected READ word line RD _ WL to a low level according to a preset Row address Row add, the program signal PGM, and the preset READ signal READ. The selected memory cell is used for storing information, and the unselected memory cell keeps an initial state.

The EFUSE array structure provided by the embodiment is a small-area array structure capable of separating a write path and a read path, so that the leakage of a non-read memory cell in a read mode is reduced, the parasitic capacitance of a read bit line can be reduced, lower read power consumption and higher read speed are obtained, and the complexity of a peripheral circuit can be obviously reduced due to the separation of the write path and the read path, so that the power consumption waste of the whole chip is saved.

Optionally, as shown in fig. 3, the programming transistor and the reading transistor are both NMOS transistors. The NMOS transistors with the same size have larger conducting current than the PMOS transistors, and the area of the EFUSE array structure can be reduced by using the NMOS transistors.

Optionally, as shown in fig. 3, the column decoding circuit includes a plurality of column decoding modules, and each column decoding module is configured to control one programming power line SL; each of the column decoding modules includes a column decoder including a plurality of input terminals and an output terminal, a fuse power switch FS SW including two input terminals and one output terminal, and a first ground switch (the first ground switch is GND SW connected to a programming power supply line SL < N-1: 0> in fig. 3) including two input terminals and one output terminal; a plurality of input terminals of the column decoder are respectively used for inputting the fuse power supply, the preset column address Col add and the programming signal PGM, and an output terminal of the column decoder is connected to one input terminal of the fuse power switch FS SW and one input terminal of the first ground switch; the other input end of the fuse power switch FS SW is used for inputting the fuse power, and the output end of the fuse power switch FS SW is connected to the output end of the first ground switch and then connected to one programming power line SL.

The column decoding circuit provided by this embodiment can control the output variation of the programming power line SL according to the variation of the programming signal PGM, thereby completing the programming operation and the reading operation of the EFUSE array structure, and can realize the bidirectional switch control in the direction of the programming power line SL, thereby completing the single-bit programming operation and the reading operation of the EFUSE memory array.

Optionally, as shown in fig. 3, the row decoding circuit includes a plurality of row decoding modules, each of which is configured to control one of the program word lines PGM _ WL and one of the read word lines RD _ WL; each of the row decoding modules includes a row decoder, a read word line switch RD _ WL SW, a second ground switch (the second ground switch is a GND SW connected to the read word line RD _ WL < M-1: 0> in fig. 3), a program word line switch PGM _ WL SW, and a third ground switch (the third ground switch is a GND SW connected to the program word line PGM _ WL < M-1: 0> in fig. 3), the row decoder including a plurality of input terminals and two output terminals, the read word line switch RD _ WL SW including two input terminals and one output terminal, the second ground switch including two input terminals and one output terminal, the program word line switch PGM _ WL SW including two input terminals and one output terminal, the third ground switch including two input terminals and one output terminal;

the Row decoder is configured to input a Row address Row add, the programming signal PGM, and the READ signal READ, one output end of the Row decoder is connected to one input end of the READ word line switch RD _ WL SW and one input end of the second ground switch, and the other output end of the Row decoder is connected to one input end of the programming word line switch PGM _ WL SW and one input end of the third ground switch; the other input end of the read word line switch RD _ WL SW is connected with VDD, the other input end of the second grounding switch is connected with the ground wire, and the output end of the read word line switch RD _ WL SW is connected with the output end of the second grounding switch and then is connected with one read word line RD _ WL; another input terminal of the program word line switch PGM _ WL SW is connected to VDDQ, another input terminal of the third ground switch is connected to ground, and an output terminal of the program word line switch PGM _ WL SW is connected to an output terminal of the third ground switch and then connected to one of the program word lines PGM _ WL. Wherein, VDD refers to the working voltage of the device; VDDQ refers to the power supply that needs to be filtered, with stability requirements higher than VDD.

The row decoding circuit provided by this embodiment may control the output of the program word line PGM _ WL and the READ word line RD _ WL to change according to the change of the program signal PGM and the READ signal READ, thereby completing the program operation and the READ operation of the EFUSE array structure.

Alternatively, as shown in fig. 3, another input terminal of each of the sense amplifiers shares one of the reference circuits. The design can further reduce the area of the EFUSE array structure. Each group of sensitive amplifying circuits share one reference EFUSE (Ref _ Res in FIG. 3), the structure of an NMOS connected with the reference EFUSE is the same as that of a reading transistor, the resistance value of the reference EFUSE is between a low resistance state and a high resistance state, if a fuse resistor is not programmed before, a reading end point BL can be in a low resistance state, and BL and BLref are further compared and amplified through a sensitive amplifier and output to a DOUT port to be 0; if the fuse resistance has been programmed before, the read node BL will appear high impedance state, and BL and BLref will be further compared and amplified by the sense amplifier to output as 1 at the DOUT port.

Based on the same technical concept as the EFUSE array structure, the embodiment further provides a programming method of the EFUSE array structure, the programming method uses the EFUSE array structure to perform programming operation, and the programming method includes:

when the program signal PGM is at a high level and the READ signal READ is at a low level, in the column decoding circuit, a low level enable signal decoded by a column decoder for a column address Col add closes a program power switch in the column and opens a first ground switch in the column, and a program voltage is transmitted to a program power line SL of the column, thereby selecting a memory cell of the column; turning on a programming power switch in the column and closing a first grounding switch in the column by using a high-level enabling signal decoded by a column decoder from a column address Col add to pull down a programming power line SL of the column to the ground, wherein the column is an unselected memory cell;

in the Row decoding circuit, a low-level enable signal decoded by a Row decoder for a Row address Row add closes a programming word line switch PGM _ WL SW in the Row and opens a third grounding switch in the Row, and a programming auxiliary voltage is transmitted to the programming word line PGM _ WL in the Row, so that the memory cells in the Row are selected; opening a programming word line switch PGM _ WL SW in the Row and closing a third grounding switch in the Row by using a high-level enabling signal decoded by a Row decoder from a Row address Row add, and pulling down the programming word line PGM _ WL in the Row to the ground, wherein the Row is a non-selected memory cell; the read word line switch RD _ WL SW in the Row is turned on and the second ground switch in the Row is turned off by the high level enable signal decoded from the Row address Row add by the Row decoder, respectively, and the read word line RD _ WL in the Row is pulled down to the ground, so that each read word line RD _ WL is at a low level.

In order to reduce the voltage drop loss on the programming path, the width-to-length ratio of the SL signal line on the layout is larger as much as possible, and the dimension of the FS _ SW pipe is generally selected to be larger so as to reduce the loss of the switching voltage, so as to ensure that a larger programming current flows under the programming path and improve the programming efficiency of the EFUSE.

Based on the same technical concept as the EFUSE array structure, the present embodiment further provides a reading method of the EFUSE array structure, where the reading method uses the EFUSE array structure to perform a reading operation, and the reading method includes:

when the program signal PGM is at a low level and the READ signal READ is at a high level, in the column decoding circuit, a high-level enable signal decoded by a decoder from a column address Col add is used to open the program power switches in the column and close the first ground switch in the column, and the program power lines SL of the column are pulled down to the ground, so that the program power lines SL are at a low level;

in the Row decoding circuit, a high-level enable signal decoded by a Row decoder for a Row address Row add is used for opening a programming word line switch PGM _ WL SW in the Row and closing a third grounding switch in the Row respectively, and the programming word lines PGM _ WL in the Row are pulled down to the ground, so that all the programming word lines PGM _ WL are in a low level; the low level enable signal decoded by the Row decoder for the Row address Row add closes the read word line switch RD _ WL SW in the Row and opens the second ground switch in the Row, and the read voltage is applied to the read word line RD _ WL in the Row.

FIG. 4 shows an EFUSE memory cell structure that can separate the read/write paths separately. The program path is the last path from the high program voltage FS (i.e., VPGM) terminal to the source terminal of the NM1 transistor to ground. The read path is the path from the VBL end to the NM2 end and finally to ground. In the programming operation, a programming voltage VFS is applied to the anode terminal of the EFUSE fuse resistor, then the NM1 tube is opened under the enable of the PGM _ WL signal, a sufficiently large programming current (6 mA-10 mA) flows across the EFUSE fuse resistor, the physical structure of the fuse resistor is changed through thermal rupture or Electromigration (EM), and the EFUSE fuse resistor is changed from a low resistance state before being programmed to a high resistance state, so that the EFUSE fuse resistor is programmed. During a read operation, a BL terminal applies a precharge voltage, the NM2 tube is opened under the enabling of the RD _ WL signal, if the fuse resistance is programmed before, a high impedance state, equivalent to VDD, occurs at a read terminal BL; if the fuse resistance is not programmed before, the read terminal BL will present a low impedance state, equivalent to VSS; the read BL voltage is finally transferred to the sense amplifier output 0 or 1.

Fig. 3 is a novel memory cell array structure built based on the memory cells shown in fig. 4, and an M × N array is taken as an example, wherein the programming power line includes SL <0> to SL < N-1>, the programming word line includes PGM _ WL <0> to PGM _ WL < M-1>, the reading word line includes RD _ WL <0> to RD _ WL < M-1>, the first column of programming transistors includes NM1<0, 0> to NM1< M-1, 0>, and the first row of programming transistors includes NM2<0, 0> to NM2<0, N-1 >. The bias conditions of the respective signals in the program mode and the read mode are as follows:

assuming that the programmed cell in the programming mode is row 0 and column 0, and row 0 is read in the reading mode, the bias conditions of the signals are as follows:

in summary, the EFUSE array structure, the programming method and the reading method thereof provided by the present invention reduce the leakage of the non-read memory cell in the read mode by the array structure with a small area and capable of separating the write path and the read path, and simultaneously reduce the parasitic capacitance of the read bit line, thereby obtaining a lower read power consumption and a faster read speed, and simultaneously significantly reducing the complexity of the peripheral circuit due to the separation of the write path and the read path, thereby saving the power consumption waste of the whole chip.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the present invention.