阅读说明：本技术 具有分隔有源区的半导体装置及其制造方法 (Semiconductor device with separated active regions and method of manufacturing the same ) 是由 林韦志 于 2019-11-12 设计创作，主要内容包括：本发明公开了一种具有分隔有源区的半导体装置及其制造方法。半导体装置包括衬底、多个隔离岛、源极区以及漏极区。所述衬底包括第一有源区、第二有源区以及多个分隔有源区。所述多个分隔有源区与第一有源区和第二有源区连接,并且与所述多个分离隔离岛交替设置。所述栅极结构包括主体部与多个延伸部。主体部设置在部分所述第一有源区上。多个延伸部与所述主体部连接,自所述主体部延伸至所述多个隔离岛上。源极区与漏极区分别位于所述第一有源区与所述第二有源区的所述衬底中。(The invention discloses a semiconductor device with separated active regions and a manufacturing method thereof. The semiconductor device includes a substrate, a plurality of isolation islands, a source region, and a drain region. The substrate includes a first active region, a second active region, and a plurality of spaced-apart active regions. The plurality of separation active regions are connected to the first active region and the second active region, and are alternately disposed with the plurality of separation islands. The gate structure includes a main body portion and a plurality of extension portions. The body portion is disposed on a portion of the first active region. And the plurality of extension parts are connected with the main body part and extend from the main body part to the plurality of isolation islands. A source region and a drain region are located in the substrate of the first active region and the second active region, respectively.)

1. A semiconductor device, comprising:

a substrate, comprising:

a first active region;

a second active region; and

a plurality of divided active regions extending in a first direction and arranged in a second direction, located between the first and second active regions, and connected to the first and second active regions, respectively;

a plurality of isolation islands in the substrate, alternating with the plurality of partitioned active regions in the second direction;

a gate structure on the substrate, the gate structure comprising:

a body portion extending in the second direction and disposed on a portion of the first active region;

the extension parts are connected with the main body part, extend to the isolation islands from the main body part in the first direction, and are alternately arranged with the separation active regions in the second direction;

a source region in the substrate of the first active region; and

a drain region in the substrate of the second active region.

2. The semiconductor device of claim 1, wherein the gate structure is comb-shaped.

3. The semiconductor device of claim 1, wherein the gate structure comprises a plurality of long portions alternating with a plurality of short portions alternating with each other and covering a portion of the plurality of isolated islands, and a plurality of short portions not covering a portion of the plurality of isolated islands.

4. The semiconductor device according to claim 1, further comprising:

and the doped region is positioned in the substrate, wherein the plurality of isolation islands and the drain region are positioned in the doped region, and the grid structure covers part of the doped region.

5. The semiconductor device according to claim 4, further comprising:

a first well region in the substrate, wherein the first well region partially overlaps the doped region, and the drain region and a portion of the plurality of isolation islands are in the first well region;

a second well region in the substrate, wherein the second well region has a different conductivity type than the first well region, and the source region is in the second well region, and the body portion of the gate structure covers a portion of the second well region; and

and the doped buried layer is positioned in the substrate, extends from the lower part of the first well region to the lower part of the second well region and is electrically connected with the first well region.

6. The semiconductor device according to claim 1, further comprising:

a barrier layer overlying the plurality of spaced active regions between the body portion and the drain region of the gate structure and overlying a portion of the substrate of the first active region; and

and the metal silicide layer is positioned on the source region, the drain region and the gate structure.

7. A method of manufacturing a semiconductor device, comprising:

forming an isolation structure in a substrate, wherein the isolation structure comprises a plurality of isolation islands, the isolation structure defines a first active region, a second active region and a plurality of separation active regions located between the first active region and the second active region in the substrate, the plurality of separation active regions extend in a first direction, are respectively connected with the first active region and the second active region, and are alternately arranged with the plurality of isolation islands in a second direction;

forming a gate structure on the substrate, the gate structure comprising:

a body portion extending in the second direction and disposed on a portion of the first active region;

a plurality of extension portions connected to the main body portion, extending from the main body portion to the plurality of isolation islands in the first direction, and alternately disposed with the plurality of partitioned active regions in the second direction;

forming a source region in the substrate of the first active region; and

a drain region is formed in the substrate of the second active region.

8. The method of claim 7, further comprising forming a doped region in the substrate, wherein the plurality of isolated islands and the drain region are in the doped region, and the gate structure covers a portion of the doped region.

9. The method for manufacturing a semiconductor device according to claim 8, further comprising:

forming a doped buried layer in the substrate;

forming a first well region in the substrate, wherein the first well region is connected with the doped buried layer and partially overlapped with the doped region, and the drain region is located in the first well region;

forming a second well region in the substrate, wherein the second well region and the first well region have different conductivity types, the source region is located in the second well region, and the main portion of the gate structure covers a portion of the second well region.

10. The method for manufacturing a semiconductor device according to claim 7, further comprising:

forming a barrier layer on the substrate to cover the plurality of spaced active regions and a portion of the substrate of the first active region between the body portion and the drain region of the gate structure; and

and forming a metal silicide layer on the source region, the drain region and the main body part of the gate structure.

Technical Field

The invention relates to a semiconductor device and a manufacturing method thereof.

Background

High-voltage (HV) transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), may act as high-voltage switches in high-voltage switching regulators and power management Integrated Circuits (ICs). In order to handle the high voltages involved in these and other high voltage applications, it is desirable to have high breakdown voltages (breakdown voltages) and low on-resistances (on-resistances) for the high voltage transistors.

Disclosure of Invention

Embodiments of semiconductor devices having partitioned active regions that achieve high breakdown voltages and low on-resistance and methods of making such devices are described.

An embodiment of the invention provides a semiconductor device, which includes a substrate, a plurality of isolation islands, a gate structure, a source region and a drain region. The substrate includes a first active region, a second active region, and a plurality of spaced-apart active regions. The plurality of divided active regions extend in a first direction, are arranged in a second direction, are positioned between the first active region and the second active region, and are respectively connected with the first active region and the second active region. And the plurality of isolation islands are positioned in the substrate and are arranged alternately with the plurality of separated active regions in the second direction. The gate structure is located on the substrate. The gate structure includes a main body portion and a plurality of extension portions. The body portion extends in the second direction and is disposed on a portion of the first active region. The plurality of extension portions are connected with the main body portion, extend from the main body portion to the plurality of isolation islands in the first direction, and are alternately arranged with the plurality of separated active regions in the second direction. A source region is located in the substrate of the first active region. A drain region is in the substrate of the second active region.

An embodiment of the invention provides a method for manufacturing a semiconductor device, which includes the following steps. Forming an isolation structure in a substrate, wherein the isolation structure comprises a plurality of isolation islands, the isolation structure defines a first active region, a second active region and a plurality of separated active regions located between the first active region and the second active region in the substrate, and the plurality of separated active regions extend in a first direction, are respectively connected with the first active region and the second active region, and are alternately arranged with the plurality of isolation islands in a second direction. And forming a gate structure on the substrate. The gate structure includes a main body portion and a plurality of extension portions. The body portion extends in the second direction and is disposed on a portion of the first active region. The plurality of extension portions are connected with the main body portion, extend upwards from the main body portion to the first direction to the plurality of isolation islands, and are alternately arranged with the plurality of separation active regions in the second direction. A source region is formed in the substrate of the first active region. A drain region is formed in the substrate of the second active region.

The semiconductor device of the embodiment of the invention can achieve high breakdown voltage and low on-resistance.

The details of one or more disclosed embodiments are set forth in the accompanying drawings and the description below. Other features, embodiments, and advantages will be apparent from the description, the drawings, and the claims.

Drawings

Fig. 1A illustrates a top view of a semiconductor device having separate active regions in accordance with one or more embodiments.

Fig. 1B shows an enlarged view of the region R in fig. 1A.

FIG. 2A is a cross-sectional view taken along line I-I' of FIG. 1B.

FIG. 2B is a cross-sectional view of line II-II' of FIG. 1B.

Fig. 3A to 3E are plan views illustrating an exemplary manufacturing method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 4A to 4E show cross-sectional views of the cut line III-III' in fig. 3A to 3E.

Fig. 4F shows a cross-sectional view of line IV-IV' of fig. 3E.

Fig. 5 is a graph of drain electrical characteristics of the semiconductor device of the present invention and a conventional semiconductor device.

[ notation ] 10: semiconductor device with a plurality of semiconductor chips

100: substrate

102: n-type deep well region

104: isolation structure

106: n-type doped drift region

108: n-type well region

109: drift region

110: p-well region

112: gate dielectric layer

114: gate electrode

116: spacer wall

118: grid structure

118L: long part

118S: short part

120: n + drain region

122: n + source region

124: p + body contact region

126: barrier section

130: metal silicide layer

A1: a first active region

A2: a second active region

AA: active region

D: transverse distance

D1: a first direction

D2: second direction

IOI: isolation island

O1, O2: opening of the container

P1: main body part

P2: extension part

R: region(s)

SSA: separating active regions C1, C1 ', C2, C2', C3, C4: curve line

L1, L2, L3, L4: length of

I-I ', II-II ', III-III, IV-IV ': tangent line

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.

Embodiments of the present invention provide a semiconductor device. The semiconductor device is, for example, a high voltage transistor device having a high breakdown voltage and a low on-resistance. The high voltage transistor device has a separation active region for separating an isolation structure between a source region and a drain region into a plurality of isolation islands separated from each other.

The techniques disclosed herein can optimize the on-resistance and breakdown voltage of high voltage transistor devices without the need for additional masks, such as photoresist masks. The high voltage transistor device may be fabricated by standard processes, such as triple well process (triple well process), Bipolar-complementary metal-oxide-semiconductor (cmos), double-diffused metal-oxide-semiconductor (dmos), BCD) process, non-epitaxial-grown layer (non-EPI) process with triple well process or double well process (twin well process), and/or single or double polysilicon process (single or double polysilicon process). The high voltage transistor device may be a low side switching Metal Oxide Semiconductor (MOS) transistor, a high side switching MOS transistor, a fully isolated switching MOS transistor, or a high voltage low surface electric field (RESURF) LDMOS transistor. The high voltage transistor may be an n-channel metal oxide semiconductor (n-channel MOS, NMOS) transistor, a p-channel metal oxide semiconductor (p-channel MOS, PMOS) transistor, or a Complementary Metal Oxide Semiconductor (CMOS) transistor. The techniques may be applied to any suitable structure, any suitable process, and/or any suitable operating voltage. In addition to high voltage devices, the techniques may also be used for Direct Current (DC) applications and/or low voltage applications.

The techniques may be applied to any suitable transistor device in any suitable substrate. For purposes of illustration only, some examples in the following description pertain to an n-channel Laterally Diffused (LD) metal oxide semiconductor field effect transistor (or LDMOS transistor) as one type of high voltage transistor. The n-channel LDMOS transistor may be located in a p-type semiconductor substrate or, alternatively, may be located in a p-type epitaxial layer formed on the substrate. Some examples in the following description pertain to the fabrication of a single transistor by a fabrication process, or the simultaneous formation of multiple transistors. In addition, in the following description, the p-type may be doped with boron or Boron Fluoride (BF), for example₂) Doping; n-type is doped with, for example, phosphorus or arsenic dopants.

Fig. 1A illustrates a top view of an exemplary semiconductor device having separate active regions in accordance with one or more embodiments. Fig. 1B shows an enlarged view of the region R in fig. 1A. FIG. 2A is a cross-sectional view taken along line I-I' of FIG. 1B. FIG. 2B is a cross-sectional view of line II-II' of FIG. 1B. The two High Voltage (HV) transistor devices in fig. 1A share a source region, however, the HV transistor devices of the present invention are not limited thereto.

Referring to fig. 1A, 1B, 2A, and 2B, the semiconductor device 10 is, for example, a high voltage transistor device. The high voltage transistor device may be an LDNMOS transistor, or a drain extended NMOS transistor. The semiconductor device 10 is formed in a p-type semiconductor substrate 100. The p-type semiconductor substrate 100 may be a p-type silicon wafer or a p-type epitaxial layer formed on a substrate. The p-type semiconductor substrate 100 may have 10¹⁴cm^-3To 10¹⁶cm^-3P-type doping concentration of (a).

In one embodiment, the semiconductor device 10 is configured to be completely isolated from the substrate 100 to be able to be independently biased. The semiconductor device 10 may include an n-type doped deep well (NBL) 102 and an n-type well 108. The n-type deep well region 102 is also called an n-type doped buried layer. The n-well region 108 is also referred to as the first well region. The n-type deep well region 102 is configured to provide vertical isolation; the n-type well region 108 is configured to provide lateral isolation. In one embodiment, the n-type deep well region 102 may have a 10¹⁶cm^-3To 10¹⁹cm^-3N-type doping concentration of (a). The high voltage n-type well region 108 may have a 10¹⁵cm^-3To 10¹⁸cm^-3N-type doping concentration of (a).

An isolation structure 104 is formed in the p-type semiconductor substrate 100. The isolation structure 104 electrically isolates the semiconductor device 10 from other transistor devices and devices formed on the p-type semiconductor substrate 100. The isolation structure 104 is, for example, a Shallow Trench Isolation (STI) or a thick Field Oxide (FOX) layer. The isolation structure 104 may comprise a single layer or multiple layers. The material of the isolation structure 104 includes silicon oxide, silicon nitride, or a combination thereof. The isolation structure 104 defines an active area AA in the substrate 100. The active region AA includes a first active region a1, a second active region a2, and a plurality of spaced-apart active regions SSA between the first active region a1 and the second active region a 2. The first active region a1 and the second active region a2 extend along the second direction D2 and are juxtaposed along the first direction D1. The plurality of partition active regions SSA extend along the first direction D1, connect the first active region a1 and the second active region a2, and are arranged along the second direction D2. In addition, the separation active region SSA also separates the isolation structure 104 between the first active region a1 and the second active region a2 into a plurality of isolation islands IOI. The plurality of partitioned active regions SSA and the plurality of isolation islands IOI alternate with each other along the second direction D2. In some embodiments, the top views of the first active region a1, the second active region a2, the separation active regions SSA, and the isolation islands IOI are, for example, rectangles, respectively. The length L1 in the first direction of the first active region a1 is, for example, greater than the length L2 in the first direction of the second active region a 2.

In the semiconductor substrate 100, the p-type doping concentration is higher (e.g. 10) than that of the p-type semiconductor substrate 100¹⁶cm^-3To 10¹⁸cm^-3) P-well region 110 is implanted and diffused. The p-well region 110 is also referred to as a second well region. The p-well region 110 partially overlaps the first active region a 1. Heavily doped (heavily doped) p + body contact regions 124 (e.g., having a 10) are formed in the first active region a1 of the p-well region 110¹⁹cm^-3To 10²¹cm^-3P-type doping concentration) and heavily doped n + source regions 122 (e.g., having a 10¹⁹cm^-3To 10²¹cm^-3N-type doping concentration). The p + body contact regions 124 may be further from the gate structure 118 (described in detail below) than the n + source regions 122. The p-well region 110 may extend laterally beyond the p + body contact regions 124 and the n + source regions 122 and vertically below the p + body contact regions 124 and the n + source regions 122. The p + body contact region 124 and the n + source region 122 are in direct electrical contact with each other.

In a p-type substrate 100, with a higher n-type doping concentration (e.g., 10)¹⁶cm^-3To 10¹⁸cm^-3) An n-type doping drift (NDD) region 106 is implanted and diffused. The isolated islands IOI are located in the n-type doped drift region 106. The n-doped drift region 106 may extend laterally in the direction of the gate structure 118, partially overlapping the first active region a1, but laterally spaced from the p-well region 110. The n-doped drift region 106 also extends toward the second active region a2 such that the spaced-apart active region SSA and the second active region a2 completely overlap therewith. The second active region a2 of the n-doped drift region 106 contains a heavy dopingN + drain region 120 (e.g., having a 10¹⁹cm^-3To 10²¹cm^-3N-type doping concentration). The n + drain region 120 may be more heavily doped than the n-doped drift region 106.

A gate structure 118 is disposed over the substrate 100 between the n + source region 122 and the n + drain region 120.

The gate structure 118 includes a gate dielectric layer 112, a gate electrode 114, and spacers 116. The gate dielectric layer 112 may comprise silicon oxide (SiO)₂) Or a high dielectric constant dielectric material (e.g., silicon dioxide (SiO)₂) High dielectric constant (3.9) high). A gate electrode 114 partially overlies the p-well region 110 and the n-doped drift region 106. The gate electrode 114 is separated from the semiconductor substrate 100, the p-well region 110 and the n-doped drift region 106 by a gate dielectric layer 112. The gate electrode 114 may comprise doped polysilicon (poly) disposed over the gate dielectric layer 112. Spacers 116 are located on the sidewalls of the gate electrode 114. The spacer 116 may be a single layer or a multi-layer, such as comprising silicon oxide, silicon nitride, or a combination thereof.

Referring to fig. 1B, the gate structure 118 is comb-shaped, for example. The gate structure 118 covers a portion of the first active region a1 and a portion of the isolation structure 104. In some embodiments, the gate structure 118 includes a body portion P1 and a plurality of extension portions P2. The body portion P1 extends in the second direction D2, covering a portion of the first active region a1, exposing the first active regions a1 on both sides of the body portion P1. The extension portion P2 extends in the first direction D1 and is connected to the main body portion P1. Each extension P2 covers a portion of first active region a1 and a portion of isolation island IOI. The plurality of extension portions P2 are alternately arranged with the plurality of spaced active regions SSA in the second direction D2.

On the other hand, the gate structure 118 includes a plurality of long portions 118L and a plurality of short portions 118S. The plurality of long portions 118L and the plurality of short portions 118S alternate with each other in the second direction D2. The long portion 118L has a length L3 in the first direction D1; the short portion 118S has a length L4 in the first direction D1. The length L4 is equal to the length of the main body portion P1 in the first direction D1. The length L3 is equal to the sum of the length of the main body portion P1 in the first direction D1 and the length of the extension portion P2 in the first direction D1.

Referring to fig. 2A, one side of the short portion 118S of the gate structure 118 exposes the n + source region 122 and the p + body contact region 124. Short portion 118S covers a portion of p-well region 110, substrate 100, and a first portion of n-type doped drift region 106. The surface of p-well region 110 and substrate 100 covered by short portion 118S serves as a channel region. One side of the short portion 118S of the gate structure 118 exposes the second portion of the n-doped drift region 106 and the n + drain region 120. The absence of isolation structures in the n-doped drift region 106 may provide a low on-resistance for the semiconductor device 10.

The gate electrode 114 of the short portion 118S adjoins the n + source region 122 at one end and extends over the first portion of the n-doped drift region 106 at the other end. A second portion of the n-doped drift region 106 (from the other end of the gate electrode 114 to the n + drain region 120) adjoins the first portion of the n-doped drift region 106 and has a lateral distance D. The second portion of the n-doped drift region 106 may be considered a drift region 109 for charge carriers to move from the n + source region 122 to the n + drain region 120. The on-resistance of the semiconductor device 10 is correlated to the doping concentration of the drift region 109 (i.e. the concentration of the n-type doped drift region 106) and the lateral distance D. The higher the doping concentration of the drift region 109, the lower the on-resistance; the longer the lateral distance D, the higher the on-resistance.

Referring to fig. 2B, one side of the long portion 118L of the gate structure 118 exposes the n + source region 122 and the p + body contact region 124. Long portion 118L covers a portion of p-well region 110, substrate 100, and a portion of isolated islands IOI. The surface of p-well region 110 and substrate 100 covered by long portion 118L serves as a channel region. One side of the long portion 118L of the gate structure 118 exposes another portion of the isolated island IOI and the n + drain region 120. The placement of the isolation islands IOI may provide a high breakdown voltage for the semiconductor device 10.

A barrier (PRO)126 is formed on the substrate 100 covering the plurality of spaced-apart active regions SSA and the plurality of isolation islands IOI, exposing the first active region a1 and the second active region a 2. In some embodiments, the barrier 126 covers the n-type doped drift region 106 and the isolation islands IOI, exposing the p + body contact regions 124, the n + source regions 122, the gate structure 118, and the n + drain regions 120. In other embodiments, the barrier portion 126 also covers a portion of the long portion 118L and a portion of the short portion 118S of the portion of the gate structure 118. The barrier 126 may be a single layer or a plurality of layers. The material of barrier 126 comprises silicon oxide, silicon nitride, or a combination thereof.

A metal silicide layer 130 is formed on the p + body contact region 124, the n + source region 122, the gate structure 118, and the n + drain region 120 not covered by the barrier 126. The metal silicide layer 130 may comprise cobalt silicide, titanium nitride/titanium/cobalt silicide, cobalt polycide or titanium nitride/titanium polycide, titanium nitride/titanium/cobalt polycide.

The embodiment of the invention can optimize the on-resistance and breakdown voltage of the semiconductor device 10 by changing and designing the lengths and widths of the isolation islands and the plurality of isolation islands, i.e., the lengths and the widths of the isolation islands and the doping concentration of the drift region 109. For example, increasing the doping concentration of the drift region 109, shortening the length of the separation active region SSA in the first direction D1 or increasing the length ratio of the separation active region SSA to the isolation island IOI in the second direction D2 can reduce the on-resistance of the semiconductor device 10. Otherwise, the breakdown voltage of the semiconductor device 10 can be increased.

Fig. 3A to 3E are plan views illustrating an exemplary manufacturing method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 4A to 4E show cross-sectional views of the cut line III-III' in fig. 3A to 3E. Fig. 4F shows a cross-sectional view of line IV-IV' of fig. 3E.

Referring to fig. 3A and fig. 4A, an n-type deep well region 102 is formed in a substrate 100. The substrate 100 is, for example, a p-type semiconductor substrate, for example, a p-type silicon substrate. The n-type deep well 102 is formed by, for example, forming an ion implantation mask on the substrate 100, and then performing an ion implantation process to implant n-type dopants into the substrate 100. Thereafter, the implantation mask is removed.

Next, an isolation structure 104 is formed in the substrate 100. The isolation structure 104 includes a plurality of isolation islands IOI. The isolation structure 104 is formed by a shallow trench isolation method, for example. The shallow trench isolation method comprises the following steps. A plurality of trenches are formed in the substrate 100 by photolithography and etching processes. Thereafter, an insulating material is formed on the substrate 100 and in the channel. Then, a planarization process is performed by using a chemical mechanical polishing method or an etching-back method to remove the insulating material on the substrate 100. The insulating material comprises silicon oxide, silicon nitride or a combination thereof formed by chemical vapor deposition or thermal oxidation. The isolation structure 104 defines an active area AA in the substrate 100. The active region AA includes a first active region a1, two second active regions a2, and a plurality of spaced-apart active regions SSA. The first active region a1 is located between two second active regions a 2. The separate active regions SSA are respectively located between the first active region a1 and the second active region a 2.

Referring to fig. 3B and fig. 4B, an n-type doped drift region 106, an n-type well region 108 and a p-type well region 110 are formed in the substrate 100 above the n-type deep well region 102. The doping concentration of the n-type well region 108 may be the same as, slightly higher than, or slightly lower than the doping concentration of the n-type deep well region 102. The n-well 108 and the p-well 110 may be formed on the substrate 100 by forming an implantation mask, and then performing an ion implantation process to implant n-type dopants and p-type dopants into the substrate 100, respectively. Thereafter, the implantation mask is removed. The n-type well region 108 partially overlaps the second active region a2, the plurality of spaced-apart active regions SSA, and the isolation structure 104. The n-well 108 may be ring-shaped, and the bottom surface of the n-well 108 is deeper than the bottom surface of the isolation structure 104 and is adjacent to the top surface of the n-deep well 102. Thus, the n-type well region 108 and the n-type deep well region 102 may together enclose an independent area, and the transistor devices formed in this independent area may be completely isolated from the substrate 100 to be able to be independently biased.

Referring to fig. 3B and fig. 4B, the doping concentration of the n-type doped drift region 106 may be slightly higher than that of the n-type well region 108. The n-type doped drift region 106 may be formed on the substrate 100 by forming an implantation mask and then performing an ion implantation process to implant n-type dopants into the substrate 100. Thereafter, the implantation mask is removed. The implantation mask has two openings O1. The opening O1 exposes a portion of the first active region a1, and exposes the plurality of separation active regions SSA, the plurality of isolation islands IOI, the two second active regions a2, and a portion of the isolation structure 104 adjacent to the second active region a 2. Therefore, the n-type doped drift region 106 partially overlaps the first active region a1, completely overlaps the plurality of spaced-apart active regions SSA, the plurality of isolation islands IOI, and the two second active regions a2, and partially overlaps the n-type well region 108 and the isolation structure 104. The n-type doped drift region 106 extends vertically downward from the surface of the substrate 100 until its bottom surface abuts the top surface of the n-type deep well region 102 (as shown in fig. 3B) or is between the top surface of the n-type deep well region 102 and the bottom surface of the isolation islands IOI (not shown). The n-type doped drift region 106 surrounds and encapsulates a plurality of isolation islands IOI therein.

The doping concentration of the p-well region 110 is slightly higher than the doping concentration of the substrate 100. The p-well regions 110 may be formed on the substrate 100 by forming an implantation mask, respectively, and then performing an ion implantation process to implant n-type dopants into the substrate 100. Thereafter, the implantation mask is removed. The implantation mask has an opening O2. The opening O2 exposes a central region of a portion of the first active region a 1. The n-doped drift region 106 partially overlaps the first active region a1 and is laterally spaced from the p-well region 110. The p-well region 110 extends vertically downward from the surface of the substrate 100, but its bottom surface is not contiguous with the top surface of the n-type deep well region 102, but is longitudinally spaced apart. For simplicity, the p-well region 110 and the opening O2 are not shown in fig. 3C and 3D.

Referring to fig. 3C and fig. 4C, two gate structures 118 are formed on the substrate 100. The gate structure 118 includes a gate dielectric layer 112, a gate electrode 114, and spacers 116. The gate structure 118 is formed by, for example, forming a gate dielectric material layer on the substrate 100 to form a gate electrode material layer, and then patterning the gate dielectric material layer by photolithography and etching processes to form a gate electrode material layer. And then forming a spacer material layer, and carrying out an anisotropic etching process on the spacer material layer. The gate structure 118 is, for example, comb-shaped (as shown in fig. 3C). The gate structure 118 includes a plurality of long portions 118L and a plurality of short portions 118S alternating with each other in the second direction D2. The plurality of long portions 118L and the plurality of short portions 118S of the gate structure 118 cover a portion of the p-well region 110, a portion of the n-doped drift region 106, and a portion of the plurality of isolation islands IOI. A portion of the isolated island IOI is covered by the long portion 118L and another portion of the isolated island IOI is exposed by the long portion 118L of the gate structure 118. The isolated island IOI is not covered by the short portion 118S of the gate structure 118.

Referring to fig. 3C and 4C, a p + body contact region 124 and an n + source region 122 are formed in the first active region a1, and an n + drain region 120 is formed in the two second active regions a 2. The doping concentration of the p + body contact regions 124 is higher than the doping concentration of the p-well region 110. The doping concentration of the n + source region 122 and the n + drain region 120 is higher than the doping concentration of the n-type doped drift region 106. The p + body contact region 124 and the n + source region 122 and the n + drain region 120 may be formed by forming an implantation mask on the substrate 100, respectively, and then performing an ion implantation process to implant p-type or n-type dopants into the substrate 100. Thereafter, the implantation mask is removed. The n + source region 122 and the n + drain region 120 may be formed simultaneously.

Referring to fig. 3D and fig. 4D, a barrier (PRO)126 is formed on the substrate 100 to cover a portion of the gate structure 118, the n-type doped drift regions 106 in the plurality of separated active regions SSA, and the plurality of isolation islands IOI, and to expose another portion of the gate structure 118, the p + body contact regions 124 and the n + source regions 122 in the first active region a1, and the n + drain regions 120 in the second active region a 2. In some embodiments, barrier 126 does not cover gate electrode 114 of gate structure 118 (not shown).

Referring to fig. 3E, 4E and 4F, a self-aligned silicidation process is performed to form a metal silicide layer 130 on the gate electrode 114, the p + body contact region 124, the n + source region 122 and the n + drain region 120.

Fig. 5 is a graph of drain electrical characteristics of the semiconductor device of the present invention and a conventional semiconductor device.

Referring to fig. 5, the semiconductor device of the present invention has smooth drain saturation current curves C1, C2, C3, and C4. The saturation current curves C1 ', C2' of the conventional semiconductor device are relatively steep. As can be seen from fig. 5, the semiconductor device of the present invention has a smoother saturation current curve compared to the prior art.

In the embodiment of the present invention, by forming the plurality of divided active regions SSA which communicate the first active region with the second active region, the current at the short portion of the gate electrode can flow through the drift region of low resistance in the divided active region SSA in a shorter path, and thus the on-resistance of the transistor device can be reduced. Experiments have shown that the on-resistance of the semiconductor device of the present invention can be reduced to about 9.4 ohm-mm, since the on-resistance of the known semiconductor device is about 14 ohm-mm.

In addition, through the arrangement of a plurality of isolation islands IOI between the first active region and the second active region, the transistor device can be maintained at a predetermined breakdown voltage.

In addition, the long portion of the gate electrode extends over the plurality of isolation islands IOI, and can be used as a local field plate (partial field plate) to make the electric field uniform.

Therefore, the embodiment of the invention can optimize the on-resistance and breakdown voltage of the transistor device by changing and designing the length and width of the isolation island SSA and the isolation island IOI, the length of the gate electrode, and the doping concentration of the drift region without adding additional masks and processes.

Although the present invention may have been described in considerable detail, such detail is not to be understood as limitations on the claimed invention or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination. Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that: these operations should be performed in the particular order shown or in sequential order, or all illustrated operations should be performed, to achieve desirable results.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.