阅读说明：本技术 一种高k围栅场介质纵向双扩散功率器件 (high-K gate-surrounding field medium longitudinal double-diffusion power device ) 是由 姚佳飞 张振宇 郭宇锋 李曼 于 2021-02-03 设计创作，主要内容包括：本发明公开了一种高K围栅场介质纵向双扩散功率器件,包括半导体漂移区、设置在半导体漂移区上方的半导体阱区、以及设置在半导体漂移区下方的半导体漏区；还包括高K围场介质,将高K围场介质上部刻蚀形成高K围栅介质；所述半导体阱区上方设置有半导体体接触区和半导体源区。本发明在开态时,高K围栅介质降低了器件的阈值电压、沟道电阻以及栅极泄漏电流,增加了器件的跨导和输出电流；栅端金属电极、高K围栅场介质和半导体漂移区构成了MIS电容,在开态时,在漂移区与高K围栅场介质界面处产生电子积累层,降低器件的比导通电阻；在关态时,高K围栅场介质对漂移区有辅助耗尽作用,能够使漂移区具有更高的掺杂浓度,降低器件的比导通电阻。(The invention discloses a high-K surrounding gate field medium longitudinal double-diffusion power device, which comprises a semiconductor drift region, a semiconductor well region arranged above the semiconductor drift region, and a semiconductor drain region arranged below the semiconductor drift region; the high-K gate dielectric is formed by etching the upper part of the high-K enclosure field dielectric; and a semiconductor body contact region and a semiconductor source region are arranged above the semiconductor well region. When the high-K surrounding gate dielectric is in an on state, the threshold voltage, the channel resistance and the gate leakage current of the device are reduced, and the transconductance and the output current of the device are increased; the gate end metal electrode, the high-K surrounding gate field medium and the semiconductor drift region form an MIS capacitor, and when the MIS capacitor is in an on state, an electron accumulation layer is generated at the interface of the drift region and the high-K surrounding gate field medium, so that the specific on-resistance of the device is reduced; in an off state, the high-K surrounding gate field medium has an auxiliary depletion effect on the drift region, so that the drift region has higher doping concentration, and the specific on-resistance of the device is reduced.)

1. A high-K surrounding gate field medium longitudinal double-diffusion power device is characterized by comprising a semiconductor drift region (2), a semiconductor well region (3) arranged above the semiconductor drift region (2), and a semiconductor drain region (1) arranged below the semiconductor drift region (2); the high-K gate-surrounding dielectric (7) is formed by etching the upper part of the high-K gate-surrounding dielectric (6); a semiconductor body contact region (5) and a semiconductor source region (4) are arranged above the semiconductor well region (3); a drain end metal electrode (10) is arranged at the bottom of the longitudinal double-diffusion power device and is positioned below the semiconductor drain region (1); and a source end metal electrode (9) is arranged at the top of the longitudinal double-diffusion power device and is in contact with the semiconductor source region (4) and the semiconductor body contact region (5).

2. The high-K surrounding gate field medium longitudinal double-diffused power device according to claim 1, wherein the high-K surrounding gate medium (6) is located around the semiconductor drift region (2), the semiconductor source region (4) is surrounded outside the semiconductor body contact region (5), the high-K surrounding gate medium (7) is surrounded around the semiconductor well region (3) and the semiconductor source region (4), and the gate end metal electrode (8) is arranged around the high-K surrounding gate medium (7) to form a metal high-K surrounding gate structure.

3. The high-K gate-all-around field dielectric longitudinal double-diffused power device according to claim 1, wherein the semiconductor drift region (2) is located around the high-K gate-all-around dielectric (6), the semiconductor body contact region (5) surrounds the outside of the semiconductor source region (4), the semiconductor well region (3) and the semiconductor source region (4) surround the high-K gate-all-around dielectric (7), and a gate end metal electrode (8) is arranged inside the high-K gate-all-around dielectric (7) to form a metal high-K gate-all-around structure.

4. The high-K wrap gate field dielectric longitudinal double diffusion power device as claimed in claim 1, wherein the dielectric constant of the high-K wrap gate dielectric (7) is 20-2000, and the adopted material is HfO₂、TiO₂、SrTiO₃Or PZT.

5. The high-K wrap gate field dielectric longitudinal double diffused power device according to claim 4, wherein the thickness of the high-K wrap gate dielectric (7) ranges from 0.05 μm to 0.5 μm, the thickness of the high-K wrap gate dielectric (6) ranges from 0.5 μm to 1.5 μm, and the thickness of the high-K wrap gate dielectric (6) is larger than that of the high-K wrap gate dielectric (7).

6. The high-K gate-all-around field dielectric longitudinal double-diffused power device according to claim 1, wherein the high-K gate-all-around field dielectric (6) surrounds the periphery of the semiconductor drift region (2), and the high-K gate-all-around field dielectric (6) is in contact with the semiconductor drain region (1); or the high-K enclosure field medium (6) surrounds a part of the periphery of the semiconductor drift region (2), and the bottom of the high-K enclosure field medium (6) is not contacted with the semiconductor drain region (1).

7. The high-K wrap gate field dielectric longitudinal double diffused power device according to claim 1, characterized in that the high-K wrap gate dielectric (6) and the high-K wrap gate dielectric (7) are in direct contact with a semiconductor active region; or growing a thin silicon oxide layer between the semiconductor active region and the high-K medium to serve as a buffer layer, wherein the thickness of the buffer layer is 0.5-10 nm.

8. The high-K wrap gate field dielectric longitudinal double diffused power device of claim 1, wherein the longitudinal double diffused power device is of a cubic type or a cylindrical type.

9. The high-K wrap gate field dielectric longitudinal double diffusion power device of claim 1, wherein the double diffusion power device is made of Si, SiC or Ga₂O₃The semiconductor drain region (1) is heavily doped, and the semiconductor drift region (2) is lightly doped.

Technical Field

The invention relates to the field of semiconductor power devices, in particular to a high-K gate-all-around field dielectric longitudinal double-diffusion power device.

Background

The longitudinal double-diffusion power device has the advantages of high voltage resistance, large current, high switching speed and the like, and is widely applied to power integrated circuits. However, a high breakdown voltage usually requires a long drift region and a low doping concentration of the drift region, which increases the specific on-resistance of the device, so one of the main goals of designers is to reduce the contradiction between the breakdown voltage and the specific on-resistance of the vertical double-diffused power device.

Patent CN1181559C discloses a semiconductor device, wherein a high-K dielectric pillar is introduced into a sidewall of a voltage-withstanding layer of a conventional trench-gate vertical double-diffused power device, and compared with the conventional trench-gate vertical double-diffused power device under the same voltage withstanding, the proposed device realizes a lower specific on-resistance, but the modulation effect of the high-K dielectric is limited to a drift region, and a conductive channel cannot be modulated.

Patent CN107437566A discloses a semiconductor longitudinal double-diffused metal oxide semiconductor field effect transistor with a composite dielectric layer wide band gap and a manufacturing method thereof, wherein a high-K dielectric pillar is prepared and arranged in a region below the groove bottom of a conventional groove gate longitudinal double-diffused power device, the high-K dielectric only modulates a drift region, and does not modulate a conducting channel.

Disclosure of Invention

The purpose of the invention is as follows: in view of the above problems, the present invention aims to provide a high-K gate-all-around field dielectric longitudinal double-diffusion power device, which improves the overall performance of the device by introducing the high-K gate-all-around dielectric.

The technical scheme is as follows: the invention relates to a high-K surrounding gate field medium longitudinal double-diffusion power device which comprises a semiconductor drift region, a semiconductor well region and a semiconductor drain region, wherein the semiconductor well region is arranged above the semiconductor drift region; the high-K gate dielectric is formed by etching the upper part of the high-K enclosure field dielectric; a semiconductor body contact region and a semiconductor source region are arranged above the semiconductor well region, and a drain electrode metal electrode is arranged at the bottom of the longitudinal double-diffusion power device and is positioned below the semiconductor drain region; and a source metal electrode is arranged at the top of the longitudinal double-diffusion power device and is in contact with the semiconductor source region and the semiconductor body contact region.

The high-K surrounding field medium is positioned around the semiconductor drift region, the semiconductor source region surrounds the outside of the semiconductor body contact region, the high-K surrounding gate medium surrounds the periphery of the semiconductor well region and the semiconductor source region, and the periphery of the high-K surrounding gate medium is provided with a gate end metal electrode, so that a metal high-K surrounding gate structure is formed.

The semiconductor drift region is located around the high-K enclosure field medium, the semiconductor body contact region surrounds the outer portion of the semiconductor source region, the semiconductor well region and the semiconductor source region surround the periphery of the high-K enclosure gate medium, and the gate end metal electrode is arranged inside the high-K enclosure gate medium to form a metal high-K enclosure gate structure.

The dielectric constant of the high-K surrounding gate dielectric is 20-2000, and the adopted material is HfO₂、TiO₂、SrTiO₃Or PZT.

The thickness range of the high-K surrounding gate dielectric is 0.05-0.5 mu m, the thickness range of the high-K surrounding field dielectric is 0.5-1.5 mu m, and the thickness of the high-K surrounding field dielectric is larger than that of the high-K surrounding gate dielectric.

The high-K enclosure field medium surrounds the periphery of the semiconductor drift region, and the high-K enclosure field medium is in contact with the semiconductor drain region.

The high-K enclosure field medium surrounds a part of the periphery of the semiconductor drift region, and the bottom of the high-K enclosure field medium is not contacted with the semiconductor drain region.

The high-K enclosure field medium and the high-K enclosure gate medium are in direct contact with the semiconductor active region.

A thin silicon oxide layer is grown between the semiconductor active region and the high-K medium and serves as a buffer layer, and the thickness of the buffer layer ranges from 0.5 nm to 10 nm.

The longitudinal double-diffusion power device is in a cubic type or a cylindrical type.

The preparation material of the double-diffusion power device is Si, SiC or Ga₂O₃。

The semiconductor drain region is heavily doped, and the semiconductor drift region is lightly doped.

Has the advantages that: compared with the prior art, the invention has the following remarkable advantages:

1. when the gate is in an on state, the high-K surrounding gate dielectric reduces the threshold voltage, channel resistance and gate leakage current of the device, and increases transconductance and output current of the device;

2. the gate end metal electrode, the high-K surrounding gate field medium and the semiconductor drift region form an MIS capacitor, and when the MIS capacitor is in an on state, an electron accumulation layer is generated at the interface of the drift region and the high-K surrounding gate field medium, so that the specific on-resistance of the device is further reduced;

3. in an off state, the high-K surrounding gate field medium has an auxiliary depletion effect on the drift region, so that the drift region has higher doping concentration, and the specific on-resistance of the device is reduced;

4. the high-K surrounding gate field medium modulates the electric field distribution of the drift region in an all-around manner, so that the electric field of the drift region is more uniform, and the breakdown voltage of the device is increased.

Drawings

FIG. 1 is a schematic structural view of the present invention;

FIG. 2 is a schematic view of a half cell of the present invention along line AA';

FIG. 3 is a schematic structural diagram of the present high-K fringing field dielectric in contact with a semiconductor drain region;

FIG. 4 is a schematic structural diagram after well, source and body contact regions are fabricated over a semiconductor drift region;

FIG. 5 is a schematic diagram of an integrated high-K wrap gate field dielectric structure after forming a high-K wrap gate;

fig. 6 is a schematic structural diagram after forming a gate end metal electrode and a source end metal electrode;

FIG. 7 is a schematic structural diagram of a cylindrical vertical double-diffused power device;

FIG. 8 is a schematic diagram of a vertical double diffused power device structure with a high-K confining field dielectric partially surrounding a semiconductor drift region;

FIG. 9 is a schematic structural diagram of a vertical double-diffused power device in which a high-K gate-all-around field dielectric is formed in an active region;

FIG. 10 is a schematic diagram of a half cell of a vertical double diffused power device structure along the line BB';

FIG. 11 is a schematic diagram of a symmetrical vertical insulated gate bipolar transistor with a high-K wrap-gate field dielectric;

fig. 12 is a schematic diagram of a structure in which a high-K wrap-gate field dielectric is fabricated in an asymmetric vertical insulated gate bipolar transistor.

Detailed Description

Example 1

Fig. 1 is a schematic structural diagram, and fig. 2 is a half cell diagram cut along an AA' line in fig. 1, and includes a heavily doped semiconductor drain region 1, a lightly doped semiconductor drift region 2 above the semiconductor drain region 1, and a high-K enclosure field medium 6 around the semiconductor drift region 2; a semiconductor well region 3 is arranged above the semiconductor drift region 2; a semiconductor source region 4 and a semiconductor body contact region 5 are arranged above the semiconductor well region 3, and the semiconductor source region 4 surrounds the semiconductor body contact region 5; the high-K surrounding gate dielectric 7 is positioned at the periphery of the semiconductor well region 3 and the semiconductor source region 4; the high-K gate surrounding medium 7 is formed by etching the upper layer of the high-K gate surrounding medium 6 to form an integrated high-K gate surrounding medium; the periphery of the high-K surrounding gate dielectric 7 is provided with a gate end metal electrode 8, so that a metal high-K surrounding gate structure is formed; the source end metal electrode 9 is in contact with the semiconductor source region 4 and the semiconductor body contact region 5; the drain terminal metal electrode 10 is located below the semiconductor drain region 1.

In this embodiment, the vertical double diffused power device is exemplified by an N-type drift region, and the structure of the high-K wrap gate field dielectric vertical double diffused power device in this embodiment will be described in detail below.

The high-K surrounding gate field medium longitudinal double-diffusion power device is formed on a highly doped semiconductor drain region 1, and the phosphorus ion doping concentration of the drain region can be 5 multiplied by 10¹⁹Per cm^-3-1×10²⁰Per cm^-3. Forming a low-doped semiconductor drift region 2 on the high-doped semiconductor drain region 1, wherein the doping concentration range of the phosphorus ions is 1 × 10¹⁵Per cm^-3-2×10¹⁷Per cm^-3The thickness of the semiconductor drift region 2 is determined according to the required withstand voltage value.

Etching a high-K enclosure field medium 6 groove in the semiconductor drift region 2, depositing the high-K medium in the high-K enclosure field medium 6 groove through magnetron sputtering, and polishing to make the height of the high-K enclosure field medium 6 consistent with that of the top of the active region, wherein the thickness of the high-K enclosure field medium 6 ranges from 0.5 mu m to 1.5 mu m, and the high-K enclosure field medium 6 is in contact with the semiconductor drain region 1, as shown in FIG. 3.

A semiconductor well region 3, a semiconductor source region 4 and a semiconductor body contact region 5 are sequentially formed on the top of the drift region by ion implantation, and the prepared structure of the active region is shown in fig. 4 by annealing to activate the activity of impurity atoms and repair the lattice damage caused by the ion implantation. The high-K gate surrounding medium 7 is formed by etching the high-K gate surrounding medium 6, the thickness range of the high-K gate surrounding medium 7 is 0.05-0.5 mu m, the etching depth of the high-K gate surrounding medium 7 is enough to ensure the opening of a device, and the formed high-K gate surrounding medium structure is shown in figure 5.

And depositing and etching metal to form a gate end metal electrode 8 and a source end metal electrode 9, wherein the structure of the front electrode after preparation is shown in fig. 6, and the gate end metal electrode 8 and the high-K surrounding gate dielectric 7 form a metal high-K surrounding gate structure. And depositing back metal to form a drain metal electrode 10.

The high-K gate-all-around field dielectric is cubic or cylindrical, and the structure of the cylindrical high-K gate-all-around field dielectric longitudinal double-diffusion power device is shown in figure 7.

Example 2

The present embodiment is different from embodiment 1 in that the high-K confining field medium 6 in the present embodiment partially surrounds the semiconductor drift region 2, and the high-K confining field medium 6 does not contact with the semiconductor drain region 1, and the structure of the vertical double-diffused power device is shown in fig. 8.

Example 3

The difference between this embodiment and embodiment 1 is that the semiconductor drift region 2 in this embodiment is located around the high-K gate-surrounding medium 6, the semiconductor body contact region 5 is surrounded outside the semiconductor source region 4, the semiconductor well region 3 and the semiconductor source region 4 are surrounded around the high-K gate-surrounding medium 7, and the gate end metal electrode 8 is arranged inside the high-K gate-surrounding medium 7, so as to form a metal high-K gate-surrounding structure. Fig. 9 shows a vertical double-diffused power device structure in which a high-K gate-all-around field dielectric is formed in the active region, and the high-K gate-all-around field dielectric formed in the active region can also comprehensively modulate the semiconductor drift region 2 and the conduction channel. The half cell structure along line BB' in FIG. 9 is shown in FIG. 10.

Example 4

This embodiment differs from embodiment 1 in that the semiconductor drain region 1 is replaced by a semiconductor collector region 11, the semiconductor collector region 11 being highly doped, the doping type being opposite to that of the semiconductor drift region 2. The high-K gate-all-around field dielectric is prepared in the vertical insulated gate bipolar transistor, the function of the high-K gate-all-around field dielectric is the same as that of the high-K gate-all-around field dielectric in the vertical double-diffused power device, and the structure of the high-K gate-all-around field dielectric prepared in the symmetrical vertical insulated gate bipolar transistor is shown in fig. 11.

Example 5

The present embodiment is different from embodiment 4 in that a semiconductor buffer layer 12 is disposed above the semiconductor collector region 11, the semiconductor buffer layer 12 is a medium doping, and the doping type is the same as that of the semiconductor drift region 2. The structure of a high-K wrap-gate field dielectric fabricated in an asymmetric vertical insulated gate bipolar transistor is shown in fig. 12.