阅读说明：本技术 一种抗辐照锁存器单元电路 (Anti-irradiation latch unit circuit ) 是由 赵强 赵丽 彭春雨 卢文娟 吴秀龙 黎轩 蔺智挺 陈军宁 于 2020-12-31 设计创作，主要内容包括：本发明公开了一种抗辐照锁存器单元电路,包括十九个NMOS晶体管、十三个PMOS晶体管、三个反相器和一个钟控反相器。PMOS晶体管P1、P6、P7、P8对X5、X6包围加固,NMOS晶体管N1～N4、N6～N9对X1～X4包围加固；PMOS晶体管P2～P5作为上拉管,NMOS晶体管N5、N10作为下拉管,反相器I3与钟控反相器CI构成弱上拉；四个锁存器节点X1、X2、X3、X4通过四个NMOS晶体管N16～N19连接到输入D和DN,四个NMOS晶体管N16～N19的开启由时钟信号CLK控制。上述电路可以提高锁存器单元的速度、提高锁存器单元抗单粒子翻转的能力,解决由电荷共享引起的双节点翻转问题。(The invention discloses an anti-irradiation latch unit circuit which comprises nineteen NMOS transistors, thirteen PMOS transistors, three inverters and a clocked inverter. PMOS transistors P1, P6, P7 and P8 surround and reinforce X5 and X6, and NMOS transistors N1 to N4 and N6 to N9 surround and reinforce X1 to X4; PMOS transistors P2-P5 are used as pull-up tubes, NMOS transistors N5 and N10 are used as pull-down tubes, and the inverter I3 and the clock-controlled inverter CI form weak pull-up; the four latch nodes X1, X2, X3, X4 are connected to the inputs D and DN through four NMOS transistors N16-N19, the turn-on of the four NMOS transistors N16-N19 being controlled by the clock signal CLK. The circuit can improve the speed of the latch unit, improve the single event upset resistance of the latch unit and solve the problem of double-node upset caused by charge sharing.)

1. An anti-irradiation latch unit circuit is characterized by comprising nineteen NMOS transistors, thirteen PMOS transistors, three inverters and a clocked inverter, wherein the nineteen NMOS transistors are sequentially recorded as N1-N19, the thirteen PMOS transistors are sequentially recorded as P1-P13, the three inverters are sequentially recorded as I1-I3, and the clocked inverter is recorded as CI, wherein:

the drain of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P7, and the gate of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P8;

the drain of the PMOS transistor P2 is electrically connected to the drain of the NMOS transistor N1, and the gate of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P7;

the drain of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N2, and the gate of the PMOS transistor P3 is electrically connected to the source of the PMOS transistor P8;

the drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N3, and the gate of the PMOS transistor P4 is electrically connected to the source of the PMOS transistor P7;

the drain of the PMOS transistor P5 is electrically connected to the drain of the NMOS transistor N4, and the gate of the PMOS transistor P5 is electrically connected to the source of the PMOS transistor P8;

the drain of the PMOS transistor P6 is electrically connected to the source of the PMOS transistor P8, and the gate of the PMOS transistor P6 is electrically connected to the source of the PMOS transistor P7;

the source of the PMOS transistor P7 is electrically connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P7 is electrically connected to the drain of the NMOS transistor N5, and the gate of the PMOS transistor P7 is electrically connected to the drain of the NMOS transistor N7;

the source of the PMOS transistor P8 is electrically connected to the drain of the PMOS transistor P6, the drain of the PMOS transistor P8 is electrically connected to the drain of the NMOS transistor N10, and the gate of the PMOS transistor P8 is electrically connected to the drain of the NMOS transistor N6;

the drain of the PMOS transistor P9 is electrically connected to the source of the PMOS transistor P10, and the gate of the PMOS transistor P9 is electrically connected to the drain of the NMOS transistor N7;

the drain of the PMOS transistor P10 is electrically connected to the source of the PMOS transistor P11, and the gate of the PMOS transistor P10 is electrically connected to the drain of the NMOS transistor N9;

the drain of the PMOS transistor P11 is electrically connected to the drain of the PMOS transistor N11, and the gate of the PMOS transistor P11 is electrically connected to the source of the PMOS transistor P7;

the drain of the PMOS transistor P12 is electrically connected to the output Q of the latch, the source of the PMOS transistor P12 is electrically connected to the drain of the PMOS transistor P11, and the gate of the PMOS transistor P12 is electrically connected to the clock signal CLK;

the source of PMOS transistor P13 is electrically connected to input D, the drain of PMOS transistor P13 is electrically connected to output Q of the latch, and the gate of PMOS transistor P13 is electrically connected to clock signal CLKB;

the drain of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor P2, the source of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N6, and the gate of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N8;

the drain of the NMOS transistor N2 is electrically connected to the drain of the PMOS transistor P3, the source of the NMOS transistor N2 is electrically connected to the drain of the NMOS transistor N7, and the gate of the NMOS transistor N2 is electrically connected to the drain of the NMOS transistor N9;

the drain of the NMOS transistor N3 is electrically connected to the drain of the PMOS transistor P4, the source of the NMOS transistor N3 is electrically connected to the drain of the NMOS transistor N8, and the gate of the NMOS transistor N3 is electrically connected to the drain of the NMOS transistor N6;

the drain of the NMOS transistor N4 is electrically connected to the drain of the PMOS transistor P5, the source of the NMOS transistor N4 is electrically connected to the drain of the NMOS transistor N9, and the gate of the NMOS transistor N4 is electrically connected to the drain of the NMOS transistor N7;

the drain of the NMOS transistor N5 is electrically connected to the drain of the PMOS transistor P7, and the gate of the NMOS transistor N5 is electrically connected to the drain of the NMOS transistor N8;

the drain of the NMOS transistor N6 is electrically connected to the source of the NMOS transistor N1, and the gate of the NMOS transistor N6 is electrically connected to the drain of the NMOS transistor N9;

the drain of the NMOS transistor N7 is electrically connected to the source of the NMOS transistor N2, and the gate of the NMOS transistor N7 is electrically connected to the drain of the NMOS transistor N6;

the drain of the NMOS transistor N8 is electrically connected to the source of the NMOS transistor N3, and the gate of the NMOS transistor N8 is electrically connected to the drain of the NMOS transistor N7;

the drain of the NMOS transistor N9 is electrically connected to the source of the NMOS transistor N4, and the gate of the NMOS transistor N9 is electrically connected to the drain of the NMOS transistor N8;

the drain of the NMOS transistor N10 is electrically connected to the drain of the PMOS transistor P8, and the gate of the NMOS transistor N10 is electrically connected to the drain of the NMOS transistor N9;

the drain of the NMOS transistor N11 is electrically connected to the drain of the PMOS transistor P11, the source of the NMOS transistor N11 is electrically connected to the drain of the NMOS transistor N12, and the gate of the NMOS transistor N11 is electrically connected to the drain of the NMOS transistor N7;

the drain of the NMOS transistor N12 is electrically connected to the source of the NMOS transistor N11, the source of the NMOS transistor N12 is electrically connected to the drain of the NMOS transistor N13, and the gate of the NMOS transistor N12 is electrically connected to the drain of the NMOS transistor N9;

the drain of the NMOS transistor N13 is electrically connected to the source of the NMOS transistor N12, and the gate of the NMOS transistor N13 is electrically connected to the drain of the PMOS transistor P1;

the drain of the NMOS transistor N14 is connected to the output Q of the latch, the source of the NMOS transistor N14 is electrically connected to the drain of the NMOS transistor N11, and the gate of the NMOS transistor N14 is electrically connected to the clock signal CLKB;

the source of the NMOS transistor N15 is electrically connected to the input D, the drain of the NMOS transistor N15 is electrically connected to the output Q of the latch, and the gate of the NMOS transistor N15 is electrically connected to the clock signal CLK;

the input end of the inverter I1 is electrically connected with an external input signal D of the latch, and the output end of the inverter I1 is electrically connected with an opposite signal DN of the external input signal D of the latch;

the input end of the inverter I2 is electrically connected with a clock signal CLK, and the output end is electrically connected with a clock signal CLKB;

the input end of the inverter I3 is electrically connected with the end M, and the output end of the inverter I3 is electrically connected with the input end of the clocked inverter CI;

the output end of the clocked inverter CI is electrically connected with the input end of the inverter I3;

the external input signal D of the latch is electrically connected to the sources of the NMOS transistors N16 and N18, and the opposite signal DN of the external input signal D of the latch is electrically connected to the sources of the NMOS transistors N17 and N19;

the clock signal CLK is electrically connected with the gates of the NMOS transistors N16-N19, the drain of the NMOS transistor N16 is electrically connected with the drain of the NMOS transistor N6, the drain of the NMOS transistor N17 is electrically connected with the drain of the NMOS transistor N7, the drain of the NMOS transistor N18 is electrically connected with the drain of the NMOS transistor N8, and the drain of the NMOS transistor N19 is electrically connected with the drain of the NMOS transistor N9;

the power supply VDD is electrically connected with the sources of the PMOS transistors P1-P6 and P9;

the sources of the NMOS transistors N5-N10 and N13 are grounded;

based on the circuit structure, the PMOS transistors P1, P6, P7 and P8 surround and reinforce X5 and X6, and the NMOS transistors N1 to N4 and N6 to N9 surround and reinforce X1 to X4;

PMOS transistors P2-P5 are used as pull-up tubes, NMOS transistors N5 and N10 are used as pull-down tubes, an inverter I3 and a clock-controlled inverter CI form weak pull-up, and PMOS transistors P9-P11 and NMOS transistors N11-N13 form a C unit;

the four internal storage nodes X1, X2, X3, X4 of the latch are connected to the inputs D and DN through four NMOS transistors N16-N19, the turn-on of the four NMOS transistors N16-N19 being controlled by the clock signal CLK.

2. The radiation-resistant Latch unit circuit according to claim 1, wherein based on the above circuit configuration, when the circuit operates in the transparent transmission mode, assuming that the input signal D is 1, the clock signal CLK is 1, and the four NOMS transistors N16 to N19 are in an on state, the input signal D writes data to the Latch internal node through the four NOMS transistors N16 to N19, so that the NMOS transistors N1, N3, N5, N7, and N9 are turned on, and the NMOS transistors N2, N4, N6, N8, and N10 are turned off;

PMOS transistor P7 is turned on and P8 is turned off, so that node X5 is equal to 0; the PMOS transistors P2, P4 and P6 are turned on, the node X6 is pulled up to 1, the PMOS transistors P1, P3 and P5 are turned off, the PMOS transistor P13 and the NMOS transistor N15 are turned on, the PMOS transistor P12 and the NMOS transistor N14 are turned off, the PMOS transistors P9 to P11 are turned on, and the NMOS transistors N11 to N13 are turned off;

the final node X1, X3, X6, X2, X4, X5, is 1, and the output Q is driven directly from the input D through the transmission gate, thus greatly reducing the transmission delay from D to Q.

3. The radiation-resistant Latch unit circuit of claim 1, wherein based on the above circuit structure, when the circuit operates in the data Latch mode, the clock signal CLK is equal to 0, the four NOMS transistors N16-N19 are turned off, the PMOS transistor P13 and the NMOS transistor N15 are turned off, the PMOS transistor P12 and the NMOS transistor N14 are turned on, and the output Q is driven by the C unit with three inputs, and the feedback loop inside Latch can ensure that the value of the output Q is in a stable state.

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to an anti-irradiation latch unit circuit.

Background

The main effects on semiconductor integrated circuits in the space irradiation environment are divided into Total Dose effects (TID) caused by long-term irradiation accumulation and Single Event Effects (SEE) caused by Single energetic particle Ionizing irradiation. With the continuous evolution of integrated circuit technology and the development of technology, the influence of total dose effect is smaller and smaller, and the main reason of semiconductor failure is soft error in single event effect, which makes the development requirement of integrated circuit radiation-resistant reinforcement technology more and more urgent. The Single Event Upset (SEU) is a form of SEE, and belongs to a soft error, which is non-destructive, and generally occurs in an irradiation Event of a Single particle, wherein a Single energetic particle generates a bundle of electron-hole pairs in a digital integrated circuit device, the electron-hole pairs are collected by electrodes of the device, and when the number of the electron-hole pairs is large enough, data of a latch unit is erroneous, so that the logic state of a circuit node is abnormally changed, and finally, a soft error occurs in an integrated circuit system.

For an anti-irradiation circuit of a basic latch unit, the prior art mainly researches an SRAM latch unit, a trigger and a latch, and in a deep submicron integrated circuit, the SRAM latch unit, the trigger and the latch are influenced by a charge sharing effect, single-particle bombardment can simultaneously influence a plurality of sensitive nodes, so that the plurality of nodes in a single latch structure simultaneously collect charges and overturn, and accordingly, the data of the latch is overturned, so that the latch is more and more seriously influenced by the charge sharing effect, and the reinforcement of the latch is an important scheme for improving the SEU resistance of the latch unit.

Disclosure of Invention

The invention aims to provide an anti-irradiation latch unit circuit which can improve the speed of a latch unit, improve the single event upset resistance of the latch unit and solve the problem of double-node upset caused by charge sharing.

The purpose of the invention is realized by the following technical scheme:

an anti-irradiation latch unit circuit comprises nineteen NMOS transistors, thirteen PMOS transistors, three inverters and a clocked inverter, wherein the nineteen NMOS transistors are sequentially marked as N1-N19, the thirteen PMOS transistors are sequentially marked as P1-P13, the three inverters are sequentially marked as I1-I3, and the clocked inverter is marked as CI, and the circuit comprises:

the drain of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P7, and the gate of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P8;

the drain of the PMOS transistor P2 is electrically connected to the drain of the NMOS transistor N1, and the gate of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P7;

the drain of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N2, and the gate of the PMOS transistor P3 is electrically connected to the source of the PMOS transistor P8;

the drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N3, and the gate of the PMOS transistor P4 is electrically connected to the source of the PMOS transistor P7;

the drain of the PMOS transistor P5 is electrically connected to the drain of the NMOS transistor N4, and the gate of the PMOS transistor P5 is electrically connected to the source of the PMOS transistor P8;

the drain of the PMOS transistor P6 is electrically connected to the source of the PMOS transistor P8, and the gate of the PMOS transistor P6 is electrically connected to the source of the PMOS transistor P7;

the source of the PMOS transistor P7 is electrically connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P7 is electrically connected to the drain of the NMOS transistor N5, and the gate of the PMOS transistor P7 is electrically connected to the drain of the NMOS transistor N7;

the source of the PMOS transistor P8 is electrically connected to the drain of the PMOS transistor P6, the drain of the PMOS transistor P8 is electrically connected to the drain of the NMOS transistor N10, and the gate of the PMOS transistor P8 is electrically connected to the drain of the NMOS transistor N6;

the drain of the PMOS transistor P9 is electrically connected to the source of the PMOS transistor P10, and the gate of the PMOS transistor P9 is electrically connected to the drain of the NMOS transistor N7;

the drain of the PMOS transistor P10 is electrically connected to the source of the PMOS transistor P11, and the gate of the PMOS transistor P10 is electrically connected to the drain of the NMOS transistor N9;

the drain of the PMOS transistor P11 is electrically connected to the drain of the PMOS transistor N11, and the gate of the PMOS transistor P11 is electrically connected to the source of the PMOS transistor P7;

the drain of the PMOS transistor P12 is electrically connected to the output Q of the latch, the source of the PMOS transistor P12 is electrically connected to the drain of the PMOS transistor P11, and the gate of the PMOS transistor P12 is electrically connected to the clock signal CLK;

the source of PMOS transistor P13 is electrically connected to input D, the drain of PMOS transistor P13 is electrically connected to output Q of the latch, and the gate of PMOS transistor P13 is electrically connected to clock signal CLKB;

the drain of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor P2, the source of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N6, and the gate of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N8;

the drain of the NMOS transistor N2 is electrically connected to the drain of the PMOS transistor P3, the source of the NMOS transistor N2 is electrically connected to the drain of the NMOS transistor N7, and the gate of the NMOS transistor N2 is electrically connected to the drain of the NMOS transistor N9;

the drain of the NMOS transistor N3 is electrically connected to the drain of the PMOS transistor P4, the source of the NMOS transistor N3 is electrically connected to the drain of the NMOS transistor N8, and the gate of the NMOS transistor N3 is electrically connected to the drain of the NMOS transistor N6;

the drain of the NMOS transistor N4 is electrically connected to the drain of the PMOS transistor P5, the source of the NMOS transistor N4 is electrically connected to the drain of the NMOS transistor N9, and the gate of the NMOS transistor N4 is electrically connected to the drain of the NMOS transistor N7;

the drain of the NMOS transistor N5 is electrically connected to the drain of the PMOS transistor P7, and the gate of the NMOS transistor N5 is electrically connected to the drain of the NMOS transistor N8;

the drain of the NMOS transistor N6 is electrically connected to the source of the NMOS transistor N1, and the gate of the NMOS transistor N6 is electrically connected to the drain of the NMOS transistor N9;

the drain of the NMOS transistor N7 is electrically connected to the source of the NMOS transistor N2, and the gate of the NMOS transistor N7 is electrically connected to the drain of the NMOS transistor N6;

the drain of the NMOS transistor N8 is electrically connected to the source of the NMOS transistor N3, and the gate of the NMOS transistor N8 is electrically connected to the drain of the NMOS transistor N7;

the drain of the NMOS transistor N9 is electrically connected to the source of the NMOS transistor N4, and the gate of the NMOS transistor N9 is electrically connected to the drain of the NMOS transistor N8;

the drain of the NMOS transistor N10 is electrically connected to the drain of the PMOS transistor P8, and the gate of the NMOS transistor N10 is electrically connected to the drain of the NMOS transistor N9;

the drain of the NMOS transistor N11 is electrically connected to the drain of the PMOS transistor P11, the source of the NMOS transistor N11 is electrically connected to the drain of the NMOS transistor N12, and the gate of the NMOS transistor N11 is electrically connected to the drain of the NMOS transistor N7;

the drain of the NMOS transistor N12 is electrically connected to the source of the NMOS transistor N11, the source of the NMOS transistor N12 is electrically connected to the drain of the NMOS transistor N13, and the gate of the NMOS transistor N12 is electrically connected to the drain of the NMOS transistor N9;

the drain of the NMOS transistor N13 is electrically connected to the source of the NMOS transistor N12, and the gate of the NMOS transistor N13 is electrically connected to the drain of the PMOS transistor P1;

the drain of the NMOS transistor N14 is connected to the output Q of the latch, the source of the NMOS transistor N14 is electrically connected to the drain of the NMOS transistor N11, and the gate of the NMOS transistor N14 is electrically connected to the clock signal CLKB;

the source of the NMOS transistor N15 is electrically connected to the input D, the drain of the NMOS transistor N15 is electrically connected to the output Q of the latch, and the gate of the NMOS transistor N15 is electrically connected to the clock signal CLK;

the input end of the inverter I1 is electrically connected with an external input signal D of the latch, and the output end of the inverter I1 is electrically connected with an opposite signal DN of the external input signal D of the latch;

the input end of the inverter I2 is electrically connected with a clock signal CLK, and the output end is electrically connected with a clock signal CLKB;

the input end of the inverter I3 is electrically connected with the end M, and the output end of the inverter I3 is electrically connected with the input end of the clocked inverter CI;

the output end of the clocked inverter CI is electrically connected with the input end of the inverter I3;

the external input signal D of the latch is electrically connected to the sources of the NMOS transistors N16 and N18, and the opposite signal DN of the external input signal D of the latch is electrically connected to the sources of the NMOS transistors N17 and N19;

the clock signal CLK is electrically connected with the gates of the NMOS transistors N16-N19, the drain of the NMOS transistor N16 is electrically connected with the drain of the NMOS transistor N6, the drain of the NMOS transistor N17 is electrically connected with the drain of the NMOS transistor N7, the drain of the NMOS transistor N18 is electrically connected with the drain of the NMOS transistor N8, and the drain of the NMOS transistor N19 is electrically connected with the drain of the NMOS transistor N9;

the power supply VDD is electrically connected with the sources of the PMOS transistors P1-P6 and P9;

the sources of the NMOS transistors N5-N10 and N13 are grounded;

based on the circuit structure, the PMOS transistors P1, P6, P7 and P8 surround and reinforce X5 and X6, and the NMOS transistors N1 to N4 and N6 to N9 surround and reinforce X1 to X4;

PMOS transistors P2-P5 are used as pull-up tubes, NMOS transistors N5 and N10 are used as pull-down tubes, an inverter I3 and a clock-controlled inverter CI form weak pull-up, and PMOS transistors P9-P11 and NMOS transistors N11-N13 form a C unit;

the four internal storage nodes X1, X2, X3, X4 of the latch are connected to the inputs D and DN through four NMOS transistors N16-N19, the turn-on of the four NMOS transistors N16-N19 being controlled by the clock signal CLK.

According to the technical scheme provided by the invention, the circuit can improve the speed of the latch unit, improve the single event upset resistance of the latch unit and solve the problem of double-node upset caused by charge sharing.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

FIG. 1 is a schematic structural diagram of an anti-radiation latch unit circuit according to an embodiment of the present invention;

FIG. 2 is a timing waveform diagram of an embodiment of an anti-radiation latch unit circuit;

fig. 3 is a simulation diagram of transient waveforms of the radiation-resistant latch unit circuit injected by current source pulses at different times at internal nodes and output nodes;

fig. 4 is a simulation diagram of transient waveforms of current source pulse injection at different times of an internal node and a floating node of the anti-radiation latch unit circuit provided in the embodiment of the present invention;

FIG. 5 is a voltage versus delay comparison of a prior art circuit and an irradiation resistant latch cell circuit provided by an embodiment of the present invention;

FIG. 6 is a graph of voltage versus power consumption for a prior art circuit and an irradiation resistant latch cell circuit provided by an embodiment of the present invention;

FIG. 7 is a temperature versus delay diagram of a prior art circuit and an irradiation resistant latch cell circuit provided by an embodiment of the present invention;

figure 8 is a graph of temperature versus power consumption for a prior art circuit and an embodiment of the present invention providing an irradiation resistant latch cell circuit.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

The embodiment of the present invention will be further described in detail with reference to the accompanying drawings, and as shown in fig. 1, is a schematic structural diagram of an anti-irradiation latch unit circuit provided by the embodiment of the present invention, where the circuit includes nineteen NMOS transistors, thirteen PMOS transistors, three inverters, and a clocked inverter, the nineteen NMOS transistors are sequentially denoted as N1 to N19, the thirteen PMOS transistors are sequentially denoted as P1 to P13, the three inverters are sequentially denoted as I1 to I3, and the clocked inverter is denoted as CI, where:

the drain of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P7, and the gate of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P8;

the drain of the PMOS transistor P2 is electrically connected to the drain of the NMOS transistor N1, and the gate of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P7;

the drain of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N2, and the gate of the PMOS transistor P3 is electrically connected to the source of the PMOS transistor P8;

the drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N3, and the gate of the PMOS transistor P4 is electrically connected to the source of the PMOS transistor P7;

the drain of the PMOS transistor P5 is electrically connected to the drain of the NMOS transistor N4, and the gate of the PMOS transistor P5 is electrically connected to the source of the PMOS transistor P8;

the drain of the PMOS transistor P6 is electrically connected to the source of the PMOS transistor P8, and the gate of the PMOS transistor P6 is electrically connected to the source of the PMOS transistor P7;

the source of the PMOS transistor P7 is electrically connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P7 is electrically connected to the drain of the NMOS transistor N5, and the gate of the PMOS transistor P7 is electrically connected to the drain of the NMOS transistor N7;

the source of the PMOS transistor P8 is electrically connected to the drain of the PMOS transistor P6, the drain of the PMOS transistor P8 is electrically connected to the drain of the NMOS transistor N10, and the gate of the PMOS transistor P8 is electrically connected to the drain of the NMOS transistor N6;

the drain of the PMOS transistor P9 is electrically connected to the source of the PMOS transistor P10, and the gate of the PMOS transistor P9 is electrically connected to the drain of the NMOS transistor N7;

the drain of the PMOS transistor P10 is electrically connected to the source of the PMOS transistor P11, and the gate of the PMOS transistor P10 is electrically connected to the drain of the NMOS transistor N9;

the drain of the PMOS transistor P11 is electrically connected to the drain of the PMOS transistor N11, and the gate of the PMOS transistor P11 is electrically connected to the source of the PMOS transistor P7;

the drain of the PMOS transistor P12 is electrically connected to the output Q of the latch, the source of the PMOS transistor P12 is electrically connected to the drain of the PMOS transistor P11, and the gate of the PMOS transistor P12 is electrically connected to the clock signal CLK;

the source of PMOS transistor P13 is electrically connected to input D, the drain of PMOS transistor P13 is electrically connected to output Q of the latch, and the gate of PMOS transistor P13 is electrically connected to clock signal CLKB;

the drain of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor P2, the source of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N6, and the gate of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N8;

the drain of the NMOS transistor N2 is electrically connected to the drain of the PMOS transistor P3, the source of the NMOS transistor N2 is electrically connected to the drain of the NMOS transistor N7, and the gate of the NMOS transistor N2 is electrically connected to the drain of the NMOS transistor N9;

the drain of the NMOS transistor N3 is electrically connected to the drain of the PMOS transistor P4, the source of the NMOS transistor N3 is electrically connected to the drain of the NMOS transistor N8, and the gate of the NMOS transistor N3 is electrically connected to the drain of the NMOS transistor N6;

the drain of the NMOS transistor N4 is electrically connected to the drain of the PMOS transistor P5, the source of the NMOS transistor N4 is electrically connected to the drain of the NMOS transistor N9, and the gate of the NMOS transistor N4 is electrically connected to the drain of the NMOS transistor N7;

the drain of the NMOS transistor N5 is electrically connected to the drain of the PMOS transistor P7, and the gate of the NMOS transistor N5 is electrically connected to the drain of the NMOS transistor N8;

the drain of the NMOS transistor N6 is electrically connected to the source of the NMOS transistor N1, and the gate of the NMOS transistor N6 is electrically connected to the drain of the NMOS transistor N9;

the drain of the NMOS transistor N7 is electrically connected to the source of the NMOS transistor N2, and the gate of the NMOS transistor N7 is electrically connected to the drain of the NMOS transistor N6;

the drain of the NMOS transistor N8 is electrically connected to the source of the NMOS transistor N3, and the gate of the NMOS transistor N8 is electrically connected to the drain of the NMOS transistor N7;

the drain of the NMOS transistor N9 is electrically connected to the source of the NMOS transistor N4, and the gate of the NMOS transistor N9 is electrically connected to the drain of the NMOS transistor N8;

the drain of the NMOS transistor N10 is electrically connected to the drain of the PMOS transistor P8, and the gate of the NMOS transistor N10 is electrically connected to the drain of the NMOS transistor N9;

the drain of the NMOS transistor N11 is electrically connected to the drain of the PMOS transistor P11, the source of the NMOS transistor N11 is electrically connected to the drain of the NMOS transistor N12, and the gate of the NMOS transistor N11 is electrically connected to the drain of the NMOS transistor N7;

the drain of the NMOS transistor N12 is electrically connected to the source of the NMOS transistor N11, the source of the NMOS transistor N12 is electrically connected to the drain of the NMOS transistor N13, and the gate of the NMOS transistor N12 is electrically connected to the drain of the NMOS transistor N9;

the drain of the NMOS transistor N13 is electrically connected to the source of the NMOS transistor N12, and the gate of the NMOS transistor N13 is electrically connected to the drain of the PMOS transistor P1;

the drain of the NMOS transistor N14 is electrically connected to the output Q of the latch, the source of the NMOS transistor N14 is electrically connected to the drain of the NMOS transistor N11, and the gate of the NMOS transistor N14 is electrically connected to the clock signal CLKB;

the source of the NMOS transistor N15 is electrically connected to the input D, the drain of the NMOS transistor N15 is electrically connected to the output Q of the latch, and the gate of the NMOS transistor N15 is electrically connected to the clock signal CLK;

the input end of the inverter I1 is electrically connected with the latch external input signal D, and the output end of the inverter I1 is electrically connected with the opposite signal DN of the latch external input signal D;

the input end of the inverter I2 is electrically connected with a clock signal CLK, and the output end is electrically connected with a clock signal CLKB;

the input end of the inverter I3 is electrically connected with the end M, and the output end of the inverter I3 is electrically connected with the input end of the clocked inverter CI;

the output end of the clocked inverter CI is electrically connected with the input end of the inverter I3;

the latch external input signal D is electrically connected to the sources of the NMOS transistors N16 and N18, and the opposite signal DN of the latch external input signal D is electrically connected to the sources of the NMOS transistors N17 and N19;

the clock signal CLK is electrically connected with the gates of the NMOS transistors N16-N19, the drain of the NMOS transistor N16 is electrically connected with the drain of the NMOS transistor N6, the drain of the NMOS transistor N17 is electrically connected with the drain of the NMOS transistor N7, the drain of the NMOS transistor N18 is electrically connected with the drain of the NMOS transistor N8, and the drain of the NMOS transistor N19 is electrically connected with the drain of the NMOS transistor N9;

the power supply VDD is electrically connected with the sources of the PMOS transistors P1-P6 and P9;

the sources of the NMOS transistors N5-N10 and N13 are grounded;

based on the circuit structure, PMOS transistors P1, P6, P7 and P8 surround and reinforce the latch internal storage nodes X5 and X6, and NMOS transistors N1 to N4 and N6 to N9 surround and reinforce the latch internal storage nodes X1 to X4;

PMOS transistors P2-P5 are used as pull-up tubes, NMOS transistors N5 and N10 are used as pull-down tubes, an inverter I3 and a clock-controlled inverter CI form weak pull-up, PMOS transistors P9-P11 and NMOS transistors N11-N13 form a three-input C unit, and the C unit has the functions of: when the input signals are all equal, the output signal is opposite to the input signal, otherwise, the output is kept unchanged;

the four internal storage nodes X1, X2, X3, and X4 of the latch are connected to the latch external input signal D and the opposite signal DN of the latch external input signal D through four NMOS transistors N16 to N19, and the turn-on of the four NMOS transistors N16 to N19 is controlled by a clock signal CLK.

The circuit is designed by adopting a polarity reinforcement principle, when the improvement of the anti-irradiation performance of the circuit structure is only considered, the internal storage nodes X1-X4 of the latch adopt a form surrounded by all NMOS tubes, and according to the polarity reinforcement principle, when the four internal nodes are bombarded by single particles, electrons are only accumulated at a drain end to form a negative pulse, so that the value of the node only generates the jump from '1' to '0'; the storage nodes X5 and X6 are surrounded by full PMOS tubes, and when the nodes are bombarded by single particles, holes are only accumulated at the drain end to form positive pulses, so that the values of the nodes only jump from '0' to '1', and the output nodes are not affected. When the floating nodes of F1-F6 are bombarded by the single particle, the output nodes are not affected; when the output node is bombarded, the feedback loop in the circuit can also recover to a normal state in a short time, and the design ensures the stability of the internal nodes X1-X6, thereby enhancing the single event upset resistance of the internal nodes in the circuit. The data stored by the latch is connected with the output end Q through the C unit, so that when the output signal is bombarded by particles, the correct output of the data can be ensured.

In addition, the output Q of the circuit is directly driven by the input D through a transmission gate, thus greatly reducing the transmission delay from D to Q.

Based on the above circuit configuration, when the circuit Latch operates in the transparent transmission mode, assuming that the input signal D is 1, the clock signal CLK is 1, and the four NOMS transistors N16 to N19 are in an on state, the input signal D writes data to the Latch internal node through the four NOMS transistors N16 to N19, so that the NMOS transistors N1, N3, N5, N7, and N9 are turned on, and the NMOS transistors N2, N4, N6, N8, and N10 are turned off;

PMOS transistor P7 is turned on and P8 is turned off, so that node X5 is equal to 0; the PMOS transistors P2, P4 and P6 are turned on, the node X6 is pulled up to 1, the PMOS transistors P1, P3 and P5 are turned off, the PMOS transistor P13 and the NMOS transistor N15 are turned on, the PMOS transistor P12 and the NMOS transistor N14 are turned off, the PMOS transistors P9 to P11 are turned on, and the NMOS transistors N11 to N13 are turned off;

the final node X1, X3, X6, X2, X4, X5, is 1, and the output Q is driven directly from the input D through the transmission gate, thus greatly reducing the transmission delay from D to Q.

When the Latch circuit works in the data Latch mode, the clock signal CLK is equal to 0, the four NOMS transistors N16 to N19 are turned off, the PMOS transistor P13 and the NMOS transistor N15 are turned off, the PMOS transistor P12 and the NMOS transistor N14 are turned on, and at this time, the output Q is driven by a C unit with three inputs, and a feedback loop inside the Latch circuit can ensure that the value of the output Q is in a stable state.

In order to more clearly show the technical solutions and the technical effects provided by the present invention, the following compares the circuit of the radiation-resistant latch unit provided by the embodiment of the present invention with the circuit of the prior art with reference to the accompanying drawings, and specifically includes the following contents:

(1) as shown in fig. 2, which is a timing waveform diagram of the radiation-resistant latch unit circuit provided by the embodiment of the present invention, it can be seen from the diagram that under the simulation conditions of 1.2V power supply voltage, TT process angle, and 27 ℃, the result of transient simulation shows that the transmission delay from the input D to the output Q of the RHPDL circuit is very small.

(2) As shown in fig. 3, which is a simulation diagram of transient waveforms (simulation condition: VDD: 1.2V) of internal nodes and output nodes of the irradiation-resistant latch unit circuit provided by the embodiment of the present invention, which are injected by current source pulses at different times, it can be seen from the diagram that the RHPDL circuit can implement all internal single-node inversion recovery and part of double-node inversion recovery, and by means of a layout optimization technique, all double-node inversion recovery can be implemented, and the irradiation-resistant latch unit circuit has good single-node and multi-node inversion immunity characteristics.

(3) FIG. 4 is a simulation diagram of transient waveforms of the internal node and the floating node injected by the current source pulse at different times in the irradiation-resistant latch unit circuit provided by the embodiment of the invention (simulation condition: VDD: 1.2V). As can be seen from the figure, the correct output of Q is guaranteed for both the toggling between the internal node and the floating node and the output node and the floating node.

(4) Table 1 is a simulation comparison table of area, read time and power consumption of the RHPL radiation-resistant latch unit circuit provided by the prior art circuit and the embodiment of the invention (simulation conditions are: Corner: TT; Temperature: 27 ℃; VDD: 1.2V):

TABLE 1

As can be seen from the table, the transmission delay of the present invention is minimal, and the value of PDA (product of power consumption, delay, area) also has great advantages compared to other circuits.

(5) Table 2 is a table comparing the SEU and DEU tolerance conditions of the RHPDL radiation-resistant latch unit circuit provided in the embodiments of the present invention and the prior art circuit:

TABLE 2

Latch	SNU Tolerant	SNU Resilent	DNU Tolerant	DNU Resilent
					T-Latch	×	×	×	×
ST	×	×	×	×
					DICE	√	√	×	×
TPDICE	√	√	√	×
					RH	√	√	√	√
FERST	√	×	×	×
					HSMUF	√	√	√	×
CLCT	√	×	×	×
					RFC	√	√	×	×
RHPDL	√	√	√	×

As can be seen from Table 2, three √ marks of SNU tolerant, SNU resilient and DNU resilient are obtained, and the RHPLD radiation-resistant latch unit circuit provided by the embodiment of the invention has better tolerance.

(6) Table 3 is a key charge comparison table (simulation conditions: VDD: 1.2V) of the RHPLD radiation-resistant latch unit circuit provided by the prior art circuit and the embodiment of the invention:

TABLE 3

As can be seen from table 3, the key charges of the RHPDL radiation-resistant latch unit circuit provided in the embodiment of the present invention are infinite, and no matter how much the node is attacked by the pulse, the logic of the output node is not inverted.

(7) Table 4 shows the stability comparison of SNU and DNU under process fluctuation of the RHPLD irradiation-resistant latch unit circuit provided by the embodiment of the invention and the prior art circuit (simulation conditions are VDD: 1.2V):

TABLE 4

As can be seen from Table 4, for 1000 Monte Carlo simulations, the failure rate of the present invention is 0, and the stability against SNU and DNU is high.

(8) FIG. 5 shows a voltage-to-delay comparison diagram (simulation conditions: VDD: 1.2V-1.4V) for the circuit of the prior art and the circuit of the radiation-resistant latch unit provided by the embodiment of the present invention. It can be seen from the figure that the transmission delay of the present invention is also minimal at low supply voltage (0.6V) and the rate of change of the delay is small as the supply voltage increases.

(9) FIG. 6 is a graph showing voltage vs. power consumption of the prior art circuit and the irradiation resistant latch unit circuit provided by the embodiment of the present invention (simulation conditions: VDD: 1.2V-1.4V). It can be seen from the figure that the power consumption of the invention is not greatly changed with the increase of the power supply voltage, and the invention has obvious advantages compared with the RH structure and is similar to other structures.

(10) FIG. 7 is a Temperature vs. delay diagram of a prior art circuit and a radiation-resistant latch cell circuit provided by an embodiment of the present invention (simulation conditions: VDD: 1.2V, Temperature: -40 ℃ -120 ℃). As can be seen from the figure, the delay of the circuit of the invention is not changed greatly with the continuous increase of the temperature, and is obviously better than other circuit structures.

(11) FIG. 8 is a Temperature vs. power diagram of a prior art circuit and an embodiment of the invention providing a radiation-resistant latch cell circuit (simulation conditions: VDD: 1.2V, Temperature: -40 deg.C-120 deg.C). As can be seen from the figure, with the continuous increase of the temperature, the power consumption of the invention is not greatly changed, and is better than RH, TPDICE and HSMUF circuits, and is similar to other structures.

It is noted that those skilled in the art will recognize that embodiments of the present invention are not described in detail herein.

Therefore, the radiation-resistant latch unit provided by the embodiment of the invention can improve the SEU resistance of the latch unit, greatly improve the reading speed of the unit and solve the problem of double-node overturning caused by charge sharing.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.