阅读说明：本技术 一种用于对存储器芯片进行测试的系统及方法 (System and method for testing memory chip ) 是由 李求洋 张蓬鹤 徐英辉 熊素琴 陈思禹 袁翔宇 杨巍 郭建宁 秦程林 王雅涛 于 2020-12-30 设计创作，主要内容包括：本发明公开了一种用于对存储器芯片进行测试的系统及方法,包括：包括：上位机,通过数字通道与测试平台系统相连接,用于根据测试需求产生与所述测试需求对应的波形激励样式和波形激励样式的调用顺序命令；用于获取被测存储器芯片输出的波形数据,将所述被测存储器输出的波形数据和预设的期望数据进行比较,获取测试结果,并根据所述测试结果确定所述被测存储器芯片的运行状态；测试平台系统,与被测存储器芯片相连接,用于根据所述波形激励样式的调用顺序命令和波形激励样式产生激励波形以驱动所述被测存储器芯片。本发明能够提供多个通道,通过更换测量夹具设计不同的测试子板,实现多种存储器芯片的测试。(The invention discloses a system and a method for testing a memory chip, which comprises the following steps: the method comprises the following steps: the upper computer is connected with the test platform system through a digital channel and used for generating a waveform excitation pattern corresponding to the test requirement and a calling sequence command of the waveform excitation pattern according to the test requirement; the device comprises a test module, a memory chip and a control module, wherein the test module is used for acquiring waveform data output by the memory chip to be tested, comparing the waveform data output by the memory chip to be tested with preset expected data to acquire a test result, and determining the running state of the memory chip to be tested according to the test result; and the test platform system is connected with the tested memory chip and used for generating an excitation waveform according to the calling sequence command of the waveform excitation pattern and the waveform excitation pattern so as to drive the tested memory chip. The invention can provide a plurality of channels, and realizes the test of various memory chips by replacing the measuring clamp to design different test daughter boards.)

1. A system for testing memory chips, the system comprising:

the upper computer is connected with the test platform system through a digital channel and used for generating a waveform excitation pattern corresponding to the test requirement and a calling sequence command of the waveform excitation pattern according to the test requirement; the device comprises a test module, a memory chip and a control module, wherein the test module is used for acquiring waveform data output by the memory chip to be tested, comparing the waveform data output by the memory chip to be tested with preset expected data to acquire a test result, and determining the running state of the memory chip to be tested according to the test result;

and the test platform system is connected with the tested memory chip and used for generating an excitation waveform according to the calling sequence command of the waveform excitation pattern and the waveform excitation pattern so as to drive the tested memory chip.

2. The system of claim 1, wherein the test platform system is connected to the memory chips under test disposed on the test daughter board through a connector; the test daughter board is provided with different types of measuring clamps, and for different types of memory chips, the coverage of test requirements is realized by replacing the corresponding measuring clamps.

3. The system of claim 2, wherein the test platform system communicates with the memory chip under test through 2 100pin connectors, each 200pin connector includes a ground, a power supply and a digital channel portion, the coverage of the test is completed by calling corresponding resources according to the test requirements of the memory chip under test, the number of digital channels that can be called in the whole connector is 96, and each digital channel can be configured as an input, output or bidirectional IO resource and is allocated to a pin of the memory chip under test.

4. The system of claim 1, wherein the upper computer generates a waveform file capable of identifying the bottom firmware according to the state of the received user output stimulus according to each written cycle, and sends the waveform file to the bottom firmware, so that the execution unit of the bottom firmware generates a corresponding execution program according to the waveform file, and obtains a stimulus waveform test data stream after the translation processing of the bottom layer, and outputs the stimulus waveform to the stimulus pin of the tested memory chip one by one according to the clock cycle, thereby completing the output of the test stimulus waveform.

5. The system of claim 1, wherein the host computer further comprises:

a user interface module comprising: the window management submodule, the configuration information management submodule and the display management submodule are used for managing the window information, the configuration information and the display information;

the chip information management module is used for realizing the addition, deletion and modification of chip information and realizing the loading and storage of data by operating the chip information data model and the file management module;

the hardware communication module is used for realizing the communication work with a lower computer and comprises a data conversion sub-module, a communication protocol sub-module and a port module;

and the test flow control module is used for controlling the test flow of the chip.

6. A method for testing a memory chip, the method comprising:

the upper computer generates a waveform excitation pattern corresponding to the test requirement and a calling sequence command of the waveform excitation pattern according to the test requirement;

the test platform system generates an excitation waveform according to the calling sequence command of the waveform excitation pattern and the waveform excitation pattern so as to drive the tested memory chip;

the upper computer obtains waveform data output by a tested memory chip, compares the waveform data output by the tested memory with preset expected data to obtain a test result, and determines the running state of the tested memory chip according to the test result.

7. The method of claim 6, further comprising:

connecting the test platform system with a tested memory chip arranged on the test daughter board through a connector, and replacing a corresponding measuring clamp according to the type of the memory chip to realize the coverage of test requirements; and different types of measuring clamps are arranged on the test daughter board.

8. The method of claim 7, wherein the test platform system communicates with the memory chip under test through 2 100pin connectors, each 200pin connector includes a ground, a power supply and a digital channel portion, the coverage of the test is completed by calling corresponding resources according to the test requirements of the memory chip under test, the number of digital channels that can be called in the whole connector is 96, and each digital channel can be configured as an input, output or bidirectional IO resource and is allocated to a pin of the memory chip under test.

9. The method as claimed in claim 6, wherein the upper computer generates a waveform file capable of enabling the bottom firmware to recognize according to the state of the received user output excitation according to each written cycle, and sends the waveform file to the bottom firmware, so that the execution unit of the bottom firmware generates a corresponding execution program according to the waveform file, and obtains an excitation waveform test data stream after the translation processing of the bottom layer, and outputs the excitation waveform test data stream to the excitation pin of the tested memory chip one by one according to the clock cycle, thereby completing the output of the test excitation waveform.

10. The method of claim 6, further comprising:

the upper computer manages the window information, the configuration information and the display information through a window management submodule, a configuration information management submodule and a display management submodule of the user interface module;

the upper computer realizes the addition, deletion and modification of chip information through a chip information management module, and realizes the loading and storage of data through operating a chip information data model and a file management module;

the upper computer realizes the communication work with the lower computer through a hardware communication module, and the hardware communication module comprises a data conversion sub-module, a communication protocol sub-module and a port module;

and the upper computer controls the test flow of the chip through the test flow control module.

Technical Field

The present invention relates to the field of memory testing technologies, and more particularly, to a system and method for testing a memory chip.

Background

The realization of the full-parameter test of the mass storage is time-consuming, and in the actual test, the traditional test system and method are difficult to realize the complete coverage of each unit of the storage or the coverage is not comprehensive enough.

The test of the memory chip is greatly different from the test of the common digital logic circuit in principle and algorithm, and according to the test method of the common digital logic circuit, a method for infinitely supporting the storage of test vectors cannot be found, and the test requirement of the memory cannot be met. In addition, the failure modes of the memory are various, some failures are failures of a single memory cell, such as locking to 0, locking to 1 and the like, and the failure modes can be tested and discovered through reading and writing operations of the memory cell; some failure modes are the mutual influence between adjacent storage units, and some failures are even unstable, and the failure modes cannot be found by means of simple read-write operation and can be detected by adopting various complex storage testing algorithms. At present, the commonly used memory test algorithms include a checkerboard algorithm, a March algorithm, a diagonal algorithm, a moving diagonal algorithm, a row and column skipping algorithm, a walking algorithm and the like. Some specific failure modes of the memory cells targeted by each algorithm. To realize the testing of mass storage and the memory testing algorithm, a special memory testing pattern generation mode is needed to solve the problem.

Disclosure of Invention

The invention provides a system and a method for testing a memory chip, which aim to solve the problem of how to test the memory chip.

In order to solve the above-mentioned problems, according to an aspect of the present invention, there is provided a system for testing a memory chip, the system including:

the upper computer is connected with the test platform system through a digital channel and used for generating a waveform excitation pattern corresponding to the test requirement and a calling sequence command of the waveform excitation pattern according to the test requirement; the device comprises a test module, a memory chip and a control module, wherein the test module is used for acquiring waveform data output by the memory chip to be tested, comparing the waveform data output by the memory chip to be tested with preset expected data to acquire a test result, and determining the running state of the memory chip to be tested according to the test result;

and the test platform system is connected with the tested memory chip and used for generating an excitation waveform according to the calling sequence command of the waveform excitation pattern and the waveform excitation pattern so as to drive the tested memory chip.

Preferably, the test platform system is connected with a tested memory chip arranged on the test daughter board through a connector; the test daughter board is provided with different types of measuring clamps, and for different types of memory chips, the coverage of test requirements is realized by replacing the corresponding measuring clamps.

Preferably, the test platform system communicates with the memory chip under test through 2 100pin connectors, each 200pin connector includes a ground part, a power part and a digital channel part, the coverage of the test is completed by calling corresponding resources according to the test requirement of the memory chip under test, the number of the digital channels that can be called in the whole connector is 96, and each digital channel can be configured as an input, output or bidirectional IO resource and is allocated to the pins of the memory chip under test.

Preferably, the upper computer generates a waveform file capable of identifying the bottom firmware according to the state of the received user output excitation in each written cycle, and sends the waveform file to the bottom firmware, so that the execution unit of the bottom firmware generates a corresponding execution program according to the waveform file, and obtains an excitation waveform test data stream after translation processing of the bottom, and outputs the excitation waveform test data stream to the excitation pin of the tested memory chip one by one according to the clock cycle, thereby completing output of the test excitation waveform.

Preferably, wherein the host computer further includes:

a user interface module comprising: the window management submodule, the configuration information management submodule and the display management submodule are used for managing the window information, the configuration information and the display information;

the chip information management module is used for realizing the addition, deletion and modification of chip information and realizing the loading and storage of data by operating the chip information data model and the file management module;

the hardware communication module is used for realizing the communication work with a lower computer and comprises a data conversion sub-module, a communication protocol sub-module and a port module;

and the test flow control module is used for controlling the test flow of the chip.

According to another aspect of the present invention, there is provided a method for testing a memory chip, the method including:

the upper computer generates a waveform excitation pattern corresponding to the test requirement and a calling sequence command of the waveform excitation pattern according to the test requirement;

the test platform system generates an excitation waveform according to the calling sequence command of the waveform excitation pattern and the waveform excitation pattern so as to drive the tested memory chip;

the upper computer obtains waveform data output by a tested memory chip, compares the waveform data output by the tested memory with preset expected data to obtain a test result, and determines the running state of the tested memory chip according to the test result.

Preferably, wherein the method further comprises:

connecting the test platform system with a tested memory chip arranged on the test daughter board through a connector, and replacing a corresponding measuring clamp according to the type of the memory chip to realize the coverage of test requirements; and different types of measuring clamps are arranged on the test daughter board.

Preferably, the test platform system communicates with the memory chip under test through 2 100pin connectors, each 200pin connector includes a ground part, a power part and a digital channel part, the coverage of the test is completed by calling corresponding resources according to the test requirement of the memory chip under test, the number of the digital channels that can be called in the whole connector is 96, and each digital channel can be configured as an input, output or bidirectional IO resource and is allocated to the pins of the memory chip under test.

Preferably, the upper computer generates a waveform file capable of identifying the bottom firmware according to the state of the received user output excitation in each written cycle, and sends the waveform file to the bottom firmware, so that the execution unit of the bottom firmware generates a corresponding execution program according to the waveform file, and obtains an excitation waveform test data stream after translation processing of the bottom, and outputs the excitation waveform test data stream to the excitation pin of the tested memory chip one by one according to the clock cycle, thereby completing output of the test excitation waveform.

Preferably, wherein the method further comprises:

the upper computer manages the window information, the configuration information and the display information through a window management submodule, a configuration information management submodule and a display management submodule of the user interface module;

the upper computer realizes the addition, deletion and modification of chip information through a chip information management module, and realizes the loading and storage of data through operating a chip information data model and a file management module;

the upper computer realizes the communication work with the lower computer through a hardware communication module, and the hardware communication module comprises a data conversion sub-module, a communication protocol sub-module and a port module;

and the upper computer controls the test flow of the chip through the test flow control module.

The invention provides a system and a method for testing a memory chip.A host computer can determine an excitation waveform according to a test requirement, send the excitation waveform to a test system platform to act on the tested memory chip, acquire waveform data output by the tested memory chip, compare the waveform data output by the tested memory with preset expected data, acquire a test result and determine the running state of the tested memory chip according to the test result; the system can provide a plurality of channels, and different test daughter boards are designed by replacing the measuring clamp, so that the test of various memory chips is realized.

Drawings

A more complete understanding of exemplary embodiments of the present invention may be had by reference to the following drawings in which:

FIG. 1 is a block diagram of a system 100 for testing memory chips according to an embodiment of the invention;

FIG. 2 is an architecture diagram of a test system according to an embodiment of the present invention;

FIG. 3 is a block diagram of a host computer according to an embodiment of the present invention;

FIG. 4 is a diagram of a user's main interface of a system according to an embodiment of the present invention;

FIG. 5 is an exemplary diagram of testing a master form according to an embodiment of the present invention;

FIG. 6 is a flow chart of a method 600 for testing a memory chip according to an embodiment of the invention.

Detailed Description

The exemplary embodiments of the present invention will now be described with reference to the accompanying drawings, however, the present invention may be embodied in many different forms and is not limited to the embodiments described herein, which are provided for complete and complete disclosure of the present invention and to fully convey the scope of the present invention to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the accompanying drawings is not intended to be limiting of the invention. In the drawings, the same units/elements are denoted by the same reference numerals.

Unless otherwise defined, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Further, it will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

FIG. 1 is a block diagram of a system 100 for testing memory chips according to an embodiment of the invention. As shown in fig. 1, in the system for testing a memory chip according to the embodiment of the present invention, an upper computer can determine an excitation waveform according to a test requirement, send the excitation waveform to a test system platform to act on the memory chip to be tested, obtain waveform data output by the memory chip to be tested, compare the waveform data output by the memory chip to be tested with preset expected data, obtain a test result, and determine an operating state of the memory chip to be tested according to the test result; the system can provide a plurality of channels, and different test daughter boards are designed by replacing the measuring clamp, so that the test of various memory chips is realized. The system 100 for testing a memory chip provided by the embodiment of the invention comprises: host computer 101 and test platform system 102.

Preferably, the upper computer 101 is connected to the test platform system through a digital channel, and is configured to generate a waveform excitation pattern corresponding to the test requirement and a call sequence command of the waveform excitation pattern according to the test requirement; the device comprises a test module, a memory chip and a control module, wherein the test module is used for acquiring waveform data output by the memory chip to be tested, comparing the waveform data output by the memory chip to be tested with preset expected data, acquiring a test result and determining the running state of the memory chip to be tested according to the test result.

Preferably, the test platform system is connected with a tested memory chip arranged on the test daughter board through a connector; the test daughter board is provided with different types of measuring clamps, and for different types of memory chips, the coverage of test requirements is realized by replacing the corresponding measuring clamps.

Preferably, the test platform system communicates with the memory chip under test through 2 100pin connectors, each 200pin connector includes a ground part, a power part and a digital channel part, the coverage of the test is completed by calling corresponding resources according to the test requirement of the memory chip under test, the number of the digital channels that can be called in the whole connector is 96, and each digital channel can be configured as an input, output or bidirectional IO resource and is allocated to the pins of the memory chip under test.

Preferably, the upper computer generates a waveform file capable of identifying the bottom firmware according to the state of the received user output excitation in each written cycle, and sends the waveform file to the bottom firmware, so that the execution unit of the bottom firmware generates a corresponding execution program according to the waveform file, and obtains an excitation waveform test data stream after translation processing of the bottom, and outputs the excitation waveform test data stream to the excitation pin of the tested memory chip one by one according to the clock cycle, thereby completing output of the test excitation waveform.

Preferably, the test platform system 102 is connected to the memory chip under test, and is configured to generate an excitation waveform according to the calling sequence command of the waveform excitation pattern and the waveform excitation pattern to drive the memory chip under test.

Preferably, wherein the host computer further includes:

a user interface module comprising: the window management submodule, the configuration information management submodule and the display management submodule are used for managing the window information, the configuration information and the display information;

the chip information management module is used for realizing the addition, deletion and modification of chip information and realizing the loading and storage of data by operating the chip information data model and the file management module;

the hardware communication module is used for realizing the communication work with a lower computer and comprises a data conversion sub-module, a communication protocol sub-module and a port module;

and the test flow control module is used for controlling the test flow of the chip.

Referring to fig. 2, in the dedicated memory test system of the present invention, the memory chip is connected to the test platform system through the connector, and the test platform system needs to be controlled by the upper computer to obtain programmable test waveform excitation from the upper computer to cover the test items of the chip under test. The system can flexibly test different memory chips, complete the functional coverage of the memory chips, and measure the write-in and read-out of data and the direct current parameters of the memory chips. The test system can provide a plurality of channels, different test daughter boards are designed by replacing the measuring clamp, and the test of various memory chips can be completed.

The upper computer needs to generate a programmable waveform excitation pattern and a sequence command for calling the pattern, and the sequence command is downloaded to the test platform system. The upper computer also needs to support functions of management, detection, analysis of test results and the like of the platform system. And supporting the generation of various memory chip waveforms, transmitting the generated waveform files to the test platform system, and controlling the operation of the platform system to finish the test.

The upper computer is connected with the test platform system through the gigabit Ethernet, the transmission rate of 1Gbps is realized, the excitation waveform data is sent to the test platform system in the form of sending Ethernet messages, and the test platform system responds to the Ethernet messages of the upper computer and transmits the data output by the tested memory chip back to the upper computer according to the agreed communication protocol.

The upper computer can be programmed to generate a specific excitation waveform, the waveform is written according to a fixed period, and a user can designate the state of excitation output in each period. The states may be high, low, and high impedance states. A certain number of periodic states form an excitation waveform which can be continuously executed for a certain time, and the upper computer downloads the change data to the test platform system.

As shown in fig. 3, the upper computer software includes a chip user interface module, an information management module, a hardware communication module, a test flow control module, and sub-modules (data conversion, file management, text output, etc.) for implementing each specific function. The user interface module mainly comprises: the system comprises a window management module, a configuration information management module, a display management module and the like. The chip information management module is responsible for adding, deleting and modifying chip information, and loading and storing of data are achieved by operating the chip information data model and the file management module. The hardware communication module is responsible for communication work with the lower computer and comprises a data conversion module, a communication protocol module and a port module. The test flow control module realizes all methods of chip test by calling each sub-module, and then organizes the methods to form a whole set of test flow.

As shown in fig. 4, the user interface is composed of a main interface and a main test form, a test item list, a parameter list, a summary list and a log form contained in the main interface. The main interface is used as other child form containers and is responsible for controlling the overall process (starting and ending tests) and managing and coordinating the states of the child forms. The test master window manages the state of each slot (enabled or disabled slot), and displays the test information (test result, error type, number of test completed, number of passed slots, and number of failed slots) of each slot, as shown in fig. 5.

The upper computer enables a user to input waveform information in a form of a human-computer interface, the user can easily edit an excitation waveform according to the time sequence requirement of the chip to be tested, and the upper computer software can generate a waveform file which can be identified by the bottom firmware according to the excitation waveform generated by the user editing and send the waveform file to the bottom execution unit. The bottom firmware can generate a corresponding execution program according to a programming file of the upper computer, and a test data stream of the excitation waveform is obtained after translation processing of the bottom, wherein the test data stream is the excitation waveform of the time dimension and is output to an excitation pin of the tested chip one by one according to the clock period, so that the output of the test excitation is completed. The upper computer can collect and detect the waveform data output by the memory through the bottom firmware, compares the waveform data according to expected values transmitted by the upper computer, stores the compared results in the test platform system, reads out the test results from the test platform, and can know the running state of the tested chip through analysis of the test results.

For the DC parameter of the tested memory chip, the upper computer can control the operation of the test platform through programming, the test platform can read the ADC parameter on the system to obtain the numerical values of current and voltage, the data sampling of the DC parameter is completed, the sampled data can be stored in the test platform system, and the upper computer can read the corresponding numerical value to complete the test of the DC parameter.

In the invention, the test platform system provides a plurality of connectors to be connected with the test daughter board, the tested memory chip is connected with the test platform system through the test daughter board and the connectors, and the waveform excitation generated by the test platform system can drive the tested memory chip. When the generated excitation meets the requirements of the manual of the tested chip, the corresponding read-write operation is verified. For different memory chips, the test requirements can be covered only by replacing the measuring clamp or the test daughter board.

The test platform system provides 2 100pin connectors for the test daughter board to be connected with a chip to be tested, the 200pin connector comprises a ground part, a power supply part and a digital channel part, and when the platform is used, corresponding resources can be called to complete test coverage according to the requirement of an actual device to be tested. The total number of digital channels that can be called in the whole connector is 96, and the digital channels can be configured to be input, output and bidirectional IO resources and are allocated to the pins of the chip to be tested.

Aiming at different test daughter boards, the upper computer can update and distribute the attribute of 96 digital channels, before a test is started, the upper computer needs to input the pin position information of a tested memory ram, the distribution of the 96 digital channels is completed according to the information, each digit is independent, no interference exists between the digits, different digital channels can be bound together to form a bus of a desired address or data, the bound digital channels are controlled, the numerical value of the bus can be changed, and different stimuli can be obtained.

For example, when measuring the memory ram, the upper computer may set the execution period of the ram to be measured by editing the period parameter, so as to achieve the purpose of adjusting the read-write speed of the ram, so as to measure the performance of the chip to be measured in different clock periods. Different digital channels can be activated by calling, the number of the address and the data channel of the ram is expanded, a wider address is allocated to cover a deeper ram space, the bit width can be adjusted according to different ram configurations, and different bit widths of the same ram under different configurations are covered. And finally, the purpose of measuring the rams with different depths and bit widths by using the same measuring platform system is achieved.

FIG. 6 is a flow chart of a method 600 for testing a memory chip according to an embodiment of the invention. As shown in fig. 6, a method 600 for testing a memory chip according to an embodiment of the present invention starts with step 601, and the upper computer generates a waveform excitation pattern and a calling sequence command of the waveform excitation pattern corresponding to a test requirement according to the test requirement at step 601.

In step 602, the test platform system generates an excitation waveform according to the calling sequence command of the waveform excitation pattern and the waveform excitation pattern to drive the tested memory chip.

In step 603, the upper computer obtains waveform data output by the tested memory chip, compares the waveform data output by the tested memory chip with preset expected data to obtain a test result, and determines the running state of the tested memory chip according to the test result.

Preferably, wherein the method further comprises:

connecting the test platform system with a tested memory chip arranged on the test daughter board through a connector, and replacing a corresponding measuring clamp according to the type of the memory chip to realize the coverage of test requirements; and different types of measuring clamps are arranged on the test daughter board.

Preferably, the test platform system communicates with the memory chip under test through 2 100pin connectors, each 200pin connector includes a ground part, a power part and a digital channel part, the coverage of the test is completed by calling corresponding resources according to the test requirement of the memory chip under test, the number of the digital channels that can be called in the whole connector is 96, and each digital channel can be configured as an input, output or bidirectional IO resource and is allocated to the pins of the memory chip under test.

Preferably, the upper computer generates a waveform file capable of identifying the bottom firmware according to the state of the received user output excitation in each written cycle, and sends the waveform file to the bottom firmware, so that the execution unit of the bottom firmware generates a corresponding execution program according to the waveform file, and obtains an excitation waveform test data stream after translation processing of the bottom, and outputs the excitation waveform test data stream to the excitation pin of the tested memory chip one by one according to the clock cycle, thereby completing output of the test excitation waveform.

Preferably, wherein the method further comprises:

the upper computer manages the window information, the configuration information and the display information through a window management submodule, a configuration information management submodule and a display management submodule of the user interface module;

the upper computer realizes the addition, deletion and modification of chip information through a chip information management module, and realizes the loading and storage of data through operating a chip information data model and a file management module;

the upper computer realizes the communication work with the lower computer through a hardware communication module, and the hardware communication module comprises a data conversion sub-module, a communication protocol sub-module and a port module;

and the upper computer controls the test flow of the chip through the test flow control module.

The method 600 for testing a memory chip according to an embodiment of the present invention corresponds to the system 100 for testing a memory chip according to another embodiment of the present invention, and is not described herein again.

The invention has been described with reference to a few embodiments. However, other embodiments of the invention than the one disclosed above are equally possible within the scope of the invention, as would be apparent to a person skilled in the art from the appended patent claims.

Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a/an/the [ device, component, etc ]" are to be interpreted openly as referring to at least one instance of said device, component, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.