阅读说明：本技术 一种无频率损耗的集成电路抗单粒子瞬态加固方法 (Frequency-loss-free integrated circuit single-particle transient-resistant reinforcing method ) 是由 宋睿强 邵津津 吴振宇 刘必慰 梁斌 池雅庆 陈建军 于 2020-12-24 设计创作，主要内容包括：本发明公开一种无频率损耗的集成电路抗单粒子瞬态加固方法,步骤包括：S1.获取目标集成电路中各条数据路径的最后一级组合电路单元；S2.对获取的各最后一级组合电路单元进行静态时序分析,得到通过各最后一级组合电路单元的最大数据通路,并计算最大数据通路的时序余量；S3.根据计算出的各最大数据通路的时序余量对应确定具有匹配滤波参数的滤波单元；S4.将确定得到的滤波单元对应插入至各条数据路径中最后一级组合电路单元的输出端,得到加固后的集成电路。本发明能够抗单粒子瞬态,同时能够保持集成电路工作频率不变,实现无频率损耗。(The invention discloses a single event transient resistance reinforcing method for an integrated circuit without frequency loss, which comprises the following steps: s1, acquiring a last-stage combined circuit unit of each data path in a target integrated circuit; s2, performing static time sequence analysis on each acquired last-stage combined circuit unit to obtain a maximum data path passing through each last-stage combined circuit unit, and calculating the time sequence allowance of the maximum data path; s3, correspondingly determining a filtering unit with matched filtering parameters according to the calculated time sequence allowance of each maximum data path; and S4, correspondingly inserting the filter unit obtained by determination into the output end of the last-stage combined circuit unit in each data path to obtain the reinforced integrated circuit. The invention can resist single-particle transient, can keep the working frequency of the integrated circuit unchanged, and realizes no frequency loss.)

1. A method for reinforcing single event transient resistance of an integrated circuit without frequency loss is characterized by comprising the following steps:

s1, obtaining a combined circuit: acquiring a last-stage combined circuit unit of each data path in a target integrated circuit;

s2, timing sequence allowance calculation: performing static time sequence analysis on each acquired last-stage combined circuit unit to obtain a maximum data path passing through each last-stage combined circuit unit, and calculating the time sequence allowance of the maximum data path;

s3, the filtering unit determines: according to the calculated time sequence allowance of each maximum data path, correspondingly determining a filter unit with matched filter parameters for each last-stage combined circuit unit;

s4, reinforcing the integrated circuit: and correspondingly inserting the filter unit obtained by determination into the output end of the last-stage combined circuit unit in each data path to obtain the reinforced integrated circuit.

2. The method according to claim 1, wherein in step S1, for a target data path, the last-stage combinational circuit unit directly connected to the next-stage flip-flop is obtained by using the current-stage flip-flop as a data path starting point and the next-stage flip-flop as a data path ending point.

3. The method of claim 1, wherein the step of calculating the timing margin of the largest data path in step S2 comprises:

s21, calculating a delay parameter of the current maximum data path;

s22, calculating data transmission of the current maximum data path according to the delay parameters obtained by calculationArrival time T of the trigger broadcast to the next stage_i，arrive；

S23, obtaining the arrival time T which must be met by data propagation to the next stage trigger_i，require；

S24, according to the arrival time T of the data to be transmitted to the next stage trigger_i，arriveAnd the arrival time T that must be met for the data to propagate to the next level of triggers_i，requireAnd obtaining the timing sequence allowance of the current maximum data path.

4. The method according to claim 3, wherein the delay parameters include circuit unit delay and interconnect line delay parameters.

5. The method according to claim 3, wherein the arrival time T that must be satisfied for the data to propagate to the next stage flip-flop in step S23 is specified_i，requireMinus the arrival time T of the data propagating to the next stage flip-flop_i，arriveAnd obtaining the timing sequence allowance of the current maximum data path.

6. The method according to any one of claims 1 to 5, wherein the last stage of the combinational circuit unit is a combinational circuit unit directly connected to the next stage of the flip-flop in each data path.

Technical Field

The invention relates to the technical field of large-scale integrated circuit design, in particular to a single-particle transient-resistant reinforcing method for an integrated circuit without frequency loss.

Background

In the cosmonautic space, there are a large number of energetic particles. After being bombarded by the high-energy particles, the integrated circuit can generate single-particle transient pulses. For example, when a single-event transient pulse propagates to a data port of a sequential circuit unit, if a timing constraint condition of the sequential unit is satisfied, a data value stored in the sequential unit is changed, so that the stored data is erroneous.

In order to inhibit the single-event transient pulse from being transmitted to the input end of the trigger, a reinforcement method is required to be adopted to reinforce the integrated circuit, wherein the most common reinforcement method is the reinforcement method adopting a filter circuit, the filter circuit usually consists of a delay unit and a decision circuit, data signals respectively reach the decision circuit from two paths, wherein the first path directly reaches the decision circuit, and the second path reaches the decision circuit after passing through the delay unit; when the data signal results on the two paths are the same, the decision circuit outputs the same data value, and when the data signal results on the two paths are different, the decision circuit keeps the data value of the previous clock period. After the single-event transient pulse is propagated into the filtering unit, due to the existence of the delay unit, the time for the transient pulse to reach the decision circuit on the two paths is different, and the decision circuit still keeps the data value of the previous clock, so that the propagation of the single-event transient pulse to the input end of the sequence unit is inhibited.

However, when the above-mentioned conventional filter circuit strengthening method is adopted, due to the introduction of the delay circuit and the decision circuit, unit delay is introduced in the data path, so that the maximum frequency at which the whole data path can operate is reduced, and for a large-scale integrated circuit, the maximum operating frequency is determined by the critical data path in the circuit. In the integrated circuit design stage, the critical data path is usually configured to just meet the timing requirement of the circuit, and no more timing margin remains. At this point, if the conventional filter circuit reinforcement method is still used, critical data path timing violations may be incurred, thereby reducing the overall integrated circuit operating frequency, which is unacceptable for frequency sensitive integrated circuits. Therefore, it is desirable to provide a method for reinforcing an integrated circuit against a single-event transient, so as to resist the single-event transient, and simultaneously maintain the operating frequency of the integrated circuit unchanged, thereby achieving no frequency loss.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the method for reinforcing the single-event transient resistance of the integrated circuit, which is simple in implementation method, can resist the single-event transient, can keep the working frequency of the integrated circuit unchanged, and realizes no frequency loss.

In order to solve the technical problems, the technical scheme provided by the invention is as follows:

a frequency-loss-free integrated circuit single event transient resistance reinforcing method comprises the following steps:

s1, obtaining a combined circuit: acquiring a last-stage combined circuit unit of each data path in a target integrated circuit;

s2, timing sequence allowance calculation: performing static time sequence analysis on each acquired last-stage combined circuit unit to obtain a maximum data path passing through each last-stage combined circuit unit, and calculating the time sequence allowance of the maximum data path;

s3, the filtering unit determines: according to the calculated time sequence allowance of each maximum data path, correspondingly determining a filter unit with matched filter parameters for each last-stage combined circuit unit;

s4, reinforcing the integrated circuit: and correspondingly inserting the filter unit obtained by determination into the output end of the last-stage combined circuit unit in each data path to obtain the reinforced integrated circuit.

Further, in step S1, for a target data path, the last-stage combinational circuit unit directly connected to the next-stage flip-flop is obtained by specifically using the current-stage flip-flop as the start point of the data path and the next-stage flip-flop as the end point of the data path.

Further, the step of calculating the timing margin of the maximum data path in step S2 includes:

s21, calculating a delay parameter of the current maximum data path;

s22, calculating the arrival time T of the data transmission of the current maximum data path to the next-stage trigger according to the calculated delay parameters_i，arrive；

S23, obtaining the arrival time T which must be met by data propagation to the next stage trigger_i，require；

S24, according to the arrival time T of the data to be transmitted to the next stage trigger_i，arriveAnd the arrival time T that must be met for the data to propagate to the next level of triggers_i，requireAnd obtaining the timing sequence allowance of the current maximum data path.

Furthermore, the delay parameters include circuit unit delay and interconnection line delay parameters.

Further, the arrival time T that must be satisfied for the data to propagate to the next level trigger in step S23 is specified_i，_requireMinus the arrival time T of the data propagating to the next stage flip-flop_i，arriveAnd obtaining the timing sequence allowance of the current maximum data path.

Further, the last stage of combinational circuit unit is specifically a combinational circuit unit directly connected with the next stage of flip-flop in each data path.

Compared with the prior art, the invention has the advantages that:

1. according to the invention, through analyzing the time sequence allowance of each data path in the integrated circuit and selecting the filtering units with different filtering parameters according to the time sequence allowance of different data paths, the data paths of each level of the integrated circuit can still meet the static time sequence requirement after the filtering units are inserted, so that the integrated circuit can still normally work under the original frequency, and meanwhile, the single-particle transient resistance of the integrated circuit is improved, thereby realizing no frequency loss.

2. The invention can selectively insert the filter unit in the physical design process of the large-scale integrated circuit, thereby being suitable for the characteristic of less time sequence allowance of the large-scale integrated circuit and improving the single-event transient resistance of the integrated circuit on the basis of keeping the working frequency of the integrated circuit unchanged.

Drawings

Fig. 1 is a schematic flow chart of an implementation process of the single-event transient hardening resisting method of the integrated circuit without frequency loss in the embodiment.

Fig. 2 is a schematic diagram of circuit structures of an nth stage flip-flop to an N +1 th stage flip-flop in an embodiment of specific application.

Fig. 3 is a schematic circuit diagram of the circuit structure from the N-th stage flip-flop to the N + 1-th stage flip-flop after the reinforcement in the embodiment of the present invention.

Detailed Description

The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.

As shown in fig. 1, the steps of the method for reinforcing the single-event transient resistance of the integrated circuit without frequency loss in this embodiment include:

s1, obtaining a combined circuit: acquiring a last-stage combined circuit unit of each data path in a target integrated circuit;

s2, timing sequence allowance calculation: performing static time sequence analysis on each acquired last-stage combined circuit unit to obtain a maximum data path passing through each last-stage combined circuit unit, and calculating the time sequence allowance of the maximum data path;

s3, the filtering unit determines: correspondingly determining a filter unit with matched filter parameters for each last-stage combined circuit unit according to the calculated time sequence allowance of each maximum data channel;

and S4, correspondingly inserting the filter unit obtained by determination into the output end of the last-stage combined circuit unit in each data path to obtain the reinforced integrated circuit.

In the embodiment, the time sequence allowance of each data path in the integrated circuit is analyzed, and the filter units with different filter parameters are selected according to the time sequence allowances of different data paths, so that after the filter units are inserted, each level of data path of the integrated circuit still meets the static time sequence requirement, the integrated circuit can still normally work under the original frequency, the single-particle transient resistance of the integrated circuit is improved, and no frequency loss is realized.

In step S1 of this embodiment, for a target data path, a last-stage combinational circuit unit directly connected to a next-stage flip-flop is obtained by specifically using a current-stage flip-flop as a data path starting point and a next-stage flip-flop as a data path ending point.

In a specific application embodiment, in the physical design stage of the integrated circuit, the nth stage flip-flop is used as the starting point of the data path, the (N + 1) th stage flip-flop is used as the end point of the data path, and N is 0,1,2 …, the name of the last stage combined circuit unit directly connected with the (N + 1) th stage flip-flop can be obtained through the physical design tool of the integrated circuit, and the names of the last stage combined circuit units of all the data paths are sequentially obtained according to the above method.

And after the last-stage combined circuit unit is obtained, the maximum data path passing through the last-stage combined circuit unit is obtained through static time sequence analysis, and the time sequence allowance of the maximum data path is determined by the maximum data path. The step of calculating the timing margin of the maximum data path in step S2 in this embodiment includes:

s21, calculating a delay parameter of the current maximum data path;

s22, calculating the arrival time T of the data transmission of the current maximum data path to the next stage trigger according to the calculated delay parameters_i，arrive；

S23, obtaining the arrival time T which must be met by data propagation to the next stage trigger_i，require；

S24, according to the arrival time T of data propagation to the next stage trigger_i，arriveAnd the arrival time T that must be met for the data to propagate to the next level of triggers_i，requireObtaining the time sequence residue of the current maximum data pathAmount of the compound (A).

The delay parameters specifically include circuit unit delay and interconnection line delay parameters, and the arrival time T of data transmission to the next-stage trigger is obtained according to the circuit unit delay and interconnection line delay parameters in the maximum data path_i，arriveCalculating the arrival time T which must be satisfied for the data to propagate to the (N + 1) th trigger by static timing analysis according to the working frequency of the circuit_i，requireThe arrival time T that must be satisfied to propagate the data to the next level flip-flop_i，requireMinus the arrival time T of the data propagating to the next stage flip-flop_i，arriveAnd obtaining the time sequence allowance of the current maximum data path. And then selecting the filtering units with different filtering parameters according to the time sequence margin value.

Referring to fig. 1, the detailed steps of the method for reinforcing the single event transient resistance of the integrated circuit without frequency loss in this embodiment are as follows:

step S1: in the physical design stage of the integrated circuit, traversing all triggers, taking the nth level trigger as a data path starting point and the (N + 1) th level trigger as a data path end point each time, obtaining the name of the last level combined circuit unit directly connected with the (N + 1) th level trigger through a physical design tool of the integrated circuit, and turning to the step S2;

step S2: static analysis

S21, obtaining a maximum data path passing through the last-stage combined circuit unit through a static time sequence analysis tool, calculating circuit unit delay and interconnection line delay of the data path, and obtaining arrival time T of data transmitted to the (N + 1) th-stage trigger_i，arrive；

S22, calculating the arrival time T which must be met when the data is transmitted to the (N + 1) th trigger by using a static time sequence analysis tool according to the working frequency of the circuit_i，require；

Step S23, adding T_i，requireParameter minus T_i，arriveObtaining parameters, namely obtaining the time sequence allowance of the maximum data path;

s24, selecting filtering units with different filtering parameters for each data path according to the calculated time sequence residual value;

s3, inserting the selected filter unit into the output end of the last-stage combined circuit unit directly connected with the (N + 1) th-stage trigger;

s4, judging whether all the triggers are traversed or not, if so, turning to the step S5, otherwise, extracting the next last-stage combined circuit unit, and returning to the step S2;

and S5, completing physical placement and physical connection of the inserted filter units through an integrated circuit physical design tool, finally obtaining integrated circuit layout data after the inserted filter units, and completing the single-event transient resistance reinforcement of the integrated circuit.

The method is further explained by taking the method for realizing the single-event transient resistance reinforcement of the integrated circuit in the specific application embodiment as an example, and the detailed realization steps are as follows:

step 1) firstly, obtaining a combinational logic unit name U5 directly connected with an N +1 level trigger FF4 through an integrated circuit physical design tool, and obtaining a combinational logic unit name U6 directly connected with an N +1 level trigger FF 5;

step 2) there are four data paths through U5, FF1/U2/U5, FF2/U1/U2/U5, FF2/U1/U3/U5 and FF3/U3/U5, respectively. As seen from the number of cells, the number of cells on the second data path FF2/U1/U2/U5 and the third data path FF2/U1/U3/U5 is the largest, and the maximum delay data path through U5 is FF2/U1/U3/U5 because the delay of the XOR gate cell of U3 is larger than that of the XOR gate cell of U2.

For the sake of calculation, assuming that the cell delay of the flip-flop FF2 is 100 picoseconds, the cell delay of the U1 is 50 picoseconds, the cell delay of the U3 is 150 picoseconds, and the cell delay of the U5 is 100 picoseconds, the arrival time of data at the N +1 th stage flip-flop FF4 is the sum of the cell delays, i.e., 400 picoseconds. In the same way, the maximum delay data path through U6 is FF 3/U4/U6. Assuming that the cell delay of the flip-flop FF3 is 100 picoseconds, the cell delay of the U4 is 100 picoseconds, and the cell delay of the U6 is 100 picoseconds, the arrival time of data at the N +1 stage flip-flop FF5 is the sum of the cell delays, i.e., 300 picoseconds.

Step 3) assume that the operating frequency of the circuit of fig. 2 is 2GHz, i.e. one clock cycle is 500 picoseconds, while assuming that the setup times of the flip-flops FF4 and FF5 are both 50 picoseconds. Then the arrival time that must be satisfied by the data passing through the U5 and U6 cells is 450 picoseconds.

And 4) subtracting the time calculated in the two steps to obtain a time sequence margin of 50 picoseconds passing through the U5 unit, a time sequence margin of 100 picoseconds passing through the U6 unit, namely a filter unit with a filter parameter of 50 picoseconds matched with the output end of the U5 unit, and a filter unit with a filter parameter of 100 picoseconds matched with the output end of the U6 unit, so that a filter unit with a filter parameter of 50 picoseconds can be inserted into the output end of the U5 unit, and a filter unit with a filter parameter of 100 picoseconds is inserted into the output end of the U6 unit.

The above is only an idealized calculation method for more intuitively embodying the solution of the present invention, and in practical applications, a static timing analysis tool can be used to obtain the accurate data arrival time through the units U5 and U6, and the arrival time that the data must satisfy.

And 5) inserting the two filter units into the output end of the U5 and the output end of the U6 respectively through an integrated circuit physical design tool. The circuit diagram after the insertion is completed is shown in fig. 3. And then, the physical placement and physical connection of the insertion units are completed by adopting an integrated circuit physical design tool, and finally the reinforcement of the whole circuit against single-particle transient is completed.

The invention can selectively insert the filter unit in the physical design process of the large-scale integrated circuit by selecting the corresponding filter unit based on the time sequence allowance of the data path in the integrated circuit, thereby being suitable for the characteristic of less time sequence allowance of the large-scale integrated circuit and improving the single-particle transient resistance of the integrated circuit on the basis of keeping the working frequency of the integrated circuit unchanged.

The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.