阅读说明：本技术 混合自旋转移矩磁性随机存取存储器(h-stt-mram) (Hybrid spin transfer torque magnetic random access memory (H-STT-MRAM) ) 是由 霍素国 张瑞华 于 2020-09-25 设计创作，主要内容包括：本发明是一种由非磁夹层隔离的垂直磁向异性磁隧道结(pma-MTJ)和面内磁向异性磁隧道结(ima-MTJ)面对面堆叠组成的混合型自旋转移矩磁阻随机存取存储器(H-STT-MRAM)。其中在任一个MTJ磁自由层写入时,会受到来自另一个MTJ磁自由层通过非磁夹层施加的一个垂直于普通自旋转移矩(STT)的附加自旋转移矩(STT)来协助写入,以提高MTJ的写入性能。还提出了一种由Ru夹层隔开的两个磁自由层组成的合成反铁磁体自由层(SAF FL)结构来替代ima-MTJ中的磁自由层(FL),以改善其面内磁向异性自由层存储的稳定性,从而由进一步减小存储单元的尺寸来实现ima-MTJ和pma-MTJ面内尺寸匹配的高密度存储。还提出了高位H-STST-MRAM器件及其读、写方法和其组成的2D和3D阵列以实现超高面密度存储。(The invention is a hybrid spin transfer torque magnetoresistive random access memory (H-STT-MRAM) comprised of a face-to-face stack of perpendicular magnetic anisotropy magnetic tunnel junctions (pma-MTJs) and in-plane magnetic anisotropy magnetic tunnel junctions (ima-MTJs) separated by nonmagnetic interlayers. When any one MTJ magnetic free layer is written, the additional Spin Transfer Torque (STT) which is perpendicular to the common Spin Transfer Torque (STT) and applied by the other MTJ magnetic free layer through the nonmagnetic interlayer assists writing so as to improve the writing performance of the MTJ. A synthetic antiferromagnet free layer (SAF FL) structure composed of two magnetic free layers separated by a Ru interlayer is also proposed to replace the magnetic Free Layer (FL) in the ima-MTJ to improve the stability of its in-plane magnetic anisotropy free layer storage, thereby achieving high density storage of matching in-plane dimensions of the ima-MTJ and pma-MTJ by further reducing the size of the storage cell. High bit H-STST-MRAM devices and methods of reading and writing the same and 2D and 3D arrays formed therefrom are also presented to achieve ultra high areal density storage.)

1. A hybrid spin-torque transfer magnetic random access memory (H-STT-MRAM) device, comprising:

a face-to-face stack of a perpendicular magnetic anisotropy tunnel junction (pma-MTJ) stack and an in-plane magnetic anisotropy tunnel junction (ima-MTJ) stack separated by a nonmagnetic spacer disposed between two free layers of the two MTJs, and

wherein the MTJ comprises the following separated by an MgO tunnel barrier interlayer:

a magnetic Reference Layer (RL) whose magnetization is fixed in one direction; and

a magnetic Free Layer (FL) whose magnetization can be rotated to be parallel or anti-parallel to the RL fixed magnetization.

2. The H-MRAM device of claim 1, wherein the device comprises:

a bottom pma-MTJ stack with its FL and RL disposed directly above and below its MgO tunneling barrier, respectively; and an overlying top ima-MTJ stack with its FL and RL disposed directly below and above its MgO tunneling barrier, respectively;

a nonmagnetic spacer layer disposed between the two FLs in the bottom pma-MTJ stack and the top ima-MTJ stack.

3. The H-STT-MRAM device of claim 1, wherein the apparatus further comprises

A bottom ima-MTJ stack with its FL and RL disposed directly above and below its MgO tunnel barrier;

a top pma-MTJ stack with FL and RL disposed directly below and above their MgO tunnel barriers;

a nonmagnetic spacer layer disposed between the two FLs in the bottom ima-MTJ stack and the top pma-MTJ stack.

4. The H-STT-MRAM device of claim 1, wherein the nonmagnetic spacer layer between the FL of the MTJ-MTJ stack and the FL of the PMA-MTJ stack comprises a tunneling barrier TMR layer of MgO or AlOx, a Cu interlayer in GMR, or a barrier layer of Ta, Au, W, V, Mo, Ru, Cr or Nb to intercept exchange coupling between the two FLs and can also facilitate polarized electron spin transport.

5. The H-STT-MRAM device of claim 1, wherein RL in the pma-MTJ can be one of three cases:

a permanent Perpendicular Magnetic Anisotropy (PMA) magnetic layer comprising a HCP (002) Co alloy, an L10 alloy, such as FePd, FePt or CoPt, or a multilayer of CO2/PD9 or CO2/PT 9;

a Synthetic Antiferromagnet (SAF) stack of two perpendicular magnetic anisotropy layers separated by a Ru interlayer;

a SAF stack is vertically pinned by an Antiferromagnetic (AFM) layer.

6. The H-STT-MRAM device of claim 1, wherein the RL in the ima-MTJ is a SAF stack of AFM pinned in an in-plane direction consisting of two in-plane magnetically anisotropic layers separated by a Ru interlayer.

7. The H-STT-MRAM device of claim 1, wherein the FL in the ima-MTJ can also be an SAF FL structure comprising two magnetic free layers separated by a Ru layer to improve the free layer stability and facilitate memory miniaturization-can break the limit of 60nm memory cell size in an ima-MTJ of a single layer FL and potentially be used to fabricate sub-10 nanometer memory.

8. The H-STT-MRAM device of claim 7, wherein the ima-MTJ with a SAF free layer structure can also be used to fabricate an in-plane STT-MRAM device to break the limit of 60nm memory cell size in an in-plane STT-MRAM of a single layer F and further reduce the memory cell size to sub-10 nm for high areal density storage.

9. The H-STT-MRAM device of claim 1, and wherein the two magnetic layers in the FL and perpendicular SAF structures in the pma-MTJ, in-plane SAF RL and SAF free layer structures are CoFe, CoFeB and CoFe alloy magnetic materials.

10. The H-STT-MRAM device of claim 1, wherein the AFM in-plane pinned layer in the ima-MTJ and the AFM perpendicular pinned layer in the pma-MTJ are two different AFM materials, including IrMn, NiMn, FeMn, PtMn, or IrMn/FeMn multilayers, in order to have different anneal block temperatures.

11. The H-STT-MRAM device of claim 1, wherein the FL in the pma-MTJ can further be a multilayer structure with high Tunneling Magnetoresistance (TMR) effect formed alternately of CoFeB and nonmagnetic layers (e.g., Ta, Au, W, V, Mo, Ru, Cr, or Nb).

12. The H-STT-MRAM device of claim 10, further comprising a sequence of two anneals as described above on the two different block temperatures AFM in the ima-MTJ stack and the pma-MTJ stack to ensure that the results of a first AFM anneal can also be maintained in a second anneal:

firstly, performing high annealing block temperature AFM annealing in a high-temperature furnace, and raising the temperature to be just higher than the block temperature with the high block temperature AFM under a corresponding high magnetic field to induce the MTJ lamination which is fixed by the high block temperature AFM and has corresponding magnetic anisotropy;

then, a relatively low anneal block temperature AFM high temperature furnace anneal is performed to raise the temperature to just above the block temperature with the low anneal block temperature AFM under a correspondingly high magnetic field to induce the MTJ stack with the corresponding magnetic anisotropy pinned by the high anneal block temperature AFM.

13. The H-STT-MRAM device of claim 12, two different temperature anneals in the AFM pinned MTJ stack are also applicable to the ima-PMJ with AFM pinning and pma-MTJ with perpendicular magnetic anisotropy Permanent Magnet (PM) for RL, where PM comprises multiple layers such as hcp (002) Co alloy, L10 alloy (e.g. FePd, FePt or CoPt), or Co2/PD9 or Co2/PT9 or (and) perpendicular magnetic anisotropy FL that requires high temperature annealing.

14. The H-STT-MRAM device of claim 13, wherein the first high temperature furnace anneal further comprises high perpendicular magnetic fields for PM RL and FL in pma-MTJ and magnetic film deposition at high temperature, then ima-MTJ with low anneal block temperature AFM in high temperature furnace only needed for high in-plane magnetic field is low temperature annealed.

15. The H-STT-MRAM device of claim 1, further comprising a transistor, all of the MTJ stacks being placed above or below the transistor.

16. The H-STT-MRAM device of claim 1, wherein the memory cell shape comprises a cylinder, an elliptical cylinder, a square cylinder, a rectangular cylinder.

Two-step write method in H-STT-MRAM device obtained in two opposite-face MTJ after removing saturation current and current pulse write (R)_ima ^max，R_pma ^min) And (R)_ima ^min，R_pma ^max) In addition to the two resistance states, two maximum resistance states (R) may be obtained which are required for 2-bit storage_ima ^max，R_pma ^max) And two lowest resistance states (R)_ima ^min，R_pma ^min) Wherein the two-step writing step comprises:

firstly, increasing current and current pulse to make two MTJs to be written in saturation;

then an opposing current and current pulse are applied with relatively small amplitudes that are large enough to invert the magnetization of the FL in a soft (relatively easy to write) MTJ and small enough to invert the FL of the magnetization disk of the FL in a hard (relatively hard to write) MTJ.

18. The H-STT-MRAM device of claim 1, further comprising a 4-bit H-STT-MRAM device:

a first 2-bit H-STT-MRAM stack;

a second 2-bit H-STT-MRAM stack having a face-to-face reverse stacking order of the PMA-MTJ stack and the IMAP-MTJ stack is disposed over the first 2-bit H-STT-MRAM described above such that the top SAF RL of the first 2-bit H-STT-MRAM and the bottom SAF RL of the second 2-bit H-STT-MRAM share an AFM pinning layer;

side contact electrodes maximally covering two adjacent reference layers to be shared when written and read by two 2-bit H-STT-MRAM stacks, respectively.

19. The H-STT-MRAM device of claim 18, wherein the n 4-bit H-STT-MRAM devices are stackable to form a 4 n-bit H-STT-MRAM device and n-1 side contacts thereof, wherein a maximum coverage of each side contact is two adjacent reference layer stacks of its two adjacent 4-bit H-STT-MRAM stacks for a total number of 4 n-bit H-STT-MRAM side contacts to use in their writing and reading.

20. The H-STT-MRAM device of claim 19, further comprising a (4n-2) bit H-STT-MRAM device stacked by removing one 2-bit H-STT-MRAM device from the 4 n-bit H-STT-MRAM device of claim 19.

21. The high bit H-STT-MRAM device of claim 19, and wherein each side contact may be replaced by an additional conductive layer between two adjacent 2-bit H-STT-MRAM device stacks, and the stacking of 2-bit H-STT-MRAM devices may be in any regular order, as the two adjacent 2-bit H-STT-MRAM do not share one AFM layer.

22. A method of reading each MTJ resistance state in a 4 n-bit H-STT-MRAM device sharing one transistor, comprising:

sensing a first resistance of R1 in a first 2-bit H-STT-MRAM stack, including passing a current through the transistor and the first side contact to sense resistance states of its two MTJs, R¹＝(R¹ _ima+R¹ _pma)；

Sensing the resistance of two 2-bit H-STT-MRAM devices by passing a current through the transistor and the second side contact, equal to R¹+R²(ii) a Wherein R is²Is the resistance of the second 2-bit H-STT-MRAM, which can be determined by subtracting the known R¹To obtain: r²＝(R¹+R²)-R¹＝（R² _ima+R² _pma)；

Sensing a total resistance of current through said transistor and said 2k side contact asIts 2k th H-STT-MRAM resistance is equal toTaking out the data obtained from reading through the transistors to (2k-1) side contactsThen obtaining

Obtaining transistor and top electrode resistance states for reading out total resistance of 4 n-bit H-STT-MRAM deviceThe resistance of the 2n bit H-STT-MRAM is equal to that of theTaking out the known result from reading through the transistors to (2n-1) side contactsThen obtainingThereby obtaining a 4n bit stored resistance state { (R)¹ _ima+R¹ _pma)(R² _ima+R² _pma)……(R^k _ima+R^k _pma)……(R²ⁿ _ima+R²ⁿ _pma)}。

23. The high bit H-STT-MRAM device of claim 19, further comprising a 2-dimensional (2D) array of the high bit H-STT-MRAM devices, wherein adjacent high bit H-STT-MRAM devices are insulated from each other with their side contacts connectable to the planar upper side contact shared read and write circuitry.

24. The high bit H-STT-MRAM device of claim 19, further comprising a 2D array of 2 bit H-STT-MRAM devices or a stack of 2D arrays of high bit H-STT-MRAM devices to form a 3-dimensional (3D) array for increased storage capacity.

25. The H-STT-MRAM device of claim 1, wherein the SAF FL structure in each ima-MTJ stack having a SAF FL structure is further usable to store about two (or three) more magnetoresistive states. In addition to storing at 180 and 0 relative to the RL magnetization direction, the FL magnetization of the SAF FL structure can be written and stored at 45, 90, 135 relative to the RL magnetization direction to obtain a magnetization other than R_ima ^maxAnd R_ima ^minR of exo-corresponding_ima ^π/4、(R_ima ^±π/2) And R_ima ^3π/4Additional resistance state of (1). This may make their constituent H-STT-MRAM and in-plane STT-MRAM devices into 3-bit (or 3.32192809-bit) memory devices and 2-bit (or 2.32192809-bit) memory devices, respectively, to further increase the in-plane storage density.

Technical Field

The present invention relates to the field of information memory technology, and more particularly to high bit spin transfer torque magnetoresistive random access memory cells and magnetic memories.

Background

With the advent of high performance computing and mobile devices, a large amount of information is generated and needs to be stored, which has been satisfied by gradually shrinking the size of the storage units in memory, and has driven the rapid growth of storage and memory technology. Although conventional semiconductor memories utilizing electron charge properties have been well utilized and developed, but have approached their limits, the Giant Magnetoresistance (GMR) effect discovered in 1998 has broken the nobel prize of physics in 2004, opened up a new field of electron spinology, and led to the application and development of a range of electron spin techniques. New technologies for spintronic transfer torque memory that employ and manipulate the spin properties of electrons have been intensively studied in the last decade.

Dynamic Random Access Memory (DRAM) using electronic charge capacity has approached its limit in maintaining significant growth to meet the demand for data storage. As DRAM cell sizes shrink, charge leakage can cause power consumption and other problems. Compared with the electronic charge based DRAM, the Magnetic Random Access Memory (MRAM) based on electron spin is a non-volatile memory, has the advantages of low power consumption, and the like, and is considered to be a good candidate for replacing the semiconductor charge based memory technology. Two types of MRAM have been developed and are based on magnetic field written MRAM and Spin Transfer Torque (STT) written MRAM (STT-MRAM). Compared to magnetic field driven MRAM, STT-MRAM has found its place in the profitable market products due to its small power consumption, process simplification and cell miniaturization.

A typical STT-MRAM device is basically a Magnetic Tunnel Junction (MTJ) stack that includes two magnetic layers sandwiched by a magnesium oxide (MgO) barrier layer, one of which is referred to as the Reference Layer (RL), whose magnetization is fixed in one direction; and the other, called the Free Layer (FL), whose magnetization can be rotated to be parallel or anti-parallel to the RL magnetization, is achieved by operating the spin-transfer torque by: writing and storing of information is accomplished by passing current through the MgO barrier layer from RL to FL of the MTJ or from FL to RL of the MTJ, respectively. The information stored in the FL layer can be read out based on a Tunneling Magnetoresistance (TMR) effect after passing a current through the MTJ stack, obtaining a maximum resistance or a minimum resistance when the FL magnetization is stored anti-parallel or parallel to the RL magnetization, respectively.

There are two types of STT-MRAM devices: in-plane STT-MRAM, where the magnetization in both FL and RL is along the plane of their magnetic films; and perpendicular STT-MRAM, where the magnetization in the FL and RL is perpendicular to the plane of their magnetic films. Like any memory, STT-MRAM devices need to have three functions, write, store, and read. In STT-MRAM, spin transfer torque is used to write bits in the Free Layer (FL), the bits stored in the free layer need to be stored for long periods of time, such as 10 years; the TMR effect (similar to that in TMR readers) is then used to read out the bit stored in the free layer after passing a current through the device. The FL in STT-MRAM devices differs from the FL in TMR readers in that the FL in STT-MRAM is more or less similar to magnetic recording media with strong magnetic anisotropy in magnetic hard disk storage to preserve its stored information for long periods of time. Therefore, the magnetic anisotropy of the FL in STT-MRAM devices must have balanced properties, requiring a magnetic anisotropy that is not too strong in order to be written into a bit with spin transfer torque, and yet not too weak in order to be able to sustain storage for the written bit length time. To date, the best FL magnetic material is still a cobalt iron (CoFe) alloy because of its good spintronic effect required in spin-torque transfer torque writing and TMR reading. CoFe alloy is a typical soft ferromagnetic material, and the challenge of it as a memory cell is instability of bit storage and limits memory miniaturization, because large memory cells are more stable and have fewer boundary effects in-plane STT-MRAM, which is a typical problem. The perpendicular STT-MRAM device of the invention has strong perpendicular anisotropy to solve the stability problem of the in-plane STT-MRAM memory. It was found that a CoFe alloy perpendicular magnetic anisotropy film is also the best spintronic material, and that a CoFe alloy film less than 1.5nm would have a much stronger perpendicular magnetic anisotropy than its in-plane magnetic anisotropy in films thicker than 1.5 nm. This can solve the FL bit memory stability problem and also allows further miniaturization of the memory cell to increase the in-plane memory density. However, the strong magnetic anisotropy of the FL in the vertical STT-MRAM memory described above would require a large STT to write the bit information in the FL cell. Perpendicular STT-MRAM devices having magnetic anisotropy with a slightly tilted perpendicular direction have been proposed to reduce their requirements for writing STT. Perpendicular STT-MRAM fabrication processes and controls are much more complex than in-plane STT-MRAM, and its FL memory is only capable of storing two pieces of information, a "0" and a "1". Recently, a polarized magnetic layer with in-plane magnetic anisotropy can generate an additional spin transfer torque perpendicular to the normal STT on the FL of a perpendicular STT-MRAM by providing a nonmagnetic spacing between the polarized magnetic layer and the MTJ free layer to improve free layer write performance.

In general, the electron spin-based STST-MRAM is an information 1-bit memory capable of storing only two of "0" and "1", which is a disadvantage compared to the semiconductor charge-based DRAM high-bit memory. Proposed perpendicular STT-MRAM of multiple free layers achieves high bit storage by gradually writing each individual FL starting from the free layer adjacent to the MgO barrier. However, this process is very difficult to control and prone to errors. High bit STT-MRAM devices formed using stacks based on different magnetic properties of multiple perpendicular MTJ cells of one semiconductor transistor are also proposed. A memory composed of MTJs of different sizes will affect the optimization of the MTJs and limit the miniaturization of its memory cells in addition to the complexity of the fabrication process. This simple stack of perpendicular MTJs does share one transistor, provided that the transistor can provide the premise of delivering sufficient write current and not breaking down the transistor barrier, but the structure still fails to exploit possible additional spin-transfer torque from its neighboring MTJ stack.

The dual STT-MRAM (D-STT-MRAM) device has been proposed to include a top MJT and a bottom MTJ, and the two MTJs share a single FL. In one configuration where the two RLs in the two MTJs have reversed fixed magnetizations, the FL will have two identical sign spin-transfer torques from the bottom RL and the top RL while writing to enhance writing, however, the total resistance in reading will always be the sum of the maximum and minimum resistances in the two MTJs. Therefore, even though its two MTJs have different resistances, D-STST-MRAM is only a 1-bit memory at best, but this still does not solve the problem of two MTJ TMR cancellation at read. If a D-STST-MRAM is designed with the same fixed magnetization in both RLs, both MTJs can obtain the maximum or minimum resistance state at the same time when they are read, but when they are written, the two opposing spin-transfer torques from the RL for the bottom MTJ and the RL for the top MTJ will act on the FL at the same time, reducing the writing function. Therefore, D-STT-MRAM devices have little practical value.

The novel hybrid spin transfer torque magnetoresistive random access memory (H-STT-MRAM) device proposed by the present invention solves the above-mentioned problems of STT-MRAM to a great extent.

Disclosure of Invention

The present disclosure is a hybrid spin-transfer torque magnetoresistive random access memory (H-STT-MRAM) device, comprising: a face-to-face stack of perpendicular magnetic anisotropy MTJ (pma-MTJ) and in-plane magnetic anisotropy MTJ (ima-MTJ) separated by a nonmagnetic spacer layer, the nonmagnetic spacer being disposed between two MTJs FL, either of which FL writes, the other FL will write-assisted by the nonmagnetic spacer layer simultaneously applying an additional spin transfer torque perpendicular to the normal STT on the FL being written. The proposed H-SST-MRAM can implement 2-bit storage by using the proposed two-step writing method, in which after the saturation writing of the first step is completed, FL magnetization of a soft MTJ in the H-STT-MRAM is inverted a second time using a reverse current and a current pulse having a small amplitude to increase storage capacity.

In one embodiment, an H-STT-MRAM device includes: bottom pma-MTJ, with RL and FL directly above and below the MgO barrier, respectively; and a top ima-MTJ above it with RL and FL directly below and above the MgO barrier; the bottom pma-MTJ stack and the top ima-MTJ stack are separated by a nonmagnetic spacer, the nonmagnetic spacer layer being disposed directly above the FL of the bottom pma-MTJ and directly below the FL of the top ima-MTJ.

In another embodiment, an H-STT-MRAM device includes a bottom ima-MTJ and a top pma-MTJ separated by a nonmagnetic spacer layer.

In another embodiment, a Synthetic Antiferromagnet (SAF) FL structure including two magnetic Free Layers (FLs) separated by a Ru interlayer is used in place of a single FL in the ima-MTJ stack in both embodiments described above to improve stability of the in-plane magnetic anisotropy free layer to reduce memory cell size and increase areal storage density.

In another embodiment, the free layer in the pma-MTJ stack is multiple perpendicular magnetic anisotropy magnetic films separated by nonmagnetic layers to improve the pma-MTJ TMR effect.

The reference RL in the ima-MTJ stack of all of the above H-STT-MRAM embodiments proposed is an in-plane magnetically anisotropic SAF structure fixed by AFM, which includes two in-plane magnetically anisotropic layers separated by a Ru layer. The reference layer in the pma-MTJ stack may be a permanent magnet with strong perpendicular magnetic anisotropy; or a plurality of perpendicular magnetic films separated by nonmagnetic layers; or a perpendicular magnetic anisotropy SAF structure fixed by AFM, comprising two perpendicular magnetic anisotropy magnetic films separated by a Ru layer.

A two-step write method is also claimed to achieve 2-bit storage in the proposed H-STT-MRAM. After normal writing using current and current pulses to saturate the two MTJs of the H-STT-MRAM device in either direction through the stack, the two MTJs will always be in the maximum resistance state and minimum resistance state, respectively, to get the two bits of (01) and (10), where "0" and "1" mean the minimum resistance and maximum resistance, respectively, of the MTJ. The second step of the write method is to use an inversion current and current pulse with small amplitude just large enough to invert the magnetization in the free layer of the soft (relatively easy to write) MTJ stack after completing the saturation write on the two MTJ stacks in order to obtain (00) bits for the two minimum resistance states and (11) bits for the two maximum resistance states. Thus, 2-bit storage of (01), (10), (00), and (11) can be obtained in the proposed H-MRAM device. High bit H-STST-MRAM devices such as 4 bits, 6 bits, 1 byte and 4n bits have also been proposed to further increase areal storage density. And arranging the 2D array and the 3D array of high bit H-STT-MRAM devices for future high performance computing, mobile devices, and information storage.

High bit storage can also be achieved in the proposed ima-MTJ stack with the SAF FL by controlling the STT to rotate the SAF FL magnetization to store along 45, 135, and + -90 with respect to the fixed magnetization direction in the RL to obtain the divisionNormal maximum resistance R_ima ^πMinimum resistance R of state sum_ima ⁰R out of state_ima ^π/4State (FL magnetization to resistance at 45 ° along the fixed magnetization direction in the RL), R_ima ^3π/4State (FL magnetization to resistance at 135 ° along the fixed magnetization direction in the RL), R_ima ^±π/2The state (FL magnetization to resistance along ± 90 ° with respect to the fixed magnetization direction in the RL) in order to further increase the storage capacity. The ima-MTJ with SAF FL can also break the size limit of about 60nm in a single FL ima-MTJ and can be reduced below 10nm to further increase the area storage density in-plane STT-MRAM devices as well as H-STT-MRAM devices.

Drawings

FIGS. 1(a) and 1(b) are schematic diagrams of a cross-sectional view and a top view, respectively, of a first embodiment of an H-STT-MRAM, taken from the middle of the cell and perpendicular to the device substrate surface.

FIG. 2 is a schematic diagram of a cross-sectional view of a second embodiment of an H-STST-MRAM device having transistors, word lines, source lines, and bit lines, where the cross-section is taken from the middle of the cell and perpendicular to the device substrate surface.

FIGS. 3(a) and 3(b) are schematic diagrams of cross-sectional views of a third embodiment of in-plane STT-MRAM and H-STST-MRAM devices having a SAF FL structure, respectively, with the cross-section taken from the middle of the cell and perpendicular to the device substrate surface.

FIG. 4 is a schematic diagram of a cross-sectional view of a fourth embodiment of an H-STST-MRAM device, where the cross-section is taken from the middle of the cell and perpendicular to the device substrate surface.

FIGS. 5(a) -5(d) show schematic diagrams of cross-sectional views of a third embodiment of a 2-bit H-STT-MRAM device using a cross-sectional diagram for (R) respectively, assuming that the ima-MTJ stack is relatively easy to write compared to the pma-MTJ stack_pma ^min+R_ima ^max) Resistance state of (R)_pma ^max+R_ima ^min) Resistance state of (R)_pma ^min+R_ima ^min) Resistance state ofAnd (R)_pma ^max+R_ima ^max) The resistance state of (2) represents a two-step writing method.

FIGS. 6(a) -6(d) show schematic diagrams of cross-sectional views of a third embodiment of a 2-bit H-STT-MRAM device using respective pairs of (R) for (R-STT-MRAM) devices, assuming that the pma-MTJ stack is relatively easy to write compared to the ima-MTJ stack, where the cross-section is taken perpendicular to the device substrate_pma ^min+R_ima ^max) Resistance state of (R)_pma ^max+R_ima ^min) Resistance state of (R)_pma ^max+R_ima ^max) Resistance state of (R) and_pma ^min+R_ima ^min) The resistance state of (2) represents a two-step writing method.

FIGS. 7(a) -7(c) show schematic diagrams of cross-sectional views of a 4-bit H-STT-MRAM device, a 6-bit H-STT-MRAM device, and a 1-bit H-STT-MRAM device, respectively, where the cross-sections are taken perpendicular to the device substrate.

Detailed Description

Before describing the details of an embodiment of an H-STT-MRAM device, although STT-MRAM is in mass production, a manufacturing stage to replace DRAM in computers and mobile devices, problems in current STT-MRAM devices are summarized.

The main problem with in-plane magnetic anisotropy STT-MRAM devices is the memory cell miniaturization limitation, as cell sizes smaller than 60nm will suffer from instability and uniformity of stored FL magnetization, which will limit the storage area density increase and keep it from windmilling in competition with semiconductor DRAM devices.

Perpendicular magnetic anisotropy STT-MRAM devices can overcome the memory size miniaturization problem in-plane magnetic anisotropy STT-MRAM devices, but still have two drawbacks compared to semiconductor DRAMs. The first is a single bit storage with only two resistance states of "0" and "1" per vertical STT-MRAM memory cell, while semiconductor DRAMs can store more bits. The second problem is that if the FL has a strong perpendicular magnetic anisotropy needed for the FL magnetization to be stored for a long time, the electron spin transfer torque may not be sufficient to reverse the FL magnetization for writing.

To solve the first problem, perpendicular STT-MRAM is proposed with a simple stack of MTJs with different magnetic properties including different TMR and even different memory cell sizes, which will affect the MTJ optimization and greatly increase the complexity of the fabrication process.

To solve the second problem, a write line can be added to generate an additional magnetic field to assist STT writing after being powered on, but the method will increase power consumption, generate additional heat and have the disadvantages of process complexity and the like. If a non-magnetic layer is placed between the perpendicular magnetic anisotropy FL of the pma-MTJ and the in-plane magnetic anisotropy polarizing layer, the polarized magnetic layer with in-plane magnetic anisotropy will produce an additional STT perpendicular to the normal STT on the FL in the pma-MTJ to assist in writing. However, it has not fully used a polarized magnetic layer, and still has the first problem of obtaining only 1-bit storage.

The present invention proposes several embodiments of H-STT-MRAM devices to solve the above-mentioned problems in current STT-MRAM devices, which are structures consisting of a face-to-face stack of pma-MTJ stacks and ima-MTJ stacks separated by a nonmagnetic separation between the two FLs of the two MTJs. And proposes to replace the single FL in ima-MTJs by a SAF free layer structure comprising two magnetic layers sandwiched by a Ru layer forming a strong antiferromagnetic coupling between the two magnetic layers, which is a very stable magnetic structure with near zero demagnetization effect and uniform magnetization distribution, even for small memory cells.

In the proposed H-STT-MRAM device, the in-plane magnetic anisotropy FL in the ima-MTJ stack and the perpendicular magnetic anisotropy FL in the pma-MTJ stack are separated by a nonmagnetic layer, either FL being automatically the other FL written polarized magnetic layer: writing is assisted by supplying an additional spin transfer torque through the nonmagnetic spacer layer that is perpendicular to the normal spin transfer torque from the RL. In addition, the optimized ima-MTJ and the optimized pma-MTJ have different magnetic properties and TMR, which makes the H-STT-MRAM device as excellent 2-bit memory device. A high bit H-STT-MRAM device based on a 2 bit H-STT-MRAM composition is also presented. Thus, the proposed prior art H-STT-MRAM device can solve the problems in current STT-MRAM devices and has superior properties of STT-MRAM, such as non-volatility, less power consumption, fast read and write, as well as the advantages of better write performance, high bit, high in-plane storage density, etc., of additional STT compared to semiconductor charge based DRAM devices.

FIGS. 1(a) and 1(b) illustrate a cross-sectional view and a top view, respectively, of a first embodiment 100 of an H-STT-MRAM device. The embodiment of 100 includes a bottom perpendicular magnetic anisotropy magnetic tunneling junction (pma-MTJ)120, and a top in-plane magnetic anisotropy magnetic tunneling junction (ima-MTJ)110 above it, and a non-magnetic spacer layer 130 sandwiched between 110 and 120.

The bottom pma-MTJ 120 includes: a reference layer stack comprising a bottom Antiferromagnet (AFM)126 pinned perpendicular magnetic anisotropy SAF structure 140, a Pinned Layer (PL)125 and a Reference Layer (RL)123 separated by a Ru layer 124 to form a strong antiferromagnetic coupling between the PL 125 and RL 123; a perpendicular magnetic anisotropy Free Layer (FL)121 over the RL 123; and MgO tunnel barrier layer 122 between FL 121 and RL 123. AFM 126 serves to fix the magnetization of PL 125 and may further enhance the magnetic field against reversing the magnetization of PL 125.

The top ima-MTJ 110 includes: a reference layer stack comprising a top AFM 111 disposed over the in-plane magnetically-anisotropic SAF structure 150 and serving to fix its PL 112 in-plane magnetically-anisotropy, the SAF 150 comprising an in-plane magnetically-anisotropic PL 112 and an in-plane magnetically-anisotropic RL 114 separated by a Ru layer 113 to form a strong antiferromagnetic coupling between the PL 112 and RL 114; in-plane magnetic anisotropy FL116 below SAF 150; and MgO tunnel barrier layer 115 between FL116 and RL 114. The in-plane magnetically anisotropic SAF structure 150 fixed by AFM 111 is used as a RL, and in addition to having a similar function as the perpendicular magnetically anisotropic SAF structure 140 fixed by AFM 126, the in-plane magnetically anisotropic SAF structure 150 composed of magnetically matched PL 112 and RL 113 is a perfect zero demagnetization structure.

The nonmagnetic spacer layer 130 is between the top ima-MTJ 110 and the bottom pma-MTJ 120 and more specifically between the FL116 of the ima-MTJ 110 and the FL 121 of the pma-MTJ 110. The nonmagnetic spacer layer 130 may be a TMR tunneling barrier layer of MgO or AlO, or a Cu interlayer between RL and FL in GMR, or a barrier material of Ta, Au, W, V, Mo, Ru, Cr, or Nb to cut off the exchange coupling of the two free layers in the bottom Pma-MTJ 120 and the top Ima-MTJ 110, and the magnetically polarized layer that automatically becomes the other one facilitates writing by polarized electron spin transport between its two adjacent free layers.

100, the FL116 in the top ima-MTJ 110 and the FL 121 in the bottom pma-MTJ 120 strength are shown as double arrows to indicate that the magnetization in the FL can be reversed or rotated by a magnetic field or spin transfer torque.

The proposed H-STT-MRAM 100 can illustrate the Spin Transfer Torque (STT) writing in either MTJ FL by passing the other MTJ free layer through the nonmagnetic spacer 130 while applying an additional spin transfer torque on the write free layer that is perpendicular to the normal spin transfer torque. In the embodiment of 100 with a top-down write current and current pulse to rotate the magnetization in FL 121 to the direction of the magnetization in RL 123 written by the bottom pma-MTJ, as in the case of normal STT-MRAM, this operation is subject to an additional spin transfer torque of FL116 with in-plane magnetization from the top ima-MTJ 110 through the nonmagnetic gap 130 to assist its writing in addition to the spin transfer torque from RL 123 through the MgO tunnel barrier 122. This additional spin transfer torque from FL116 is perpendicular to the normal spin transfer torque from RL 123 throughout, although the magnitude of this additional spin transfer torque will vary with magnetization, similar to the variation in the magnitude of the normal spin transfer torque from RL 123. This additional spin transfer torque has been discussed in the background section above, our innovation is that this FL116 serves not only as a source of additional spin transfer torque, but also as a storage unit in the ima-MTJ 110 stack, and it will also benefit from the additional spin transfer torque from the pma-MTJ FL 121 to assist in its writing. At the time of ima-MTJ 110 writing, as in the case of normal STT-MRAM, the write current and current pulse from top to bottom through 100 will generate a normal spin transfer torque from RL 114 acting on FL116 through MgO tunnel barrier 115 to rotate its magnetization to an anti-parallel direction to the magnetization in RL 114; at the same time, FL116 is also subjected to an additional spin transfer torque generated from FL 121 across nonmagnetic spacer 130, perpendicular to the normal spin transfer torque, to assist in the rotation of its magnetization.

FIG. 1b shows a top view 111 of the H-STT-MRAM device 100 and has a disk shape, with the H-STT-MRAM device memory cell being cylindrical in shape, but including other shapes as well, such as an elliptical cylinder, a square cylinder, or a rectangular cylinder.

The RL stack in the pma-MTJ 120 can also be a perpendicular magnetic anisotropy permanent magnetic film, such as an hcp (002) Co alloy, an L10 alloy (such as FePd, FePt, or CoPt), or a Co2/Pd9 or Co2/Pt9 or a perpendicular anisotropy SAF formed from two perpendicular magnetic anisotropy permanent magnetic films separated by a Ru layer.

The free layer in both the pma-MTJ stack and the ima-MTJ stack is CoFe, CoFeB or other CoFe alloy, but the FL in the pma-MTJ can be a multilayer film of CoFeB/Ta or CoFe alloy layers separated by nonmagnetic layers comprising Au, W, V, Mo, Ru, Cr, or Nb to maximize the use of surface perpendicular magnetic anisotropy in the CoFeB layer to increase TMR effect.

The AFM 111 in the ima-MTJ 110 and the AFM 126 in the pma-MTJ 120 are preferably different AFM materials with different anneal block temperatures, which can be IrMn, NiMn, FeMn, PtMn, or IrMn/FeMn multilayers. The high and low anneal block temperature AFMs are referred to as the first AFM and the second AFM, respectively. In two high temperature furnace anneals, strong horizontal and vertical magnetic fields need to be applied to the ima-MTJ 110 and pma-MTJ 120 anneals, respectively. The two annealing processes are high temperature annealing, the temperature is raised to be higher than the high block temperature of the first AFM, and simultaneously, a high magnetic field in the corresponding direction is applied to induce the magnetic anisotropy required by the first AFM fixed field and the MTJ fixed by the AFM; then a relatively low temperature anneal is performed, just above the low bulk temperature of the second AFM, while simultaneously applying a high magnetic field in its corresponding direction to induce the magnetic anisotropy of its second AFM pinning field and the AFM pinned MTJ. In this sequence, since the second anneal temperature is lower than the high bulk temperature of the first AFM, the second anneal will not destroy the effect of the first AFM at the first anneal. We exemplify in the following cases where AFM 111 of the ima-MTJ is the second AFM with a low bulk temperature of IrMn of about 300℃, and AFM 126 of the pma-MTJ is the first AFM with a high bulk temperature NiMn of about 400℃. Based on the proposed annealing sequence, the H-STT-MRAM is first subjected to a high temperature anneal in a high temperature furnace above 400 ℃ under a strong perpendicular magnetic field to induce NiMn AFM to vertically fix PL 125 and also to induce a better perpendicular magnetic anisotropy in FL 121 of pma-MTJ 120. Then, a low temperature anneal is performed in a strong horizontal magnetic field at a temperature just above 300 ℃ of the IrMn AFM bulk temperature, but below 400 ℃ of the NiMn AFM bulk temperature, to fix PL 112 of ima-MTJ in the IrMn AFM sensing plane, but not to destroy the effect of the NiMn AFM to fix PL 125 vertically, since the temperature of the low temperature anneal is below the NiMn AFM bulk temperature of 400 ℃.

In the case of the permanent magnet RL stack in the pma-MTJ stack, especially the hcp (002) Co alloy, the permanent magnet RL of an L10 alloy (such as FePd, FePt or CoPt), or the perpendicular anisotropy SAF of multiple layers of Co2/Pd9 or Co2/Pt9 or formed of only two perpendicular magnetic anisotropy permanent magnet films with Ru as interlayer. The perpendicular magnetic anisotropy RL and FL would need to be deposited at high temperature and perpendicular magnetic field, or annealed in a high temperature furnace under strong perpendicular magnetic field after normal temperature deposition. The perpendicular magnetic anisotropy FL and RL in the pma-MTJ can also be a multilayer film of CoFeB separated by nonmagnetic spacers of Ta, Au, W, V, Mo, Ru, Cr, or Nb, and its magnetic properties can be further improved by high temperature furnace annealing under a perpendicular magnetic field after normal temperature deposition. In this case, it is desirable that the bulk temperature of the AFM in the ima-MTJ should be different from the annealing temperature required in the pma-MTJ stack with the permanent magnet RL, and that the annealing sequence of the two anneals be the same as proposed on the two AFMs with different bulk temperatures, or vice versa with a high temperature anneal first followed by a low temperature anneal.

FIG. 2 illustrates another embodiment 200 of an H-STT-MRAM device 200 having two MTJs that are reversed in stacking order compared to the embodiment of 100 in FIG. 1, but still maintaining a face-to-face stacking of ima-MTJ and pma-MTJ as proposed. An embodiment of 200 comprises: the bottom ima-MTJ 220 and the top pma-MTJ 210 above it, with the interlayer between the FL 216 of the top pma-MTJ 210 and the FL 221 of the bottom ima-MTJ stack 220, are also the nonmagnetic spacer layer 130. The top pma-MTJ 210 includes: a RL stack comprising a perpendicular magnetic anisotropy SAF 217, the perpendicular magnetic anisotropy SAF 217 comprising a PL 212 and a RL 214 separated by a Ru interlayer 213, the PL 212 vertically pinned by a top AFM 211; FL 216 below the RL stack; and a tunneling gap MgO 215 disposed between the FL 216 and the RL 214 of the SAF structure 217 that is vertically fixed by the top AFM 211. The bottom ima-MTJ stack 220 includes: a RL stack comprising an in-plane magnetically-anisotropic SAF stack 227, the in-plane magnetically-anisotropic SAF stack 227 comprising a PL 225 and a RL 223 separated by a Ru interlayer 224, the PL 225 in-plane pinned by a bottom AFM 226; FL 221 over the RL stack; and a tunneling barrier MgO 222 between FL 221 and RL 223.

The nonmagnetic barrier layer 130 is disposed between the FL 216 of the top pma-MTJ 210 and the FL 221 of the bottom ima-MTJ 220. As discussed in the first embodiment 100 of the H-STT-MRAM device, both FLs in 200, in addition to their memory function, also have an additional spin transfer torque across the nonmagnetic spacer 130 perpendicular to the normal spin transfer torque from the corresponding RL to assist in their writing.

The H-STT-MRAM device 200 also shows a complete stack including a bottom transistor 230 for the signal amplifier, a word line 240 on the emitter of the transistor, a source line 250 on the base of the transistor, and a bit line 260 on the top electrode of the stack.

The H-STT-MRAM embodiments presented in 100 and 200, each comprising an ima-MTJ with a single layer FL, will limit device cell miniaturization for high areal storage densities due to their weak in-plane magnetic anisotropy, edge effects, and demagnetization effects that can cause typical problems with in-plane STT-MRAM devices such as thermal instability and cell magnetization maldistribution uniformity. The present invention proposes to replace the FL in the ima-MTJ cell by an SAF FL structure. The SAF FL structure is a strongly antiferromagnetically coupled structure formed of two ferromagnetic layers separated by a Ru interlayer, which has a demagnetization field of almost zero if the two ferromagnetic films have matching magnetic properties and dimensions. This strong antiferromagnetically coupled SAF free layer structure can break through the miniaturization limit of a single FL size of about 60nm and can potentially be used for ultra-high areal density memories with memory cell sizes down to below 10 nm.

FIGS. 3(a) and (b) illustrate the use of a SAF free layer structure instead of FL in an ima-MTJ stack to break the 60nm size limit in a third embodiment 300 of an H-STT-MRAM device and an in-plane magnetic anisotropy STT-MRAM device, respectively, and for below 10nm memory to increase the area storage density.

FIG. 3(a) illustrates a third embodiment 300 of an H-STT-MRAM device comprised of a bottom pma-MTJ stack 120 separated by a nonmagnetic spacer 130 and a top ima-MTJ stack 310 with an SAL FL structure 320 thereabove. In contrast to embodiment 100 shown in FIG. 1a, embodiment 300 replaces FL116 in the top ima-MTJ 110 in 100 with an SAF FL structure 320, which SAF FL structure 320 includes a free layer 1(FL _1)321 and a free layer 2(FL _2)322 disposed directly below the MgO tunneling barrier 115, which forms a strong antiferromagnetic coupling at its antiferromagnetic peak thickness by the Ru layer 323 sandwiched between FL _ 1321 and FL _ 2322.

FIG. 3(b) shows an in-plane STT-MRAM device having a SAF FL structure, which is simply a cut through the top ima-MTJ 310 from the third embodiment 300 of the H _ STT-MRAM in FIG. 3(a) and replacing the nonmagnetic spacer layer 130 with a nonmagnetic capping layer 324. The memory cell in ima-STT-MRAM with SAF FL structure can also break the 60nm limit due to the strong AFM coupling of FL 1321 and FL 2322 through the spacer layer Ru 323 in the SAF FL structure 320, and can be scaled down below 10nm for high performance computing, high in-plane storage density storage in mobile devices and other memory devices. The in-plane STT-MRAM with SAF FL structure can be written to and maintained at more than two resistance states, maximum and minimum, because the FL magnetization can also be written to and stored at, for example, 45, 90, 135 relative to the RL fixed magnetization direction by controlling the spin transfer torque when current and current pulses are written to obtain other than R_ima ^maxAnd R_ima ^minOther than at R_ima ^π/4、(R_ima ^±π/2) And R_ima ^3π/4A read resistance in (1); and a stable SAF FL with zero demagnetizing field will maintain those resistance states for a long time to read them out using the TMR effect. This may make the in-plane STT-MRAM and H-STT-MRAM a 2-bit (or 2.32192809-bit) memory device and a 3-bit (or 3.32192809-bit) memory device, respectively) Memory devices to further increase areal storage density.

FIG. 4 illustrates a fourth embodiment 400 of an H-STT-MRAM device that includes a top pma-MTJ stack 210 separated by a nonmagnetic spacer layer 130 and a bottom ima-MTJ stack 410 with an SAL FL structure 320. In contrast to the embodiment 200 shown in FIG. 2, the embodiment of 400 simply replaces FL 221 in bottom ima-MTJ 220 in 200 by a SAF FL structure 320, which SAF FL structure 320 includes free layer 1(FL _1)321 and free layer 2(FL _2)322 disposed directly on MgO tunneling barrier 222, sandwiched between FL _ 1321 and FL _ 2322 by Ru layer 323, forming a strong antiferromagnetic coupling through Ru layer 323 at its antiferromagnetic peak thickness. Similarly, the memory size of the fourth embodiment 400 may also break a single FL in-plane MTJ size limit of about 60nm and may drop below 10nm for in-plane high density storage due to the stable SAL free layer structure in the ima-MTJ stack.

After discussing the burst size miniaturization constraints in the third and fourth embodiments of H-STT-MRAM, including the face-to-face stacking of the ima-MTJ stack and the pma-MTJ stack with the SAF FL structure separated by the nonmagnetic spacer layer, writing and reading of H-STT-MRAM is illustrated for embodiment 300 in FIG. 5, assuming that the ima-MTJ stack is relatively easy to write and a two-step writing method is proposed to obtain four resistance states for 2-bit storage to fully use the H-STT-MRAM device capacity for further increasing storage capacity.

After having the magnetizations of both free layers in the ima-MTJ stack and the pma-MTJ written saturated by the spin transfer torque, the ima-MTJ stack and the pma-MTJ stack of the proposed H-STT-MRAM device will always have a maximum resistance and a minimum resistance, respectively: regardless of how the saturated write current and current pulse flow in either the bottom-up or top-down direction (R) is always obtained_ima ^min+R_pma ^max) And (R)_ima ^max+R_pma ^min) Two resistance states. To make (R) to_ima ^min+R_pma ^max) And (R)_ima ^max+R_pma ^min) Representing two resistance states, an ima-MTJ stack in an H-STT-MRAM device andthe pma-MTJ stack must have different TMR effects, and the ima-MTJ stack and the pma-MTJ stack automatically satisfy this requirement because they have magnetic properties including different TMR effects even when they are both optimally designed. The 2 nd step of the proposed two-step writing method is that the writing is achieved by applying a small reverse current and current pulses in the saturated resistance state (R)_ima ^min+R_pma ^min) And (R)_ima ^max+R_pma ^max) The two additional resistance states, then a total of four resistance states, may make the H-STT-MRAM a 2-bit memory device for further increasing storage capacity.

FIGS. 5(a) - (d) illustrate the 2-bit spin-transfer torque writing process at a third embodiment 300 of an H-STT-MRAM device having a relatively soft (easy to write) ima-MTJ stack using the proposed two-step writing method.

FIG. 5(a) shows the spin-transfer torque writing process after passing the saturation current and current pulses through the H-STT-MRAM 300 FIG. 3a stack from top to bottom. After passing the write current and current pulse from the top ima-MTJ 310 to the bottom pma-MTJ 120, the magnetization in the FL 121 of the bottom pma-MTJ 120 will rotate to the magnetization direction in the PL 123 at the normal spin transfer torque from the RL 123 and also the FL _ 2322 from the top ima-MTJ 310, through the nonmagnetic spacer 130, and at an additional spin transfer torque perpendicular to the normal spin transfer torque, resulting in the minimum resistance in the pma-MTJ stack. At the same time, the magnetization in FL _ 2322 will also have an opposite additional spin torque transfer from FL 121 based on Newton's third law and this additional STT is transferred to FL _ 1321 through the strong AFM coupling of FL _ 2322 and FL _ 1321 to assist FL _ 1321 writing; while FL _ 1321 is also subjected to the normal spin-transfer torque from RL 114 to rotate its magnetization to a direction antiparallel to the magnetization in RL 114. Thus, the magnetization of FL _ 1321 will also assist its writing by the normal spin transfer torque from RL 114 and the additional spin transfer torque from FL 121 perpendicular to the normal spin transfer torque through nonmagnetic spacer 130 and FL _ 2323. The SAF FL structure 320 can also be considered to be perpendicular to the nonmagnetic spacer 130 between the normal spin transfer torque from RL 114 and from FL 121 through the nonmagnetic spacer 130The entire structure under the additional spin transfer torque of the normal spin transfer torque rotates the FL _ 1321 magnetization to a direction antiparallel to the magnetization in the RL 114. Thus, a top-down write current and current pulse will result in a minimum resistance in the bottom pma-MTJ stack and a maximum resistance in the top ima-MTJ stack, and a total read resistance of (R) is obtained_pma ^min+R_ima ^max) (R) of_ima ^min，R_ima ^max) A resistive state.

FIG. 5(b) shows the bottom up write current flowing through the H-STT-MRAM stack 300. Similar to the case of top-down writing, an additional spin-transfer torque having the same amplitude and opposite direction perpendicular to its normal spin-transfer torque will act on the two free layers directly above and below the nonmagnetic spacer in the top ima-MTJ and bottom pma-MTJ, respectively. Minimum and maximum resistances are obtained in the top ima-MTJ and the bottom pma-MTJ, respectively, and a total read resistance of (R) is obtained_pma ^max+R_ima ^min) (R) of_pma ^max，R_ima ^min) The resistance state of (1).

Much attention need not be paid to the dual STT-MRAM device since maximum or minimum resistance cannot be achieved in the dual STT-MRAM device. Will the disclosed H-STT-MRAM device have the same fate? The answer is no. As mentioned above, magnetic properties including different TMR effects can be obtained in the ima-MTJ stack and the pma-MTJ stack, and (R)_pma ^min+R_ima ^max) And (R)_pma ^max+R_ima ^min) Having different values that can be used to represent two different memory states. Furthermore, indeed the (R) in fig. 5(c) and fig. 5(d) can be obtained using the two-step STT write method proposed in this disclosure, respectively_pma ^max+R_ima ^max) And (R)_pma ^min+R_ima ^min) Two maximum and minimum resistance states. Therefore, it shares { (R)_pma ^min+R_ima ^max)；(R_pma ^max+R_ima ^min)；(R_pma ^max+R_ima ^max)；(R_pma ^min+R_ima ^min) The four resistance states of H-STT-MRAM will make the H-STT-MRAM a 2-bit storage memory device to further increase storage capacity.

The proposed two-step spin-transfer torque writing method uses a second step write that applies current and current pulses with opposite directions and relatively small amplitudes to the saturated written state obtained in the first step write in order to reverse only the FL magnetization in the soft (relatively easy to write) MTJ stack to obtain two maximum or two minimum resistance states in both the top MTJ stack and the bottom MTJ stack, respectively. In the saturated writing state (R) in FIG. 5(a)_pma ^min，R_ima ^max) After applying the second bottom-up small write current and current pulse, the FL _1 and FL _2 magnetizations for the top ima-MTJ can be rotated to directions parallel and anti-parallel, respectively, to their RL magnetization directions (which is still under the two spin transfer torques, but the FL magnetization in the bottom pma-MTJ remains unchanged, as shown in FIG. 5 (c)), to obtain a magnetic memory with a total read resistance of (R) ((R))_pma ^max+R_ima ^max) Maximum resistance state (R) of the two MTJs_pma ^max，R_ima ^max). Similarly, a second step small top-down write current and current pulse may be applied in the saturated write state (R) in FIG. 5(b)_pma ^min，R_ima ^max) In which the FL _1 magnetization and FL _2 magnetization of the top ima-MTJ are rotated to directions parallel and anti-parallel to the RL magnetization direction, respectively (which is also under two spin transfer torques, but the FL magnetization in the bottom pma-MTJ remains unchanged, as shown in FIG. 5 (d)), to obtain a magnetic memory with a total read resistance of (R;)_pma ^min+R_ima ^min) Minimum resistance state (R) of the two MTJs_pma ^min，R_ima ^min). Thus, 2-bit STT storage can be achieved in the disclosed H-STT-MRAM device, with the advantage of an additional spin transfer torque perpendicular to the normal spin transfer torque to assist writing.

Fig. 6(a) - (d) show a pair of write-in methods using the proposed two-step methodThird embodiment 300 of H-STT-MRAM device with relatively soft (easy to write) pma-MTJ stack the two STT write process on FIG. 3 a. Fig. 6(a) and 6(b) are the same as in fig. 5(a) and 5 (b): rotating the magnetization of ima-MTJ FL to the opposite direction of the ima-MTJ RL magnetization by a top-down saturated write current and STT write after the current pulse, while rotating the magnetization of pma-MTJ FL to a direction parallel to the pma-MTJ RL magnetization, results in the total resistance shown in FIG. 6(a) as (R)_pma ^min+R_ima ^max) (R) of_pma ^min，R_ima ^max) A state; and the total resistance (R) in FIG. 6(b) is obtained after the bottom-up saturated write current and current pulse are applied_pma ^max+R_ima ^min) (R) of_pma ^max，R_ima ^min) Status. The second write step is to just reverse FL in the soft pma-TMJ stack, and R in the ima-MTJ, with a bottom-up write current and current pulse using a reverse and relatively small amplitude_ima ^maxThe state was kept constant while obtaining a resistance having a total resistance (R) shown in FIG. 6(c) at two spin transfer torques_pma ^max+R_ima ^max) (R) of_pma ^max，R_ima ^max) Status. Similarly, in (R) for FIG. 6(b)_pma ^max+R_ima ^min) The second step maintains R of the ima-MTJ with a relatively small amplitude of write current and current pulse from top to bottom_ima ^minAt R at two spin transfer torques with the state remaining unchanged and at inversion_pma ^maxR obtained after magnetization of FL in pma-TMJ of states_pma ^maxTo obtain a resistance having a total resistance of (R) shown in FIG. 6(d)_pma ^min+R_ima ^min) (R) of_pma ^min，R_ima ^min) Status. Thus, what can also be obtained in an H-STT-MRAM device having a relatively soft pma-MTJ stack for 2-bit storage is { (R)_pma ^min+R_ima ^max)；(R_pma ^max+R_ima ^min)；(R_pma ^max+R_ima ^max)；(R_pma ^min+R_ima ^min) Four resistance states of.

The 2-bit H-STT-MRAM device can be further extended for use with an n-bit H-STT-MRAM device for further increasing areal storage density.

FIGS. 7(a) - (c) illustrate 4-bit, 6-bit, and 8-bit H-STT-MRAM device designs 700, respectively. The 4-bit H-STT-MRAM device is formed by stacking the 2-bit H-STT-MRAM device 400 on the 2-bit H-STT-MRAM device 300, FIG. 3a (hereinafter referred to as 300) or in reverse order so that the same AFM pinned layer is shared by either two adjacent pma-MTJs or two adjacent ima-MTJs. FIG. 7(a) shows a 4-bit H-STT-MRAM device 710 formed by stacking a 2-bit H-STT-MRAM 300 on the 2-bit H-STT-MRAM 400, wherein the top ima-MTJ in 400 and the bottom ima-MTJ in 300 share one AFM pinned layer 714 and a side contact 712 between 400 and 300, the maximum coverage of the side contact 712 is from the RL stack of the top ima-MTJ in the H-STT-MRAM 400 to the RL stack of the bottom ima-MTJ in the H-STT-MRAM 300. The side contact 712 is used for STT writing and TMR reading to achieve 4-bit storage in 700. To prevent the transistor from being broken down by the large current and current pulse through the entire stack, two 2-bit H-STT-MRAMs can be separately written using side contacts 712: the bottom electrode contact and side contact 712 may be used to write the 2-bit H-STT-MRAM 400 and the top electrode contact and side contact 712 may be used to write the 2-bit H-STT-MRAM 300. Since the read current is much smaller than the write current and the current pulses, there is not much risk of breaking down the transistor as long as the read voltage is smaller than the transistor breakdown voltage. By using the proposed two-step write method at 300 and 400, respectively { (R)¹ _pmaR¹ _ima)(R² _imaR² _pma) The 4-bit stored 16 resistance states represented by are (00) (00); { (11) (11) }; { (00) (01) }; { (00) (10) }; { (01) (00) }; { (10) (00) }; { (00) (11) }; { (11) (00) }; { (10) (10) }; { (01) (10) }; { (01) (01) }; { (10) (01) }; { (01) (11) }; { (10) (11) }; { (10) (01) }; { (11) (10) }, wherein "1" and "0" respectively mean to be { (R)¹ _pmaR¹ _ima)(R² _imaR² _pma) Maximum and minimum resistance states in the order, and RⁱRepresenting the ith 2-bit H-STT-MRAM stack. The 2 bits stored in 300 are first obtained as R by passing a read current through the transistor and the first side contact 712¹＝(R¹ _pma+R¹ _ima) Then, the total resistance R in the embodiment of 700 formed by 300 and 400¹+R²＝(R¹ _pma+R¹ _ima)+(R² _pma+R² _ima) Obtained by passing a read current through the transistor and top bit line to obtain by taking R out of 300¹To calculate R in 400²Of the memory resistance R²＝(R1_pma+R¹ _ima)+(R² _pma+R² _ima)-R¹＝(R² _pma+R² _ima). FIG. 7(b) shows a 6-bit H-STT-MRAM device 720 formed by stacking a 2-bit H-STT-MRAM device 300 on a 4-bit H-STT-MRAM device 710, where the bottom pma-MTJ in 300 and the top pma-MTJ in 710 also share the same AFM pinning layer 724. Similar to 712, the maximum coverage of side contact 722 is from the RL stack of the top pma-MTJ in 710 to the RL stack of the bottom pma-MTJ in 300. Similarly, writing to the top 2-bit H-STT-MRAM 300 can be obtained by passing a write current from the device top electrode and side contact 722. The reading of the 6-bit H-STT-MRAM 720 may be accomplished in a manner similar to the reading in the 4-bit H-STT-MRAM 710 device. FIG. 7(c) shows a 1 byte H-STT-MRAM device 730 formed by stacking two 4-bit H-STT-MRAM 710, where the top pma-MTJ in the lower portion 710 and the bottom pma-MTJ in the top portion 710 share the same AFM layer, and the side contact 722 in 720 can still be used for writing, and a total of 32 resistance states can be written and read out similar to that in the 4-bit H-STT-MRAM 710.

In a similar manner, a 4 n-bit H-STT-MRAM device having one transistor may be obtained by stacking a total of n 4-bit H-STT-MRAM devices having a total of (2n-1) side contacts between two adjacent ima-MTJs or two adjacent RLs in two adjacent pma-MTJs. If necessary, by shifting from 4n bitsThe H-STT-MRAM device takes the 2-bit H-STT-MRAM stack away to obtain any (4n-2) bit H-STT-MRAM device. One of the purposes of the high bit H-STT-MRAM device is to take full advantage of the transistor without being sufficient to break down the transistor barrier when the current through the transistor is reading the high bit H-STT-RAM memory bit. To accurately read the information stored in each MTJ of a 4 n-bit H-STT-MRAM stack, a read current needs to pass from the transistor to the first side contact for reading out the R¹＝(R¹ _ima+R¹ _pma) The state of (1); then to the second contact for reading R¹+R²＝(R¹ _ima+R¹ _pma+R² _pma+R² _ima) In order to obtain a known (R)¹ _ima+R¹ _pma) Thereafter obtaining R²＝(R² _ima+R² _pma) … … then, to the top bit line for reading out the total resistance of the 4n bit H-STT-MRAM device, which is equal toIn the known method of obtaining a read pass transistor to (2n-1) side contactsThen obtainingIf the constant read current is well below the transistor barrier breakdown critical current, the constant read current will be a good choice to avoid breakdown of the transistor barrier. The write current completes the entire write process by completing on any intermediate 2-bit H-STT-MRAM by passing through two adjacent side contacts in addition to passing through the transistor. Breakdown of the transistor when large write currents and current pulses pass should be avoided. When two adjacent 2-bit H-STT-MRAM devices cannot share the same AFM, the side contact may further comprise a contact layer between the two adjacent devices, whose stacking of the 2-bit H-STT-MRAM can be arranged in other orders, but a regular stacking order is preferred to determine each 2-bit while writing and readingSeparate pma-MTJ resistance states and ima-MTJ resistance states in an H-STT-MRAM. The high bit H-STT-MRAM device adds a bit if its write current is not large enough to break down the transistor.

To this end, each ima-MTJ stack or pma-MTJ stack in the H-STT-MRAM is written in either a maximum resistance state or a minimum resistance state. A pma-MTJ stack with magnetic perpendicular anisotropy typically has only two stable resistance storage states, maximum and minimum. As previously mentioned, an ima-MTJ stack having an SAF FL structure may have a R that may form a 3-bit (or 3.3219280949-bit) H-STT-MRAM device_ima ^max、R_ima ^min、R_ima ^π/4、(R_ima ^±π/2) And R_ima ^3π/4The 4 (or 5) resistance states of the proposed H-STT-MRAM device can greatly increase the storage capacity of the proposed H-STT-MRAM device.

2D arrays and even 3D arrays of high bit H-STT-MRAM devices can be made for high performance computing, mobile devices, and information storage devices. In a 2D array of high bit H-STT-MRAM devices, side contacts can be connected to the read and write circuitry shared by the side contacts on the plane, but isolation is required between adjacent high bit H-STT-MRAM devices. The 3D array of high bit H-STT-MRAM devices is a 2D array of high bit H-STT-MRAM devices, including a stack of transistors of each high bit H-STT-MRAM, in the height direction, to maximize the storage capacity with one substrate.

The above-mentioned embodiments of the H-STT-MRAM device are illustrated to achieve only the features and advantages of the present disclosure, are not limiting and may not be drawn to scale. This disclosure is intended to encompass any and all subsequent adaptations, combinations, or variations of various embodiments that may be utilized and derived after the present disclosure, without departing from the spirit and scope of the present disclosure.