阅读说明：本技术 异步电机v/f调速轻载振荡的抑制方法及系统 (Method and system for inhibiting V/F speed regulation light-load oscillation of asynchronous motor ) 是由 翟冲 赵珊 瞿李锋 张昱科 马静雄 于 2020-12-14 设计创作，主要内容包括：本发明提出了一种异步电机V/F调速轻载振荡的抑制方法及系统,所述方法通过采集定子的相电流来提取定子无功电流,经过低通滤波后得到其波动分量,经过PI调节器给已知的定子电压矢量垂直方向增加微调量,同时调整其幅值与相位来稳定系统,达到抑制转矩波动的目的,改善了系统稳定性；由于仅利用与振荡相关的电流波动分量,通过定子电流的检测采样来获取,简单易行,且不依赖电机参数即可抑制开环v/f控制空载或者轻载电机振荡,确保电机在整个频率段轻载都能平稳运行。(The invention provides a method and a system for suppressing V/F speed regulation light-load oscillation of an asynchronous motor, wherein the method extracts stator reactive current by collecting phase current of a stator, obtains fluctuation components of the stator after low-pass filtering, increases fine adjustment quantity for the known stator voltage vector in the vertical direction through a PI regulator, and simultaneously adjusts the amplitude and the phase of the stator voltage vector to stabilize the system, thereby achieving the purpose of suppressing torque fluctuation and improving the stability of the system; the motor is simple and easy to operate, and can inhibit open-loop v/f to control no-load or light-load motor oscillation without depending on motor parameters, thereby ensuring that the motor can stably run under light load in the whole frequency band.)

1. A method for suppressing V/F speed regulation light-load oscillation of an asynchronous motor is characterized by comprising the following steps:

step S1, orienting the stator voltage vector on the D axis of the rotating coordinate system, and obtaining the stator voltage active component vd and the stator voltage reactive component vq of the stator voltage vector through coordinate transformation;

step S2, obtaining the rotation frequency f of the stator voltage vector, integrating the rotation frequency f to obtain a rotation vector angle theta r, calculating an included angle theta v between the stator voltage vector and a D axis according to the active component vd of the stator voltage and the reactive component vq of the stator voltage, and summing the rotation vector angle theta r and the included angle theta v to obtain a voltage vector angle theta;

step S3, collecting A, B phase current of a motor stator, carrying out clark transformation on the phase current, and then carrying out park transformation on the phase current according to a voltage vector angle theta to obtain a stator current active component Id and a stator current reactive component Iq of the phase current;

step S4, performing low-pass filtering on the stator current reactive component Iq to obtain a steady-state component Iqf of the stator current reactive component Iq, obtaining a fluctuation component by subtracting the stator current reactive component Iq and the steady-state component Iqf, sending the fluctuation component to a PI regulator to generate a voltage fine adjustment quantity Uq, determining the current output voltage Ud according to a V/F curve, and obtaining a current output voltage vector < Ud, Uq >;

step S5, inv-park conversion is performed on the output voltage vector < Ud, Uq > according to the rotation vector angle θ r to obtain < U α, U β >, which is input to the SVM to generate the required modulation wave.

2. The method for suppressing the V/F speed-regulation light-load oscillation of the asynchronous motor according to claim 1, wherein the method is applied to high-voltage cascade type frequency conversion.

3. The method for suppressing the V/F speed regulation light-load oscillation of the asynchronous motor according to claim 1, wherein in the step S3, the step of collecting the A, B phase current of the stator of the motor comprises:

acquiring sampling values y1, y2 and y3 of the set error allowable values x1 and x2 and phase currents at sequential acquisition moments t1, t2 and t3, wherein x1 is smaller than x2, and y3 is the current sampling value;

if the difference between y3 and y2 is not greater than x1, keeping y3 as the current sample value; if the difference value between y3 and y2 is larger than x1 and smaller than x2, taking the average value of y2 and y3 as the current sampling value; and if the difference value between y3 and y2 is not less than x2, taking the average value of y1 and y2 as the current sampling value.

4. The method for suppressing the V/F speed-regulation light-load oscillation of the asynchronous motor according to claim 1, wherein in the step S4, the step of low-pass filtering the reactive component Iq of the stator current comprises:

order S_q(k)＝S_q(k-1)+I_q(k)-I_q(k-N/6), k being the sampling number, I_q(k) The k sampling value of Iq, N is the total sampling times of phase current in a power frequency period, the time interval of each sampling is equal, and S_q(k) The cumulative sum of the results for the most recent N/6 Iq calculations,taking Iq as S_q(k)/(N/6)。

5. The method for suppressing the V/F speed-regulation light-load oscillation of the asynchronous motor according to claim 4, wherein in the step S4, the step of low-pass filtering the reactive component Iq of the stator current further comprises:

the stator current reactive component Iq is further filtered with a butterworth low pass filter.

6. A suppression system for V/F speed regulation light-load oscillation of an asynchronous motor is characterized by comprising:

the stator voltage component acquisition module is used for orienting the stator voltage vector on a D axis of a rotating coordinate system and obtaining a stator voltage active component vd and a stator voltage reactive component vq of the stator voltage vector through coordinate transformation;

the vector angle calculation module is used for acquiring the rotation frequency f of the stator voltage vector, integrating the rotation frequency f to obtain a rotation vector angle theta r, calculating an included angle theta v between the stator voltage vector and the D axis according to the active component vd of the stator voltage and the reactive component vq of the stator voltage, and summing the rotation vector angle theta r and the included angle theta v to obtain a voltage vector angle theta;

the stator current component acquisition module is used for acquiring A, B phase current of a motor stator, performing clark transformation on A, B phase current, and then performing park transformation on A, B phase current according to a voltage vector angle theta to obtain a stator current active component Id and a stator current reactive component Iq of A, B phase current;

the output voltage vector acquisition module is used for carrying out low-pass filtering on the stator current reactive component Iq to obtain a steady-state component Iqf of the stator current reactive component Iq, obtaining a fluctuation component by subtracting the stator current reactive component Iq and the steady-state component Iqf, sending the fluctuation component to the PI regulator to generate a voltage fine adjustment quantity Uq, determining the current output voltage Ud according to a V/F curve, and obtaining a current output voltage vector < Ud, Uq >;

and the modulation wave generation module is used for carrying out inv-park conversion on the output voltage vector < Ud, Uq > according to the rotation vector angle theta r to obtain < U alpha, U beta > which is input into the SVM to generate the required modulation wave.

7. The system for suppressing the V/F speed-regulating light-load oscillation of the asynchronous motor as claimed in claim 6, wherein the stator current component obtaining module comprises MOS tubes J1A, J1B, J2A, J2B, J3A, J3B, operational amplifiers U1-U3, resistors Ra, Rb, Rx, R1-R16 and capacitors Cx, C1-C11;

phase current outputs differential voltage signals to the grids of the MOS tubes J1 and J1 in a sampling mode through the Hall sensor, a positive power supply is grounded through resistors R and R in sequence, the common end of the resistors R and R is connected with the in-phase end of the operational amplifier U and the in-phase end of the operational amplifier U at the same time, capacitors C and C are connected with the resistor R in parallel, the positive power supply is connected with the output end of the operational amplifier U through the resistor R and the MOS tubes J3, R, J2, J1 and R in sequence, the positive power supply is grounded through the resistors R and the capacitors C and C in parallel, the MOS tube J2 and the common end of the resistor R are connected with the grid of the MOS tube J3, the drain of the MOS tube J2 is connected with the drain of the MOS tube J2 through the resistor Rx and the capacitor Cx in sequence, the gate of the MOS transistor J2A is connected to the source of the MOS transistor J1A, the gate of the MOS transistor J2B is connected to the source of the MOS transistor J1B, the source of the MOS transistor J1A is further connected to the source of the MOS transistor J1B via a resistor R1, the gate of the MOS transistor J1A is further grounded via a resistor Ra, and the gate of the MOS transistor J1B is further grounded via a resistor Rb;

the common end of the MOS tube J2A and the resistor R4 is further sequentially grounded through a resistor R6 and a capacitor C6, the common end of the resistor R6 and the capacitor C6 is connected with the inverting end of the operational amplifier U1, the inverting end of the operational amplifier U1 is further sequentially connected with the output end of the operational amplifier U1 through a resistor R11 and a capacitor C8 which are connected in series, the common end of the MOS tube J2B and the resistor R5 is further sequentially grounded through a resistor R7 and a capacitor C7, the common end of the resistor R7 and the capacitor C7 is connected with the inverting end of the operational amplifier U2, and the inverting end of the operational amplifier U2 is further sequentially connected with the output end of the operational amplifier U2 through a resistor R12 and a capacitor C5 which are connected in series;

the output end of the operational amplifier U1 is further connected with the in-phase end of the operational amplifier U3 through a resistor R13, the in-phase end of the operational amplifier U3 is further connected with the output end of the operational amplifier U3 through a resistor R15, a capacitor C10 is connected with the resistor R15 in parallel, the output end of the operational amplifier U2 is further connected with the inverting end of the operational amplifier U3 through a resistor R14, the inverting end of the operational amplifier U3 is further grounded through a resistor R16 and a capacitor C11 which are connected in parallel, and the output of the operational amplifier U3 is used for AD conversion of a later stage.

8. The system for suppressing the V/F speed-regulation light-load oscillation of the asynchronous motor as claimed in claim 7, wherein the stator current component obtaining module further comprises MOS transistors J4A, J5B, resistors R17-R22, a capacitor C12 and an operational amplifier U4;

the output end of the operational amplifier U3 is connected with the grid electrode of the MOS tube J4A, the positive power supply is connected with the drain electrode of the MOS tube J4A through a resistor R17, and is connected with the drain electrode of the MOS tube J5B through a resistor R18, the drain electrode of the MOS tube J4A is further connected with the drain electrode of the MOS tube J5B through a capacitor C12 and a resistor R19 which are connected in series in sequence, the common end of the source electrode of the MOS tube J4A and the source electrode of the MOS tube J5B is connected with the negative power supply through a resistor R20, the drain electrode of the MOS tube J4A is further connected with the same-phase end of the operational amplifier U4, the drain electrode of the MOS tube J5B is further connected with the inverting end of the operational amplifier U4, the output end of the operational amplifier U4 is grounded through resistors R21 and R22 in sequence, the common end of the resistors R21 and R22 is connected with.

Technical Field

The invention relates to the technical field of high-voltage cascade variable-frequency speed regulation, in particular to a method and a system for inhibiting V/F speed regulation light-load oscillation of an asynchronous motor.

Background

In practical engineering application, under the condition of light load or no load of a large-capacity motor, torque pulsation is often generated when a V/F control mode is used, so that large mechanical oscillation is caused, and waveform pulsation of output current of a frequency converter is very serious. Because the open-loop control cannot inhibit the phenomenon and the motor cannot be effectively inhibited when the motor oscillates, the phenomena of overcurrent and the like can occur under severe conditions, and the stability of the asynchronous motor and the stability of the V/F control system are seriously influenced.

When the cascade type frequency converter drives the asynchronous motor to work in a V/F mode, the system is easy to suffer from the problem of continuous oscillation, which is particularly prominent under the conditions of light load and low frequency. The common traditional method is to keep the reactive current of the motor constant to inhibit the motor oscillation, but the reactive current of the motor needs to be known in the method, the idle load exciting current of the motor is generally used for approximating the reactive current of the motor in engineering, but the motor parameter needs to be set when the idle load exciting current is obtained, so that the traditional method depends on the motor parameter.

Disclosure of Invention

In view of the above, on the one hand, the invention provides a method for suppressing V/F speed regulation light-load oscillation of an asynchronous motor, so as to solve the problem that the conventional method for suppressing V/F speed regulation light-load oscillation of the asynchronous motor depends on motor parameters.

The technical scheme of the invention is realized as follows: a method for suppressing V/F speed regulation light-load oscillation of an asynchronous motor comprises the following steps:

step S1, orienting the stator voltage vector on the D axis of the rotating coordinate system, and obtaining the stator voltage active component vd and the stator voltage reactive component vq of the stator voltage vector through coordinate transformation;

step S2, obtaining the rotation frequency f of the stator voltage vector, integrating the rotation frequency f to obtain a rotation vector angle theta r, calculating an included angle theta v between the stator voltage vector and a D axis according to the active component vd of the stator voltage and the reactive component vq of the stator voltage, and summing the rotation vector angle theta r and the included angle theta v to obtain a voltage vector angle theta;

step S3, collecting A, B phase current of a motor stator, carrying out clark transformation on the phase current, and then carrying out park transformation on the phase current according to a voltage vector angle theta to obtain a stator current active component Id and a stator current reactive component Iq of the phase current;

step S4, performing low-pass filtering on the stator current reactive component Iq to obtain a steady-state component Iqf of the stator current reactive component Iq, obtaining a fluctuation component by subtracting the stator current reactive component Iq and the steady-state component Iqf, sending the fluctuation component to a PI regulator to generate a voltage fine adjustment quantity Uq, determining the current output voltage Ud according to a V/F curve, and obtaining a current output voltage vector < Ud, Uq >;

step S5, inv-park conversion is performed on the output voltage vector < Ud, Uq > according to the rotation vector angle θ r to obtain < U α, U β >, which is input to the SVM to generate the required modulation wave.

Optionally, in step S3, the step of collecting A, B phase current of the motor stator includes:

acquiring sampling values y1, y2 and y3 of the set error allowable values x1 and x2 and phase currents at sequential acquisition moments t1, t2 and t3, wherein x1 is smaller than x2, and y3 is the current sampling value;

if the difference between y3 and y2 is not greater than x1, keeping y3 as the current sample value; if the difference value between y3 and y2 is larger than x1 and smaller than x2, taking the average value of y2 and y3 as the current sampling value; and if the difference value between y3 and y2 is not less than x2, taking the average value of y1 and y2 as the current sampling value.

Optionally, in step S4, the step of low-pass filtering the stator current reactive component Iq includes:

order S_q(k)＝S_q(k-1)+I_q(k)-I_q(k-N/6), k being the sampling number, I_q(k) The k sampling value of Iq, N is the total sampling times of phase current in a power frequency period, the time interval of each sampling is equal, and S_q(k) For the cumulative sum of the most recent N/6 Iq calculations, take Iq as S_q(k)/(N/6)。

Optionally, in step S4, the step of low-pass filtering the stator current reactive component Iq further includes:

the stator current reactive component Iq is further filtered with a butterworth low pass filter.

Compared with the prior art, the method for inhibiting the V/F speed regulation light-load oscillation of the asynchronous motor has the following beneficial effects:

(1) the method comprises the steps of extracting stator current reactive current by collecting A, B phase current of a stator, obtaining fluctuation components of the stator current reactive current after low-pass filtering, increasing fine adjustment quantity in the vertical direction of a known stator voltage vector through a PI (proportional-integral) regulator, and adjusting the amplitude and phase of the stator voltage vector to stabilize a system, so that the aim of inhibiting torque fluctuation is fulfilled, the system stability is improved, and the motor current reactive current is obtained by detecting and sampling the stator current only by utilizing the current fluctuation components related to oscillation, is simple and easy to implement, can inhibit open-loop v/f to control no-load or light-load motor oscillation without depending on motor parameters, and ensures that the motor can stably run under light load in the whole frequency band;

(2) when the difference value between the current sampling value and the last sampling value is large, the current sampling value is considered to be possibly a random current peak, the current sampling value is not simply replaced by the last sampling value, but the current sampling value is replaced by the average value of two continuous sampling values, the random current peak is eliminated, the continuity of the sampling value is ensured, and the smoothness is improved;

(3) by calculating S_q(k)＝S_q(k-1)+I_q(k)-I_q(k-N/6), taking the average value of the period of Iq as S_q(k) /(N/6), when the phase current changes, S_q(k) And the current also changes immediately, and only 1/6 power frequency cycles are needed at most to reach a new steady state, so that the Iq is subjected to low-pass filtering by the formula to have a faster response speed, and the obtained d-axis current can reach the steady state in a faster time.

On the other hand, the invention also provides a suppression system for V/F speed regulation light-load oscillation of the asynchronous motor, so as to solve the problem that the V/F speed regulation light-load oscillation suppression system of the traditional asynchronous motor depends on motor parameters.

The technical scheme of the invention is realized as follows: a suppression system for V/F speed regulation light-load oscillation of an asynchronous motor comprises:

the stator voltage component acquisition module is used for orienting the stator voltage vector on a D axis of a rotating coordinate system and obtaining a stator voltage active component vd and a stator voltage reactive component vq of the stator voltage vector through coordinate transformation;

the vector angle calculation module is used for acquiring the rotation frequency f of the stator voltage vector, integrating the rotation frequency f to obtain a rotation vector angle theta r, calculating an included angle theta v between the stator voltage vector and the D axis according to the active component vd of the stator voltage and the reactive component vq of the stator voltage, and summing the rotation vector angle theta r and the included angle theta v to obtain a voltage vector angle theta;

the stator current component acquisition module is used for acquiring A, B phase current of a motor stator, performing clark transformation on A, B phase current, and then performing park transformation on A, B phase current according to a voltage vector angle theta to obtain a stator current active component Id and a stator current reactive component Iq of A, B phase current;

the output voltage vector acquisition module is used for carrying out low-pass filtering on the stator current reactive component Iq to obtain a steady-state component Iqf of the stator current reactive component Iq, obtaining a fluctuation component by subtracting the stator current reactive component Iq and the steady-state component Iqf, sending the fluctuation component to the PI regulator to generate a voltage fine adjustment quantity Uq, determining the current output voltage Ud according to a V/F curve, and obtaining a current output voltage vector < Ud, Uq >;

and the modulation wave generation module is used for carrying out inv-park conversion on the output voltage vector < Ud, Uq > according to the rotation vector angle theta r to obtain < U alpha, U beta > which is input into the SVM to generate the required modulation wave.

Optionally, the stator current component obtaining module includes MOS transistors J1A, J1B, J2A, J2B, J3A, J3B, operational amplifiers U1 to U3, resistors Ra, Rb, Rx, R1 to R16, and capacitors Cx and C1 to C11;

phase current outputs differential voltage signals to the grids of the MOS tubes J1 and J1 in a sampling mode through the Hall sensor, a positive power supply is grounded through resistors R and R in sequence, the common end of the resistors R and R is connected with the in-phase end of the operational amplifier U and the in-phase end of the operational amplifier U at the same time, capacitors C and C are connected with the resistor R in parallel, the positive power supply is connected with the output end of the operational amplifier U through the resistor R and the MOS tubes J3, R, J2, J1 and R in sequence, the positive power supply is grounded through the resistors R and the capacitors C and C in parallel, the MOS tube J2 and the common end of the resistor R are connected with the grid of the MOS tube J3, the drain of the MOS tube J2 is connected with the drain of the MOS tube J2 through the resistor Rx and the capacitor Cx in sequence, the gate of the MOS transistor J2A is connected to the source of the MOS transistor J1A, the gate of the MOS transistor J2B is connected to the source of the MOS transistor J1B, the source of the MOS transistor J1A is further connected to the source of the MOS transistor J1B via a resistor R1, the gate of the MOS transistor J1A is further grounded via a resistor Ra, and the gate of the MOS transistor J1B is further grounded via a resistor Rb;

the common end of the MOS tube J2A and the resistor R4 is further sequentially grounded through a resistor R6 and a capacitor C6, the common end of the resistor R6 and the capacitor C6 is connected with the inverting end of the operational amplifier U1, the inverting end of the operational amplifier U1 is further sequentially connected with the output end of the operational amplifier U1 through a resistor R11 and a capacitor C8 which are connected in series, the common end of the MOS tube J2B and the resistor R5 is further sequentially grounded through a resistor R7 and a capacitor C7, the common end of the resistor R7 and the capacitor C7 is connected with the inverting end of the operational amplifier U2, and the inverting end of the operational amplifier U2 is further sequentially connected with the output end of the operational amplifier U2 through a resistor R12 and a capacitor C5 which are connected in series;

the output end of the operational amplifier U1 is further connected with the in-phase end of the operational amplifier U3 through a resistor R13, the in-phase end of the operational amplifier U3 is further connected with the output end of the operational amplifier U3 through a resistor R15, a capacitor C10 is connected with the resistor R15 in parallel, the output end of the operational amplifier U2 is further connected with the inverting end of the operational amplifier U3 through a resistor R14, the inverting end of the operational amplifier U3 is further grounded through a resistor R16 and a capacitor C11 which are connected in parallel, and the output of the operational amplifier U3 is used for AD conversion of a later stage.

Optionally, the stator current component obtaining module further includes MOS transistors J4A, J5B, resistors R17 to R22, a capacitor C12, and an operational amplifier U4;

the output end of the operational amplifier U3 is connected with the grid electrode of the MOS tube J4A, the positive power supply is connected with the drain electrode of the MOS tube J4A through a resistor R17, and is connected with the drain electrode of the MOS tube J5B through a resistor R18, the drain electrode of the MOS tube J4A is further connected with the drain electrode of the MOS tube J5B through a capacitor C12 and a resistor R19 which are connected in series in sequence, the common end of the source electrode of the MOS tube J4A and the source electrode of the MOS tube J5B is connected with the negative power supply through a resistor R20, the drain electrode of the MOS tube J4A is further connected with the same-phase end of the operational amplifier U4, the drain electrode of the MOS tube J5B is further connected with the inverting end of the operational amplifier U4, the output end of the operational amplifier U4 is grounded through resistors R21 and R22 in sequence, the common end of the resistors R21 and R22 is connected with.

Compared with the prior art, the suppression system for the V/F speed regulation light-load oscillation of the asynchronous motor has similar advantages to the suppression method for the V/F speed regulation light-load oscillation of the asynchronous motor, and is not repeated.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of the method for restraining the V/F speed regulation light-load oscillation of the asynchronous motor according to the invention;

FIG. 2 is a flow chart of the method for suppressing the V/F speed regulation light-load oscillation of the asynchronous motor of the present invention;

FIG. 3 is a block diagram of the suppression system for V/F speed regulation light-load oscillation of the asynchronous motor of the present invention;

FIG. 4 is a partial circuit diagram of a stator current component acquisition module of the present invention;

fig. 5 is another circuit diagram of a portion of the stator current component obtaining module according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

As shown in fig. 1 and fig. 2, the method for suppressing V/F speed regulation light-load oscillation of an asynchronous motor in the present embodiment includes:

step S1, orienting the stator voltage vector on the D axis of the rotating coordinate system, and obtaining the stator voltage active component vd and the stator voltage reactive component vq of the stator voltage vector through coordinate transformation;

step S2, obtaining the rotation frequency f of the stator voltage vector, integrating the rotation frequency f to obtain a rotation vector angle theta r, calculating an included angle theta v between the stator voltage vector and a D axis according to the active component vd of the stator voltage and the reactive component vq of the stator voltage, and summing the rotation vector angle theta r and the included angle theta v to obtain a voltage vector angle theta;

step S3, collecting A, B phase current of a motor stator, carrying out clark transformation on the phase current, and then carrying out park transformation on the phase current according to a voltage vector angle theta to obtain a stator current active component Id and a stator current reactive component Iq of the phase current;

step S4, performing low-pass filtering on the stator current reactive component Iq to obtain a steady-state component Iqf of the stator current reactive component Iq, obtaining a fluctuation component by subtracting the stator current reactive component Iq and the steady-state component Iqf, sending the fluctuation component to a PI regulator to generate a voltage fine adjustment quantity Uq, determining the current output voltage Ud according to a V/F curve, and obtaining a current output voltage vector < Ud, Uq >;

step S5, inv-park conversion is performed on the output voltage vector < Ud, Uq > according to the rotation vector angle θ r to obtain < U α, U β >, which is input to the SVM to generate the required modulation wave.

In step S2, rotation vector angle θ r ═ fdt, and included angle θ v ═ arctan (vq/vd); in step S3, the phase C current may be calculated according to the theory that the sum of the three-phase current vectors of the stator is zero, the phase A, B current may be transformed from the abc coordinate system to the α β coordinate system by using a click transformation, and the phase A, B current may be transformed from the α β coordinate system to the dq coordinate system by using a park transformation; in step S5, the output voltage vector < Ud, Uq > can be transformed from the dq coordinate system to the α β coordinate system using the inv-park transformation.

In general, when oscillations occur in the frequency conversion system of an asynchronous machine, the active power and the reactive power of the machine will also oscillate, and the oscillations of the stator active power and the reactive power are almost entirely reflected in the active and reactive components of the stator current. In the embodiment, the reactive current of the stator is extracted by collecting the phase current of the stator, the fluctuation component of the reactive current is obtained after low-pass filtering, the fine adjustment quantity is added to the known stator voltage vector in the vertical direction through the PI regulator, and the amplitude and the phase of the fine adjustment quantity are adjusted to stabilize the system, so that the aim of inhibiting torque fluctuation is fulfilled, and the stability of the system is improved; the motor is simple and easy to operate, and can inhibit open-loop v/f to control no-load or light-load motor oscillation without depending on motor parameters, thereby ensuring that the motor can stably run under light load in the whole frequency band.

In the embodiment, A, B phase current of the motor stator can be collected through the hall sensor, and a voltage signal obtained from the hall sensor is amplified and then input into an AD module of the microprocessor. Due to interference of a power electronic circuit, a random current peak appears in a sampled value of a phase current, an error allowable value is generally set, and a last sampled value is used for replacing the current sampled value when a difference value between the current sampled value and the last sampled value is larger than the error allowable value. The motor phase current is a dynamic signal, and both the real-time property and the continuity of a sampling value need to be considered. In step S3, the step of collecting A, B phase current of the stator of the motor includes: acquiring sampling values y1, y2 and y3 of the set error allowable values x1 and x2 and phase currents at sequential acquisition moments t1, t2 and t3, wherein x1 is smaller than x2, and y3 is the current sampling value; if the difference between y3 and y2 is not greater than x1, keeping y3 as the current sample value; if the difference value between y3 and y2 is larger than x1 and smaller than x2, taking the average value of y2 and y3 as the current sampling value; and if the difference value between y3 and y2 is not less than x2, taking the average value of y1 and y2 as the current sampling value. Assuming that the error tolerance values x1 and x2 are 1 and 2, respectively, and the sampled values y1, y2 and y3 are f, f +1 and f +3, respectively, the conventional error tolerance value is x 1. For the conventional filtering, y1 and y2 are effective values, the difference value between y3 and y2 is 2, the current sample value of y3 is invalid, y2 is used for replacing y3, and three continuous sample values are f, f +1 and f +1 respectively. For the filtering method of this embodiment, the difference between y3 and y2 is not less than x2, the average value of y1 and y2 is taken as the current sample value, and three consecutive sample values are f, f +1, (2f +1)/2, respectively. It can be seen from the above example that, in this embodiment, when the difference between the current sampling value and the previous sampling value is large, it is considered that the current sampling value may be a random current spike, and instead of simply replacing the current sampling value with the previous sampling value, the current sampling value is replaced with the average value of two consecutive sampling values, so that the random current spike is eliminated, the continuity of the sampling values is ensured, and the smoothness is improved.

In step S4, the low-pass filter filters out the fluctuation component in Iq, the remainder is the steady-state component Iqf, the unprocessed stator current reactive component Iq includes the steady-state component Iqf and the fluctuation component, the unprocessed stator current reactive component Iq is subtracted from the steady-state component Iqf to obtain the fluctuation component, and the performance of the low-pass filter determines the accuracy of the fluctuation component. In this embodiment, assuming that the three-phase circuit of the motor stator is balanced, after the phase current is converted to the synchronous rotating coordinate system, the expression of the reactive component Iq of the stator current in the dq coordinate system is

In the formula I_nEffective value of the fluctuation component of degree n, theta_nThe initial phase angle of the n fluctuation components is n-6 k-1. Under the synchronous rotating coordinate system, the fluctuation component becomes a frequency multiplication component of 6, and Iq is a periodic signal of 1/6 power frequency periods. If the Butterworth filter is used for filtering the fluctuation component, complex calculation cannot be avoided, the calculated amount of the microprocessor is too large, and the response time is short. Therefore, the step of low-pass filtering the stator current reactive component Iq by the priority step S4 of the present embodiment includes: order S_q(k)＝S_q(k-1)+I_q(k)-I_q(k-N/6), k being the sampling number, I_q(k) The sampling value of the kth time is Iq, N is the total sampling times of the microprocessor to the phase current in a power frequency period, and the time intervals of each sampling are equal, then S is_q(k) The cumulative sum of the results for the most recent N/6 Iq calculations, so the periodic average of Iq is S_q(k) /(N/6), when the phase current changes, S_q(k) Will also change immediately, requiring only at most 1/6 power frequency cycles to reach the new steady state, thus passing throughThe low-pass filtering on Iq by the formula has faster response speed, and the obtained d-axis current can reach a steady state in a faster time.

When the filtering method filters the fluctuation component of the 6 times frequency component, the response speed is faster, but the filtering effect cannot be guaranteed to be optimal, and in order to further improve the filtering effect of the low-pass filter, in this embodiment, preferably, the step of performing the low-pass filtering on the stator current reactive component Iq in step S4 further includes: and further filtering the reactive component Iq of the stator current by using a Butterworth low-pass filter, namely connecting a Butterworth low-pass filter in series after the filtering method, so that the detection precision and the response speed can be effectively coordinated.

As shown in fig. 3, this embodiment further provides a system for suppressing V/F speed regulation light-load oscillation of an asynchronous motor, including: the stator voltage component acquisition module is used for orienting the stator voltage vector on a D axis of a rotating coordinate system and obtaining a stator voltage active component vd and a stator voltage reactive component vq of the stator voltage vector through coordinate transformation; the vector angle calculation module is used for acquiring the rotation frequency f of the stator voltage vector, integrating the rotation frequency f to obtain a rotation vector angle theta r, calculating an included angle theta v between the stator voltage vector and the D axis according to the active component vd of the stator voltage and the reactive component vq of the stator voltage, and summing the rotation vector angle theta r and the included angle theta v to obtain a voltage vector angle theta; the stator current component acquisition module is used for acquiring A, B phase current of a motor stator, performing clark transformation on A, B phase current, and then performing park transformation on A, B phase current according to a voltage vector angle theta to obtain a stator current active component Id and a stator current reactive component Iq of A, B phase current; the output voltage vector acquisition module is used for carrying out low-pass filtering on the stator current reactive component Iq to obtain a steady-state component Iqf of the stator current reactive component Iq, obtaining a fluctuation component by subtracting the stator current reactive component Iq and the steady-state component Iqf, sending the fluctuation component to the PI regulator to generate a voltage fine adjustment quantity Uq, determining the current output voltage Ud according to a V/F curve, and obtaining a current output voltage vector < Ud, Uq >; and the modulation wave generation module is used for carrying out inv-park conversion on the output voltage vector < Ud, Uq > according to the rotation vector angle theta r to obtain < U alpha, U beta > which is input into the SVM to generate the required modulation wave.

The suppression system of the embodiment extracts the reactive current of the stator by collecting the phase current of the stator, obtains the fluctuation component of the stator after low-pass filtering, increases the fine adjustment quantity to the known stator voltage vector in the vertical direction through the PI regulator, and simultaneously adjusts the amplitude and the phase of the stator voltage vector to stabilize the system, thereby achieving the purpose of suppressing the torque fluctuation and improving the stability of the system; the motor is simple and easy to operate, and can inhibit open-loop v/f to control no-load or light-load motor oscillation without depending on motor parameters, thereby ensuring that the motor can stably run under light load in the whole frequency band.

As can be seen from the above, in the present embodiment, A, B phase currents of the motor stator can be collected by a hall sensor sampling manner, and a voltage signal obtained from the hall sensor is amplified and then input to the AD module of the microprocessor. The amplification circuit of the voltage signal obtained from the hall sensor should have the following characteristics: low drift and high stability; strong anti-interference and low noise; a proper passband is provided, and higher gain is provided in the passband; the linearity is good, the waveform of the output signal is not distorted, and the signal can be effectively amplified; the high input impedance can absorb the signal source to the maximum, and the low output impedance makes the circuit performance reach the optimum.

In this embodiment, as shown in fig. 4, the stator current component obtaining module preferably includes MOS transistors J1A, J1B, J2A, J2B, J3A, and J3B, operational amplifiers U1 to U3, resistors Ra, Rb, Rx, R1 to R16, and capacitors Cx and C1 to C11, and is configured to amplify a differential voltage signal output by a hall sensor sampling method of phase current. Specifically, a phase current outputs a differential voltage signal to the gates of the MOS tubes J1 and J1 in a sampling mode through the Hall sensor, a positive power supply is grounded through resistors R and R in sequence, the common end of the resistors R and R is simultaneously connected with the in-phase end of the operational amplifier U and the in-phase end of the operational amplifier U, capacitors C and C are both connected with the resistor R in parallel, the positive power supply is connected with the output end of the operational amplifier U through the resistor R and the MOS tube J3, the resistor R, the MOS tube J2, the MOS tube J1 and the resistor R in sequence, the positive power supply is connected with the output end of the operational amplifier U through the resistor R and the MOS tube J3, the resistor R and the MOS tube J2, the gate of the MOS tube J3 is connected with the common end of the resistor R and the drain of the MOS tube J2 is connected with the drain of the MOS tube J2 through the resistor Rx and the drain of the capacitor Cx in sequence, the gate of MOS transistor J2A is connected to the source of MOS transistor J1A, the gate of MOS transistor J2B is connected to the source of MOS transistor J1B, the source of MOS transistor J1A is also connected to the source of MOS transistor J1B via resistor R1, the gate of MOS transistor J1A is also grounded via resistor Ra, and the gate of MOS transistor J1B is also grounded via resistor Rb. The common end of the MOS tube J2A and the resistor R4 is further sequentially grounded through a resistor R6 and a capacitor C6, the common end of the resistor R6 and the capacitor C6 is connected with the inverting end of the operational amplifier U1, the inverting end of the operational amplifier U1 is further sequentially connected with the output end of the operational amplifier U1 through a resistor R11 and a capacitor C8 which are connected in series, the common end of the MOS tube J2B and the resistor R5 is further sequentially grounded through a resistor R7 and a capacitor C7, the common end of the resistor R7 and the capacitor C7 is connected with the inverting end of the operational amplifier U2, and the inverting end of the operational amplifier U2 is further sequentially connected with the output end of the operational amplifier U2 through a resistor R12 and a capacitor C5 which are connected in series. The output end of the operational amplifier U1 is further connected with the in-phase end of the operational amplifier U3 through a resistor R13, the in-phase end of the operational amplifier U3 is further connected with the output end of the operational amplifier U3 through a resistor R15, a capacitor C10 is connected with the resistor R15 in parallel, the output end of the operational amplifier U2 is further connected with the inverting end of the operational amplifier U3 through a resistor R14, the inverting end of the operational amplifier U3 is further grounded through a resistor R16 and a capacitor C11 which are connected in parallel, and the output of the operational amplifier U3 is used for AD conversion of a later stage.

In this embodiment, J1A, J1B, J2A and J2B together form an input differential pair, and J3A and J3B form an adjustable self-bias constant current source to provide bias current for the differential pair. Resistors Ra and Rb are two large resistors to stabilize the bias voltage at the input terminal. The potentials of the same-phase ends of the operational amplifier U1 and the U2 are the same, so that the potentials of the opposite-phase ends of the U1 and the U2 are also the same, so that the potentials of the resistors R4 and R5 are the same, namely the U1 and the U2 play a role in potential clamping, and the voltages of the two sides of the differential pair are stable. U1 and U2 are provided with phase compensation circuits inside, which can prevent oscillation and adjust the internal signal of the circuit under the condition of using the amplifier alone, and maintain the stable operation of the circuit. However, the external circuit with voltage gain may cause unstable operation of the whole circuit. When a circuit with voltage gain is input to the operational amplifier, the stability of the circuit may be deteriorated or even oscillation may occur due to the negative feedback applied. In order to ensure the stability of the whole circuit, a phase compensation circuit is added, and an RC phase compensation circuit is added between two drains of the differential pair J2A and J2B, and the RC phase compensation circuit is formed by connecting Rx and Cx in series. When the frequency range of the input is high, the RC phase compensation circuit can attenuate the output signals of the differential pair, so that the input signals of U1 and U2 are attenuated, the total gain of the circuit is reduced, and the stability of the circuit is improved. R6, C6, R7 and C7 are low pass filters before the inputs of U1 and U2 to cut off the high frequency signals output by the differential pair from flowing into the operational amplifiers U1 and U2, but their cut-off frequency cannot be too low, which would otherwise limit the frequency bandwidth of the amplifying circuit. The input voltage signal is input to the operational amplifiers U1, U2 through a differential pair. The output signals of U1 and U2 are fed back to the sources of the differential pair J1A and J1B through resistors R2 and R3, the magnitude of Vgs is changed, the net input signal is reduced, and a voltage negative feedback circuit is formed. Since the differential pair J1A, J1B has nonlinear characteristics, the output signal is easily distorted, and by introducing negative feedback, such distortion can be reduced. The transmission function of the feedback circuit is reduced along with the change of the transistor parameters due to feedback, so that the gain is more stable, and the voltage gain sensitivity of the circuit is improved. Setting R13-R15-R14-R16 makes U3 constitute a differential amplifier circuit with an amplification factor of 1, so that common-mode signals at the output ends of U1 and U2 can be suppressed, and the output signals at the two ends of U1 and U2 are changed into single-ended signals to be output. Therefore, when the signals output by the U1 and the U2 contain common-mode signals, the common-mode signals are inhibited by the amplifying circuit; when the output signal is a differential mode signal, the two differential mode signals are superposed into one signal to be output through the amplifying circuit.

In this embodiment, the above circuit has a higher voltage gain and well suppresses noise, and the gain of the circuit needs to be further increased to obtain a lower output impedance and have as small power consumption as possible, for this reason, as shown in fig. 5, the stator current component obtaining module of this embodiment further includes MOS transistors J4A and J5B, resistors R17 to R22, a capacitor C12, and an operational amplifier U4. MOS tubes J4A and J5B, resistors R17-R22, a capacitor C12 and an operational amplifier U4 are connected between the circuit and the later stage AD conversion. The output end of the operational amplifier U3 is connected with the grid electrode of the MOS tube J4A, the positive power supply is connected with the drain electrode of the MOS tube J4A through a resistor R17, and is connected with the drain electrode of the MOS tube J5B through a resistor R18, the drain electrode of the MOS tube J4A is further connected with the drain electrode of the MOS tube J5B through a capacitor C12 and a resistor R19 which are connected in series in sequence, the common end of the source electrode of the MOS tube J4A and the source electrode of the MOS tube J5B is connected with the negative power supply through a resistor R20, the drain electrode of the MOS tube J4A is further connected with the same-phase end of the operational amplifier U4, the drain electrode of the MOS tube J5B is further connected with the inverting end of the operational amplifier U4, the output end of the operational amplifier U4 is grounded through resistors R21 and R22 in sequence, the common end of the resistors R21 and R22 is connected with. This further increases the gain of the circuit, resulting in a lower output impedance and at the same time a power consumption as low as possible.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.