阅读说明：本技术 用于自测试模式中止电路的设备及方法 (Apparatus and method for self-test mode abort circuit ) 是由 藤原敬典 于 2021-02-04 设计创作，主要内容包括：本发明涉及用于自测试模式中止电路的设备、系统及方法。存储器装置可进入自测试模式且对所述存储器阵列执行测试操作。在所述自测试模式期间,所述存储器装置可忽略外部通信。所述存储器包含中止电路,其可在所述自测试模式无法正确结束的情况下终止所述自测试模式。举例来说,所述中止电路可对自所述自测试模式开始以来的时间量进行计数,并且在所述时间量达到或超过阈值的情况下结束所述自测试模式,所述阈值可基于完成所述测试操作所需的预期时间量。(The invention relates to an apparatus, system, and method for self-test mode abort circuits. The memory device may enter a self-test mode and perform a test operation on the memory array. During the self-test mode, the memory device may ignore external communications. The memory includes an abort circuit that can terminate the self-test mode if the self-test mode fails to end properly. For example, the abort circuit may count an amount of time since the self-test mode started and end the self-test mode if the amount of time meets or exceeds a threshold, which may be based on an expected amount of time needed to complete the test operation.)

1. An apparatus, comprising:

command/address circuitry configured to provide a self-test enable signal at a valid level during a self-test mode;

a clock circuit configured to provide a self-test clock signal;

a self-test circuit configured to perform a test operation on a memory array in response to the self-test enable signal being at an active level; and

a suspend circuit configured to change a count value in response to the self-test clock and provide a suspend signal when the count value matches or exceeds a threshold, wherein the command/address circuit is configured to stop providing the self-test enable signal at the active level in response to the suspend signal.

2. The apparatus of claim 1, wherein the clock circuit is further configured to provide the self-test clock signal in response to the self-test enable signal being at the active level.

3. The apparatus of claim 1, wherein the command/address circuit is further configured to ignore external commands when the self-test enable signal is at the active level.

4. The apparatus of claim 1, wherein the threshold is based on an expected completion time of the self-test pattern.

5. The apparatus of claim 1, wherein the abort circuit includes a counter configured to increment the count value in response to each rising edge of the BIST clock signal.

6. The apparatus of claim 5, wherein the counter is configured to reset the count value in response to the self-test enable signal becoming invalid.

7. The apparatus of claim 1, wherein said self-test circuit is configured to provide a self-test end signal at an active level upon completion of said test operation, and wherein said C/a logic is configured to provide said self-test enable signal at an inactive level in response to said self-test end signal at said active level.

8. A method, comprising:

entering a self-test mode of the memory device and activating a self-test enable signal;

counting a number of times a test clock is provided during the self-test mode; and

ending the first test mode in response to the count value reaching or exceeding a threshold.

9. The method of claim 8, further comprising:

performing a test operation on a memory array of the memory device during the self-test mode; and

ending the self-test mode upon completion of the test operation.

10. The method of claim 9, further comprising:

loading instructions into self-test circuitry of the memory device, wherein the test operation is performed based on the load instructions.

11. The method of claim 8, further comprising providing the test clock in response to the self-test enable signal activating.

12. The method of claim 8, further comprising determining a value of the threshold based on an expected duration of test operation during the self-test mode.

13. The method of claim 8, further comprising ignoring external commands to the memory device when the self-test enable signal is active.

14. An apparatus, comprising:

a memory array; and

an interface die configured to enter a self-test mode and perform at least one test operation on the memory array, wherein the interface die is configured to exit the self-test mode after entering the self-test mode for a first amount of time, provided that the self-test mode has not ended before the first amount of time has elapsed.

15. The apparatus of claim 14, wherein said self-test pattern is expected to end after a second amount of time that is shorter than said first amount of time.

16. The apparatus of claim 15, wherein the first amount of time is based on the second amount of time.

17. The apparatus of claim 14, wherein a self-test clock is provided during said self-test mode.

18. The apparatus of claim 17, wherein the interface die includes an abort counter configured to count the self-test clock.

19. The apparatus of claim 18, wherein said self-test mode ends when said abort counter reaches a threshold.

20. The apparatus of claim 14, wherein the interface die is configured to ignore external commands during the self-test mode.

Technical Field

The present disclosure relates generally to semiconductor devices, such as semiconductor memory devices.

Background

The semiconductor device may include various circuits, and may generally receive an instruction loaded from outside the semiconductor device. These instructions may be loaded into self-test circuitry that may execute the instructions to execute a sequence of commands on a semiconductor device.

The self-test circuit may execute instructions to perform one or more test operations while the device is in a self-test mode. During self-test mode, to prevent interference, the device may ignore other data and/or commands received by the device. It may be useful to ensure that the self-test mode terminates properly to prevent the device from ignoring external communications indefinitely.

Disclosure of Invention

In one aspect, the invention relates to an apparatus comprising: command/address circuitry configured to provide a self-test enable signal at a valid level during a self-test mode; a clock circuit configured to provide a self-test clock signal; a self-test circuit configured to perform a test operation on a memory array in response to the self-test enable signal being at an active level; and an abort circuit configured to change a count value in response to the self-test clock and provide an abort signal when the count value matches or exceeds a threshold, wherein the command/address circuit is configured to stop providing the self-test enable signal at the active level in response to the abort signal.

In another aspect, the invention relates to a method comprising: entering a self-test mode of the memory device and activating a self-test enable signal; counting a number of times a test clock is provided during the self-test mode; and ending the first test mode in response to the count value reaching or exceeding a threshold.

In another aspect, the invention relates to an apparatus comprising: a memory array; and an interface die configured to enter a self-test mode and perform at least one test operation on the memory array, wherein the interface die is configured to exit the self-test mode after entering the self-test mode for a first amount of time, provided that the self-test mode has not ended before the first amount of time has elapsed.

Drawings

Fig. 1 is a cross-section of a System In Package (SiP) device according to some embodiments of the invention.

FIG. 2 is a block diagram of a memory device according to an embodiment of the invention.

FIG. 3 is a block diagram of a test and abort circuit in accordance with some embodiments of the invention.

Fig. 4 is a timing diagram of signals during a test operation in which an end-of-test signal is correctly provided, according to some embodiments of the invention.

Fig. 5 is a timing diagram of signals during a test operation in which an end-of-test signal is not properly provided, according to some embodiments of the invention.

FIG. 6 is a flow diagram of a method of aborting a test operation according to some embodiments of the invention.

Detailed Description

The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the invention or its application or uses. In the following detailed description of embodiments of the present systems and methods, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, and it is to be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Furthermore, for the purpose of clarity, detailed descriptions of certain features will not be discussed in order not to obscure the description of the embodiments of the invention, as will be apparent to those skilled in the art. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.

A memory device includes a number, typically a large number, of memory cells arranged in a memory array at intersections of word lines (rows) and bit lines (columns). The memory device may also include a built-in self-test (BIST) circuit that may be used to check the operation of one or more of the memory cells in the memory array. The BIST circuit may be preloaded with instructions for test operations that may be executed as part of a self-test pattern. In an example test operation, the BIST may write test data to one or more memory cells and then read test data back from the memory cells. The BIST may compare the read test data to the original data written to the cell and generate a result based on the comparison (e.g., report an error if the read test data does not match the write test data).

During the self-test mode, the BIST circuit may typically perform a large number of individual test operations (e.g., a large number of sequential read and write operations). To prevent interference with the test operation, the memory may ignore external communications during the self-test mode. For example, when the internal self-test enable signal is active, the memory device may ignore commands and/or data received at external terminals of the memory device. During the normal self-test mode, the BIST may perform a test operation based on instructions loaded in the BIST circuit, and once the final instructions are complete, a self-test end signal may be provided indicating that the test operation has been completed. The self-test end signal can cause the BIST enable signal to deactivate, indicating that the self-test pattern has ended and external communication is again allowed. However, some errors may cause one or more of the normal operations of the self-test mode to fail, which may cause the memory device to 'hang' or 'lock', which may prevent the memory device from completing the final test operation or provide a self-test end signal. Since the device will continue to ignore external commands in this state, it may be useful to have a stand-alone method of terminating the self-test mode in case of an error.

The invention relates to an apparatus, system, and method for self-test mode abort circuits. When the memory device enters a self-test mode, it may generate an internal BIST enable signal. The BIST circuit may begin a test operation while the BIST enable signal is asserted. The memory may also include an abort circuit that is separate from the BIST circuit. The abort circuit can determine whether the self-test pattern failed to terminate properly, and can provide an abort signal that can cause the device to deactivate the BIST enable signal, thereby ending the self-test pattern and allowing external communication. For example, the abort circuit may count the amount of time (e.g., number of clock cycles) since the start of the self-test and may send an abort signal once the amount of time reaches a threshold (which is longer than the expected length of test operation during normal self-test mode).

Fig. 1 is a cross-section of a System In Package (SiP) device according to some embodiments of the invention. The SiP device 100 includes a memory device 102 and a processor 110, which are packaged together with an interposer 112 on a package substrate 114. The memory device 102 may include self-test circuitry, such as BIST circuitry, for performing testing of the memory device 102.

The memory device 102 shown in the example of fig. 1 may be a high bandwidth storage (HBM) device that includes an interface die (or logic die) 104 and one or more memory core dies 106 stacked on the interface die 104. The memory device 102 includes one or more through-silicon vias (TSVs) 108 for coupling the interface die 104 and the core die 106. The processor 110 may act as a host device for the SiP 100.

Both the processor 110 and the memory device 102 are coupled to an interposer 112 through a number of microbumps 111. Some of the micro-bumps 111 coupled to the processor 110 may be coupled to respective ones of the micro-bumps 111 coupled to the memory device 102 by the vias 105 of the interposer 112 to form an interface between the memory device 102 and the processor 110. The interposer 112 may be coupled to the package substrate by one or more bumps, such as C4 bumps 113. The package substrate 114 includes bumps 115, some of which are coupled to the processor 110 and some of which are coupled to the memory device 102. Direct Access (DA) bumps 116 are coupled to the interface die 104 through the package substrate 114 and the interposer 112.

The direct access bumps 116 (e.g., the portions of the bumps 115 coupled to the interface die 104) may be organized into probe pads. In some embodiments, an external device, such as a tester, may be coupled to the probe pads in order to send and receive signals related to test operations to and from the memory device 102, without the signals needing to be passed to the processor 110. The tester may provide one or more instructions to the self-test circuitry of the memory device 102. In some embodiments, a tester may be coupled to processor 110, and processor 110 may pass instructions to a self-test circuit. In some embodiments, the processor 110 may generate and load instructions into the memory device 102.

Although a particular layout of the memory device 102 is described herein (e.g., having an interface die 104 and a plurality of stacked core dies 106), it should be understood that any layout of a memory device may be used as part of the present invention. For example, in some embodiments, the memory device may be a single die that includes components of the interface die 104 and the memory die 106. In some embodiments, the memory array may be located on an interface die. In some embodiments, the memory devices may not be stacked. In some embodiments, components such as interposer 112 and package substrate 114 may be omitted, and the memory device may not be a SiP device.

FIG. 2 is a block diagram of a memory device according to an embodiment of the invention. In some embodiments, memory device 200 may be included in memory device 102 of FIG. 1.

Similar to the memory device shown in fig. 1, the memory device 200 may be an HBM device having an interface die 204 and one or more core dies 206. For clarity, only a single core die 206 is shown in fig. 2, however it is understood that multiple core dies 206 may be coupled to the interface die 204 (e.g., there may be 3 or 7 core dies 206). Each core die may include a memory array including a number of memory cells. The interface die 204 may generally serve as an interface to write data to or retrieve data from the memory array of the core die 206. The interface die 204 may also be used to perform various other operations, such as refreshing memory cells in the core die 206 and/or performing test operations as part of a self-test mode.

To highlight the operation of the self-test program, only certain components of the interface die 204 that are involved in the testing process are shown. It should be understood that other components of interface die 204 not shown may be involved in various operations. For example, various components are shown coupled via multiplexers to represent signals that may be routed along different signaling paths. For clarity, the signals controlling these multiplexers, as well as the logic circuitry controlling this routing, are not shown. Similarly, certain connections may be omitted for clarity (e.g., P1500 pad 220 and/or direct access pad 216 may access C/a circuitry 207).

The memory device 200 includes three different interface terminals, namely a local microbump (uBump)205, a Direct Access (DA) uBump 216, and a test interface uBump 220, for accessing a core die 206 and/or one or more circuits of the memory. The test interface uBumps 220 may be part of a particular interface protocol, such as an IEEE 1500 interface (also referred to as a P1500 interface). In general, test interface ubumbs 220 may be referred to as P1500 ubumbs 220 (as well as related P1500 operating modes, P1500 circuits, etc.), however, it should be understood that other test interface protocols may be used in other example embodiments.

The device may have multiple operating modes that may determine which, if any, of the external terminals 205, 216 and/or 220 the memory device 200 is communicating through. For example, after reset, the memory may enter a 'native mode of operation' in which communications are sent and received through the native interface 205. Memory 200 may receive commands that may place memory 200 in a Direct Access (DA) mode, where memory 200 may typically communicate through DA terminals 216. During the direct access mode, the circuitry of the interface die 204 may typically be bypassed so that signals may be sent directly to the one or more core dies 206. The memory may receive a command to place it in the P1500 mode, where communications may be sent and received through the P1500 terminal 220. The P1500 mode may be used to program the BIST sequencer 228 and/or retrieve data from the BIST logic 225.

In a native mode of operation, the logic die may send and receive information over the native ubmps 205. In some embodiments, these native ubmps 205 may be included in the ubmps 111 of fig. 1. The native ubmps 205 may be coupled to a processor (e.g., the processor 110 of fig. 1) via one or more channels (e.g., 105 of fig. 1). The processor may access information in core die 206 (e.g., to perform read or write operations) by sending and receiving information through native ubmps 205. The memory may include command/address logic (C/a logic) 207 that receives raw signals from the native ubmps 205 and then operates the memory 200 based on the signals. For example, the C/a logic 207 may include a command and address decoder that may generate one or more internal command signals and/or addresses for directing operations to particular memory cells. The processor may also use the native ubmps 205 to perform one or more other operations of the memory device 200, such as initiating a refresh mode or a self-test mode of the memory device 200.

In an example access operation that is part of the native mode, a signal may be received at the native ubmps 205 requesting an access operation, such as a read operation of memory cells of one or more of the core dies 206. Based on the received signals, the C/a logic may provide command instructions indicating a read operation and an address specifying a memory cell to be read, and may be received at the native ubmps 205 as part of a data packet referred to as an 'atomic'. The AWORD may contain address information that may indicate which memory cells are to be read. For example, each of the core dies 206 may contain a memory array, which may include memory cells arranged at the intersections of rows (word lines) and columns (bit lines). The AWORD may contain address information, such as row and column addresses, that specify memory cells at the intersection of one or more rows and columns. The AWORD may also contain additional address information, such as a bank address, an address of a particular core die 206, and so on. The AWORD may also contain command information, such as a clock signal for timing of operations and commands indicating whether read or write operations are being performed. In response to address information during a read command, core chip 206 may respond by: the DWORD may be provided to the native uBumps 205 by reading data from the memory cells specified by the address information and then providing the data as part of the DWORD.

In another example operation of a native mode, information may be received at the native ubmps 205 requesting an access operation, such as a write operation, to certain memory cells of one or more of the core dies 206. The C/a circuit 207 may provide an AWORD that specifies a write operation and includes address information for the memory cell to be written, and a DWORD that contains the data to be written. The AWORD and DWORD may be provided to core chip 206, which may write the information contained in DWORD to the memory location specified by the address information in AWORD.

In some embodiments, the interface die 204 may include a serializer circuit 233 along a path that couples a DWORD off one of the core dies 206 to the native ubumbs 205. In such embodiments, the number of connections between the interface die 204 and the core die 206 may be much larger than the native ubumbs 205. Serializer circuitry 233 may receive information in parallel along a first number of data lines (e.g., from core 206) and then provide the information in serial along a second number of data lines less than the first number (e.g., to native ubumbs 205).

In some cases, it may be desirable to place the memory device 200 in a self-test mode in order to determine one or more characteristics of the memory device 200. Device 200 may include a BIST circuit 225 that may be used to perform test operations as part of a self-test pattern. The memory 200 may also include a direct test mode, where test operations are generated by an external device (e.g., a tester) and are conducted directly on the core die 206 through the DA terminals 216.

The P1500 ubumbs 220 are coupled to a test interface circuit (e.g., P1500 circuit) 224, which can interpret signals sent and received using the P1500 signaling protocol. For example, the P1500 circuitry 224 may translate signals received at the P1500 uBump into signals that may be used by other circuitry of the memory device 200, and vice versa. In the P1500 mode of operation, the memory device 200 may receive signals through the P1500 uBumps 220 and provide the signals to the P1500 circuitry 224. Similarly, signals from the memory device 200 may be provided to the P1500 circuit 224, which may then send the signals out of the memory device via the P1500 uBumps 220.

The BIST circuit 225 may include a BIST sequencer 228, which may be programmed with one or more test instructions. For example, BIST sequencer 228 may include an Algorithmic Pattern Generator (APG) that may generate test commands from test instructions during a self-test pattern. For example, the BIST sequencer 228 may be loaded with instructions that cause the BIST sequencer 228 to generate a write command to a first address, wait a set amount of time, then increment the address by 1, and continue in that manner until the maximum value of the address has been reached. As part of the P1500 mode of operation, test instructions may be programmed into the BIST sequencer 228 through the P1500 terminal 220.

The BIST sequencer 228 may also generate a sequence of test data (e.g., a string of logic bits) to write to the memory cells of the core die 206. The BIST sequencer 228 may include several registers that may be used to store the addresses of the memory cells to be tested as well as the test sequence. Because space in the BIST sequencer 228 may be limited, test sequences and/or addresses may be generated within the BIST sequencer 228 based on instructions. For example, the BIST sequencer 228 may perform a test on a certain address value, increment the address value by 1, and then perform the test again. In some embodiments, to save space in the BIST sequencer 228, the BIST sequencer 228 may load test sequences into a lookup table, such as a Data Topology (DTOPO) circuit 230. Each entry in the DTOPO circuit 230 can be associated with a pointer value (e.g., an index value), and the BIST sequencer 228 can generate a sequence of pointer values in a manner similar to an address.

The memory device 200 may enter a self-test mode during which the BIST circuit 225 may perform test operations (e.g., read and write test operations) on the core chip 206 based on previously loaded instructions. For example, the memory may receive an external command (e.g., via the local terminal 205 and/or the P1500 terminal) that causes the memory to enter a self-test mode. The memory device 200 may provide a self-test enable signal BISTE at an active level when in a self-test mode. In some embodiments, memory 200 may be placed in self-test mode by a command received via local terminal 205. In some embodiments, memory 200 may be placed in self-test mode by a command received via P1500 terminal 220. When in self-test mode, BIST circuit 225 may perform test operations based on instructions in BIST sequencer 228.

During an example write test operation, the BIST sequencer 228 may provide address information (e.g., one or more row and column addresses) and a test sequence (e.g., data to be written to the memory cells specified by the address information) to the input buffer 234. In some embodiments, BIST sequencer 228 may provide address information to input buffer 234 and may provide index information to DTOPO circuit 230, and DTOPO circuit 230 may provide test sequences to input buffer 234.

The input buffer circuitry 234 may be a register that may store values and then write them to the core die 206. The input buffer circuit 234 may operate as a first-in-first-out (FIFO) circuit and may be referred to as a write FIFO (wfifo) circuit 234. Based on the address information provided from WFIFO 234, a test sequence may be written to the memory location specified by the address information.

During an example read test operation, the BIST sequencer 228 may provide address information to retrieve test sequences previously stored in the core die 206. Information can be read out from the memory cell specified by the address information to the output buffer circuit 235. The output buffer circuitry 235 may generally be similar to the input buffer 234, except that the output buffer 235 receives information from the core chip 206 and then provides it to other circuitry of the interface chip 204. Output buffer 235 may be a read fifo (rfifo) circuit 235.

An error trapping memory (ECM) circuit 232 may be used to generate result information based on the read test sequence. The ECM circuit 232 may be coupled to the address information and test sequence provided to the input buffer 234 and further includes one or more registers for storing the write test sequence and address information regarding which memory cell the test sequence is written to. When performing a read operation, the ECM circuit 232 may compare the read test sequence from the output buffer 235 to a test sequence written to the memory cells as part of an earlier write operation, and may generate result information based on the comparison. The ECM circuitry 232 may then provide the result information (e.g., which memory cells failed, as part of what test, etc.) to the P1500 circuitry 224, which the P1500 circuitry 224 may then provide from memory via the P1500 uBumps.

To prevent interference with the test operation when the device is in the self-test mode (e.g., when the BIStin signal is active), memory 200 may ignore communications along input terminals 205, 216, and 220. When the BIST circuit 225 completes performing test operations and is ready to provide results from the ECM circuit 232, the BIST circuit 225 may signal that it has completed. Memory 200 may then exit self-test mode (e.g., by returning signal BISTING to an inactive level). As described in more detail herein, memory 200 may also include abort circuit 226, which may be used independently to exit memory 200 from self-test mode. For example, ABORT circuit 226 may track the amount of time memory 200 has been in self-test mode and may provide signal ABORT when the time exceeds a threshold. In response to signal ABORT, memory 200 may exit self-test mode. In some embodiments, if the signal ABORT is used, an error report may be generated.

In addition to the native mode and the P1500 mode, the memory device 200 may enter the DA mode. In some scenarios, it may be desirable to bypass other components of the SiP package (e.g., such as the processor 110 of fig. 1) to send and receive signals directly from the memory device 200. When the device is in one of the DA modes, signals may be sent and received along the DA ubmps 216 that may bypass other components of the SiP to allow external devices (e.g., tester circuits, probes) to send and receive signals directly from the memory device 200. This may involve activating a DA enable signal. For example, one of the DA uBumps 216 may be used as a DA enable pin, and when a DA enable signal, such as a logic high, is received at the DA enable pin, the memory may transition to DA1500 mode. In the DA direct mode, the memory device 200 may operate in a manner similar to the native mode, except that information is provided along the DA uBumps 216 instead of the native uBumps 205.

For example, in DA direct mode, DA uBumps 216 may receive (and/or provide) AWORD and DWORD in a manner similar to native mode. In some embodiments, DA ubmps 216 may be less than native ubmps 205. To simulate the operation of signals along the native ubmps 205, an deserializer circuit 222 may be used. The deserializer circuit 222 may receive an AWORD and a DWORD from the DA uBumps 216, then split the received serial data into a number of parallel channels. In some embodiments, the deserializer circuit 222 may partition the AWORD and DWORD into a number of parallel channels to simulate the number of channels along which the AWORD and DWORD are received by the native uBumps 205.

In DA direct mode, the AWORD and DWORD may be received at the DA uBumps 216, provided to the deserializer circuit 222, and then provided to the core die 206. Similarly, in the DA direct mode, the AWORD and DWORD may be provided from the mandrel 206 to the DA uBumps. In this manner, when in DA direct mode, the memory device 200 may operate with DA uBumps in a manner similar to the manner in which the memory 200 would operate with native uBumps 205 in native mode.

FIG. 3 is a block diagram of a test and abort circuit in accordance with some embodiments of the invention. FIG. 3 shows a portion 300 of a memory device, which in some embodiments may be included in the interface chip 104 of FIG. 1 and/or the memory device 200 of FIG. 2. Portion 300 is a simplified view of circuitry and signals that may be used to activate and deactivate self-test mode. Certain components and operations described in fig. 1-2 have been omitted from fig. 3 for clarity.

Section 300 includes BIST logic 304. The BIST logic circuit 304 may include various components for performing test operations. In some embodiments, the BIST logic circuit 304 may be included in the BIST circuit 225 of FIG. 2. When the BIST logic circuit 304 receives the enable signal BIST at an active level (e.g., a high logic level), the BIST logic circuit 304 may perform a test operation. For example, the BIST logic circuit 304 may be programmed to write one or more data patterns to various memory cells, read data from the memory cells, and compare the write information to the read information. This process can be relatively time consuming. For example, the test operation may take about 10 seconds. In other examples, other lengths of test operations may be used.

Portion 300 includes C/a logic 302. The C/A logic circuit 302 may represent various circuits of the memory involved in the timing and operation of the memory. For example, the C/A logic circuit 302 may include input/output circuitry, control logic, refresh circuitry, and the like. The C/a logic 302 receives external commands, such as through one or more external terminals (e.g., through the local terminal 205 of fig. 2 and/or the P1500 terminal 220 of fig. 2). The C/a logic circuit 302 may receive an external command or otherwise determine that the memory 300 should enter a self-test mode. To indicate the start of the self-test mode, the C/A logic circuit 302 may begin providing the BIST enable signal BIST at the active level.

To prevent interference with the test operation, C/A logic circuit 302 may ignore external commands when enable signal BISTEN is active. For example, C/A logic circuit 302 may receive a first external command instructing it to start a self-test mode. C/a logic circuit 302 may begin providing signal BISTEn at an active level. When BISTING is at an active level, the C/A logic circuit 302 may receive a second external command (e.g., to read data from one or more memory cells). However, since signal BISTEN is active, C/A logic 302 may ignore the second external command.

Portion 300 may also include clock circuit 308. Clock circuit 308 may provide the BIST clock signal BIST _ CLK. In some embodiments, the clock signal BIST _ CLK may be based on a system clock, such as the clock CLK of the memory device. The clock signal BIST CLK may be a periodic signal (e.g., alternating between high and low logic levels) with predictable timing. The clock signal BIST _ CLK may be used to control the timing of test operations. In some embodiments, clock circuit 308 may also receive enable signal BIST and may only provide clock signal BIST _ CLK when enable signal BIST is active.

The BIST logic 304 may be activated by the BIST enable signal BIST at an active level and, once activated, may perform a test operation. The BIST circuit 304 may be loaded with one or more test instructions. With timing based on the BIST clock BIST _ CLK, the BIST logic 304 may begin executing the instructions while the BIST enable signal BIST is at an active level. For example, the instructions may cause the BIST circuit 304 to perform test operations such as reading or writing information to the memory core dies along the command/address C/a bus. Once the BIST logic circuit 304 completes executing the stored instructions, the BIST logic circuit 304 may provide a BIST End signal BIST _ End at an active level (e.g., a high logic level). The C/a logic 302 may receive the BIST _ End signal and, in response to the BIST _ End signal being at an active level, may deactivate the BIST enable signal (e.g., by providing the signal BISTEn at a low logic level).

There may be some situations where the BIST circuit 304 cannot properly provide the End signal BIST _ End. For example, the BIST circuit 304 may encounter an internal error that causes it to 'hang' or 'freeze' when executing one or more of the lines of instructions. Since the BIST circuit 304 may provide the BIST _ End signal at an active level when it reaches the End of an instruction, it may not be able to properly provide the BIST _ End signal if the BIST circuit 304 does not reach the End of an instruction. In other examples, there may be other reasons for the BIST circuit 304 to properly provide the End signal BIST _ End.

To prevent test conditions from continuing indefinitely when BIST circuit 304 fails to properly provide the End signal BIST _ End, the memory may also include abort logic 306. The abort logic circuit 306 may represent a separate path that may be used to halt test operations in the event that the BIST logic circuit 304 fails to properly provide the End signal BIST _ End. The ABORT logic circuit 306 may use one or more conditions to determine whether the BIST logic circuit 304 failed to properly provide the End signal BIST _ End, and if so, provide the signal ABORT at the active level. In response to the signal ABORT being at an active level, the C/a logic 302 may deactivate the enable signal BISTEn, which may stop the test operation and may cause the C/a logic 302 to start receiving commands from the external terminal again.

In some embodiments, the ABORT logic circuit 306 may use the expected completion time of the test operation to determine when to provide the ABORT signal at the active level. For example, ABORT logic circuit 306 may count the time elapsed since the start of the self-test operation and provide signal ABORT at an active level once the elapsed time exceeds a threshold. The threshold may be based on an expected amount of time to perform the test operation, plus some amount of buffering time to allow for variations in the runtime of the test operation.

To track elapsed time, the abort logic circuit 306 may include a counter circuit 310, which may count time based on the BIST clock BIST _ CLK. For example, counter circuit 310 may change (e.g., increment) count value ABORT _ CNT whenever a rising edge of BIST _ CLK is received. The ABORT logic circuit 306 may include a comparator circuit 312 that compares the count value ABORT _ CNT to a Threshold value Threshold. The threshold may be stored on memory 300 (e.g., in a register of abort logic 306, in a mode register of memory 300), or may be 'hardwired' into abort logic 306. In some embodiments, the threshold value may be determined based on instructions loaded into the BIST logic circuit 304 for self-testing (e.g., based on a number of test operations). In some embodiments, the threshold may be loaded into memory with the test instruction.

When the count value ABORT CNT matches or exceeds the threshold, the signal ABORT at the active level may be provided by the comparator circuit 312. The count value may be reset (e.g., to 0) in response to the ABORT signal being at an active level (or, in some embodiments, in response to the signal BISTEn falling to an inactive level). In some embodiments, the counter may begin counting when signal BISTING becomes active. In some embodiments, the clock signal BIST _ CLK may only be provided when BIST is active, and the counter may count all rising edges of BIST _ CLK.

Fig. 4 is a timing diagram of signals during a test operation in which an end-of-test signal is correctly provided, according to some embodiments of the invention. FIG. 4 shows a timing diagram 400 of operations in a memory device, such as portion 300 of the memory device of FIG. 3. In particular, the timing diagram 400 shows the operation of the memory if the BIST circuit sends the end signal correctly.

At initial time t0, signal BISTEN rises to an active level to indicate that a test operation should begin. In the embodiment of FIG. 4, the clock signal BIST _ CLK is related to the enable signal, so shortly after t0, the clock signal BIST _ CLK begins to oscillate. In response to a rising edge of the clock signal BIST CLK, a counter in the abort circuit may be incremented. While the enable signal BIST is active, the counter may increment for each rising edge of the clock signal BIST _ CLK. Each time the counter is incremented, it may be compared to a threshold value, which in this case is a number 'N', to determine whether the ABORT signal at the active level should be provided.

At a first time t1, the test operation may End (e.g., because the BIST circuit reaches the End of its instructions) and the BIST circuit may provide the signal BIST _ End at an active level. At this point, the abort counter value is a number L that is less than the threshold count N. Thus, the signal ABORT remains at an inactive level. The signal BIST _ End being at an active level may cause the signal BISTEn to be provided at an inactive level, which in turn may reset the value of the abort counter.

Fig. 5 is a timing diagram of signals during a test operation in which an end-of-test signal is not properly provided, according to some embodiments of the invention. The timing diagram 500 of FIG. 5 may generally be similar to the timing diagram of FIG. 4, except that the BIST circuit freezes and does not properly provide the BIST _ End signal at the active level in the timing diagram of FIG. 5. For the sake of brevity, features and signals similar to those already described with respect to fig. 4 will not be described again with respect to fig. 5.

At a first time t1 (which may be the same first time t1 as the timing diagram 400 of FIG. 4), it may be expected that the test operation should have ended. However, in the timing diagram 500, the signal BIST _ End remains inactive at time t 1. Accordingly, the enable signal BIST may remain active after t1, and may continue to provide the clock signal BIST _ CLK. At a second time t2, the abort counter may reach a value N, which is the threshold of the abort logic circuit. Since the count value N matches the threshold, at time t3, the ABORT circuit may begin providing the signal ABORT at the active level. In response to the signal ABORT at the active level, the signal BIStin may be provided at the inactive level. This may reset the ABORT counter and also cause the signal ABORT to drop to an inactive level. This may end the self-test mode and reset the self-test circuit, which allows normal operation to continue even if the BIST circuit does not indicate that the test operation has completed.

FIG. 6 is a flow diagram of a method of aborting a test operation according to some embodiments of the invention. In some embodiments, the method 600 may be implemented using one or more of the circuits described in fig. 1-3.

Method 600 may generally begin at block 610, where block 610 depicts entering a self-test mode and activating a self-test enable signal. For example, the memory device may include one or more self-test circuits, such as built-in self-test (BIST) circuits (e.g., 225 of fig. 2 and/or 304 of fig. 3). In some embodiments, the memory device may receive an external command to place the device in a self-test mode. In some embodiments, the memory device may include internal logic that instructs the memory device to begin a self-test operation by entering a self-test mode. The BIST circuit may be loaded with one or more instructions, which may contain instructions for one or more test operations. During the self-test mode, the BIST circuit may perform one or more test operations based on the instructions. For example, the BIST circuit may write test data to a memory cell of the memory array, read data from the memory cell, and then compare the write data to the read data. The BIST circuit may generate a result file based on the test results.

Block 610 may generally be followed by block 620, which depicts counting a number of times a test clock is provided during self-test mode. The test clock may be used to control the timing of test operations performed as part of the self-test mode. In some embodiments, the test clock may be activated by the self-test enable signal, and the test clock may only be provided when the self-test enable signal is active. In some embodiments, the test clock may be provided without regard to the self-test enable signal. An abort circuit of a memory device (e.g., abort circuit 306 of FIG. 3) may include a counter that counts a test clock. For example, the counter may increment a count value in response to each rising edge of the clock signal. The comparator circuit may compare the count value with a threshold value each time the count value is updated.

Block 620 may generally be followed by block 630, which depicts ending the self-test mode in response to the count value exceeding the threshold. In some embodiments, the self-test mode may be ended in response to the count value reaching or exceeding a threshold value. The ABORT signal at an active level may be provided when a comparator in the ABORT circuit determines that the count value meets/exceeds a threshold. In response to the ABORT signal being at an active level, the self-test enable signal may be returned to an inactive level. In some cases, the BIST circuit may reach the end of the test operation and may provide a self-test end signal at a valid level. In response to the self-test end signal being at an active level, the self-test enable signal may be returned to an inactive level. In response to the self-test enable signal falling to an inactive level, the counter may be reset (e.g., to 0). The memory device may ignore external signals when the self-test enable signal is active. In response to the self-test enable signal becoming inactive, the memory device may again begin responding to external signals. In some embodiments, if the ABORT signal is provided at an active level (e.g., because the self-test end signal is provided at the correct time), the BIST circuit may generate an error report, such as an error code or error flag.

Of course, it should be appreciated that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and/or processes or separated and/or performed among separate devices or device portions in accordance with the present systems, devices, and methods.

Finally, the above-discussion is intended to be merely illustrative of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present system has been described in detail with reference to exemplary embodiments, it should also be appreciated that numerous modifications and alternative embodiments may be devised by those having ordinary skill in the art without departing from the broader and intended spirit and scope of the present system as set forth in the claims that follow. The specification and drawings are accordingly to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.