阅读说明：本技术 测试电路及采用该测试电路的存储芯片 (Test circuit and memory chip using the same ) 是由 王佳 张良 李红文 于 2019-10-16 设计创作，主要内容包括：本发明提供一种测试电路及存储芯片,所述测试电路用于存储器的压缩数据读取,所述测试电路包括M个存储块,所述M为大于或等于2的偶数,其中N个存储块组成一个存储组,所述N为大于或等于2且小于或等于M的偶数,所述M是所述N的整数倍,其特征在于,所述测试电路还包括：压缩数据读取单元,一个所述压缩数据读取单元对应一个所述存储组,所述压缩数据读取单元与对应的所述存储组中的所述N个存储块连接,所述压缩数据读取单元接收压缩数据读取命令和地址信息,并根据所述压缩数据读取命令和所述地址信息读取所述N个存储块中的数据。本发明的优点在于,能够既不额外增加存储芯片的尺寸又能大幅度减少测试时间。(The invention provides a test circuit and a memory chip, wherein the test circuit is used for reading compressed data of a memory, the test circuit comprises M memory blocks, M is an even number which is more than or equal to 2, N memory blocks form a memory group, N is an even number which is more than or equal to 2 and less than or equal to M, and M is an integral multiple of N, and the test circuit is characterized by further comprising: and the compressed data reading unit is connected with the N storage blocks in the corresponding storage group, receives a compressed data reading command and address information and reads data in the N storage blocks according to the compressed data reading command and the address information. The invention has the advantages that the size of the memory chip can not be additionally increased, and the test time can be greatly reduced.)

1. A test circuit for compressed data read of a memory, the test circuit comprising M memory blocks, M being an even number greater than or equal to 2, wherein N memory blocks form a memory group, N being an even number greater than or equal to 2 and less than or equal to M, M being an integer multiple of N, the test circuit further comprising:

and the compressed data reading unit is connected with the N storage blocks in the corresponding storage group, receives a compressed data reading command and address information and reads data in the N storage blocks according to the compressed data reading command and the address information.

2. The test circuit of claim 1, wherein the M memory blocks are distributed into at least one odd column and at least one even column, and wherein at least one memory block in the odd column and at least one memory block in the even column form the memory group.

3. The test circuit of claim 1, further comprising:

a test data output port connected to the compressed data read unit through a compressed data bus.

4. The test circuit of claim 3, wherein one of the test data output ports connects at least two of the compressed data read units via a compressed data bus.

5. The test circuit of claim 4, wherein the number of the test data output ports is 2, and one of the test data output ports is connected to four of the compressed data reading units via a compressed data bus.

6. The test circuit of claim 3, wherein the compressed data bus is an 8-bit bus.

7. The test circuit of claim 3, wherein M is 32 and N is 4.

8. The test circuit of claim 7, wherein the 32 memory blocks are distributed into 8 rows and 4 columns, the 4 columns are respectively an odd column one, an even column one, an odd column two, and an even column two, and one of the memory groups comprises four memory blocks distributed into 2 rows and 2 columns, the 2 columns are a combination of the odd column one and the even column one or a combination of the odd column two and the even column two, the odd column one and the even column one have four of the compressed data reading units in common, and the odd column two and the even column two have four of the compressed data reading units in common.

9. The test circuit of claim 8, wherein four packed data read cells between the odd column one and the even column one are connected by the eight bit packed data bus to one test data output port, and wherein four packed data read cells between the odd column two and the even column two are connected by the eight bit packed data bus to another test data output port.

10. A memory chip comprising a data read/write bus, further comprising the test circuit according to any one of claims 1 to 9, wherein the compressed data reading unit is disposed below the data read/write bus on the memory chip.

11. The memory chip of claim 10, wherein the data read/write bus occupies a first predetermined chip area in the memory chip, and the compressed data reading unit occupies a second predetermined chip area in the memory chip, the second predetermined area being smaller than the first predetermined area.

12. The memory chip of claim 10, wherein the projection of the compressed data read unit onto the chip substrate is overlaid by the projection of the data read/write bus onto the chip substrate.

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a test circuit and a memory chip using the same.

Background

For DRAM chips, the chip Array (Array) may have manufacturing defects, so at the test stage an engineer needs to find every defect in the Array to ensure that the defect is repaired.

Taking LPDDR4 as an example, two types of test circuits are commonly used to find defects in an array, one being the All-Bank Compression Read architecture, which has the advantage of requiring a short time to test a single DRAM chip, the disadvantage of requiring an increase in chip Size (Die Size) to house the compressed data Read circuit and 128 Lbus signal lines (signal lines dedicated to transmitting compressed data), and 4 test data output ports; the other test circuit is a One-Bank Compression Read architecture, which has the advantages that the function of compressed data reading (Compression Read) is completed by using a Gbus signal line (a signal line used for transmitting normal data of a DRAM memory array and can also be used for transmitting compressed data during compressed data reading test), the size of a chip does not need to be increased, only 1 test data output port is needed, and the defect is that the time for testing a single DRAM chip is long.

Therefore, a new test circuit is needed to overcome the above disadvantages and meet the test requirements.

Disclosure of Invention

The present invention is directed to a test circuit and a memory chip using the same, which can greatly reduce the test time without increasing the size of the memory chip.

In order to solve the above problem, the present invention provides a test circuit for compressed data reading of a memory, the test circuit including M memory blocks, where M is an even number greater than or equal to 2, N memory blocks form a memory group, N is an even number greater than or equal to 2 and less than or equal to M, and M is an integer multiple of N, the test circuit further including: and the compressed data reading unit is connected with the N storage blocks in the corresponding storage group, receives a compressed data reading command and address information and reads data in the N storage blocks according to the compressed data reading command and the address information.

Furthermore, the M storage blocks are distributed into at least one odd column and at least one even column, and at least one storage block in the odd column and at least one storage block in the even column form the storage group.

Furthermore, the test circuit also comprises a test data output port which is connected with the compressed data reading unit through a compressed data bus.

Further, one of the test data output ports is connected to at least two of the compressed data reading units through a compressed data bus.

Furthermore, the number of the test data output ports is 2, and one test data output port is connected with four compressed data reading units through a compressed data bus.

Further, the compressed data bus is an 8-bit bus.

Further, M is 32 and N is 4.

Further, the 32 storage blocks are distributed into 8 rows and 4 columns, the 4 columns are respectively an odd column one, an even column one, an odd column two and an even column two, four storage blocks included in one storage group are distributed into 2 rows and 2 columns, the 2 columns are a combination of the odd column one and the even column one or a combination of the odd column two and the even column two, four compressed data reading units are shared between the odd column one and the even column one, and four compressed data reading units are shared between the odd column two and the even column two.

Further, four packed data read units between the odd column one and the even column one are connected to one test data output port by the eight-bit packed data bus, and four packed data read units between the odd column two and the even column two are connected to the other test data output port by the eight-bit packed data bus.

The invention also provides a memory chip, which comprises a data read-write bus and the test circuit, wherein the compressed data reading unit is arranged below the data read-write bus on the memory chip.

Furthermore, the data read-write bus occupies a first preset chip area in the memory chip, the compressed data reading unit occupies a second preset chip area in the memory chip, the compressed data reading unit is arranged below the data read-write bus on the memory chip, and the second preset area is smaller than the first preset area.

Further, the projection of the compressed data reading unit on the chip substrate is covered by the projection of the data read-write bus on the chip substrate.

The test circuit of the invention enables one compressed data reading unit to correspond to a plurality of memory blocks, which can not increase the size of a memory chip additionally, but can also greatly reduce the test time.

Drawings

FIG. 1 is a block diagram of a first embodiment of a test circuit of the present invention;

FIG. 2 is a block diagram of a second embodiment of the test circuit of the present invention;

FIG. 3 is a schematic diagram of a data read/write bus and a test circuit in the memory chip of the present invention;

fig. 4 is a schematic diagram showing the relative positions of the data read-write bus and the compressed data reading unit in the direction perpendicular to the memory chip.

Detailed Description

The following describes in detail a specific embodiment of a test circuit and a memory chip using the test circuit according to the present invention with reference to the drawings.

The test circuit is used for reading compressed data of the memory. FIG. 1 is a block diagram of a first embodiment of a test circuit of the present invention. Referring to fig. 1, the test circuit includes M memory blocks 10, where M is an even number greater than or equal to 2. In this embodiment, M is 32, that is, the test circuit includes 32 memory blocks 10. In other embodiments of the present invention, the number of the memory blocks 10 may be other values. The N storage blocks 10 form a storage group 101, where N is an even number greater than or equal to 2 and less than or equal to M, and M is an integer multiple of N.

Further, the M memory blocks 10 may be distributed into at least one odd column and at least one even column. Referring to fig. 1, in the present embodiment, the M memory blocks 10 are distributed into two odd columns and two even columns, specifically, the M memory blocks 10 are distributed into an odd column a1 and an odd column two A3, an even column one B2 and an even column two B4. The odd columns and the even columns are alternately distributed, that is, the rows formed by the memory block 10 are arranged in sequence as an odd column A1, an even column B2, an odd column two A3 and an even column two B4. It is understood that, in other embodiments of the present invention, the M memory blocks 10 may also form other numbers of odd columns and even columns, respectively.

At least one memory block 10 in the odd columns and at least one memory block 10 in the even columns form the memory group 101. In this embodiment, N is 2, that is, one memory block 10 in the odd column and one memory block 10 in the even column form the memory group 101. Preferably, to facilitate the layout of the test lines, two memory blocks 10 in the memory group 101 are disposed adjacent to each other. As shown in fig. 1, two memory blocks 10 adjacent in the horizontal direction (X direction) constitute the memory group 101. In other embodiments of the present invention, N may have other values as long as M is an integer multiple of N.

The test circuit further comprises a compressed data reading unit 11. One compressed data reading unit 11 corresponds to one memory bank 101, i.e. the number of compressed data reading units 11 is the same as the number of memory banks 101. In this embodiment, the storage blocks are divided into 16 storage groups, and the number of the compressed data reading units 11 is 16.

The compressed data reading unit 11 is connected to the N storage blocks 10 in the corresponding storage group 101. In the present embodiment, the compressed data reading unit 11 is connected to one memory block 10 in the odd-numbered columns and one memory block 10 in the even-numbered columns, respectively.

The compressed data reading unit 11 receives a compressed data reading command and address information, and reads data in the N memory blocks 10 according to the compressed data reading command and the address information. Wherein the compressed data read command and the address information may be issued by a control module of a memory. The address information is used to provide the compressed data reading unit 11 with the address of the read storage block 10, and the compressed data reading unit 11 performs a reading operation on the corresponding storage block according to the address information. Specifically, if the address information corresponds to the address of the first memory block 10 of the odd column one a1, the compressed data reading unit 11 performs a read operation on the first memory block 10 of the odd column one a 1; if the address information corresponds to the address of the first memory block 10 of the even column one B2, the compressed data reading unit 11 performs a read operation on the first memory block 10 of the even column one B2.

In the test circuit of the invention, one compressed data reading unit corresponds to at least two memory blocks, compared with the prior art, the test circuit of the invention can not increase the chip size of the memory additionally, and can also greatly reduce the test time.

Further, the test circuit also includes a test data output port 12. The test data output port 12 is connected to the compressed data reading unit 11 through a compressed data bus 13. The data read by the compressed data reading unit 11 is transmitted to the test data output port 12 through the compressed data bus 13, so as to perform data acquisition and analysis. Wherein, the compressed data bus 13 is an 8-bit bus.

Further, the memory has a plurality of data input/output ports 20, and in other embodiments of the present invention, the test circuit can reuse the data input/output ports 20 of the memory as the test data output ports 12, thereby saving the wiring space and improving the integration level.

Further, one of the test data output ports 12 is connected to at least two of the compressed data reading units 11 through a compressed data bus 13. In this embodiment, the number of the test data output ports 12 is 2, and one test data output port 12 is connected to eight compressed data reading units 11 through a compressed data bus 13. Specifically, the eight compressed data reading units 11 corresponding to the odd column one A1 and the even column one B2 share the same test data output port 12, and the eight compressed data reading units 11 corresponding to the odd column two A3 and the even column two B4 share the same test data output port 12.

The present invention further provides a second embodiment of the test circuit, which is different from the first embodiment in that the memory banks include different numbers of memory blocks and compressed data reading units.

Fig. 2 is a block diagram of a second embodiment of the test circuit, please refer to fig. 2, in this second embodiment, the M is 32, that is, the test circuit includes 32 memory blocks 10, and the N is 4, that is, 4 memory blocks 10 constitute the memory group 101.

Specifically, in the second embodiment, the 32 memory blocks are distributed into 8 rows and 4 columns. The 4 rows are respectively an odd row one A1, an even row one B2, an odd row two A3 and an even row two B4. One of the memory banks 101 includes 4 memory blocks distributed in 2 rows and 2 columns, and the 2 columns are a combination of odd column one a1 and even column one B2 or a combination of odd column two A3 and even column two B4. The 2 rows are two adjacent rows, for example, four memory blocks are distributed in the first row U1 and the second row U2, or the third row U3 and the fourth row U4, or the fifth row U5 and the sixth row U6, or the seventh row U7 and the eighth row U8.

The number of the compressed data reading units 11 is 11a, 11B, 11c and 11d, and the number of the compressed data reading units 11 is 11e, 11f, 11g and 11h, respectively, between the odd column a1 and the even column B2. The compressed data reading unit 11a is connected with the memory blocks 10 of the first and second rows U1 and U2 of the odd-numbered row one A1 and the even-numbered row one B2; the compressed data reading unit 11B is connected to the storage blocks 10 of the third and fourth rows U3 and U4 of the odd column-a 1 and the even column-B2; the compressed data reading unit 11c is connected to the memory blocks 10 of the fifth row U5 and the sixth row U6 of the odd column A1 and the even column B2; the compressed data reading unit 11d is connected with the memory blocks 10 of the seventh and eighth rows U7 and U8 of the odd column-A1 and the even column-B2. The compressed data reading unit 11e is connected to the memory blocks 10 of the first and second rows U1 and U2 of the odd two A3 and even two B4 columns; the compressed data reading unit 11f is connected to the storage blocks 10 of the third row U3 and the fourth row U4 of the odd column two a3 and the even column two B4; the compressed data reading unit 11g is connected to the memory blocks 10 of the fifth row U5 and the sixth row U6 of the odd column two A3 and the even column two B4; the compressed data reading unit 11h is connected to the memory blocks 10 of the seventh and eighth rows U7 and U8 of the odd two A3 and even two B4 columns.

Further, in the second embodiment of the present invention, the number of the test data output ports 12 is 2, and one test data output port 12 is connected to four compressed data reading units through a compressed data bus 13. That is, the compressed data read unit located between the odd column one a1 and the even column one B2 is connected to the same test data output port 12 through the compressed data bus 13 of eight bits; the packed data read unit between the odd column two a3 and the even column two B4 is connected to the same test data output port 12 through the eight-bit packed data bus 13.

The following description will take an example of a memory group 101 composed of a memory block a1-UI corresponding to the odd column a1 and the first row U1, a memory block a1-U2 corresponding to the odd column a1 and the second row U2, a memory block B2-UI corresponding to the even column B2 and the first row U1, and a memory block B2-U2 corresponding to the even column B2 and the second row U2 as an example. The compressed data reading unit 11a corresponding to the storage group 101 receives a compressed data reading command and address information, wherein the address information is an address of the storage block a1-UI, and the compressed data reading unit 11a reads data in the storage block a1-UI and transmits the data to the test data output port 12 through the compressed data bus 13. Since the storage block a1-UI, the storage block a1-U2, the storage block B2-UI, and the storage block B2-U2 belong to the same storage group 101, the compressed data reading unit 11a will continue to read the data in the storage block B2-UI, the storage block a1-U2, and the storage block B2-U2 in sequence after reading the data in the storage block a1-UI, and transmit the data to the test data output port 12 in sequence through the compressed data bus 13. After all the data of the memory blocks in the memory group 101 are read, the data in the next memory group are read and transmitted.

In the present embodiment, since the compressed data reading unit between the odd column one a1 and the even column one B2 and the compressed data reading unit between the odd column two A3 and the even column two B4 are respectively connected to different test data output ports, the two can read data at the same time.

The above is only one working method of the test circuit, and other working methods can be adopted without departing from the principle of the present invention, for example, first reading the data of the memory blocks in the odd columns in the memory group, and then reading the data of the memory blocks in the even columns in the memory group.

In the second embodiment of the present invention, the test circuit achieves a better balance between the increased size of the memory, the test time and the number of the test data output ports 12, and the test circuit of the present invention can greatly reduce the test time without additionally increasing the size of the memory.

The invention also provides a memory chip. The memory chip comprises a data read-write bus and the test circuit. Fig. 3 is a schematic diagram of a data read/write bus and a test circuit in the memory chip, wherein the data read/write bus is schematically illustrated by a dotted line in fig. 3. Referring to fig. 3, in the memory chip, the compressed data reading unit 11 is disposed below the data read/write bus 30. Fig. 4 is a schematic diagram showing the relative positions of the data read/write bus and the compressed data read unit in a direction perpendicular to the memory chip. Referring to fig. 4, in a direction perpendicular to the memory chip, the compressed data reading unit 11 is located below the data read/write bus 30.

In the structure of the memory chip, the data read-write bus necessarily occupies a certain chip area, and the data read-write bus is vacant and not utilized. The memory chip of the present invention utilizes the area below the data read-write bus 30 to place the compressed data reading unit 11, thereby avoiding the compressed data reading unit 11 occupying the extra space of the memory chip and avoiding the problem of increasing the area of the memory chip due to the arrangement of the compressed data reading unit.

Further, referring to fig. 4, the data read/write bus 30 occupies a predetermined chip area of S1 in the memory chip, and the compressed data reading unit 11 occupies a predetermined chip area of two S2 in the memory chip, so that the predetermined area of two S2 is smaller than the predetermined area of one S1, thereby further preventing the compressed data reading unit from occupying additional space of the memory chip.

Further, with reference to fig. 4, the projection of the compressed data reading unit 11 on the chip substrate is covered by the projection of the data read-write bus 30 on the chip substrate, that is, the preset area two S2 of the compressed data reading unit 11 is completely located within the range of the preset chip area one S1 of the data read-write bus 30, and the compressed data reading unit does not occupy any area outside the vertical direction of the data read-write bus, so that the problem of increasing the size of the memory chip due to the arrangement of the compressed data reading unit is completely avoided.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.