Scan chain and design method thereof and serial scan reset method based on scan chain

文档序号：734106 发布日期：2021-04-20 浏览：10次中文

阅读说明：本技术 扫描链及其设计方法和基于扫描链的串行扫描复位方法 (Scan chain and design method thereof and serial scan reset method based on scan chain ) 是由刘勋张倬于 2020-11-30 设计创作，主要内容包括：本公开提供一种扫描链及其设计方法和基于扫描链的串行扫描复位方法,该方法包括：提供扫描链,扫描链包括串行级联的多个设定寄存器,其中,除扫描链的起始的设定寄存器之外的每个设定寄存器的扫描/复位输入端连接到上一相邻的设定寄存器的复位输出端；使扫描链处于扫描/复位模式,向起始的设定寄存器的扫描/复位输入端施加复位数据信号,提供时钟输入,进行串行扫描复位且使得除扫描链的起始的设定寄存器之外的每个设定寄存器的扫描/复位数据输入端被输入复位数据信号。本公开基于多个设定寄存器串行级联形成扫描链,复用扫描链进行串行扫描,将复位数据信号扫描入所有的寄存器,实现所有寄存器的复位功能,节省大量连线资源与寄存器面积。(The present disclosure provides a scan chain and a design method thereof, and a serial scan reset method based on the scan chain, the method comprising: providing a scan chain comprising a plurality of setting registers serially cascaded, wherein a scan/reset input of each setting register except a setting register at the beginning of the scan chain is connected to a reset output of a last adjacent setting register; the scan chain is put in a scan/reset mode, a reset data signal is applied to the scan/reset input terminal of the initial setting register, a clock input is provided, serial scan reset is performed and the scan/reset data input terminal of each setting register other than the initial setting register of the scan chain is inputted with a reset data signal. The method and the device have the advantages that the scan chain is formed by serially cascading a plurality of setting registers, the scan chain is multiplexed to carry out serial scanning, and the reset data signals are scanned into all the registers, so that the reset function of all the registers is realized, and a large amount of connecting line resources and the area of the registers are saved.)

1. A serial scan reset method based on a scan chain comprises the following steps:

providing a scan chain, wherein the scan chain comprises a single set-up register or comprises a plurality of set-up registers cascaded in series, any of the set-up registers comprising:

a function selection terminal configured to receive an enable signal to select the scan chain to be in a scan/reset mode or a basic operation mode by setting the enable signal;

a first input configured to receive a functional data input signal for the basic mode of operation;

a scan/reset input terminal configured to selectively receive a scan input signal for scanning or a reset data signal for resetting;

a clock input terminal configured to receive a clock input required by the setting register;

a data output configured to act as a reset output and output a reset output signal when the scan chain is in a scan/reset mode, wherein for the scan chain including a plurality of setting registers serially cascaded, comprising: the scan/reset input of each set register except the initial set register of the scan chain is operatively connected to the reset output of the last adjacent set register;

setting an enable signal of the setting register so that the scan chain is in the scan/reset mode; and is

The scan chain comprises a single setting register, a reset data signal is applied to a scan/reset input terminal of the single setting register of the scan chain, and a clock input of the single setting register is provided for serial scan reset, or the scan chain comprises a plurality of setting registers which are serially cascaded, a reset data signal is applied to a scan/reset input terminal of an initial setting register of the scan chain, a clock input of the setting register is provided for serial scan reset, and a scan/reset data input terminal of each setting register except the initial setting register of the scan chain is input with the reset data signal.

2. The serial scan reset method of claim 1, wherein,

the reset data signal is 0 or 1, and the reset output signal is 0 or 1.

3. The serial scan reset method of claim 1 or 2, comprising a plurality of set registers serially cascaded for the scan chain, further comprising:

by arranging the first phase inverter between the reset output end of one or more setting registers and the scanning/resetting input end of the corresponding next adjacent setting register, serial scanning reset is carried out in the scanning/resetting mode, and the scanning/resetting data input end of each setting register except the initial setting register of the scanning chain is input with the resetting data signal.

4. The serial scan reset method of claim 3, wherein,

the plurality of setting registers include at least one first register and/or at least one second register, wherein a reset output terminal of the reset first register outputs an inverted reset data signal, the inverted reset data signal is an inversion of the reset data signal, and a reset output terminal of the reset second register outputs the reset data signal.

5. The serial scan reset method of claim 4, wherein,

the first register includes:

a first base register, wherein the first base register includes a first base input terminal, and a scan/reset input terminal, a function selection terminal, a clock input terminal, and a reset output terminal that include the first register;

a second inverter disposed between the first base input of the first base register and the first input of the first register, wherein the output of the reset output of the first register is equal to the input of the first register and equal to the inverse of the first base input of the first base register;

the second register includes:

a second basic register, wherein the second basic register comprises a first input terminal of the second register, a scan/reset input terminal, a function selection terminal, a clock input terminal, and a reset output terminal, and an output of the reset output terminal of the second register is equal to an input of the first input terminal of the second register;

the serial scanning reset method further comprises:

by providing an odd number of the first inverters between the reset output terminal of one or more of the first registers and the scan/reset input terminal of the corresponding next adjacent setting register, respectively, and providing an even number of the first inverters between the reset output terminal of one or more of the second registers and the scan/reset input terminal of the corresponding next adjacent setting register, respectively, serial scan reset is performed in the scan/reset mode, and the scan/reset input terminal of each setting register except for the initial setting register of the scan chain is inputted with the reset data signal.

6. The serial scan reset method of claim 5, wherein,

the first base register and the second base register are D flip-flops having opposite outputs.

7. The serial scan reset method of claim 4, wherein,

the first register includes:

a first base register, wherein the first base register comprises a first base scan input and comprises a first input of the first register, a function select terminal, a clock input, and a reset output;

a second inverter interposed between the first base scan input terminal of the first base register and the scan/reset input terminal of the first register, wherein an output of the reset output terminal of the first register is equal to an input of the first input terminal of the first register;

the second register includes:

the serial scanning reset method further comprises:

by providing an odd number of the first inverters between the reset output terminals of one or more of the first registers and the scan/reset input terminals of the corresponding next adjacent setting registers, respectively, and providing an even number of the first inverters between the reset output terminals of one or more of the second registers and the scan/reset input terminals of the corresponding next adjacent setting registers, respectively, serial scan reset is performed in the scan/reset mode, and the scan/reset input terminals of each setting register except the initial setting register of the scan chain are inputted with the reset data signal.

8. The serial scan reset method of claim 7, further comprising:

the first base register and the second base register are D flip-flops having opposite outputs.

9. The serial scan reset method of any of claims 4 to 8, further comprising:

in response to the scan/reset mode, the odd number is an odd number equal to or greater than 1, and the even number is an even number equal to or greater than 0.

10. The serial scan reset method of claim 4, wherein,

applying a reset data signal to the scan chain, comprising:

a scan/reset input terminal of a setup register of a start of the scan chain receives the reset data signal output from an output terminal of an alternative multiplexer, wherein the alternative multiplexer inputs a reset data signal for reset and a scan input signal for scan, and selectively outputs the reset data signal required for responding to a reset mode in the scan/reset mode or the scan input signal required for responding to a scan mode in the scan/reset mode according to a reset control signal.

11. The serial scan reset method of claim 10, wherein,

the reset data signal output by the alternative multiplexer is a ground signal, the ground signal is 0, or the reset data signal output by the alternative multiplexer is a power signal, and the power signal is 1.

12. The serial scan reset method of any one of claims 1 to 2, 4 to 8, and 10 to 11, wherein providing the clock input of the setting register comprises:

and setting the enable signals of all the setting registers to be 1, and giving adaptive clock input according to the length of the scan chain so as to carry out serial scanning reset.

13. The serial scan reset method of claim 12, wherein,

giving an adapted clock input according to the length of the scan chain, comprising:

according to the scan chain with the length of N, the duration of enabling signals of the setting registers to be 1 is more than or equal to N clock cycles.

14. A scan chain for serial scan reset comprising a reset signal terminal and a single set register or a plurality of set registers serially cascaded, said reset signal terminal being connected to a set register at the beginning of said scan chain, wherein any of said set registers comprises:

a function selection terminal configured to receive an enable signal to select the scan chain to be in a scan/reset mode or a basic operation mode by setting the enable signal;

a first input configured to receive a functional data input signal required for the basic operating mode;

a scan/reset input terminal configured to selectively receive a scan input signal for scanning or a reset data signal for resetting;

a clock input terminal configured to receive a clock input required by the setting register;

a data output configured to act as a reset output and output a reset output signal when the scan chain is in a scan/reset mode, wherein for the scan chain including a plurality of setting registers serially cascaded, comprising: the scan/reset input end of each setting register except the initial setting register of the scan chain is connected to the reset output end of the last adjacent setting register so as to realize serial cascade connection;

wherein said scan chain includes a single set register for serial scan reset by applying a reset data signal to a scan/reset input of said single set register of said scan chain when said scan chain is in said scan/reset mode, or a plurality of set registers serially cascaded such that a scan/reset input of each set register other than an initial set register of said scan chain is input with said reset data signal during application of a reset data signal to said initial set register for said serial scan reset by said reset signal terminal when said scan chain is in said scan/reset mode.

15. The scan chain for serial scan reset of claim 14,

the reset data signal is 0 or 1, and the reset output signal is 0 or 1.

16. The scan chain for serial scan reset of claim 14 or 15,

for the scan chain comprising a plurality of setting registers in serial cascade, a first inverter is arranged between the reset output end of one or more setting registers and the scan/reset input end of the corresponding next adjacent setting register respectively, so that in the scan/reset mode, serial scan reset is carried out, and the scan/reset data input end of each setting register except the initial setting register of the scan chain is input with the reset data signal.

17. The scan chain for serial scan reset of claim 16,

18. The scan chain for serial scan reset of claim 17,

the first register includes:

the second register includes:

an odd number of the first inverters are provided between the reset output terminal of one or more of the first registers and the scan/reset input terminal of the corresponding next adjacent setting register, respectively, and an even number of the first inverters are provided between the reset output terminal of one or more of the second registers and the scan/reset input terminal of the corresponding next adjacent setting register, respectively, so that in the scan/reset mode, serial scan reset is performed, and so that the scan/reset input terminal of each setting register other than the initial setting register of the scan chain is inputted with the reset data signal.

19. The scan chain for serial scan reset of claim 17,

the first register includes:

the second register includes:

20. The scan chain for scan reset of claim 18 or 19,

the odd number is an odd number equal to or greater than 1, and the even number is an even number equal to or greater than 0.

21. The scan chain for serial scan reset of claim 18 or 19,

the reset signal end comprises an alternative multiplexer;

the output end of the alternative multiplexer is connected with the scanning/resetting input end of the initial setting register of the scanning chain, and the resetting data signal is provided for the scanning/resetting input end of the initial setting register;

the reset data signal for resetting is input to a first input terminal of the one-of-two multiplexer, and the scan input signal for scanning is input to a second input terminal of the one-of-two multiplexer.

22. The scan chain for serial scan reset of claim 21,

the initial setting register of the scan chain is the first register or the second register.

23. The scan chain for serial scan reset of claim 21,

the first input end of the alternative multiplexer is grounded or connected with a power supply.

24. A design method of a scan chain for serial scan reset comprises the following steps:

providing a single setting register or a plurality of setting registers;

the function selection end is configured to receive an enabling signal so as to select the scan chain to be in a scan/reset mode or a basic working mode by setting the enabling signal;

a first input configured to receive a functional data input signal required for the basic operating mode;

a scan/reset input terminal configured to selectively receive a scan input signal for scanning or a reset data signal for resetting;

a clock input terminal configured to receive a clock input required by the setting register;

a data output configured to serve as a reset output and output a reset output signal when the scan chain is in a scan/reset mode;

the basic register comprises a function selection end, a clock input end and a reset output end of the setting register, the basic register further comprises a first basic input end used for the basic working mode or a first input end comprising the setting register, and the basic register further comprises a first basic scanning input end used for the scanning/resetting mode or a scanning/resetting input end comprising the setting register;

for said scan chain including a plurality of setting registers, using a scan chain connection facility such that a scan/reset input of each of said setting registers except for a starting setting register of said scan chain is connected to a reset output of a last adjacent setting register to enable serial concatenation of said plurality of setting registers;

according to the time sequence requirement of the rear-end physical design, the physical position of the setting register is laid out;

checking all setting registers, wherein a single setting register is included for the scan chain such that a reset data signal is applied to the single setting register of the scan chain for the serial scan reset when the scan chain is in the scan/reset mode, or a plurality of setting registers are included for the scan chain in serial cascade such that a scan/reset input terminal in each setting register except the initial setting register of the scan chain is input with the reset data signal during the application of a reset data signal to the initial setting register of the scan chain for the serial scan reset when the scan chain is in the scan/reset mode.

25. The method for designing a scan chain of claim 24, comprising a plurality of setting registers for the scan chain, further comprising:

based on the result of the layout, the connection relationship between the reset output terminal of one of the at least two setting registers and the scan/reset input terminal of the other is adjusted so that the wire length of the scan chain is shortened.

26. The method for designing a scan chain of claim 24, comprising a plurality of setting registers for the scan chain, further comprising:

by arranging a first inverter between the reset output end of one or more setting registers and the scanning/reset input end of the corresponding next adjacent setting register, serial scanning reset is carried out in the scanning/reset mode, and the scanning/reset data input end of each setting register except the initial setting register of the scanning chain is input with the reset data signal.

27. The method for designing a scan chain of claim 26, wherein,

28. The method for designing a scan chain of claim 27, wherein,

the first register includes:

the second register includes:

the method for designing the scan chain further comprises the following steps:

29. The method for designing a scan chain of claim 27, wherein,

the first register includes:

the second register includes:

the method for designing the scan chain further comprises the following steps:

30. The method for designing a scan chain according to claim 28 or 29, further comprising:

calculating the number of the first inverters between the reset output end of any first register and the scanning/reset input end of the corresponding next adjacent setting register and recording the number as a first number, and calculating the number of the first inverters between the reset output end of any second register and the scanning/reset input end of the corresponding next adjacent setting register and recording the number as a second number;

judging whether the first number is an odd number and the second number is an even number, if so, meeting the condition of successful serial scanning reset; if not, the first inverter is arranged between the reset output end of the corresponding first register or second register and the scanning/reset input end of the next adjacent setting register, so that the first number is an odd number and the second number is an even number, and the condition of successful serial scanning reset is met.

31. The method for designing a scan chain according to claim 28 or 29, further comprising:

and verifying the correctness of serial scanning reset by verifying whether all the reset output ends of the second register output the reset data signals and all the reset output ends of the first register output inverted reset data signals which are inversions of the reset data signals.

Technical Field

The embodiment of the disclosure relates to a scan chain, a design method thereof and a serial scan reset method based on the scan chain.

Background

Design for testability (DFT) is an integrated circuit design technique that implants special structures into the circuit during the design phase for testing after the design is completed. Circuit testing is sometimes not easy because many internal node signals of the circuit are externally difficult to control and observe. By adding design for testability structures, such as scan chains, etc., internal signals can be exposed outside the circuit.

The scan chain is used as the most widely used testability design structure in the current super-large-scale integrated circuit design, so that the controllability and observability of the chip are enhanced, and good testability is provided for the chip. In general, in the design process of a semiconductor chip, not only functional circuits for realizing predetermined functions but also scan test circuits (scan chains) for testing manufacturing defects of the chip need to be designed.

In digital integrated circuits, it is generally necessary to reset a register in such a way that it has a certain initial state (e.g., 0 or 1) in order for the digital integrated circuit to operate properly. Common register reset methods in the prior art include synchronous reset and asynchronous reset.

The synchronous reset method of the digital integrated circuit has certain influence on the performance of the digital integrated circuit chip, and the asynchronous reset method of the digital integrated circuit in the prior art has potential stability problems. In addition, no matter the synchronous reset structure or the asynchronous reset structure, a global reset tree structure generally needs to be designed and implemented, which not only brings extra power consumption overhead, but also brings great difficulty to the physical implementation of the chip. Therefore, with the continuous improvement of the integrated circuit process and the continuous increase of the integration level, it is necessary to scientifically design an ideal circuit structure capable of realizing reset, so as to overcome various problems in the prior art.

Disclosure of Invention

The embodiment of the disclosure provides a scan chain, a design method thereof and a scan chain-based serial scanning reset method, wherein a scan chain is formed by adopting serial cascade based on a plurality of designed setting registers, serial scanning is carried out by multiplexing the scan chain, and reset data signals are scanned into all registers, so that the reset function of all registers is realized, and a large amount of wiring resources and register area required by the traditional reset design are saved.

At least one embodiment of the present disclosure provides a random test case generation method, including:

a serial scan reset method based on a scan chain comprises the following steps:

providing a scan chain, wherein the scan chain comprises a single set-up register or comprises a plurality of set-up registers cascaded in series, any of the set-up registers comprising:

a function selection terminal configured to receive an enable signal to select the scan chain to be in a scan/reset mode or a basic operation mode by setting the enable signal;

a first input configured to receive a functional data input signal for the basic mode of operation;

a scan/reset input terminal configured to selectively receive a scan input signal for scanning or a reset data signal for resetting;

a clock input terminal configured to receive a clock input required by the setting register;

a data output configured to act as a reset output and output a reset output signal when the scan chain is in a scan/reset mode, wherein for the scan chain including a plurality of setting registers serially cascaded, comprising: the scan/reset input of each setting register except the initial setting register of the scan chain is connected to the reset output of the last adjacent setting register;

setting an enable signal of the setting register so that the scan chain is in the scan/reset mode; and is

For example, in a serial scan reset method provided in at least one embodiment of the present disclosure, the reset data signal is 0 or 1, and the reset output signal is 0 or 1.

For example, in a serial scan reset method provided in at least one embodiment of the present disclosure, the method for resetting a scan chain includes, for the scan chain, a plurality of setting registers serially cascaded, and further includes:

For example, in a serial scan reset method provided in at least one embodiment of the present disclosure, the plurality of setting registers include at least one first register and/or at least one second register, wherein a reset output terminal of the first register that is reset outputs an inverted reset data signal, the inverted reset data signal is an inverted value of the reset data signal, and a reset output terminal of the second register that is reset outputs the reset data signal.

For example, in a serial scan reset method provided in at least one embodiment of the present disclosure, the first register includes:

the second register includes:

the serial scanning reset method further comprises:

For example, in a serial scan reset method provided in at least one embodiment of the present disclosure, the first base register and the second base register are D flip-flops having opposite outputs.

For example, in a serial scan reset method provided in at least one embodiment of the present disclosure, the first register includes:

the second register includes:

the serial scanning reset method further comprises:

For example, in a serial scan reset method provided in at least one embodiment of the present disclosure, the method further includes:

in response to the scan/reset mode, the odd number is an odd number equal to or greater than 1, and the even number is an even number equal to or greater than 0.

For example, in a serial scan reset method provided in at least one embodiment of the present disclosure, applying a reset data signal to the scan chain includes:

For example, in a serial scan reset method provided in at least one embodiment of the present disclosure, the reset data signal output by the alternative multiplexer is a ground signal, and the ground signal is 0, or the reset data signal output by the alternative multiplexer is a power signal, and the power signal is 1.

For example, in a serial scan reset method provided in at least one embodiment of the present disclosure, providing a clock input of the setting register includes:

and setting the enable signals of all the setting registers to be 1, and giving adaptive clock input according to the length of the scan chain so as to carry out serial scanning reset.

For example, in a serial scan reset method provided in at least one embodiment of the present disclosure, the method for giving an adapted clock input according to a length of the scan chain includes:

according to the scan chain with the length of N, the duration of enabling signals of the setting registers to be 1 is more than or equal to N clock cycles.

At least one embodiment of the present disclosure provides a scan chain for serial scan reset, including a reset signal terminal and a single setting register or a plurality of setting registers serially cascaded, the reset signal terminal being connected to a setting register at the beginning of the scan chain, wherein any of the setting registers includes:

a function selection terminal configured to receive an enable signal to select the scan chain to be in a scan/reset mode or a basic operation mode by setting the enable signal;

a first input configured to receive a functional data input signal required for the basic operating mode;

a scan/reset input terminal configured to selectively receive a scan input signal for scanning or a reset data signal for resetting;

a clock input terminal configured to receive a clock input required by the setting register;

a data output configured to act as a reset output and output a reset output signal when the scan chain is in a scan/reset mode, wherein for the scan chain including a plurality of setting registers serially cascaded, comprising: the scan/reset input end of each setting register except the initial setting register of the scan chain is connected to the reset output end of the last adjacent setting register so as to realize serial cascade connection;

For example, in a scan chain for serial scan reset provided in at least one embodiment of the present disclosure, the reset data signal is 0 or 1, and the reset output signal is 0 or 1.

For example, in a scan chain for serial scan reset provided in at least one embodiment of the present disclosure, the scan chain includes a plurality of setting registers serially cascaded, and a first inverter is provided between a reset output of one or more of the setting registers and a scan/reset input of a corresponding next adjacent setting register, so that in the scan/reset mode, serial scan reset is performed, and a scan/reset data input of each setting register except for a starting setting register of the scan chain is input with the reset data signal.

For example, in a scan chain for serial scan reset provided in at least one embodiment of the present disclosure, the plurality of setting registers include at least one first register and/or at least one second register, wherein a reset output terminal of the first register to be reset outputs an inverted reset data signal, the inverted reset data signal is an inverted value of the reset data signal, and a reset output terminal of the second register to be reset outputs the reset data signal.

For example, in a scan chain for serial scan reset provided in at least one embodiment of the present disclosure, the first register includes:

the second register includes:

For example, in a scan chain for serial scan reset provided in at least one embodiment of the present disclosure, the first register includes:

the second register includes:

For example, in a scan chain for serial scan reset provided in at least one embodiment of the present disclosure, the odd number is an odd number greater than or equal to 1, and the even number is an even number greater than or equal to 0.

For example, in a scan chain for serial scan reset provided in at least one embodiment of the present disclosure, the reset signal terminal includes an one-out-of-two multiplexer; the output end of the alternative multiplexer is connected with the scanning/resetting input end of the initial setting register of the scanning chain, and the resetting data signal is provided for the scanning/resetting input end of the initial setting register; the reset data signal for resetting is input to a first input terminal of the one-of-two multiplexer, and the scan input signal for scanning is input to a second input terminal of the one-of-two multiplexer.

For example, in a scan chain for serial scan reset provided in at least one embodiment of the present disclosure, the initial setting register of the scan chain is the first register or the second register.

For example, in a scan chain for serial scan reset provided in at least one embodiment of the present disclosure, the first input terminal of the two-select multiplexer is connected to ground or a power supply.

At least one embodiment of the present disclosure provides a method for designing a scan chain for serial scan reset, including:

providing a single setting register or a plurality of setting registers;

when a register transmission stage is synthesized by utilizing a synthesis tool, mapping a basic register in the setting register to a standard register element in a standard cell library, wherein any setting register comprises: the function selection end is configured to receive an enabling signal so as to select the scan chain to be in a scan/reset mode or a basic working mode by setting the enabling signal; a first input configured to receive a functional data input signal required for the basic operating mode; a scan/reset input terminal configured to selectively receive a scan input signal for scanning or a reset data signal for resetting; a clock input terminal configured to receive a clock input required by the setting register; a data output configured to serve as a reset output and output a reset output signal when the scan chain is in a scan/reset mode; the basic register comprises a function selection end, a clock input end and a reset output end of the setting register, the basic register further comprises a first basic input end used for the basic working mode or a first input end comprising the setting register, and the basic register further comprises a first basic scanning input end used for the scanning/resetting mode or a scanning/resetting input end comprising the setting register;

according to the time sequence requirement of the rear-end physical design, the physical position of the setting register is laid out;

For example, in a method for designing a scan chain provided in at least one embodiment of the present disclosure, for the scan chain including a plurality of setting registers, the method further includes:

For example, in a design method of a scan chain provided in at least one embodiment of the present disclosure, the plurality of setting registers include at least one first register and/or at least one second register, wherein a reset output terminal of the first register that is reset outputs an inverted reset data signal, the inverted reset data signal is an inverted value of the reset data signal, and a reset output terminal of the second register that is reset outputs the reset data signal.

For example, in a design method of a scan chain provided in at least one embodiment of the present disclosure, the first register includes:

the second register includes:

the method for designing the scan chain further comprises the following steps:

For example, in a design method of a scan chain provided in at least one embodiment of the present disclosure, the first register includes:

the second register includes:

the method for designing the scan chain further comprises the following steps:

For example, in a method for designing a scan chain provided in at least one embodiment of the present disclosure, the method further includes:

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a flowchart of a scan chain-based serial scan reset method according to some embodiments of the present disclosure;

fig. 2 is a schematic structural diagram of a first register according to some embodiments of the present disclosure;

fig. 3 is a schematic structural diagram of a second fixed register according to some embodiments of the present disclosure;

fig. 4 is a schematic structural diagram of a scan chain without an inverter in a path between a setting register and the setting register according to some embodiments of the present disclosure;

fig. 5 is a schematic structural diagram of a scan chain provided with an inverter in a path between a setting register and the setting register according to some embodiments of the present disclosure;

FIG. 6 is a flowchart illustrating a method for designing a scan chain for serial scan reset according to some embodiments of the present disclosure;

FIG. 7 is a flowchart illustrating a method for designing a scan chain for serial scan reset according to still other embodiments of the present disclosure;

fig. 8 is a schematic structural diagram of another form of the first register 13 according to still another embodiment of the present disclosure; and

fig. 9 is a schematic structural diagram of a scan chain for serial scan reset according to still other embodiments of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. The use of the terms "a" and "an" or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Flow charts are used in the disclosed embodiments to illustrate the steps of a method according to an embodiment of the disclosure. It should be understood that the preceding and following steps are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations may be added to the processes, or a certain step or steps may be removed from the processes.

For the register reset method, whether synchronous reset or asynchronous reset is performed, the reset is generally implemented by a reset tree (ResetTree) at present, a large amount of winding resources are required to be occupied, each register needs to be additionally matched with a two-way selector or a register with a reset port, a large amount of area is required to be occupied, and a control signal of the reset port for reset also needs winding resources. The inventor finds that: the scan test (ScanTest) at present only uses serial scan chains to test a chip, that is, scan chains in a chip are usually only used for testing, and a large amount of routing resources are also required to be occupied by required enable signals and data scan paths for scanning, so that a reset tree needs to be avoided, a dual-way selector needs to be added, or a register with a reset port needs to be used, so that a large amount of routing resources and register circuit area need to be saved.

At least one embodiment of the present disclosure provides a serial scan reset method based on a scan chain, including:

providing a scan chain, wherein the scan chain comprises a single set-up register or comprises a plurality of set-up registers cascaded in series, any set-up register comprising:

the function selection end is configured to receive an enable signal so as to select the scan chain to be in a scanning/resetting mode or a basic working mode by setting the enable signal;

a first input configured to receive a functional data input signal for a basic mode of operation;

a scan/reset input terminal configured to selectively receive a scan input signal for scanning or a reset data signal for resetting;

a clock input configured to receive a clock input required to set the register;

a data output configured to function as a reset output and output a reset output signal when the scan chain is in a scan/reset mode, wherein for a scan chain including a plurality of setting registers serially cascaded, comprising: the scan/reset input terminal of each setting register except the initial setting register of the scan chain is connected to the reset output terminal of the last adjacent setting register;

setting enable signals of a plurality of setting registers so that the scan chain is in a scan/reset mode;

for a scan chain including a single set register, a reset data signal is applied to a scan/reset input terminal of the single set register of the scan chain, and a clock input of the single set register is provided to perform serial scan reset, or for a scan chain including a plurality of set registers serially cascaded, a reset data signal is applied to a scan/reset input terminal of an initial set register of the scan chain, a clock input of the set register is provided to perform serial scan reset, and a reset data signal is input to a scan/reset data input terminal of each set register other than the initial set register of the scan chain.

At least one embodiment of the present disclosure further provides a scan chain for serial scan reset, including a reset signal terminal and a single setting register or a plurality of setting registers serially cascaded, the reset signal terminal being connected to a setting register at the beginning of the scan chain, wherein any setting register includes:

the function selection end is configured to receive an enable signal so as to select the scan chain to be in a scanning/resetting mode or a basic working mode by setting the enable signal;

a first input configured to receive a functional data input signal required for a basic mode of operation;

a scan/reset input terminal configured to selectively receive a scan input signal for scanning or a reset data signal for resetting;

a clock input configured to receive a clock input required to set the register;

wherein, for the scan chain including a single set register, serial scan reset is performed by applying a reset data signal to a scan/reset input terminal of the single set register of the scan chain when the scan chain is in the scan/reset mode, or, for the scan chain including a plurality of set registers, the plurality of set registers are serially cascaded such that, during serial scan reset by applying a reset data signal to an initial set register through a reset signal terminal when the scan chain is in the scan/reset mode, the scan/reset input terminal of each set register except the initial set register of the scan chain is inputted with the reset data signal.

At least one embodiment of the present disclosure further provides a method for designing a scan chain for serial scan reset.

In the serial scan reset method or scan chain according to the embodiments of the present disclosure, the initial reset value may be scanned into all registers by multiplexing the serial scan chain, so as to implement the reset function for all registers, and avoid using a reset tree and adding a dual selector or using a register with a reset port, thereby avoiding occupying a large area. Moreover, since the serial scan chain is multiplexed, which is equivalent to multiplexing the routing resources of the scan chain, in at least one example of the present disclosure, a large amount of routing resources and register circuit area can be saved, which is beneficial to reducing the chip area.

Fig. 1 is a flowchart of a scan chain-based serial scan reset method according to some embodiments of the present disclosure. Fig. 2 is a schematic structural diagram of a first register according to some embodiments of the present disclosure. Fig. 3 is a schematic structural diagram of a second fixed register according to some embodiments of the present disclosure.

As shown in fig. 1-3 in combination, a serial scan reset method according to at least one embodiment of the present disclosure includes steps S1 to S3.

Step S1, providing a scan chain, where the scan chain includes a plurality of setting registers cascaded in series, and any setting register includes a function selection terminal se, a first input terminal d, a scan/reset input terminal sdi, a clock input terminal clk, and a reset output terminal q.

Step S2, the enable signals of the plurality of setting registers are set so that the scan chain is in scan/reset mode.

Step S3, a reset data signal is applied to the scan/reset input sdi of the initial setting register of the scan chain, the clock input of the setting register is provided to perform serial scan reset, and the scan/reset data input sdi of each setting register other than the initial setting register of the scan chain is made to be input with the reset data signal.

First, with respect to step S1, for example, in some examples, the function selection terminal is configured to receive an enable signal to select the scan chain to be in a scan/reset mode or a basic operation mode by setting the enable signal, the first input terminal is configured to receive a function data input signal for the basic operation mode, the scan/reset input terminal is configured to selectively receive a scan input signal for scanning or a reset data signal for resetting, the clock input terminal is configured to receive a clock input required to set the register, and the reset output terminal is configured to output a reset output signal. Wherein the scan/reset input terminal of each setting register except the initial setting register of the scan chain is connected to the reset output terminal of the last adjacent setting register to realize serial cascade connection.

Next, for step S2, for example, in some examples, the enable signal is 0 or 1. For example, when the enable signal is 0, the function selection terminal selects the scan chain to be in the basic operation mode, and for example, when the enable signal is 1, the function selection terminal selects the scan chain to be in the scan/reset mode.

For example, in some examples, when the scan chain is in the basic mode of operation, the first input receives a functional data input signal, the setting registers of the scan chain are connected by a functional path, and the functional path performs a series of arithmetic logic operations to cause the chip to perform pre-designed normal functions, such as data encryption, signal processing, and the like. Since the scan chain is in the basic operation mode is not the important point in the description of the embodiments of the present disclosure, in order to ensure the clarity and conciseness of the description of the embodiments of the present disclosure, the embodiments of the present disclosure omit the related contents that the scan chain is in the basic operation mode.

For example, in some examples, the scan/reset input of the set register of the scan chain selectively receives a scan input signal for scanning or a reset data signal for resetting when the scan chain is in a scan/reset mode.

It should be noted that the scan/reset input of the setting register is actually an input terminal, and the scan/reset input corresponds to the scan/reset mode. The scan/reset mode includes a scan mode and a reset mode, and the scan mode and the reset mode can only select one of the two modes to operate correspondingly at the same time.

For example, in some examples, when a reset of a setting register of a scan chain is required, and a reset mode in the scan/reset mode is selected, the scan/reset input terminal is a reset input terminal, i.e., the scan/reset input terminal inputs a reset data signal for resetting. For another example, in some examples, when a scan test is required, and a scan mode in the scan/reset mode is selected, the scan/reset input terminal is a scan input terminal, i.e., the scan/reset input terminal inputs a scan input signal for scanning. This means that the above example multiplexes serial scan chains, which is equivalent to multiplexing routing resources of scan chains, thereby saving a lot of routing resources, which is beneficial to reducing chip area.

It should be noted that the reset output q of the embodiment of the present disclosure is an output terminal for outputting the reset output signal, which is indicated by the data output q of the setting register when the scan chain is in the scan/reset mode, and the data output q indicates an output terminal for outputting a result corresponding to the functional data input signal in the working state when the scan chain is in the basic working mode. For clarity and conciseness of the embodiment of the present disclosure, the data output terminal is described below as the reset output terminal q when the scan chain is in the scan/reset mode.

It should be noted that the selection of the scan mode or the selection of the reset mode can be freely adjusted as needed. The following description is mainly given in detail by taking a reset mode of the scan chain in the scan/reset mode as an example, therefore, the scan/reset input of the setting register in the reset mode should be the reset input, and for convenience of description, the scan/reset input is still used to replace the reset input for description, but it is only for convenience of description, and does not have any limitation on the structural features and functions of the setting register. In addition, regarding the relevant contents of the scan mode scenario of the scan chain in the scan/reset mode, a person skilled in the art can know the specific scheme of the scan chain in the scan mode according to the relevant description herein, and the embodiments of the present disclosure are not set forth in detail herein.

For example, in some examples, whether the scan mode or the reset mode in the scan/reset mode is the scan mode or the reset mode, the corresponding reset operation or the scan test operation is performed when the enable signal is 1.

Finally, for step S3, for example, in some examples, the reset data signal applied to the scan/reset input sdi of the initial setting register is denoted as R, and the scan/reset data input sdi of each setting register except the initial setting register of the scan chain is input with the reset data signal R, which means that the scan/reset inputs sdi of all the setting registers are input with the reset data signal R. And then, recording the reset output signal output by the reset output end as O, and the reset output signal O is a reset data signal R or an inverted reset data signal P, wherein the inverted reset data signal P is the inversion of the reset data signal R.

For example, in some examples, the reset data signal R applied to the scan/reset input sdi of the initial set register is 0 or 1, and the reset output signal of the set register is either the reset data signal 0 (equivalent to a reset of 0) or the inverted reset data signal 1 (equivalent to a reset of 1).

The following description mainly takes the reset data signal R as 0 and the inverted reset data signal P as 1 as an example to facilitate understanding of the embodiments of the present disclosure. However, the reset data signal and the reset output signal in the embodiment of the present disclosure are not limited to the reset values 0 and 1, and may also be other reasonable reset values.

For example, in some examples, as shown in fig. 2, the reset output signal RVAL (reset value, also called reset value) of the first register 11 is 1, wherein the reset data signal inputted to the scan/reset input sdi of the first register 11 is 0, and the reset output signal RVAL outputted from the reset output q of the first register 11 is an inverted reset data signal 1.

As shown in fig. 2, the first register 11 includes a first base register 1101 (i.e., a white box portion dff _ scan in fig. 2, representing a D flip-flop) and an inverter 1102. The first basic register 1101 includes a first basic input D, and SI, CK, SE and QB terminals, which means that the first basic register 1101 includes a scan/reset input sdi, a function selection terminal SE, a clock input clk and a reset output q of the first register 11. Since fig. 2 is to distinguish the first register 11 from the first basic register 1101, a gray box is particularly added outside the white box portion of fig. 2, but in terms of the actual circuit structure, the SI terminal, the CK terminal, the SE terminal, and the QB terminal and the sdi terminal, the SE terminal, the clk terminal, and the q terminal are the same terminals, respectively. It should be noted that fig. 2 is only a schematic diagram for easy understanding, and does not have any limitation on the features of the first register 11.

For example, in some examples, as shown in fig. 2, the inverter 1102 of the first register 11 is disposed between the first base input D of the first base register 1101 and the first input D of the first register 11.

As shown in fig. 3, the reset output signal RVAL of the second register 12 is 0, wherein the reset data signal inputted from the scan/reset input terminal sdi of the second register is 0, and the reset output terminal q of the first register 11 outputs the reset data signal 0.

For example, in some examples, as shown in fig. 3, the second register 12 includes a second base register 1201 (i.e., the white box portion dff _ scan in fig. 3, representing one D flip-flop). The second basic register 1201 includes a D terminal, an SI terminal, a CK terminal, an SE terminal, and a Q terminal, which means that the second basic register 1201 includes a first input terminal D of the second register, a scan/reset input terminal sdi, a function selection terminal SE, a clock input terminal clk, and a reset output terminal Q. Since fig. 3 is a diagram for distinguishing the second register from the second basic register, a gray frame is added outside the white frame portion of fig. 3, but in terms of an actual circuit structure, the D terminal, the SI terminal, the CK terminal, the SE terminal, the QB terminal, the D terminal, the sdi terminal, the SE terminal, the clk terminal, and the q terminal are the same terminals, respectively. It should be noted that fig. 3 is only a schematic diagram for easy understanding, and does not have any limitation on the features of the second register 12.

For example, in some examples, the first base register 1101 of the first register 11 and the second base register 1201 of the second register 12 are D flip-flops having opposite logic outputs, i.e., the output of the QB terminal of the first base register 1101 is the inverse of the output of the Q terminal of the second base register 1201, mainly due to the presence of the inverter 1102.

For example, in some examples, in response to each second register 12 passing one clock cycle, the output of the reset output Q (i.e., Q terminal) of the second register 12 in fig. 3 is equal to the input of the first input terminal D of the second register 12, so as to implement the normal D flip-flop function, that is, after one beat of clock, the reset output of the second register 12 is equal to the first input terminal D, and if there is no clock, the output of the reset output of the second register 12 will not change.

For example, in some examples, in response to each first register 11 passing one clock cycle, the output of the reset output q (i.e., QB terminal) of the first register 11 in fig. 2 is equal to the input of the first input D of the first register 11 and equal to the inverse of the first base input D of the first base register 1101, that is, after one beat of clock, the reset output of the first register 11 is equal to the first input D, and if there is no clock, the output of the reset output of the first register 11 does not change. It is worth noting that the factors considered in the design of the first register 11 include: because the first register 11 still needs to be able to implement the function of the normal D flip-flop, it means that the values of the q terminal and the D terminal need to be kept consistent, that is, when the D terminal inputs 0, the q terminal outputs 0, and when the D terminal inputs 1, the q terminal also outputs 1, and furthermore, according to the requirement of the reset function, the reset output terminal q (i.e., QB terminal) of the first register 11 needs to output the inverted reset data signal 1, at this time, the first register 11 is additionally provided with an inverter 1102, which is placed between the first basic input terminal D of the first basic register 1101 and the first input terminal D of the first register 11, so that the output of the reset output terminal q (i.e., QB terminal) and the input of the first input terminal D can be kept consistent, thereby implementing the function of the normal D flip-flop. This means that if the first register 11 does not use the QB terminal but an inverter 1102 is directly added between the first base input terminal D of the first base register 1101 and the first input terminal D of the first register 11, the first register 11 is no longer a D flip-flop. In other words, the QB terminal is equivalent to the inversion of the Q terminal, and the inverter 1102 of the D terminal of the first register 11 is equivalent to the cancellation of the inversions of the input and output sides, and the first register 11 can still realize the function of the normal D flip-flop.

As described above, the second register 12 is not provided with an inverter as compared with the first register 11. As can be seen from the above description, whether the reset output signal RVAL output from the reset output terminal q of the set register is 1 or 0 is determined by whether an inverter is provided between the base input terminal of the base register (e.g., the first base register or the second base register) and the first input terminal of the first register 11. For example, if the reset output terminal q of the set register needs to output 1, the first register 11 of fig. 2 is selected, and for example, if the reset output terminal q of the set register needs to output 0, the second register 12 of fig. 3 is selected.

For example, in some examples, for the second register 12 in fig. 3, when the scan chain is in the reset mode, the sdi terminal of the second register 12 inputs 0, and then the Q terminal of the second register outputs 0, i.e., the output of the Q terminal of the second register is equal to the input of the SI terminal; for the first register 11 in fig. 2, when the scan chain is in the reset mode, the sdi terminal of the first register 11 inputs 0, and the q terminal of the first register 11 outputs 1, i.e. the output of the QB terminal of the first register 11 is equal to the inverse of the sdi terminal (i.e. SI terminal) input. Based on the first register 11 and the second register 12 in the specific form of the above example, when the scan chain is in the scan/reset mode by setting the enable signal, 0 is input from the sdi terminal of the initial setting memory of the scan chain, and after the setting registers of each stage are transmitted, the Q terminals of all the setting registers are all output 0 and QB terminals are all output 1, at this time, if the Q terminal is connected to the Q terminal, the Q terminal is 0, and if the Q terminal is connected to the QB terminal, the Q terminal is 1, so that the value of the Q terminal is equal to the reset output signal RVAL, and the reset function is completed.

Based on the above, the QB terminal of the first register 11 and the second register 12 can respectively realize the function of the D flip-flop, and due to the existence of the distinction between the QB terminal of the first register 11 and the Q terminal of the second register 12, the verification work after the scan chain reset is completed is facilitated, that is, only the reset values of all the QB terminals and all the Q terminals need to be checked and verified, so that the verification is relatively simple, and especially, the verification is simple for chips with millions or even tens of millions of registers.

It should be noted that, for the fact that the reset output signals of some setting registers in the scan chain need to be 0 and the reset output signals of some other setting registers need to be 1, the specific need is preset according to the actual situation, and those skilled in the art may determine the actual situation, and the embodiment of the present disclosure does not limit this and is not described in detail. In addition, it should be noted that the scan chain in the embodiment of the present disclosure not only includes the setting register with the reset output signal being 0 and the setting register with the reset output signal being 1, but also all the setting registers with the reset output signal being 0 and all the setting registers with the reset output signal being 1, which depends on the requirement of the reset value, and can be adjusted freely according to the actual requirement.

For example, in some examples, the scan chain comprises a plurality of setting registers serially cascaded, the plurality of setting registers comprising at least one first register 11 and/or at least one second register 12.

Fig. 4 is a schematic structural diagram of a scan chain without an inverter provided in a path between a setting register and the setting register according to some embodiments of the present disclosure. Fig. 5 is a schematic structural diagram of a scan chain provided with an inverter in a path between a setting register and the setting register according to some embodiments of the present disclosure.

For example, in some examples, a serial scan reset method includes: by providing an inverter (e.g., inverters 2101 and 2102 in fig. 5) between the reset output of one or more setting registers and the scan/reset input of the corresponding next adjacent setting register, serial scan reset is performed in scan/reset mode, and the scan/reset data input of each setting register except the initial setting register of the scan chain is inputted with a reset data signal (e.g., the reset data signal is 0).

For the sake of distinction, some embodiments of the present disclosure denote an inverter between the reset output terminal of a setting register and the scan/reset input terminal of the corresponding setting register as a first inverter, and an inverter (e.g., inverter 1102) provided in the first register 11 itself as a second inverter.

For example, in some examples, as shown in fig. 4, scan chain 100 includes four set registers serially cascaded in sequence, set register 1201a, set register 1101a, set register 1102a, and set register 1202a, respectively. The setting register 1101a and the setting register 1102a both belong to the first register 11, and the setting register 1201a and the setting register 1202a both belong to the second register 12. The scan/reset input of the setting register 1101a is connected to the reset output of the setting register 1201a, the scan/reset input of the setting register 1102a is connected to the setting register 1101a, and the scan/reset input of the setting register 1202a is connected to the reset output of the setting register 1102 a.

For example, in some examples, scan chain 100 includes a reset signal terminal that includes an one-out-of-two multiplexer 301, as shown in fig. 4. The output terminal of the one-out-of-two multiplexer 301 is connected to the Scan/reset input terminal of the initial setting register 1201a of the Scan chain 100, and is used to provide a reset data signal to the Scan/reset input terminal of the initial setting register 1201a when the enable signal (Scan _ Shift _ En) is 1. For example, the first input terminal 3011 of the two-select multiplexer 301 is grounded, and the reset data signal output by the two-select multiplexer 301 is a ground signal, for example, the ground signal is 0. For another example, if the first input terminal 3011 of the two-way multiplexer 301 is connected to a power supply, the reset data signal output by the two-way multiplexer 301 is a power supply signal, for example, the power supply signal is 1, and the reset data signal when the first input terminal 3011 is connected to the power supply is 1, the obtained reset output signal of the setting register is the inverse of the corresponding reset output signal in the above example where the reset data signal is 0, and the specific method and principle may refer to the description of the serial scan reset method based on the scan chain, which is not described herein again. For example, the first input terminal 3011 of the one-out multiplexer 301 receives a reset Data signal 0 for reset, and the second input terminal 3012 receives a Scan input signal (Scan _ Data _ In) for Scan. Just as the reset data signal of the embodiments of the present disclosure described above is not limited to 0 or 1, and correspondingly, the first input 3011 of the alternative multiplexer 301 of the embodiments of the present disclosure is not limited to ground or power, but may be applied to the scan/reset input of the initial setting register of the scan chain 100 in other manners.

For example, in some examples, the one-of-two multiplexer 301 also includes a reset control signal terminal 3013. For example, when the Reset control signal Reset received by the control signal terminal 3013 is 1, the one-out-of-two multiplexer 301 selects the first input terminal 3011 to input the Reset data signal 0 for Reset, and at this time, serial scan Reset is performed based on the scan chain. For another example, when the Reset control signal Reset received by the control signal terminal 3013 is 0, the one-out-of-two multiplexer 301 selects the second input terminal 3012 to input the Scan input signal (Scan _ Data _ In) for scanning, and at this time, the Scan test is performed based on the Scan chain. It should be noted that the reset control signal in the embodiment of the present disclosure is not limited to 0 and 1, and may also be other reasonable reset control signals.

For example, in some examples, the initial setting register of the scan chain may be the second register 12, such as the setting register 1201a in fig. 4 and 5, and the initial setting register of the scan chain may also be the first register 11 (not shown), and the embodiments of the present disclosure are not limited herein as long as the output of the two-select multiplexer 301 can output the reset data signal 0, and the input of the scan/reset input of the initial setting register of the scan chain is also the reset data signal 0.

As shown in fig. 4, the scan/reset input terminal of the setting register 1201a inputs the reset data signal 0, the reset output terminal of the setting register 1201a outputs the reset data signal 0, and then the scan/reset input terminal of the setting register 1101a inputs the reset data signal 0, and the reset output terminal Q (i.e., QB terminal) of the setting register 1101a outputs 1, since at least one embodiment of the present disclosure requires that the scan/reset input terminals sdi of all the first registers 11 input the reset data signal 0 and the reset output terminals Q (i.e., QB terminal) output the inverted reset data signal 1, and the scan/reset input terminals sdi of all the second registers input the reset data signal 0 and the reset output terminals Q (i.e., Q terminal) output the inverted reset data signal 0, so as to complete the reset function. Therefore, when the reset output terminal of the setting register 1101a outputs 1, which causes the scan/reset input terminal of the setting register 1102a to input 1 instead of the reset data signal 0, thereby causing the inversion that the QB terminal of the register is the SI terminal to be no longer satisfied during the reset mode, in order for the scan/reset input terminal of the setting register 1102a to also input the reset data signal 0, the scan/reset input terminal sdi of the setting register 1102a inputs the reset data signal 0 by providing an odd number of first inverters (e.g., one inverter 2101 shown in fig. 5) between the reset output terminal q of the setting register 1101a and the scan/reset input terminal sdi of the setting register 1102a, as shown in fig. 5.

Similarly, since the reset output q (i.e., QB terminal) of the setting register 1102a in fig. 4 outputs 1, which causes the scan/reset input sdi of the setting register 1202 in fig. 4 to input 1 instead of the reset data signal 0, in order to input the reset data signal 0 also to the scan/reset input sdi of the setting register 1202a, a first inverter (e.g., the inverter 2102 in fig. 5) is provided between the reset output q of the setting register 1102a and the scan/reset input sdi of the setting register 1202a, so that the scan/reset input sdi of the setting register 1202a inputs the reset data signal 0.

For example, in the example of fig. 5, 0 first inverters (i.e., no first inverter is provided) are provided between the reset output terminal Q (i.e., Q terminal) of the setting register 1201a and the scan/reset input terminal sdi of the setting register 1101a, and at this time, the reset output terminal Q of the setting register 1201a outputs the reset data signal 0, and correspondingly, the scan/reset input terminal sdi of the setting register 1101a also inputs the reset data signal 0.

It should be noted that, when 3 or 5 or 7 or other 2n +1(n is an integer) first inverters are arranged between the reset output terminal q (i.e., QB terminal) of the setting register 1102a and the scan/reset input terminal sdi of the setting register 1202a, the reset output terminal q of the setting register 1102a outputs the reset data signal 1, and the output reset data signal 1 passes through odd number of first inverters such as 3 or 5 or 7, so that the scan/reset input terminal sdi of the setting register 1202a inputs the reset data signal 0.

Similarly, when 2 or 4 or 6 or another 2n (n is an integer) first inverters are provided between the reset output terminal Q (i.e., Q terminal) of the setting register 1201a and the scan/reset input terminal sdi of the setting register 1101a, the reset output terminal Q of the setting register 1201a outputs the reset data signal 0, and the output reset data signal 0 passes through an even number of first inverters such as 2 or 4 or 6, so that the scan/reset input terminal sdi of the setting register 1101a also inputs the reset data signal 0.

According to the foregoing, the serial scan reset method further includes: in response to the scan/reset mode, an odd number of first inverters (e.g., the inverter 2101 or the inverter 2102 in fig. 5) are provided between the reset output terminal of one or more first registers 11 (e.g., the setting register 1101a or 1102a including the QB terminal) and the scan/reset input terminal of the corresponding next-adjacent setting register (e.g., the setting register 1102a including the QB terminal or the setting register 1202a including the Q terminal), respectively, and an even number of first inverters are provided between the reset output terminal of one or more second registers 12 and the scan/reset input terminal of the corresponding next-adjacent setting register (which may be the first register or the second register), respectively, so that serial scan reset is performed in the scan/reset mode, and so that the scan/reset input terminal of each setting register except for the initial setting register of the scan chain is inputted with the reset data signal 0 Then all the scan/reset inputs sdi of the first register 11 input the reset data signal 0.

For example, in some examples, for convenience of description, the number x of first inverters between the reset output q of any one of the first registers 11 to the scan/reset input sdi of the corresponding next-adjacent setting register is counted as a first number x, and the number y of first inverters between the reset output q of any one of the second registers 12 to the scan/reset input sdi of the corresponding next-adjacent setting register is counted as a second number y. For example, in some examples, the second number y is an even number greater than or equal to 0 and the first number x is an odd number greater than or equal to 1.

Therefore, when the first number x is an odd number and the second number y is an even number, the conditions for successful serial scan reset are satisfied, and the reset data signal 0 is input to all the scan/reset input ends sdi of the setting registers, and the reset data signal 0 is output from both the reset output end Q (i.e., QB end) of the first register 11 and the reset data signal 0 is output from both the reset output end Q (i.e., Q end) of the second register 12, so as to achieve successful serial scan reset.

In summary, at least one embodiment of the present disclosure needs to input the reset data signal 0 from the scan/reset input sdi of the initial setting register of the scan chain, and after the transmission is connected through the scan chain (Q/QB- > SI), all the QB terminals of the first registers 11 output 1, and all the Q terminals of the second registers 12 output 0, so as to achieve the reset function. In at least one embodiment of the present disclosure, the initial reset value may be scanned into all registers by multiplexing the serial scan chain, so as to implement the reset function for all registers, and avoid using a reset tree and adding a dual selector or using a register with a reset port, thereby avoiding occupying a large area.

It should be noted that, for clarity and simplicity of description, fig. 4 and fig. 5 only illustrate a scan chain including two first registers 11 and two second registers 12, which is exemplary and not limiting to the present disclosure, and may be adjusted freely according to actual needs, and embodiments of the present disclosure are not exhaustive and repeated herein.

For example, in some examples, for providing the clock input of the setting register, include: and setting the enable signals of all the setting registers to be 1, and giving adaptive clock input according to the length of the scan chain so as to carry out serial scanning reset. When the length of the Scan chain is N, N is not less than 1 and is an integer, the duration of setting the enable signal (Scan _ shift _ En) of the register to be 1 is more than or equal to N clock cycles. For example, if the length of the scan chain is 10, the duration of the enable signal being 1 requires at least 10 clock cycles, and the input of the scan/reset input sdi of the setting register advances by one setting register per beat of clock cycle, then the total reset process requires 10 beats.

It can be seen that, for the serial scan reset method, since the inverter 1102 of the first register 11 is disposed at the D terminal, the transmission delay of Q/QB- > D is increased, which may reduce the operating frequency of the chip, but the implementation manner of this embodiment is very simple, and when verifying the correctness of the serial scan reset, because there is a distinction between the QB terminal of the first register 11 and the Q terminal of the second register 12, it is only necessary to check whether all the Q terminals of the second register 12 output the reset data signal 0 and check whether all the QB terminals of the first register 11 output the inverted reset data signal 1 after the reset is completed. If all the Q terminals of the second registers 12 output the reset data signal 0 and all the QB terminals of the first registers 11 output the inverted reset data signal 1, it indicates that the circuit design is correct and the serial scan reset is correct.

It should be noted that, in the embodiments of the present disclosure, the flows of the serial scan reset method provided in the above examples may include more or less operations, and these operations may be performed sequentially or in parallel. Although the above flow of the serial scan reset method includes a plurality of operations occurring in a specific order, it should be clearly understood that the order of the plurality of operations is not limited.

In the serial scan reset method according to the embodiment of the present disclosure, the initial reset value is scanned into all registers by multiplexing the serial scan chain, so that the reset function of all registers is realized, the use of a reset tree and the addition of a dual-path selector or the use of a register with a reset port are avoided, and a large amount of winding resources and register circuit area are saved. It should be noted that, for specific functions and technical effects of the scan chain in the embodiments of the present disclosure, reference may be made to the description above regarding the serial scan reset method, and details are not described herein again.

Fig. 6 is a flowchart illustrating a method for designing a scan chain for serial scan reset according to some embodiments of the present disclosure. As shown in fig. 6, at least one embodiment of the present disclosure provides a method for designing a scan chain for serial scan reset, which includes steps T1 to T5.

And step T1, providing a plurality of setting registers.

For step T1, for example, in some examples, the multiple setting registers provided are distributed multiple setting registers, wherein the base input D and output Q of the base register of the setting register at step T1 may be logically connected, while the SI terminal is temporarily ignored or grounded entirely at this stage of design, in other words, at the stage of design at step T1, the scan chain does not exist at this time.

And step T2, when the Register Transfer Level (RTL) is synthesized by the synthesis tool, mapping the basic register in the setting register to the standard register element in the standard cell library.

For step T2, for example, in some examples, the setting register includes a function selecting terminal, a first input terminal, a scan/reset input terminal, a clock input terminal, and a reset output terminal, and the specific configuration and function of the setting register may refer to the description above about the scan chain and the scan chain-based serial scan reset method, which is not repeated here. For example, the basic registers in the setting registers are the first basic register and the second basic register above, and thus the basic registers include the function selection terminal, the clock input terminal, and the reset output terminal of the setting registers, the basic registers further include the first basic input terminal for the basic operation mode or the first input terminal of the setting registers, and the basic registers further include the first basic scan input terminal for the scan/reset mode or the scan/reset input terminal of the setting registers. For example, in some examples, the base register in the set registers is mapped to a standard register element with an SI terminal during the synthesis phase of step T2.

Step T3, using a scan chain connection tool, so that the scan/reset input sdi of each setting register except the initial setting register of the scan chain is connected to the reset output q of the last adjacent setting register to implement serial concatenation of multiple setting registers, and finally form a serial concatenated scan chain.

And step T4, laying out the physical position of the setting register according to the time sequence requirement of the back end physical design.

For step T4, for example, in some examples, the back-end design timing requirement refers to meeting the operating frequency requirement, the layout refers to adjusting the physical positions of the setting registers, for example, if the setting registers are swung too far, the path side length delay becomes large, which reduces the operating frequency.

For example, in some examples, the scan chain design method further comprises: by providing a first inverter between the reset output terminal of one or more first registers 11 and the scan/reset input terminal of the corresponding next adjacent setting register, serial scan reset is performed in the scan/reset mode, and the scan/reset input terminal of each setting register except the initial setting register of the scan chain is input with the reset data signal 0.

Step T5, all the setting registers are checked so that during the application of the reset data signal to the initial setting register of the scan chain for serial scan reset while the scan chain is in scan/reset mode, the scan/reset input terminal in each setting register except the initial setting register of the scan chain is input with a reset data signal.

For step T5, the scan chain design method further includes:

before the production of the chip stream chip, firstly, calculating the number x of first inverters between the reset output end of any first register 11 and the scanning/reset input end of the corresponding next adjacent setting register and recording the number x as a first number x, and calculating the number y of first inverters between the reset output end of any second register 12 and the scanning/reset input end of the corresponding next adjacent setting register and recording the number y as a second number y;

then, whether the first number x is an odd number and the second number y is an even number are simultaneously satisfied is judged: if so, indicating that the design of the scan chain is correct, and meeting the condition of successful serial scan reset at the moment; if not, it indicates that the scan chain is not designed correctly, so that a first inverter is added between the reset output terminal of the corresponding first register 11 and the scan/reset input terminal of the next adjacent setting register, so that the first number x is an odd number and the second number y is an even number, to satisfy the condition that the serial scan reset is successful.

For example, in some examples, for calculating the number x and the number y, further comprising:

before the production of the chip stream chip, whether the driving of the scan/reset input ends sdi of all the setting registers is the Q end or the QB end is checked by using a script so as to respectively calculate the number of first inverters between the Q/QB end and the next adjacent sdi end for verifying the correctness of the design of the scan chain. Here, the number y of first inverters from the Q terminal of any one of the second registers 12 to the sdi terminal of the next adjacent setting register needs to be even, and the number x of first inverters from the QB terminal of any one of the first registers 11 to the sdi terminal of the next adjacent setting register needs to be odd. If not, a first inverter is automatically inserted by the script in the path, i.e. between the reset output of the respective first register 11 or second register 12 and the scan/reset input of the next adjacent set register.

For example, fig. 4 shows the state of the scan chain before the completion of step T5, fig. 5 shows the state of the scan chain after the completion of step T5, and fig. 5 shows that, based on fig. 4, a first inverter 2101 is added between the reset output terminal of set register 1101a and the scan/reset input terminal of set register 1102a, and a first inverter 2102 is added between the reset output terminal of set register 1102a and the scan/reset input terminal of set register 1202 a.

It should be noted that fig. 4 and fig. 5 are only an example of a scan chain, and the number and the specific connection manner of registers in the scan chain are not limited in this disclosure, and may be freely adjusted according to actual needs.

Fig. 7 is a flowchart illustrating a method for designing a scan chain for serial scan reset according to still other embodiments of the present disclosure. For example, in some examples, as shown in fig. 7, the design method of the scan chain includes steps P1 through P6.

Wherein, the specific contents of step P1, step P2, step P3 and step P4 are the same as those of step T1, step T2, step T3 and step T4, respectively, and the specific contents of step P6 are the same as those of step T5, and the step P5 between step P4 and step P6 further includes: based on the result of the layout, the connection relationship between the reset output terminal of one of the at least two setting registers and the scan/reset input terminal of the other is adjusted so that the wire length of the scan chain is shortened.

The reason why the step T5 is considered to be added in the scan chain design method mainly includes: after the preliminary layout in step P4, most of the registers are randomly placed in random order according to the connection order, which greatly occupies the routing resources, so that it is desirable to process the connection of the scan chain before the subsequent steps are started, and the connection is performed again (also called scan chain rearrangement) without affecting the logic function, thereby reducing the routing length of the scan chain.

For example, in some examples, the connection between the q terminal and the sdi terminal of the two setting registers follows a principle of proximity, for example, after the setting register positions are adjusted, the q terminal and the sdi terminal of the two setting registers that are close to each other are connected together, and the connection between the q terminal and the sdi terminal that are far from each other is disconnected, so that the winding length of the scan chain is shortened. It should be noted that the number of the setting registers adjusted in step P5 is not limited to two, and may also be three, four or more, and specifically, the number may be freely adjusted according to actual needs, and the embodiment of the present disclosure is not limited and will not be described herein.

Fig. 8 is a schematic structural diagram of another form of the first register 13 according to still other embodiments of the present disclosure. For example, in some examples, the first register referred to in any of the above examples no longer employs the first register 11 shown in fig. 2, but instead employs the first register 13 shown in fig. 8.

For example, in the example of fig. 8, the reset output signal RVAL of the first register 13 is 1, wherein the reset data signal inputted to the scan/reset input sdi of the first register 13 is 0, and the reset output signal RVAL outputted from the reset output q of the first register is the inverted reset data signal 1. For example, in some examples, in response to each first register 13 passing one clock cycle, the output of the reset output terminal Q (i.e., terminal Q) of the first register 13 in fig. 8 is equal to the input of the first input terminal D of the first register 13, i.e., a normal D flip-flop function can be implemented, i.e., after one beat of clock, the reset output terminal of the first register 13 is equal to the first input terminal D, and if there is no clock, the output of the reset output terminal of the first register 13 will not change.

As shown in fig. 8, the first register 13 includes a first base register 1301 (i.e., a white box portion dff _ scan in fig. 8, representing one D flip-flop) and an inverter 1302. The first basic register 1301 includes a first basic scan input SI and D, CK, SE and Q terminals, which means that the first basic register 1301 includes a first input D of the first register 13, a function selection terminal SE, a clock input clk and a reset output Q. Since fig. 8 is to distinguish the first register from the first base register, a gray frame is added outside the white frame portion of fig. 8, but in terms of the actual circuit structure, the D terminal, the CK terminal, the SE terminal, the Q terminal, the SE terminal, the clk terminal, and the Q terminal refer to the same terminal respectively. It should be noted that fig. 8 is only a schematic diagram for easy understanding, and does not have any limitation on the characteristics of the first register.

For example, in the example of fig. 8, the inverter 1302 of the first register 13 is placed between the first base scan input SI of the first base register 1301 and the scan/reset input sdi of the first register 13.

For example, in some examples, for the first register 13 in fig. 8, when the scan chain is in the reset mode, the sdi terminal of the first register 13 inputs 0 and the first basic scan input SI inputs 1, because an inverter 1302 is provided between the first basic scan input SI of the first basic register 1301 and the scan/reset input sdi of the first register 13, the Q terminal (i.e., Q terminal) of the first register 13 outputs 1, i.e., the Q terminal of the first register has an output equal to the inverse of the sdi terminal input.

As can be seen from the above, the first register 13 of fig. 8 may be adopted in the embodiment of the present disclosure instead of the first register 11 of fig. 2, because the first register 13 can also achieve the effect of inputting the reset data signal 0 from the scan/reset input sdi and outputting the inverted reset data signal 1 from the reset output q, thereby completing the reset function of the register.

Fig. 9 is a schematic structural diagram of a scan chain for serial scan reset according to some embodiments of the present disclosure. For example, in some examples, all of the first registers 11 (e.g., set registers 1101a, 1102a) in the scan chain 100 of FIG. 5 are replaced with the first registers 13 shown in FIG. 8, thereby forming the scan chain 200 shown in FIG. 9. For example, the setting register 1101a in fig. 5 is replaced with the setting register 1301a in fig. 9, and the setting register 1102a in fig. 5 is replaced with the setting register 1302a in fig. 9.

It should be noted that, except that the first register 11 is replaced by the first register 13 in the scan chain in the example of fig. 9, other contents (for example, related to a serial scan reset method, a scan chain, and a design method of the scan chain) may refer to the description above of the scan chain including the first register 11, and details of the embodiment of the present disclosure are not repeated herein.

In the scheme of serial scan reset based on the scan chain shown in fig. 9, since the inverter in the first register (i.e., the setting register whose reset output signal RVAL is 1) is arranged at the SI terminal, the transmission delay of Q- > D in this scheme is smaller, and the operating frequency can be higher, but the implementation of this scheme is more difficult than the scheme of fig. 5, because after the serial scan reset is completed, the output of the Q terminal of some setting registers in the scan chain is 1 (e.g., the setting register 1301a in fig. 9), and the output of the Q terminal of some setting registers in the scan chain is 0 (e.g., the setting register 1201a in fig. 9), and then the verification needs to check one by one according to the list. It should be noted that, for specific functions and technical effects of the serial scan reset method corresponding to the implementation of fig. 8 to fig. 9, reference may be made to the above description related to the first register 13 and the scan chain 200, and details are not repeated here.

In addition, as a special case, the scan chain of the embodiment of the present disclosure may further include only a single setting register (not shown), that is, when the length of the scan chain is N ═ 1, the single setting register may be the first register 11, or may be the second register 12 or 13, which is not limited in this embodiment of the present disclosure, and as for the specific structure and function of the setting register in this example, reference may be made to the description about the scan chain and the serial scan reset method based on the scan chain, which is not described herein again.

For example, for a scan chain including a single set register, the serial scan reset method based on the scan chain includes: a reset data signal is applied to the scan/reset input of a single set register of the scan chain, and the clock input of the single set register is provided for serial scan reset.

For example, in the design method of the scan chain, a single setting register is included in the scan chain, and the single setting register is not required to be cascaded with other setting registers by using a scan chain connecting tool. It should be noted that whether a single setting register or a plurality of setting registers are included, they may be formed as a scan chain, for example, in some examples, when setting registers are automatically connected among thousands of setting registers using a scan chain connection tool, after a plurality of scan chains including a plurality of setting registers are formed, the last setting register is left and the remaining one setting register is used as a scan chain alone. However, the number of setting registers for forming the scan chains, the number of formed scan chains, the length of each scan chain, the formation sequence of the scan chains with corresponding lengths, and the like, which are provided during the design of the scan chains, are not limited in the embodiments of the present disclosure, and are specifically adjusted freely according to actual needs, and are not described herein. It should be noted that, for other specific functions and technical effects of the example where the length of the scan chain is N ═ 1, reference may be made to the description above about the scan chain and the serial scan reset method based on the scan chain, and details are not described here again.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

36页详细技术资料下载

Scan chain and design method thereof and serial scan reset method based on scan chain

相关技术

网友询问留言