阅读说明：本技术 基于fpga的数组排序方法、系统及数据压缩方法 (Array sorting method and system based on FPGA and data compression method ) 是由 凌云 莫保健 于 2021-06-16 设计创作，主要内容包括：本发明提出了一种基于FPGA的数组排序方法、系统及数据压缩方法。方法应用于FPGA数据压缩中,包括：获取待排序数组,待排序数组中的数据按照初始顺序排列,按照初始顺序对数据进行编号,获取初始序号；按照初始顺序从待排序数组中依次选取数据作为第一数据,比较第一数据与待排序数组中的数据的大小,通过标志位记录比较结果,将第一数据的标志位数值相加得到最终序号,最终序号即为第一数据在待排序数组中按升序排序的位置序号。本发明提供的基于FPGA的数组排序方法,只需将数组遍历一次即可完成数组的排序,且时间复杂度不受数据集影响,每一次排序的时间复杂度固定为O＝n,解决了现有排序算法排序时间长、排序耗时不固定的问题。(The invention provides an array sorting method, an array sorting system and a data compression method based on an FPGA. The method is applied to FPGA data compression and comprises the following steps: acquiring an array to be sorted, arranging data in the array to be sorted according to an initial sequence, numbering the data according to the initial sequence, and acquiring an initial sequence number; sequentially selecting data from the array to be sorted as first data according to an initial sequence, comparing the first data with the data in the array to be sorted, recording a comparison result through the zone bits, and adding the numerical values of the zone bits of the first data to obtain a final sequence number, wherein the final sequence number is a position sequence number of the first data sorted in the array to be sorted in an ascending order. According to the array sorting method based on the FPGA, the array can be sorted only by traversing the array once, the time complexity is not influenced by the data set, the time complexity of each sorting is fixed to be O-n, and the problems that an existing sorting algorithm is long in sorting time and unfixed in sorting time are solved.)

1. An array sorting method based on FPGA is characterized in that the method is applied to FPGA data compression and comprises the following steps:

acquiring an array to be sorted, arranging data in the array to be sorted according to an initial sequence, numbering the data according to the initial sequence, and acquiring an initial sequence number;

sequentially selecting data from the array to be sorted as first data according to the initial sequence, comparing the first data with the data in the array to be sorted, and recording a comparison result through a zone bit, wherein the zone bit comprises a zone bit numerical value and a zone bit serial number, the zone bit serial number corresponds to the initial serial number, and the number of the zone bits of each piece of first data is the same as the number of the data in the array to be sorted;

and adding the flag bit numerical values of the first data to obtain a final sequence number, wherein the final sequence number is a position sequence number of the first data sorted in the array to be sorted according to an ascending order.

2. The array sorting method according to claim 1, wherein comparing the size of the first data with the size of the data in the array to be sorted, and recording the comparison result by a flag bit specifically comprises:

comparing the first data with each data in the array to be sorted, and recording the comparison result through a flag bit,

when the first data is larger than certain data in the array to be sorted, the value of the flag bit is marked as 1;

when the first data is smaller than certain data in the array to be sorted, the flag bit value is recorded as 0;

when the first data is equal to a certain data in the array to be sorted, judging whether the initial sequence number of the first data is larger than the initial sequence number of the data:

if yes, the value of the flag bit is marked as 1; if not, the value of the flag bit is marked as 0.

3. The array sorting method according to claim 2, wherein a counter of the FPGA is obtained;

adding 1 to the counter value every time the first data is selected, wherein each first data corresponds to a counter value which is equal to the initial sequence number of the first data;

when the first data is equal to a certain data in the array to be sorted, judging whether the counter value is larger than the initial sequence number of the data:

if yes, the value of the flag bit is marked as 1; if not, the value of the flag bit is marked as 0.

4. The array sorting method according to claim 3, wherein the array sorting method is performed under the driving of an FPGA internal clock; and completing the processes from selecting the first data to acquiring the final sequence number in one clock cycle.

5. The array sorting method according to claim 2, wherein the array to be sorted is set to D ═ { D0, D1 … Dn }, the counter value is Cnt ═ 0 to n, the first data is Dx, and the comparison results of Dx and D0 to Dn are recorded using n +1 Flag bits Flag:

Dx>D0：Flag[0]＝1

dx ═ D1: flag [1] ═ 0or 1 (Flag [1] ═ 1 when Cnt >1, and Flag [1] ═ 0 when Cnt < ═ 1)

Dx<D2：Flag[2]＝0

……

Dx<Dn：Flag[n]＝0

The n +1 Flag bit values are added, i.e., Flag [0] + Flag [1] + … + Flag [ n ] ═ Sum, which is the position of Dx in the ascending array.

6. An array sorting system based on FPGA is characterized in that the system is applied to FPGA data compression and comprises,

an array acquisition unit: the method comprises the steps of obtaining an array to be sorted, arranging data in the array to be sorted according to an initial sequence, numbering the data according to the initial sequence, and obtaining an initial sequence number;

a comparison unit: the data sorting device is used for sequentially selecting data from the array to be sorted as first data according to the initial sequence, comparing the first data with the data in the array to be sorted, and recording a comparison result through a zone bit, wherein the zone bit comprises a zone bit numerical value and a zone bit sequence number, the zone bit sequence number corresponds to the initial sequence number, and the zone bit number of each first data is the same as the data number in the array to be sorted;

a sorting unit: and the sequence number is a position sequence number of the first data in the array to be sequenced in an ascending order.

7. The array sorting system of claim 6, wherein the comparison unit further comprises:

comparing the first data with each data in the array to be sorted, and recording the comparison result through a flag bit,

when the first data is larger than certain data in the array to be sorted, the value of the flag bit is marked as 1;

when the first data is smaller than certain data in the array to be sorted, the flag bit value is recorded as 0;

when the first data is equal to a certain data in the array to be sorted, judging whether the initial sequence number of the first data is larger than the initial sequence number of the data:

if yes, the value of the flag bit is marked as 1; if not, the value of the flag bit is marked as 0.

8. The system of claim 7, wherein a counter of the FPGA is obtained;

adding 1 to the counter value every time the first data is selected, wherein each first data corresponds to a counter value which is equal to the initial sequence number of the first data;

when the first data is equal to a certain data in the array to be sorted, judging whether the counter value is larger than the initial sequence number of the data:

if yes, the value of the flag bit is marked as 1; if not, the value of the flag bit is marked as 0.

9. The array sequencing system of claim 7, wherein the array sequencing system is driven by an FPGA internal clock;

and completing the processes from selecting the first data to acquiring the final sequence number in one clock cycle.

10. An FPGA-based data compression method, characterized in that the compression method sorts data by using the FPGA-based array sorting method of any one of claims 1 to 5.

Technical Field

The invention relates to the field of data processing, in particular to an array sorting method and system based on an FPGA and a data compression method.

Background

Data sorting is to arrange data in a certain order so that researchers find some obvious features or trends by browsing the data to find clues for solving problems. In addition, ordering helps to check the data for error correction, and facilitates re-classification or grouping, etc. The good sorting method can effectively improve the sorting speed and the sorting effect. Common sorting methods include bubble sorting, quick sorting, insert sorting, hill sorting, merge sorting, and the like.

Bubble sorting method: and comparing two adjacent data in the array, moving the larger (smaller) number to the end (beginning) of the array through pairwise comparison, executing an inner-layer loop once, determining a maximum (minimum) number, and traversing the outer-layer loop from the end (beginning) to the beginning (end) of the array.

Insertion ordering method: the array to be sorted is divided into two parts, and the data with the smallest index is taken out from the latter part and inserted into the proper position of the former part each time.

A quick sequencing method: the quick sorting method is one of the most excellent algorithms at present, and the realization idea is that the sorting problem of one array is regarded as the sorting problem of two small arrays, and each small array can be continuously regarded as two smaller arrays, and recursion is carried out until the length of the array is at most 2.

However, the above-mentioned common sorting methods cannot complete array sorting by one-time traversal, and cannot achieve time complexity O ═ n; and most of the cases are influenced by the data set, and the complexity of the sequencing space and the complexity of the sequencing time are unstable.

Therefore, the sorting method in the prior art generally has the defects of high complexity, many comparison times (high spatial complexity), long sorting time (high time complexity), influence of data on the realization of the sorting time, and the like. Thus, there is a need for a sort order scheme that can solve the above problems.

Disclosure of Invention

In view of this, the invention provides an array sorting method, system and data compression method based on an FPGA, and the specific scheme is as follows:

an array sorting method based on FPGA is applied to FPGA data compression and comprises the following steps:

acquiring an array to be sorted, arranging data in the array to be sorted according to an initial sequence, numbering the data according to the initial sequence, and acquiring an initial sequence number;

sequentially selecting data from the array to be sorted as first data according to the initial sequence, comparing the first data with the data in the array to be sorted, and recording a comparison result through a zone bit, wherein the zone bit comprises a zone bit numerical value and a zone bit serial number, the zone bit serial number corresponds to the initial serial number, and the number of the zone bits of each piece of first data is the same as the number of the data in the array to be sorted;

and adding the flag bit numerical values of the first data to obtain a final sequence number, wherein the final sequence number is a position sequence number of the first data sorted in the array to be sorted according to an ascending order.

In an embodiment, "comparing the size of the first data with the size of the data in the array to be sorted, and recording the comparison result by the flag bit" specifically includes:

comparing the first data with each data in the array to be sorted, and recording the comparison result through a flag bit,

when the first data is larger than certain data in the array to be sorted, the value of the flag bit is marked as 1;

when the first data is smaller than certain data in the array to be sorted, the flag bit value is recorded as 0;

when the first data is equal to a certain data in the array to be sorted, judging whether the initial sequence number of the first data is larger than the initial sequence number of the data:

if yes, the value of the flag bit is marked as 1; if not, the value of the flag bit is marked as 0.

In a specific embodiment, a counter of the FPGA is obtained;

adding 1 to the counter value every time the first data is selected, wherein each first data corresponds to a counter value which is equal to the initial sequence number of the first data;

when the first data is equal to a certain data in the array to be sorted, judging whether the counter value is larger than the initial sequence number of the data:

if yes, the value of the flag bit is marked as 1; if not, the value of the flag bit is marked as 0.

In a specific embodiment, the array sorting method is performed under the driving of an internal clock of the FPGA; and completing the processes from selecting the first data to acquiring the final sequence number in one clock cycle. The sequencing action of the FPGA and the Count are driven by an FPGA internal clock.

In one embodiment, the array to be sorted is set as D ═ { D0, D1 … Dn }, the counter value is Cnt ═ 0 to n, the first data is Dx, and the comparison results of Dx and D0 to Dn are recorded using n +1 Flag bits Flag:

Dx>D0：Flag[0]＝1

dx ═ D1: flag [1] ═ 0or 1 (Flag [1] ═ 1 when Cnt >1, and Flag [1] ═ 0 when Cnt < ═ 1)

Dx<D2：Flag[2]＝0

……

Dx<Dn：Flag[n]＝0

The n +1 Flag bit values are added, i.e., Flag [0] + Flag [1] + … + Flag [ n ] ═ Sum, which is the position of Dx in the ascending array.

An array sorting system based on FPGA, which is applied to FPGA data compression, comprises,

an array acquisition unit: the method comprises the steps of obtaining an array to be sorted, arranging data in the array to be sorted according to an initial sequence, numbering the data according to the initial sequence, and obtaining an initial sequence number;

a comparison unit: the data sorting device is used for sequentially selecting data from the array to be sorted as first data according to the initial sequence, comparing the first data with the data in the array to be sorted, and recording a comparison result through a zone bit, wherein the zone bit comprises a zone bit numerical value and a zone bit sequence number, the zone bit sequence number corresponds to the initial sequence number, and the zone bit number of each first data is the same as the data number in the array to be sorted;

a sorting unit: and the sequence number is a position sequence number of the first data in the array to be sequenced in an ascending order.

In a specific embodiment, the comparing unit further includes:

comparing the first data with each data in the array to be sorted, and recording the comparison result through a flag bit,

when the first data is larger than certain data in the array to be sorted, the value of the flag bit is marked as 1;

when the first data is smaller than certain data in the array to be sorted, the flag bit value is recorded as 0;

when the first data is equal to a certain data in the array to be sorted, judging whether the initial sequence number of the first data is larger than the initial sequence number of the data:

if yes, the value of the flag bit is marked as 1; if not, the value of the flag bit is marked as 0.

In a specific embodiment, a counter of the FPGA is obtained;

adding 1 to the counter value every time the first data is selected, wherein each first data corresponds to a counter value which is equal to the initial sequence number of the first data;

when the first data is equal to a certain data in the array to be sorted, judging whether the counter value is larger than the initial sequence number of the data:

if yes, the value of the flag bit is marked as 1; if not, the value of the flag bit is marked as 0.

In a specific embodiment, the array sorting system is driven by an internal clock of the FPGA;

and completing the processes from selecting the first data to acquiring the final sequence number in one clock cycle.

The compression method adopts the array sorting method based on the FPGA to sort data.

Has the advantages that:

the invention provides an array sorting method, an array sorting system and a data compression method based on an FPGA (field programmable gate array).

The array sorting method based on the FPGA can finish the sorting of the arrays only by traversing the arrays once, the time complexity is not influenced by a data set, the time complexity of the sorting every time is fixed to be O ═ n, and the problems that the sorting time is long and the sorting time consumption is not fixed in the conventional sorting algorithm are solved.

The array sorting system based on the FPGA systematizes the method, so that the array sorting system has more practical applicability.

The FPGA-based data compression method realizes data compression by using the FPGA, processes a sorting algorithm in a parallel mode, finishes sorting of arrays only by traversing the arrays once, is not influenced by a data set, and fixes the time complexity of sorting every time to be O-n.

Drawings

Fig. 1 is a flowchart of an array sorting method based on FPGA according to embodiment 1 of the present invention;

FIG. 2 is a diagram illustrating results of an array to be sorted according to embodiment 1 of the present invention before sorting;

FIG. 3 is a flowchart showing the sequence of embodiment 1 of the present invention;

FIG. 4 is a diagram illustrating the result of the array to be sorted according to embodiment 1 of the present invention after sorting;

fig. 5 is a block diagram of a structure of an array sorting system based on an FPGA according to embodiment 2 of the present invention.

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Reference numerals: 1-an array acquisition unit; 2-a comparison unit; 3-ordering unit.

Detailed Description

Hereinafter, various embodiments of the present disclosure will be described more fully. The present disclosure is capable of various embodiments and of modifications and variations therein. However, it should be understood that: there is no intention to limit the various embodiments of the present disclosure to the specific embodiments disclosed herein, but rather, the disclosure is to cover all modifications, equivalents, and/or alternatives falling within the spirit and scope of the various embodiments of the present disclosure.

The invention provides an array sorting method, an array sorting system and a data compression method based on an FPGA (field programmable gate array). the array sorting can be finished by traversing the array once, the time complexity is not influenced by a data set, the time complexity of each sorting is fixed to be O-n, and the problems of long sorting time and unfixed sorting time consumption of the existing sorting algorithm are solved.

The terminology used in the various embodiments of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the disclosure belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments.

Example 1

The embodiment 1 of the invention discloses an array sorting method based on an FPGA, which is shown in the attached figure 1 of a flowchart description of the method and has the following specific scheme:

an array sorting method based on FPGA is applied to FPGA data compression and comprises the following steps:

101. acquiring an array to be sorted, arranging data in the array to be sorted according to an initial sequence, numbering the data according to the initial sequence, and acquiring an initial sequence number;

102. sequentially selecting data from the array to be sorted as first data according to the initial sequence, comparing the size of the first data with the size of the data in the array to be sorted, and recording a comparison result through a zone bit; the zone bits comprise zone bit numerical values and zone bit serial numbers, the zone bit serial numbers correspond to the initial serial numbers, and the quantity of the zone bits of each piece of first data is the same as that of the data in the array to be sorted;

103. and adding the flag bit values of the first data to obtain a final sequence number, wherein the final sequence number is a position sequence number of the first data sorted in the array to be sorted in an ascending order.

Specifically, 101, an array to be sorted is obtained, data in the array to be sorted are arranged according to an initial sequence, the data are numbered according to the initial sequence, and an initial sequence number is obtained.

In the present embodiment, the array to be sorted includes, but is not limited to, a one-dimensional array. The array to be sorted comprises a plurality of data, and the data are arranged and distributed according to an initial sequence. The initial sequence is the specific sorting position of each data in the array to be sorted. And numbering the data according to the initial sequence to obtain an initial sequence number.

For example, the array to be sorted D ═ { D0, D1 … Dn }, the array includes n +1 data, and the initial sequence is D0 and D1 … Dn. When the numbers are numbered according to the initial sequence to obtain the initial serial number, D0 is number 0, D1 is number 1, D2 is number 2 … …, and so on, and Dn is number n.

Based on this, this embodiment obtains the counter of the FPGA, and replaces the initial sequence number with the counter. And each data corresponds to a counter value by adding 1 to the counter value every time the final serial number of the data is calculated or every time the first data is selected. And calculating the final sequence number of each data according to the initial sequence, wherein the initial sequence number of each data corresponds to the respective counter value.

Specifically, 102, data are sequentially selected from the array to be sorted as first data according to the initial sequence, the size of the first data and the size of the data in the array to be sorted are compared, and the comparison result is recorded through the flag bit.

In this embodiment, the flag bits include a flag bit numerical value and a flag bit serial number, the flag bit serial number corresponds to the initial serial number, and the number of the flag bits of each first data is the same as the number of the data in the array to be sorted. For example, the Flag [ H ] ═ N, where H is the Flag number, N is the Flag value, and in this embodiment, the Flag value is 0or 1. Therefore, the flag bit can be expressed by a waveform signal, and the high level is 1 and the low level is 0.

For example, the array D to be sorted is { D0, D1 … Dn }, and the data are sequentially selected as the first data according to the initial order. Firstly, when D0 is selected as first data, D0 needs to be sequentially compared with D0-Dn, and the comparison result is recorded through Flag [0 ]; secondly, when D1 is selected as first data, D1 needs to be sequentially compared with D0-Dn, and the comparison result is recorded through Flag [1 ]; then, when selecting D2 as the first data, D2 needs to compare with D0-Dn in turn, and record the comparison result … … through Flag [2], and finally, when selecting Dn as the first data, Dn needs to compare with D0-Dn in turn, and record the comparison result through Flag [ N ]. And recording the comparison result through the flag bit, and finally summing the values of the flag bit to obtain the sequencing position of the first data.

The obtaining of the flag bit specifically includes: the first data is compared with each data in the array to be sorted, and the comparison result is recorded through the flag bit,

when the first data is larger than certain data in the array to be sorted, the value of the zone bit is marked as 1;

when the first data is smaller than certain data in the array to be sorted, the value of the zone bit is marked as 0;

when the first data is equal to a certain data in the array to be sorted, judging whether the initial sequence number of the first data is greater than the initial sequence number of the data: if yes, the flag bit value is marked as 1, and if no, the flag bit value is marked as 0.

For example, the array to be sorted is D ═ { D0, D1 … Dn }, the counter value is Cnt ═ 0 to n, the first data is Dx, and the comparison results of Dx and D0 to Dn are recorded using n +1 Flag bits Flag:

when the first data is larger than certain data in the array to be sorted, the value of the zone bit is marked as 1; dx > D0: flag [0] ═ 1

When the first data is smaller than certain data in the array to be sorted, the value of the zone bit is marked as 0; dx < D2: flag [2] ═ 0

When the first data is equal to a certain data in the array to be sorted, there are two cases: (1) the first data is a certain data in the array to be sorted. For example, in the array { D0, D1 … Dn }, when D0 is selected as the first data Dx, D0 needs to be sequentially compared with D0 to Dn, and when the first data Dx is compared with D0, Dx is D0. (2) Data with the same numerical value exists in the array to be sorted. For example, in the array { D0, D1 … Dn }, where D0 is D1, when D0 is selected as the first data Dx, D0 needs to be sequentially compared with D0 to Dn, and when the first data Dx is compared with D1, Dx is D0.

In case (1), the present embodiment determines by the flag bit number and the initial number. Judging whether the initial sequence number of the first data is greater than the initial sequence number of the data: if yes, the value of the flag bit is 1, which proves that the situation is the case (2); if not, the initial sequence number of the first data is equal to or less than the initial sequence number of the data, and the value of the flag bit is 0. When the initial sequence number of the first data is equal to the initial sequence number of the data, proving that the situation is (1); when the initial sequence number of the first data is not equal to the initial sequence number of the data, this proves to be the case (2).

In addition, in this embodiment, a counter of the FPGA is introduced, and a value of the counter corresponds to the initial sequence number, and the counter value of the first data and the initial sequence number of the data can be compared.

Dx ═ D1: flag [1] ═ 0or 1 (Flag [1] ═ 1 when Cnt >1, and Flag [1] ═ 0 when Cnt < ═ 1)

In addition, the embodiment also introduces an FPGA internal clock. The array sorting method is carried out under the drive of an FPGA internal clock, and the sorting action of the FPGA and the Count are driven by the FPGA internal clock. In a clock cycle, data is selected from an array to be ordered as first data and a final sequence number is obtained. That is, in each clock cycle, a final sequence number of one data is obtained.

Assuming that the array to be sorted is D ═ { D0, D1 … Dn }, the counter value is Cnt ═ 0 to n, the first data is Dx, and the comparison results of Dx and D0 to Dn are recorded using n +1 Flag bits Flag:

Dx>D0：Flag[0]＝1

dx ═ D1: flag [1] ═ 0or 1 (Flag [1] ═ 1 when Cnt >1, and Flag [1] ═ 0 when Cnt < ═ 1)

Dx<D2：Flag[2]＝0

……

Dx<Dn：Flag[n]＝0

The n +1 Flag bits are added, i.e., Flag [0] + Flag [1] + … + Flag [ n ] ═ Sum, which is the position of Dx in the array after ascending sort.

This example is demonstrated by the experimental results shown in FIGS. 2-4 of the specification. Fig. 2 in the description is an array {7, 2, 1, 3, 0, 5, 4, 2} to be sorted, fig. 4 in the description is a sorted array, and fig. 3 in the description is a specific processing procedure. According to the experimental result, the array sorting method provided by the embodiment can finish the sorting of the arrays only by traversing the arrays once, and the defects of the prior art are overcome.

As shown in figure 3 of the specification. The array to be sorted is { D0, D1, D2, D3, D4, D5, D6 and D7}, and the horizontal direction is a time axis. And D0, D1, D2, D3, D4, D5, D6 and D7 are sequentially selected as first data by taking the internal clock of the FPGA as a time axis and advancing according to the time sequence. The vertical axis is a flag bit, and the flag bit records the comparison result of the first data and each data. Taking D1 as an example of the first data, when Dx is 2, the counter value Cnt is 1, and D1 is D7 is 2 in the to-be-arranged group, the data values may be the same. Dx was compared sequentially with D0, D1, D2, D3, D4, D5, D6, D7:

(1)2 is less than 7, Dx is less than D0, Flag [0] is 0;

(2)2, Dx equals D1, Cnt equals 1, Flag [1] equals 0;

(3)2 is more than 1, Dx is more than D2, Flag [2] ═ 1;

(4)2 is less than 3, Dx is less than D3, Flag [3] is 0;

(5)2 is greater than 0, Dx is greater than D4, Flag [4] ═ 1;

(6)2 is less than 5, Dx is less than D5, Flag [5] is 0;

(7)2 is less than 4, Dx is less than D6, Flag [6] ═ 0;

(8)2, Dx is equal to D7, Cnt < 7, Flag [7] is 0;

Sum＝Flag[0]+Flag[1]+Flag[2]+Flag[3]+Flag[4]+Flag[5]+Flag[6]+Flag[7]＝2

d2 ranks 2 in the sorted array as shown in fig. 4 of the specification.

The embodiment provides an array sorting method based on an FPGA (field programmable gate array), the array sorting can be completed only by traversing the array once, the time complexity is not influenced by a data set, the time complexity of each sorting is fixed to be O ═ n, and the problems of long sorting time and unfixed sorting time consumption of the existing sorting algorithm are solved.

Example 2

The embodiment 2 of the invention discloses an array sorting system based on an FPGA. On the basis of the embodiment 1, the method of the embodiment 1 is systematized, the specific structure is as shown in the attached figure 5 of the specification, and the specific scheme is as follows:

an array sorting system based on an FPGA is applied to FPGA data compression and comprises an array obtaining unit 1, a comparing unit 2 and a sorting unit 3. The concrete contents are as follows

Array acquisition unit 1: the method comprises the steps of obtaining an array to be sorted, arranging data in the array to be sorted according to an initial sequence, numbering the data according to the initial sequence, and obtaining an initial sequence number;

the comparison unit 2: the data sorting device is used for sequentially selecting data from an array to be sorted as first data according to an initial sequence, comparing the first data with the data in the array to be sorted, and recording a comparison result through a zone bit, wherein the zone bit comprises a zone bit numerical value and a zone bit serial number, the zone bit serial number corresponds to the initial serial number, and the number of the zone bits of each first data is the same as the number of the data in the array to be sorted;

a sorting unit 3: and the sequence number is the position sequence number of the first data in the array to be sorted according to ascending order.

Wherein, the comparing unit 2 further comprises:

comparing the first data with each data in the array to be sorted, recording the comparison result through the flag bit,

when the first data is larger than certain data in the array to be sorted, the value of the zone bit is marked as 1;

when the first data is smaller than certain data in the array to be sorted, the value of the zone bit is marked as 0;

when the first data is equal to a certain data in the array to be sorted, judging whether the initial sequence number of the first data is greater than the initial sequence number of the data: if yes, the flag bit value is marked as 1, and if no, the flag bit value is marked as 0.

In addition, a counter of the FPGA is obtained through an array sorting system;

adding 1 to the counter value every time first data is selected, wherein each first data corresponds to one counter value;

when the first data is equal to a certain data in the array to be sorted, judging whether the counter value is larger than the initial sequence number of the data: if yes, the flag bit value is marked as 1, and if no, the flag bit value is marked as 0.

In this embodiment, the array sorting system is driven by an internal clock of the FPGA, and the sorting operation of the FPGA and the Count technology are both driven by the internal clock of the FPGA.

In a clock cycle, data is selected from an array to be ordered as first data and a final sequence number is obtained.

The embodiment provides an array sorting system based on an FPGA, and the method of the embodiment 1 is systematized on the basis of the embodiment 1, so that the array sorting system has more practical applicability.

Example 3

The embodiment provides a data compression method based on an FPGA on the basis of embodiment 1. The FPGA-based array sorting method of embodiment 1 is applied to specific data compression.

In the embodiment, the FPGA is used for realizing a data compression algorithm, a large number of sorting algorithms are required in the compression algorithm, the complex spatial complexity and the time complexity of the traditional sorting algorithm are greatly influenced by data, and the spatial complexity and the time complexity are different when different data sets are sorted. The data ordering involved in the data compression method process is performed by the method of example 1. The specific scheme is as follows:

101. acquiring an array to be sorted, arranging data in the array to be sorted according to an initial sequence, numbering the data according to the initial sequence, and acquiring an initial sequence number;

102. sequentially selecting data from the array to be sorted as first data according to the initial sequence, comparing the size of the first data with the size of the data in the array to be sorted, and recording a comparison result through a zone bit; the zone bits comprise zone bit numerical values and zone bit serial numbers, the zone bit serial numbers correspond to the initial serial numbers, and the quantity of the zone bits of each piece of first data is the same as that of the data in the array to be sorted;

103. and adding the flag bit values of the first data to obtain a final sequence number, wherein the final sequence number is a position sequence number of the first data sorted in the array to be sorted in an ascending order.

In the FPGA-based data compression method, a sorting algorithm is processed in a parallel mode in the FPGA-based compression technology, the sorting of the arrays can be completed only by traversing the arrays once, the time complexity is not influenced by a data set, the time complexity of the sorting every time is fixed to be O ═ n, and the problems that the sorting time is long and the sorting time is not fixed in the FPGA compression algorithm are solved.

The invention provides a data compression method, a data compression system and a data compression method based on an FPGA. The array sorting method based on the FPGA can finish the sorting of the arrays only by traversing the arrays once, the time complexity is not influenced by a data set, the time complexity of the sorting every time is fixed to be O ═ n, and the problems that the sorting time is long and the sorting time consumption is not fixed in the conventional sorting algorithm are solved. The array sorting system based on the FPGA systematizes the method, so that the array sorting system has more practical applicability. The FPGA-based data compression method realizes data compression by using the FPGA, processes a sorting algorithm in a parallel mode, finishes sorting of arrays only by traversing the arrays once, is not influenced by a data set, and fixes the time complexity of sorting every time to be O-n.

Those skilled in the art will appreciate that the figures are merely schematic representations of one preferred implementation scenario and that the blocks or flow diagrams in the figures are not necessarily required to practice the present invention. Those skilled in the art will appreciate that the modules in the devices in the implementation scenario may be distributed in the devices in the implementation scenario according to the description of the implementation scenario, or may be located in one or more devices different from the present implementation scenario with corresponding changes. The modules of the implementation scenario may be combined into one module, or may be further split into a plurality of sub-modules. The above-mentioned invention numbers are merely for description and do not represent the merits of the implementation scenarios. The above disclosure is only a few specific implementation scenarios of the present invention, however, the present invention is not limited thereto, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention.